High electron mobility transistor and semiconductor device

Abstract

The high electron mobility transistor comprises: a channel layer through which carriers flow; a pair of main electrodes respectively connected to one end and the other end of the channel layer; a barrier layer provided to the channel layer and inducing carriers; a gate electrode disposed to an intermediate portion of the channel layer, with the barrier layer interposed between the gate electrode and the channel layer; a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and a second spacer layer disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and trapping carriers.

Description

Technical Field

[0001] The present disclosure relates to a high electron mobility transistor and a semiconductor device. The present disclosure further relates to a high frequency switching circuit, a power amplifier and a wireless communication terminal each including a high electron mobility transistor. Background Art

[0002] Patent document 1 discloses a high electron mobility transistor (HEMT: High Electron Mobility Transistor, hereinafter, referred to as "HEMT"). HEMT includes a nitride semiconductor, specifically GaN, as a III-V compound semiconductor. GaN HEMT has characteristics such as high voltage resistance, high heat resistance, high saturation electron velocity or high channel electron concentration. Such characteristics enable the realization of a smaller GaN HEMT with higher performance, promoting the development of GaN HEMT applications in power devices and high-frequency devices.

[0003] The GaN HEMT includes: a channel layer; a spacer layer stacked on the channel layer; and a barrier layer stacked on the spacer layer. The channel layer is a carrier path through which carriers (electrons) flow. The spacer layer suppresses alloy scattering. The barrier layer guides carriers to the interface between the channel layer and the spacer layer.

[0004] In a GaN HEMT adopting an insulated gate structure (hereinafter referred to as "MIS (metal insulator semiconductor) type"), a gate electrode is provided on a barrier layer with an insulating layer (gate insulating film) interposed therebetween. The adoption of the MIS type enables low loss and high output of the GaN HEMT.

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2018-56299 Summary of the invention

[0008] During the research and development of GaN HEMT, the inventors of the present application have confirmed the following phenomenon. A carrier trap region (carrier capture region) exists at the interface between the insulating layer and the barrier layer, in the bulk of the insulating layer, and in the bulk of the barrier layer. When a high electric field or high temperature stress is repeatedly applied to the GaN HEMT when driven, carriers are trapped in the carrier trap region. The trapped carriers cause fluctuations in the threshold voltage of the GaN HEMT.

[0009] Therefore, it is desirable to effectively suppress or prevent fluctuation in the threshold voltage of the HEMT in the HEMT and a semiconductor device including the HEMT.

[0010] A HEMT according to a first embodiment of the present disclosure includes: a channel layer through which carriers flow; a pair of corresponding main electrodes coupled to one end and the other end of the channel layer; a barrier layer disposed in the channel layer and inducing carriers; a gate electrode disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer; a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and a second spacer layer disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and capturing carriers.

[0011] A semiconductor device according to a second embodiment of the present disclosure includes a HEMT, wherein the HEMT includes: a channel layer through which carriers flow; a pair of corresponding main electrodes coupled to one end and the other end of the channel layer, a barrier layer disposed in the channel layer and inducing carriers; a gate electrode disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer; a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and a second spacer layer disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and capturing carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a main portion of a semiconductor device including a HEMT according to a first embodiment of the present disclosure.

[0013] Figure 2 yes Figure 1 Composition distribution diagram of the HEMT shown in .

[0014] Figure 3 yes Figure 1 The band structure diagram of HEMT shown in .

[0015] Figure 4 yes Figure 1 The current-voltage characteristics of the HEMT shown in FIG.

[0016] Figure 5 It is a graph showing the current-voltage characteristics of a HEMT according to a comparative example.

[0017] Figure 6 : is a configuration diagram showing the composition of each semiconductor layer of the HEMT according to the first embodiment and the composition of each semiconductor layer of the HEMT according to the comparative example.

[0018] Figure 7 is a main part of a semiconductor device including a HEMT according to a second embodiment of the present disclosure. Figure 1 The corresponding cross-sectional view.

[0019] Figure 8is a diagram showing the composition of each semiconductor layer of the HEMT according to the third embodiment of the present disclosure. Figure 6 The corresponding configuration diagram.

[0020] Fig. 9 is a diagram showing the composition of each semiconductor layer of the HEMT according to the fourth embodiment of the present disclosure. Figure 6 The corresponding configuration diagram.

[0021] Fig.10 is a perspective view of a semiconductor module including a HEMT according to a fifth embodiment of the present disclosure.

[0022] Fig.11 is a block configuration diagram of an electronic device including a HEMT according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, a detailed description will be given of an embodiment of the present disclosure with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0024] 1. First Implementation

[0025] The first embodiment is a first example in which the present technology is applied to a HEMT and a semiconductor device including a HEMT. Here, a longitudinal cross-sectional structure, composition distribution, energy band structure, and current-voltage characteristics of a HEMT (specifically, a MIS GaN HEMT) including a nitride semiconductor as a group III-V compound semiconductor are described.

[0026] 2. Second Implementation

[0027] The second embodiment is a second example in which the present technology is applied to a Schottky junction (Schottky barrier junction) GaN HEMT and a semiconductor device including the HEMT instead of the MIS GaN HEMT in the semiconductor device according to the first embodiment.

[0028] 3. Third Implementation

[0029] The third embodiment is a third example in which the present technology is applied to a MIS GaN HEMT having a different structure in the semiconductor device according to the first embodiment and a semiconductor device including the HEMT.

[0030] 4. Fourth Implementation

[0031] The fourth embodiment is a fourth example in which the present technology is applied to a GaO HEMT and a semiconductor device including the HEMT instead of the MIS GaN HEMT in the semiconductor device according to the first embodiment.

[0032] 5. Fifth Implementation

[0033] The fifth embodiment describes a semiconductor module mounted with any one of the semiconductor devices according to the first to fourth embodiments. The semiconductor module is incorporated into a wireless communication terminal, for example. In addition, the semiconductor module includes a high-frequency switching circuit, a power amplifier, and the like.

[0034] 6. Sixth Implementation

[0035] Embodiment 6 describes an electronic device equipped with any one of the semiconductor devices according to Embodiments 1 to 4. The electronic device is, for example, a wireless communication terminal. In addition, the electronic device includes a high-frequency switching circuit, a power amplifier, and the like.

[0036] 7. Other Implementation Methods

[0037] <1. First Embodiment>

[0038] Reference Figures 1 to 6 , a HEMT 2 according to a first embodiment of the present disclosure and a semiconductor device 1 including the HEMT 2 according to the first embodiment of the present disclosure are described.

[0039] Here, for convenience, the arrow-X direction appropriately shown in the drawings indicates one plane direction of the semiconductor device 1 placed on a plane. The arrow-Y direction indicates another plane direction orthogonal to the arrow-X direction. In addition, the arrow-Z direction indicates an upward direction orthogonal to the arrow-X direction and the arrow-Y direction. That is, the arrow-X direction, the arrow-Y direction, and the arrow-Z direction are respectively exactly consistent with the X-axis direction, the Y-axis direction, and the Z-axis direction of the three-dimensional coordinate system.

[0040] It should be noted that these directions are shown to help understand the description and are not intended to limit the directions of the present technology.

[0041] [Configuration of HEMT 2 and Semiconductor Device 1]

[0042] (1) Basic Structure of HEMT 2 and Semiconductor Device 1

[0043] Figure 1 An example of a longitudinal cross-sectional structure of a main portion of the semiconductor device 1 according to the first embodiment is shown.

[0044] like Figure 1 As shown in FIG. 1 , for the HEMT 2 and the semiconductor device 1 according to the first embodiment, the substrate 3 is used as a base. In the first embodiment, the HEMT 2 is formed of a MIS GaN HEMT. That is, the HEMT 2 includes a channel layer 5, a spacer layer 6, a barrier layer 7, an insulating layer 8, a gate electrode 9, and a pair of main electrodes 10.

[0045] (2) Configuration of substrate 3

[0046] The substrate 3 includes a compound semiconductor material (eg, a nitride semiconductor material) as a Group III-V compound semiconductor material. Specifically, semi-insulating single crystal GaN is used.

[0047] In the first embodiment, the buffer layer 4 is provided between the substrate 3 and the channel layer 5. The buffer layer 4 controls the lattice constant. Therefore, the substrate 3 may include a semiconductor material having a lattice constant different from that of the channel layer 5. For example, a substrate such as a SiC substrate, a sapphire substrate, or a Si substrate can be used for the substrate 3.

[0048] (3) Configuration of buffer layer 4

[0049] The buffer layer 4 is stacked on the substrate 3. The buffer layer 4 includes, for example, a compound semiconductor material. The compound semiconductor material is formed on the substrate 3 using an epitaxial growth method.

[0050] In the case where the lattice constant of the channel layer 5 is different from the lattice constant of the substrate 3, the lattice constant is controlled by the buffer layer 4. Controlling the lattice constant allows the channel layer 5 to have good crystalline quality. In addition, in the manufacturing method of the semiconductor device 1, the warpage of the substrate 3 in a wafer state after forming the channel layer 5 can be controlled.

[0051] For example, in the case where the substrate 3 includes single crystal Si and the channel layer 5 includes GaN, the buffer layer 4 may include AlN, AlGaN, or GaN.

[0052] (4) Configuration of channel layer 5

[0053] The channel layer 5 is stacked on the buffer layer 4. A two-dimensional electron gas (2DEG) 50 is generated near the channel layer 5 and the spacer layer 6. The two-dimensional electron gas 50 is a region where carriers are accumulated by a difference in polarization charge amount with the barrier layer 7.

[0054] One end of the two-dimensional electron gas 50 in the arrow -X direction is electrically coupled to one of the pair of main electrodes 10. The other end of the two-dimensional electron gas 50 in the opposite direction of the arrow -X direction is electrically coupled to the other of the pair of main electrodes 10. That is, one end and the other end of the channel layer 5 are coupled to the pair of corresponding main electrodes 10, allowing the channel layer 5 to be configured as part of a current path through which carriers flow.

[0055] Here, the channel layer 5 includes a nitride semiconductor material. Specifically, the channel layer 5 includes, for example, GaN. GaN is formed using an epitaxial growth method.

[0056] The channel layer 5 may also include undoped GaN (u-GaN) that is not doped with impurities. The use of u-GaN can effectively suppress impurity scattering of carriers in the channel layer 5, thereby achieving high carrier mobility.

[0057] (5) Configuration of spacer layer 6

[0058] The spacer layer 6 includes a first spacer layer 61 and a second spacer layer 62 .

[0059] The first spacer layer 61 is stacked on the channel layer 5 and disposed between the channel layer 5 and the barrier layer 7. The second spacer layer 62 is stacked on the first spacer layer 61 and disposed between the first spacer layer 61 and the barrier layer 7.

[0060] In addition, the second spacer layer 62 is arranged at least in a region overlapping with the gate electrode 9 when viewed in the arrow -Y direction (hereinafter, simply referred to as "in a side view") and when viewed in the arrow -Z direction (hereinafter, simply referred to as "in a plan view").

[0061] Here, in the side view as well as in the plan view, the region overlapping with the gate electrode 9 includes a region overlapping with a portion of the gate electrode 9, a region overlapping with the entire gate electrode 9, and a region overlapping with a region wider than the entire gate electrode 9. For example, the second spacer 62 may be provided in a region overlapping with a portion of the gate electrode 9 on the side of the main electrode 10 serving as a drain electrode.

[0062] (5-1) Configuration of the First Spacer Layer 61

[0063] Figure 2 An example of composition distribution of HEMT 2 is shown. Figure 2 , the horizontal axis indicates, from the right to the left, the respective regions of the channel layer 5, the first spacer layer 61, the second spacer layer 62, and the barrier layer 7. The vertical axis indicates the content of the constituent elements [atomic %].

[0064] also, Figure 3 An example of the energy band structure of HEMT 2 is shown. Figure 3 , the horizontal axis indicates, from right to left, the corresponding areas of the channel layer 5, the first spacer layer 61, the second spacer layer 62, the barrier layer 7, and the insulating layer 8. The vertical axis indicates energy potential.

[0065] Return to reference Figure 1 The first spacer layer 61 includes a nitride semiconductor material having a band gap larger than the band gap (3.4 [eV]) of the channel layer 5. The first spacer layer 61 is formed using, for example, an epitaxial growth method.

[0066] like Figure 2 As shown, the first spacer layer 61 includes Al x1 In y1 Ga[1-x1-y1] N(0<x1<1, 0≤y1<1, and 0<x1+y1<1). Figure 3 As shown, the band gap of the first spacer layer 61 including a nitride semiconductor material is wider than the band gap of the channel layer 5 .

[0067] Specifically, the first spacer layer 61 may include, for example, AlN as a binary nitride semiconductor material. The first spacer layer 61 may also include, for example, AlGaN as a ternary nitride semiconductor material. In addition, for example, the first spacer layer 61 may include, for example, AlGaInN as a quaternary nitride semiconductor material.

[0068] In the first embodiment, the first spacer layer 61 in the case of using AlN is described.

[0069] When the first spacer layer 61 is disposed between the channel layer 5 and the barrier layer 7, induced carriers are accumulated at the interface of the channel layer 5 adjacent to the first spacer layer 61 to generate the two-dimensional electron gas 50. Although described later, the barrier layer 7 includes, for example, a ternary nitride semiconductor material. The first spacer layer 61 makes it possible to reduce the influence of alloy scattering from the barrier layer 7, thereby increasing carrier mobility.

[0070] Here, in the manufacturing method of the HEMT 2, the first spacer layer 61 is formed on the channel layer 5 by crystal growth using an epitaxial growth method. Therefore, Ga, which is a constituent element of the channel layer 5, is diffused in the first spacer layer 61. This allows the first spacer layer 61 to contain Ga.

[0071] like Figure 2 As shown in FIG. 1 , in the Ga composition distribution, the Ga composition ratio decreases in the crystal growth direction (i.e., from the channel layer 5 to the first spacer layer 61). Due to the thermal history obtained until the crystal growth of the barrier layer 7 is completed, the Ga composition ratio increases again from the first spacer layer 61 to the second spacer layer 62. Therefore, the Ga composition distribution of the first spacer layer 61 has a minimum value (min) in the middle portion in the thickness direction.

[0072] It should be noted that by controlling the supply amount of the semiconductor crystal growth material and intentionally adding Ga, a similar Ga composition distribution can be formed.

[0073] At the same time, Al, which is the same Group III material and enters the same lattice position, is affected by the diffusion of Ga. As a result, in the Al composition distribution, the Al composition ratio increases from the channel layer 5 to the first spacer layer 61 compared to the Ga composition distribution. In addition, due to the thermal history, the Al composition ratio decreases again from the first spacer layer 61 to the second spacer layer 62. Therefore, the Al composition distribution of the first spacer layer 61 has a maximum value (max) in the middle part in the thickness direction.

[0074] It should be noted that the N composition ratio is constant.

[0075] (5-2) Configuration of the Second Spacer Layer 62

[0076] like Figure 1 As shown, the second spacer layer 62 includes a nitride semiconductor material having a band gap smaller than that of the first spacer layer 61. The second spacer layer 62 is formed using, for example, an epitaxial growth method.

[0077] like Figure 2 As shown, in the case where the channel layer 5 includes GaN, the second spacer layer 62 may include a nitride semiconductor material including Al, Ga, and In. Specifically, the second spacer layer 62 includes Al x2 In y2 Ga [1-x2-y2] N(0<x2<1, 0<y2<1, and 0<x2+y2<1). It should be noted that Figure 2 In the figure, AlInGaN is represented as AlGaInN, etc., but AlInGaN and AlGaInN are the same material.

[0078] Here, the constituent element ratios x1 and y1 of the first spacer layer 61 and the constituent element ratios x2 and y2 of the second spacer layer 62 each satisfy the following relational expressions: <1> and relational expressions <2> .

[0079] x1>x2... <1>

[0080] x1+y1>x2+y2... <2>

[0081] like Figure 3 As shown, the band gap of the second spacer layer 62 including a nitride semiconductor material is narrower than the band gap of the first spacer layer 61 and the band gap of the barrier layer 7 described later. In addition, the band gap of the second spacer layer 62 is wider than the band gap of the channel layer 5.

[0082] Therefore, the second spacer layer 62 has an energy potential formed toward the Fermi level E relative to the energy potential of the first spacer layer 61 and the energy potential of the barrier layer. F The energy potential of the first spacer layer 61 and the energy potential of the barrier layer 7 are determined by the conduction band E C Instructions (see Figure 3 Even when a positive bias is applied to the gate electrode 9 during driving, the energy potential of the second spacer layer 62 (conduction band E C ) is also higher than the conduction band E of the channel layer 5 C and the Fermi level E F .

[0083] Furthermore, the second spacer layer 62 including the quaternary nitride semiconductor material as described above allows easy formation of a mixed crystal having superior single crystallinity than a nitride semiconductor material used in the barrier layer 7 described later.

[0084] like Figure 3 As shown, carriers (e.g., electrons in this case) generated by stress during driving and transfer from the two-dimensional electron gas 50 to the gate electrode 9 side are captured (trapped) in the energy potential region of the second spacer layer 62 in the HEMT 2. The stress includes at least voltage applied stress and high temperature applied stress. That is, the second spacer layer 62 forms a region that captures carriers.

[0085] In addition, if Figure 3 As shown, the HEMT 2 includes a body trap region Tr1 generated in the barrier layer 7, an interface trap region Tr2 generated at the interface between the barrier layer 7 and the insulating layer 8, and a body trap region Tr3 generated in the insulating layer 8. The HEMT 2 including the second spacer layer 62 makes it possible to reduce the crystal defect level at the interface between the first spacer layer 61 and the barrier layer 7.

[0086] In addition, as the thickness of the spacer layer 6 including the first spacer layer 61 and the second spacer layer 62 increases, the surface morphology of the barrier layer 7 tends to deteriorate. At the same time, the excessively thin thickness of the spacer layer 6 makes it impossible to achieve the effect brought about by including the spacer layer 6, and alloy scattering is obviously exhibited. This reduces the carrier mobility.

[0087] Therefore, the thickness of the spacer layer 6 including the first spacer layer 61 and the second spacer layer 62 is formed to be equal to or less than 3nm. The thickness of the first spacer layer 61 is formed to be equal to or greater than 0.5nm, for example. In addition, the thickness of the second spacer layer 62 is formed to be smaller than the thickness of the first spacer layer 61.

[0088] (6) Configuration of barrier layer 7

[0089] like Figure 1 As shown, the barrier layer 7 includes a nitride semiconductor material having a band gap larger than that of the channel layer 5. The barrier layer 7 is formed using, for example, an epitaxial growth method.

[0090] like Figure 2 As shown, the barrier layer 7 comprises Al x3 In [1-x3] N(0<x3<1). The constituent element ratio x2 of the second spacer layer 62 and the constituent element ratio x3 of the barrier layer 7 each satisfy the following relational expression <3> .

[0091] x3>x2... <3>

[0092] like Figure 3As shown, the band gap of the barrier layer 7 including the nitride semiconductor material is narrower than the band gap of the first spacer layer 61 , and wider than the band gap of the second spacer layer 62 .

[0093] Furthermore, the barrier layer 7 may include undoped AlInN (u-AlInN) which is not doped with impurities. The barrier layer 7 including U-AlInN makes it possible to effectively suppress impurity scattering of carriers in the channel layer 5. This makes it possible to achieve high carrier mobility.

[0094] Furthermore, it is sufficient that the barrier layer 7 is a compound semiconductor material that allows carriers to be accumulated at the interface of the channel layer 5 adjacent to the first spacer layer 61 by the difference in the amount of polarization charge with the channel layer 5 to generate the two-dimensional electron gas 50. In the case where the channel layer 5 is a compound semiconductor material containing Al or In (not limited to GaN as described above), the barrier layer 7 may include, for example, Al 1-x-y In x Ga y N (0≤x<1, 0≤y<1, and x+y≤1) For example, AlInGaN can be formed using an epitaxial growth method.

[0095] The barrier layer 7 may also include undoped AlInGaN.

[0096] (7) Configuration of the main electrode 10

[0097] like Figure 1 As shown, the pair of corresponding main electrodes 10 are electrically coupled to one end and the other end of the channel layer 5. One of the pair of main electrodes 10 is used as a source electrode, and the other of the pair of main electrodes 10 is used as a drain electrode. In the first embodiment, the main electrodes 10 are both coupled to the channel layer 5, wherein the contact layer 11 is interposed between the main electrodes 10 and the channel layer 5.

[0098] The main electrodes 10 are each formed of, for example, a composite film in which Ti, Al, Ni, and Au are sequentially stacked.

[0099] It should be noted that the HEMT 2 may adopt a structure in which the main electrodes 10 are directly coupled to the channel layer 5 .

[0100] (8) Configuration of Contact Layer 11

[0101] like Figure 1 As shown, the contact layer 11 is interposed between the channel layer 5 and the corresponding main electrode 10 and is provided at the corresponding end of the channel layer 5. The contact layer 11 forms a portion of a current path between the pair of main electrodes 10. Here, the contact layer 11 includes GaN which is the same nitride semiconductor material as the nitride semiconductor material of the channel layer 5.

[0102] In addition, the contact layer 11 may include In which can be grown at a lower temperature than GaN. x Ga 1-x N(0≤x≤1).

[0103] In the method of manufacturing the HEMT 2, a selective mask in which a region for forming the main electrode 10 is opened is used to form the contact layer 11 on the channel layer 5 only in the region for forming the main electrode 10. At this time, the contact layer 11 is formed using an epitaxial growth method.

[0104] In addition, in the case of using growth conditions that achieve low selective growth characteristics, the contact layer 11 is first grown in the formation region of the main electrode 10 and on the selective mask. Thereafter, the selective mask and the contact layer 11 grown on the selective mask are removed. Therefore, the contact layer 11 is formed only in the formation region of the main electrode 10.

[0105] The contact layer 11 is doped with impurities at a high density to reduce the contact resistance with the main electrode 10, thereby forming an ohmic connection (ohmic contact). The HEMT 2 according to the first embodiment is of an n-channel conductivity type. Therefore, n-type impurities are used as impurities. For example, Si or Ge can be used as the n-type impurities. In addition, the impurity density of the contact layer 11 is set to, for example, 1×10 19 [atoms / cm -3 ]above.

[0106] (9) Configuration of Insulation Layer 8

[0107] like Figure 1 As shown, the insulating layer 8 is provided at the middle portion of the channel layer 5 between the pair of main electrodes 10. In addition, the insulating layer 8 is arranged on the barrier layer 7 between the barrier layer 7 and the gate electrode 9. It is sufficient that the insulating layer 8 is provided at least directly under the gate electrode 9.

[0108] The insulating layer 8 is a gate insulating film. The insulating layer 8 is insulated from the barrier layer 7 and the gate electrode 9. For the insulating layer 8, a material such as SiO2, which is a high dielectric constant material, can be used. 2 、Si 3 N 4 and HfO 2 At least one or more dielectric films of materials selected from the group consisting of:

[0109] (10) Arrangement of Gate Electrode 9

[0110] like Figure 1 As shown, the gate electrode 9 is provided on the insulating layer 8. For example, a composite film in which Ni and Au are sequentially stacked is used for the gate electrode 9.

[0111] [Current-voltage characteristics of HEMT 2]

[0112] Figure 4An example of the current-voltage characteristics of the HEMT 2 according to the first embodiment is shown. The horizontal axis indicates the gate voltage Vg [au]. The vertical axis indicates the drain current Id [au]. The symbol "▲" indicates the current-voltage characteristics in the early stage of driving the HEMT 2. The symbol "○" indicates the current-voltage characteristics after stress is applied to the HEMT 2.

[0113] also, Figure 5 An example of the current-voltage characteristics of the HEMT according to the comparative example is shown. The horizontal axis, the vertical axis, and the symbol indicate the current-voltage characteristics of the HEMT according to the comparative example. Figure 4 The horizontal axis, vertical axis and symbols shown are the same.

[0114] also, Figure 6 An example of the configuration of constituent elements of each semiconductor layer of the HEMT 2 according to the first embodiment and constituent elements of each semiconductor layer of the HEMT according to the comparative example is shown.

[0115] First, if Figure 6 As shown, the HEMT according to the comparative example is not provided with the second spacer layer 62. In the HEMT 2 of the first embodiment, the second spacer layer 62 is provided between the first spacer layer 61 and the barrier layer 7. That is, the HEMT according to the comparative example has a configuration in which the barrier layer 7 is directly provided on the first spacer layer 61.

[0116] like Figure 5 As shown, the HEMT according to the comparative example has a phenomenon in which the current-voltage characteristics after stress is applied are shifted to the high voltage side relative to the current-voltage characteristics in the early stage of driving.

[0117] Specifically, as the stress increases, the offset of the current-voltage characteristic increases. This increases the threshold voltage of the HEMT. It is speculated that one of the reasons is that, due to driving the HEMT, the carriers (electrons) transferred from the two-dimensional electron gas in the direction of the gate electrode are captured in the above Figure 3 In one of the body trap region Tr1, interface trap region Tr2 or body trap region Tr3 shown in FIG.

[0118] Unlike the HEMT according to the comparative example, the HEMT 2 according to the first embodiment includes a second spacer layer 62, such as Figures 1 to 3 and Figure 6 shown.

[0119] like Figure 4 As shown, the current-voltage characteristics after stress application are substantially unchanged relative to the current-voltage characteristics in the early stage of driving. That is, even if the stress increases, the threshold voltage of the HEMT 2 is constant. This results in no change in the threshold voltage.

[0120] Before being captured in the body trap region Tr1, the interface trap region Tr2 or the body trap region Tr3, the carriers (electrons) generated by driving the HEMT 2 and transferred from the two-dimensional electron gas 50 in the direction of the gate electrode 9 are captured by the energy potential generated by the second spacer layer 62 (see Figure 3 ).

[0121] Since the thickness of the first spacer layer 61 is small, the trapped carriers are transferred to the two-dimensional electron gas 50 side through the first spacer layer 61 by the tunnel effect.

[0122] Furthermore, in the first embodiment, one end and the other end of the second spacer layer 62 are disposed in contact with the contact layer 11. Therefore, driving the HEMT 2 allows trapped carriers to flow between the pair of main electrodes 10 to be removed.

[0123] [Function and Effect]

[0124] like Figures 1 to 3 and Figure 6 As shown, the HEMT 2 according to the first embodiment includes a channel layer 5 , a pair of main electrodes 10 , a barrier layer 7 , a gate electrode 9 , and a first spacer layer 61 .

[0125] The carriers flow through the channel layer 5. The pair of corresponding main electrodes 10 are coupled to one end and the other end of the channel layer 5. The barrier layer 7 is disposed on the channel layer 5 and induces the carriers. The gate electrode 9 is disposed in the middle portion of the channel layer 5, wherein the barrier layer 7 is interposed between the gate electrode 9 and the channel layer 5. The first spacer layer 61 is disposed between the channel layer 5 and the barrier layer 7 and reduces alloy scattering.

[0126] Here, the HEMT 2 further includes a second spacer layer 62. The second spacer layer 62 is disposed in a region overlapping the gate electrode 9 between the first spacer layer 61 and the barrier layer 7 and captures carriers. Figure 3 As shown, carriers are trapped in the second spacer layer 62 before being trapped in each of the body trap region Tr1 present in the blocking layer 7, the interface trap region Tr2 present at the interface between the blocking layer 7 and the insulating layer 8, and the body trap region Tr3 present in the insulating layer 8.

[0127] Such a configuration can effectively suppress or prevent carriers from being trapped in each of the body trap region Tr1, the interface trap region Tr2, and the body trap region Tr3 even when a high electric field or high temperature stress is repeatedly applied during driving. Figure 4 As shown, this configuration can effectively suppress or prevent fluctuations in the threshold voltage of the HEMT 2.

[0128] In addition, if Figure 3As shown, in the HEMT 2, the band gap of the second spacer layer 62 is narrower than the corresponding band gaps of the first spacer layer 61 and the barrier layer 7, and wider than the band gap of the channel layer 5. Such a configuration allows the second spacer layer 62 of the HEMT 2 to have a configuration that is formed toward the Fermi level E with respect to the energy potential of the first spacer layer 61 and the energy potential of the barrier layer. F The energy potential of a concave shape with side curvature.

[0129] This configuration makes it possible to easily construct a carrier trap region in the second spacer layer 62 before carriers are trapped in each of the body trap region Tr1, the interface trap region Tr2, and the body trap region Tr3. Therefore, as described above, fluctuations in the threshold voltage of the HEMT 2 can be effectively suppressed or prevented.

[0130] In addition, if Figure 1 , Figure 2 and Figure 6 As shown, the channel layer 5 of the HEMT 2 is a nitride semiconductor. Specifically, the channel layer 5 is GaN.

[0131] Therefore, a HEMT2 having high withstand voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration can be constructed.

[0132] In addition, if Figures 1 to 3 and Figure 6 As shown, the barrier layer 7 of the HEMT 2 is a nitride semiconductor having a band gap wider than that of the channel layer 5. For example, the barrier layer 7 is Al x3 In [1-x3] N(0<x3<1).

[0133] The first spacer layer 61 is a nitride semiconductor having a band gap wider than that of the channel layer 5. For example, the first spacer layer 61 is Al x1 In y1 Ga [1-x1-y1] N(0<x1<1, 0≤y1<1, and 0<x1+y1<1).

[0134] The second spacer layer 62 is a nitride semiconductor having a band gap narrower than that of the first spacer layer 61 and the barrier layer 7 and wider than that of the channel layer 5. For example, the second spacer layer 62 is Al x2 In y2 Ga [1-x2-y2] N(0<x2<1, 0<y2<1, and 0<x2+y2<1).

[0135] In addition, if Figure 2As shown, the Al composition distribution of the first spacer layer 61 has a maximum value and the Ga composition distribution has a minimum value in the thickness direction. On the other hand, the Al composition distribution of the second spacer layer 62 has a minimum value and the Ga composition distribution has a maximum value in the thickness direction.

[0136] Specifically, from the channel layer 5 to the first spacer layer 61, the Al composition ratio increases; from the first spacer layer 61 to the second spacer layer 62, the Al composition ratio decreases; and from the second spacer layer 62 to the barrier layer 7, the Al composition ratio increases. On the other hand, from the channel layer 5 to the first spacer layer 61, the Ga composition ratio decreases; from the first spacer layer 61 to the second spacer layer 62, the Ga composition ratio increases; from the second spacer layer 62 to the barrier layer 7, the Ga composition ratio decreases. From the second spacer layer 62 to the barrier layer 7, the In composition ratio increases.

[0137] This makes it possible to easily construct a carrier trap region by generating a concave energy potential for the second spacer layer 62. Therefore, as described above, fluctuations in the threshold voltage of the HEMT 2 can be effectively suppressed or prevented.

[0138] Furthermore, if Figures 1 to 3 As shown, in the HEMT 2, the thickness of the first spacer layer 61 is greater than the thickness of the second spacer layer 62. For example, the thickness of the first spacer layer 61 is equal to or greater than 0.5 nm.

[0139] Such a configuration can ensure a sufficient effect of the spacer layer 6, thereby effectively suppressing alloy scattering. Therefore, this configuration makes it possible to achieve high carrier mobility in the HEMT 2.

[0140] In addition, if Figure 3 As shown, when a positive bias is applied to the gate electrode 9, the conduction band E of the second spacer layer 62 in the HEMT 2 C Above the Fermi level E F and the conduction band E of the channel layer 5 C .

[0141] Therefore, when the HEMT 2 is driven, carriers trapped in the energy potential region generated in the second spacer layer 62 flow between the pair of main electrodes 10 to be removed. That is, fluctuation of the threshold voltage of the HEMT 2 can be effectively suppressed or prevented.

[0142] Furthermore, the HEMT 2 includes an insulating layer 8 between the barrier layer 7 and the gate electrode 9, such as Figure 1 The insulating layer 8 is used as a gate insulating film to construct a MIS field effect transistor.

[0143] Such a configuration enables the insulating layer 8 to effectively reduce leakage current between the barrier layer 7 and the gate electrode 9 in the HEMT 2. Furthermore, this configuration enables a high gate voltage to be applied to the main electrode 10 and the gate electrode 9 in the HEMT 2, thereby achieving a high withstand voltage.

[0144] Furthermore, the semiconductor device 1 according to the first embodiment includes the above-described HEMT 2. As described above, since fluctuations in the threshold voltage of the HEMT 2 can be effectively suppressed or prevented, the semiconductor device 1 having stable characteristics can be realized.

[0145] <2. Second Embodiment>

[0146] Reference Figure 7 The HEMT 2 according to the second embodiment of the present disclosure and the semiconductor device 1 including the HEMT 2 according to the second embodiment of the present disclosure are described.

[0147] Note that, in the second embodiment and the embodiments described hereinafter, the same components or substantially the same components as those of the first embodiment are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0148] [Configuration of HEMT 2 and Semiconductor Device 1]

[0149] Figure 7 An example of a longitudinal cross-sectional structure of a main portion of the HEMT 2 and the semiconductor device 1 according to the second embodiment is shown.

[0150] like Figure 7 As shown, the HEMT 2 according to the second embodiment includes a Schottky junction GaN HEMT (Schottky junction field effect transistor). That is, the gate electrode 9 is directly bonded to the barrier layer 7 without the insulating layer 8 being provided therebetween. The gate electrode 9 includes a Schottky junction material.

[0151] Components other than those described above are the same as those of the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0152] [Function and Effect]

[0153] The HEMT 2 and the semiconductor device 1 according to the second embodiment make it possible to achieve actions and effects similar to those achievable by the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0154] <3. Third Embodiment>

[0155] Reference Figure 8The HEMT 2 according to the third embodiment of the present disclosure and the semiconductor device 1 including the HEMT 2 according to the third embodiment of the present disclosure are described.

[0156] [Configuration of HEMT 2 and Semiconductor Device 1]

[0157] Figure 8 An example of the configuration of main parts of the HEMT 2 and the semiconductor device 1 according to the third embodiment is shown.

[0158] like Figure 8 As shown, the channel layer 5 of the HEMT 2 according to the third embodiment includes AlGaInN having a low Al composition. The band gap of the channel layer 5 is, for example, 3.4 [eV] or more and 3.6 [eV] or less.

[0159] The first spacer layer 61 includes AlGaInN having a high Al composition. The second spacer layer 62 includes AlGaInN having a medium Al composition.

[0160] Furthermore, the barrier layer 7 includes AlGaInN having a high Al composition.

[0161] Components other than those described above are the same as those of the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0162] [Function and Effect]

[0163] The HEMT 2 and the semiconductor device 1 according to the third embodiment make it possible to achieve actions and effects similar to those achievable by the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0164] Furthermore, the channel layer 5, the first spacer layer 61, the second spacer layer 62, and the barrier layer 7 of the HEMT 2 each include similar AlGaInN, in which only the Al composition ratio is appropriately changed. Such a configuration makes it possible to easily construct the HEMT 2 and the semiconductor device 1.

[0165] <4. Fourth Embodiment>

[0166] Reference Fig. 9 The HEMT 2 according to the fourth embodiment of the present disclosure and the semiconductor device 1 including the HEMT 2 according to the fourth embodiment of the present disclosure are described.

[0167] [Configuration of HEMT 2 and Semiconductor Device 1]

[0168] Fig. 9 An example of the configuration of main parts of the HEMT 2 and the semiconductor device 1 according to the fourth embodiment is shown.

[0169] like Fig. 9 As shown, the channel layer 5 of the HEMT 2 according to the fourth embodiment includes β-Ga 2 O 3 The band gap of the channel layer 5 is, for example, 4.9 [eV].

[0170] The first spacer layer 61 includes N-pole AlGaInN. The AlGaInN of the spacer layer 6 has a high Al composition. The second spacer layer 62 includes N-pole AlGaInN. The AlGaInN of the second spacer layer 62 has a medium Al composition.

[0171] Furthermore, the barrier layer 7 includes AlN.

[0172] Components other than those described above are the same as those of the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0173] [Function and Effect]

[0174] The HEMT 2 and the semiconductor device 1 according to the fourth embodiment make it possible to achieve actions and effects similar to those achievable by the HEMT 2 and the semiconductor device 1 according to the first embodiment.

[0175] <5. Fifth embodiment>

[0176] Reference Fig.10 A semiconductor module 100 according to a fifth embodiment of the present disclosure is described. The semiconductor module 100 constitutes, for example, a wireless communication terminal.

[0177] [Configuration of Semiconductor Module 100]

[0178] Fig.10 An example of a schematic structure of a semiconductor module 100 according to a fifth embodiment is shown.

[0179] The semiconductor module 100 according to the fifth embodiment is, for example, an antenna integrated module including an edge antenna 101 and a front end portion. The edge antenna 101 and the front end portion arranged in an array are mounted on a substrate 110 as a module. The front end portion includes a switch 102, a low noise amplifier 103, a bandpass filter 104, a power amplifier 105, etc. The switch 102 is a high-frequency switching circuit. For example, the semiconductor module 100 can be used as a wireless communication terminal such as a communication transceiver.

[0180] The semiconductor module 100 includes, for example, a semiconductor device 1 on which the HEMT 2 according to any one of the first to fourth embodiments is mounted as a transistor configuring a switch 102 , a low-noise amplifier 103 , or a power amplifier 105 .

[0181] [Function and Effect]

[0182] The semiconductor module 100 according to the fifth embodiment includes the semiconductor device 1 on which the HEMT 2 is mounted, so that higher speed, higher efficiency, and lower power consumption of wireless communication can be achieved.

[0183] <6. Sixth Implementation>

[0184] Reference Fig.11 The wireless communication terminal 200 as the electronic device according to the sixth embodiment of the present disclosure is described.

[0185] [Configuration of Wireless Communication Terminal 200]

[0186] Fig.11 An example of a schematic block configuration of the wireless communication terminal 200 according to the sixth embodiment is shown.

[0187] The wireless communication terminal 200 according to the sixth embodiment includes an antenna ANT, an antenna switch circuit 201, a high power amplifier (HPA) 202, a radio frequency integrated circuit (RFIC: radio frequency integrated circuit) 203, a baseband unit (BB) 204, an audio output unit (MIC) 205, a data output unit DT and an interface unit I / F. The interface unit I / F includes, for example, a wireless LAN (W-LAN: wireless local area network), Bluetooth (registered trademark, Bluetooth (registered trademark)). The wireless communication terminal 200 is, for example, a mobile phone system having multiple functions such as voice and data communication or LAN connection.

[0188] The wireless communication terminal 200 includes the semiconductor device 1 mounted with the HEMT 2 according to any one of the first to fourth embodiments as a transistor configuring the antenna switch circuit 201 , the high power amplifier 202 , the RF IC 203 , or the baseband unit 204 .

[0189] [Function and Effect]

[0190] The wireless communication terminal 200 according to the sixth embodiment includes the semiconductor device 1 mounted with the HEMT 2, so that higher speed, higher efficiency and lower power consumption of wireless communication can be achieved. Therefore, in the case where the wireless communication terminal 200 is a portable communication terminal, the wireless communication terminal 200 can further extend the operating time, thereby further improving portability.

[0191] <7. Other Implementation Methods>

[0192] The present technology is not limited to the above-described embodiments and may be modified in various ways without departing from the gist thereof.

[0193] For example, two or more of the HEMTs and semiconductor devices according to the above-described first to sixth embodiments may be combined.

[0194] A HEMT according to a first embodiment of the present disclosure includes a channel layer, a pair of main electrodes, a barrier layer, a gate electrode, and a first spacer layer.

[0195] Carriers flow through the carrier layer. The pair of corresponding main electrodes are coupled to one end and the other end of the channel layer. The barrier layer is disposed in the channel layer and induces carriers. The gate electrode is disposed in the middle portion of the channel layer, wherein the barrier layer is between the gate electrode and the channel layer. The first spacer layer is disposed between the channel layer and the barrier layer and reduces alloy scattering.

[0196] Here, the HEMT further includes a second spacer layer. The second spacer layer is provided in a region overlapping with the gate electrode between the first spacer layer and the barrier layer and captures carriers. The carriers are captured in the second spacer layer before being captured in a body trap region or the like present in the barrier layer. Such a configuration makes it possible to effectively suppress or prevent fluctuations in the threshold voltage of the HEMT.

[0197] Furthermore, a semiconductor device according to a second embodiment of the present disclosure includes the HEMT according to the first embodiment.

[0198] Therefore, a semiconductor device including a HEMT capable of effectively suppressing or preventing fluctuation in threshold voltage can be realized.

[0199] <Configuration of this technology>

[0200] The present technology has the following configuration. According to the present technology configured below, fluctuation of the threshold voltage of a high electron mobility transistor (HEMT) in a high electron mobility transistor, a semiconductor device, a high frequency switching circuit, a power amplifier, and a wireless communication terminal can be effectively suppressed or prevented. (1)

[0202] A high electron mobility transistor, comprising:

[0203] a channel layer through which carriers flow;

[0204] a pair of corresponding main electrodes coupled to one end and the other end of the channel layer;

[0205] a barrier layer disposed on the channel layer and inducing carriers;

[0206] A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer;

[0207] a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and

[0208] The second spacer layer is disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and captures carriers. (2)

[0210] The high electron mobility transistor according to (1), wherein the band gap of the second spacer layer is narrower than the band gap of the first spacer layer and the band gap of the barrier layer and is wider than the band gap of the channel layer. (3)

[0212] The high electron mobility transistor according to (2), wherein the second spacer layer has an energy potential formed in a concave shape curved toward the Fermi level side with respect to the energy potential of the first spacer layer and the energy potential of the barrier layer. (4)

[0214] The high electron mobility transistor according to any one of (1) to (3), wherein the channel layer is a nitride semiconductor. (5)

[0216] The high electron mobility transistor according to any one of (1) to (4), wherein the channel layer is GaN. (6)

[0218] The high electron mobility transistor according to (5), wherein the barrier layer is a nitride semiconductor having a band gap wider than a band gap of the channel layer. (7)

[0220] The high electron mobility transistor according to (6), wherein the barrier layer is Al x3 In [1-x3] N, where 0<x3<1 is satisfied. (8)

[0222] The high electron mobility transistor according to (7), wherein the first spacer layer is a nitride semiconductor having a band gap wider than a band gap of the channel layer. (9)

[0224] The high electron mobility transistor according to (8), wherein the first spacer layer is Al x1 In y1 Ga [1-x1-y1] N, wherein 0<x1<1, 0≤y1<1 and 0<x1+y1<1 are satisfied. (10)

[0226] The high electron mobility transistor according to (9), wherein the second spacer layer is a nitride semiconductor having a band gap narrower than a band gap of the first spacer layer and a band gap of the barrier layer and wider than a band gap of the channel layer. (11)

[0228] The high electron mobility transistor according to (10), wherein the second spacer layer is Al x2 In y2 Ga [1-x2-y2] N, wherein 0<x2<1, 0<y2<1 and 0<x2+y2<1 are satisfied. (12)

[0230] The high electron mobility transistor according to (11), wherein the Al composition distribution of the first spacer layer has a maximum value in the thickness direction and the Ga composition distribution has a minimum value in the thickness direction. (13)

[0232] The high electron mobility transistor according to (11) or (12), wherein the Al composition distribution of the second spacer layer has a minimum value in the thickness direction and the Ga composition distribution has a maximum value in the thickness direction. (14)

[0234] A high electron mobility transistor according to (13), wherein:

[0235] From the channel layer to the first spacer layer, the Al composition ratio increases;

[0236] The Al composition ratio decreases from the first spacer layer to the second spacer layer; and

[0237] The Al composition ratio increases from the second spacer layer to the barrier layer. (15)

[0239] A high electron mobility transistor according to (14), wherein

[0240] From the channel layer to the first spacer layer, the Ga composition ratio decreases;

[0241] The Ga composition ratio increases from the first spacer layer to the second spacer layer; and

[0242] The Ga composition ratio decreases from the second spacer layer to the barrier layer. (16)

[0244] The high electron mobility transistor according to (15), wherein the In composition ratio increases from the second spacer layer to the barrier layer. (17)

[0246] The high electron mobility transistor according to any one of (1) to (16), wherein a thickness of the first spacer layer is greater than a thickness of the second spacer layer. (18)

[0248] The high electron mobility transistor according to any one of (1) to (17), wherein a thickness of the first spacer layer is equal to or greater than 0.5 nm. (19)

[0250] A high electron mobility transistor according to any one of (1) to (18), (22) and (23), wherein, in a state where a positive bias is applied to the gate electrode, a conduction band of the second spacer layer is higher than a Fermi level and a conduction band of the channel layer. (20)

[0252] A semiconductor device comprising a high electron mobility transistor, wherein:

[0253] High Electron Mobility Transistors include:

[0254] The channel layer through which the carriers flow,

[0255] a pair of corresponding main electrodes coupled to one end and the other end of the channel layer;

[0256] a barrier layer disposed on the channel layer and inducing carriers;

[0257] A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer;

[0258] a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and

[0259] The second spacer layer is disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and captures carriers. (twenty one)

[0261] The high electron mobility transistor according to any one of (1) to (19), further comprising an insulating layer arranged between the blocking layer and the gate electrode, wherein

[0262] High electron mobility transistors include insulated gate field effect transistors. (twenty two)

[0264] The high electron mobility transistor according to any one of (1) to (19), wherein

[0265] The gate electrode is coupled to the barrier layer through a Schottky junction, and

[0266] High electron mobility transistors include Schottky junction field effect transistors. (twenty three)

[0268] A high frequency switching circuit comprising a high electron mobility transistor, wherein:

[0269] High Electron Mobility Transistors include:

[0270] a channel layer through which carriers flow;

[0271] a pair of corresponding main electrodes coupled to one end and the other end of the channel layer;

[0272] a barrier layer disposed on the channel layer and inducing carriers;

[0273] A gate electrode is arranged in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer;

[0274] a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and

[0275] The second spacer layer is disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and captures carriers. (twenty four)

[0277] A power amplifier comprising a high electron mobility transistor, wherein:

[0278] High Electron Mobility Transistors include:

[0279] a channel layer through which carriers flow;

[0280] a pair of corresponding main electrodes coupled to one end and the other end of the channel layer;

[0281] a barrier layer disposed on the channel layer and inducing carriers;

[0282] A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer;

[0283] a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and

[0284] The second spacer layer is disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and captures carriers.

[0285] (25) A wireless communication terminal, comprising a high electron mobility transistor, wherein:

[0286] High Electron Mobility Transistors include:

[0287] a channel layer through which carriers flow;

[0288] a pair of corresponding main electrodes coupled to one end and the other end of the channel layer;

[0289] a barrier layer disposed on the channel layer and inducing carriers;

[0290] A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer;

[0291] a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and

[0292] The second spacer layer is disposed in a region overlapping the gate electrode between the first spacer layer and the barrier layer and captures carriers.

[0293] This application claims the benefit of Japanese Priority Patent Application No. 2022-084836 filed in the Japan Patent Office on May 24, 2022, the entire contents of which are incorporated herein by reference.

[0294] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A high electron mobility transistor, comprising: a channel layer through which carriers flow; a pair of corresponding main electrodes coupled to one end and the other end of the channel layer; A blocking layer, disposed on the channel layer and inducing the carriers; A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer; a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and A second spacer layer is provided in a region between the first spacer layer and the barrier layer and overlapping the gate electrode and captures the carriers.

2. The high electron mobility transistor according to claim 1, wherein: The band gap of the second spacer layer is narrower than the band gap of the first spacer layer and the band gap of the barrier layer and is wider than the band gap of the channel layer.

3. The high electron mobility transistor according to claim 2, wherein: The second spacer layer has an energy potential formed in a concave shape curved toward the Fermi level side with respect to the energy potential of the first spacer layer and the energy potential of the barrier layer.

4. The high electron mobility transistor according to claim 1, wherein: The channel layer is a nitride semiconductor.

5. The high electron mobility transistor according to claim 4, wherein: The channel layer is GaN.

6. The high electron mobility transistor according to claim 5, wherein: The barrier layer is a nitride semiconductor having a band gap wider than a band gap of the channel layer.

7. The high electron mobility transistor according to claim 6, wherein: The barrier layer is Al x3 In [1-x3] N, where 0<x3<1 is satisfied.

8. The high electron mobility transistor according to claim 7, wherein: The first spacer layer is a nitride semiconductor having a band gap wider than a band gap of the channel layer.

9. The high electron mobility transistor according to claim 8, wherein: The first spacer layer is Al x1 In y1 Ga [1-x1-y1] N, wherein 0<x1<1, 0≤y1<1 and 0<x1+y1<1 are satisfied.

10. The high electron mobility transistor according to claim 9, wherein: The second spacer layer is a nitride semiconductor having a band gap narrower than the band gap of the first spacer layer and the band gap of the barrier layer and wider than the band gap of the channel layer.

11. The high electron mobility transistor according to claim 10, wherein: The second spacer layer is Al x2 In y2 Ga [1-x2-y2] N, wherein 0<x2<1, 0<y2<1 and 0<x2+y2<1 are satisfied.

12. The high electron mobility transistor according to claim 11, wherein: The Al composition distribution of the first spacer layer has a maximum value in a thickness direction and the Ga composition distribution has a minimum value in the thickness direction.

13. The high electron mobility transistor according to claim 12, wherein: The second spacer layer has an Al composition distribution having a minimum value in the thickness direction and a Ga composition distribution having a maximum value in the thickness direction.

14. The high electron mobility transistor according to claim 13, wherein: The Al composition ratio increases from the channel layer to the first spacer layer; The Al composition ratio decreases from the first spacer layer to the second spacer layer; and The Al composition ratio increases from the second spacer layer to the barrier layer.

15. The high electron mobility transistor according to claim 14, wherein: The Ga composition ratio decreases from the channel layer to the first spacer layer; The Ga composition ratio increases from the first spacer layer to the second spacer layer; and The Ga composition ratio decreases from the second spacer layer to the barrier layer.

16. The high electron mobility transistor according to claim 15, wherein: The In composition ratio increases from the second spacer layer to the barrier layer.

17. The high electron mobility transistor according to claim 1, wherein: The thickness of the first spacer layer is greater than that of the second spacer layer.

18. The high electron mobility transistor according to claim 17, wherein: The thickness of the first spacer layer is equal to or greater than 0.5 nm.

19. The high electron mobility transistor according to claim 1, wherein: In a state where a positive bias is applied to the gate electrode, a conduction band of the second spacer layer is higher than a Fermi level and a conduction band of the channel layer.

20. A semiconductor device comprising a high electron mobility transistor, wherein: The high electron mobility transistor comprises: a channel layer through which carriers flow; a pair of corresponding main electrodes coupled to one end and the other end of the channel layer; A blocking layer, disposed on the channel layer and inducing the carriers; A gate electrode is disposed in a middle portion of the channel layer, wherein the barrier layer is interposed between the gate electrode and the channel layer; a first spacer layer disposed between the channel layer and the barrier layer and reducing alloy scattering; and A second spacer layer is provided in a region between the first spacer layer and the barrier layer and overlapping the gate electrode and captures the carriers.

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