Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device (100) is provided with: a semiconductor substrate (10) which has an active section (120) in which transistor sections (70) and diode sections (80) are alternately provided, and which is provided with a plurality of trench sections (30, 40) extending in the direction in which the transistor sections and the diode sections extend; an emitter electrode (52) provided above the front surface of the semiconductor substrate; and a polyimide protective film (150) provided on the upper surface of the emitter electrode, the diode portion having a lifetime control region (85) containing a lifetime inhibitor irradiated from the front surface side of the semiconductor substrate. The active portion has a protective region (151-1) provided with the protective film, and a non-protective region (152-2) not provided with the protective film, the diode portion is included in the non-protective region, and the protective region is included in the transistor portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, the following technology is known: in a semiconductor device in which a transistor portion such as an insulated gate bipolar transistor (IGBT) and a diode portion are formed on the same substrate, a particle beam such as helium ions is irradiated to a predetermined depth position of the semiconductor substrate to provide a lifetime control region including a lifetime inhibitor (for example, Patent Document 1). In addition, there is a semiconductor device in which a protective film made of a polyimide resin formed in a cross-shaped pattern is provided on the surface of an element electrode made of an aluminum thin film (for example, Patent Document 2).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2017-135339 Patent Document 2: Japanese Patent Application Publication No. 2009-38140 Summary of the invention

[0004] Technical issues When light ions such as helium ions are irradiated from the front surface side of the semiconductor substrate, the range of the light ions in the semiconductor substrate differs depending on the presence or absence of polyimide.

[0005] Technical Solution In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having an active portion in which a transistor portion and a diode portion are alternately provided, and having a plurality of groove portions extending along the extending directions of the transistor portion and the diode portion; an emitter electrode provided above the front surface of the semiconductor substrate; and a protective film of polyimide provided on the upper surface of the emitter electrode, wherein the diode portion has a lifetime control region, the lifetime control region contains a lifetime inhibitor irradiated from the front side of the semiconductor substrate, the active portion has a protection region provided with the protective film, and a non-protection region not provided with the protective film, the diode portion is included in the non-protection region, and the protection region is included in the transistor portion.

[0006] The width of the transistor portion in the trench arrangement direction may be greater than or equal to 300 μm and less than or equal to 2000 μm.

[0007] The width of the diode portion in the trench arrangement direction may be greater than or equal to 200 μm and less than or equal to 2000 μm.

[0008] In the groove arrangement direction, the width of the protection zone may be greater than or equal to 100 μm and less than or equal to 1800 μm.

[0009] In the trench arrangement direction, the distance between the protection area and the diode portion may be greater than the thickness of the semiconductor substrate.

[0010] The lifetime control region can be arranged in a manner extending from the diode portion to at least a portion of the transistor portion in the groove arrangement direction, and in the groove arrangement direction, the distance that the lifetime control region extends in the transistor portion can be greater than 80% and less than 250% of the thickness of the semiconductor substrate.

[0011] The semiconductor substrate may have a thickness of 50 μm or more and 150 μm or less.

[0012] The lifetime control region may be provided only in the non-protection region, and in the groove arrangement direction, the distance between the protection region and the lifetime control region may be greater than 20 μm and less than 1800 μm.

[0013] The semiconductor device may further include a first plated portion and a second plated portion, wherein the first plated portion and the second plated portion are arranged on the upper surface of the emitter electrode, and the protective film is sandwiched between the first plated portion and the second plated portion. The emitter electrode may be extended below the protective film, the first plated portion and the second plated portion.

[0014] The protective film may include a first protective film and a second protective film sandwiching the first plated portion, and the thickness of the first protective film and the second protective film may be greater than the thickness of the first plated portion.

[0015] The non-protection zone may include a first non-protection zone and a second non-protection zone, and the protection zone may be sandwiched between the first non-protection zone and the second non-protection zone.

[0016] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes: forming an active portion on a semiconductor substrate, the active portion alternately provided with a transistor portion and a diode portion; forming a plurality of groove portions on the semiconductor substrate, the plurality of groove portions extending along the extension direction of the transistor portion and the diode portion; forming an emitter electrode above the front surface of the semiconductor substrate; forming a protective film of polyimide on the upper surface of the emitter electrode; and irradiating a lifetime inhibitor from the front side of the semiconductor substrate in the diode portion to form a lifetime control region, the active portion having a protection region provided with the protective film and a non-protection region not provided with the protective film when viewed from above, the diode portion being included in the non-protection region, and the protection region being included in the transistor portion.

[0017] The lifetime inhibitor may be irradiated via a resist disposed above the protective film, and a width of the resist may be greater than a width of the protective film in a trench arrangement direction.

[0018] The resist may be configured to cover at least the entire protective film in a plan view.

[0019] In the trench arrangement direction, a distance between an end portion of the resist and an end portion of the protective film may be greater than or equal to 0 μm and less than or equal to 1800 μm.

[0020] The resist may be arranged in the transistor portion in a manner separated from the diode portion, and in the trench arrangement direction, a distance between the diode portion and the resist may be greater than 80% and less than 250% of the thickness of the semiconductor substrate.

[0021] In the trench arrangement direction, the distance between the diode portion and the protection zone may be greater than the thickness of the semiconductor substrate.

[0022] The semiconductor substrate may have a thickness of 50 μm or more and 150 μm or less.

[0023] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 An example of the arrangement of the components on the front side of the semiconductor device 100 according to the embodiment is shown.

[0025] Figure 2 An example of the arrangement of the emitter electrode 52 provided on the front surface of the semiconductor device 100 is shown.

[0026] Figure 3 An example of the arrangement of the protective film 150 provided on the front surface of the semiconductor device 100 is shown.

[0027] Figure 4 Show Figure 3 An example of the a-a' cross section.

[0028] Figure 5 An example of a top view of the semiconductor device 100 is shown.

[0029] Figure 6 The structure of the front surface of the semiconductor substrate 10 in the vicinity of the protection zone 151 - 1 is schematically shown.

[0030] Figure 7 Show Figure 6 An example of the b-b' cross section.

[0031] Figure 8 An example of a method for manufacturing the semiconductor device 100 is shown.

[0032] Explanation of symbols 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 18…drift region, 20…buffer region, 21…front surface, 22…collector region, 23…back surface, 24…collector electrode, 25…connection portion, 29…extension portion, 30…dummy groove portion, 31…connection portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 39…extension portion, 40…gate groove portion, 41…connection portion, 42…gate insulating film, 44…gate conductive portion, 48…gate metal layer, 49…contact hole, 50…gate pad, 52…emitter electrode, 54…contact hole, 55…contact hole, 56…contact hole, 70…transistor portion, 80…diode portion, 82…cathode region, 85…lifetime control region, 90…separation portion, 100…semiconductor device, 102…end edge, 110…current sensing portion, 120…active portion, 130…well region, 150…protective film, 151…protection area, 152…non-protection area, 153…opening portion, 154…opening portion, 161…plating portion, 172…current sensing pad, 174…anode pad, 176…cathode pad, 178…temperature sensing portion, 180…anode wiring, 182…cathode wiring, 190…resist, 210…bidirectional diode portion, 220…output comparison diode portion. DETAILED DESCRIPTION

[0033] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention.

[0034] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "front" or "upper", and the other side is referred to as "back" or "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "front", "upper", "back", and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0035] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z-axis and the -Z-axis. In addition, in this specification, the situation of observing from the +Z-axis direction is sometimes referred to as a bird's-eye view.

[0036] In this specification, when it is said that they are “same” or “equal”, it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0037] In this specification, the conductivity type of the doping region doped with impurities is set to P type or N type for description. However, the conductivity type of each doping region can also be opposite to each other. In addition, in this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0038] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes set to the concentration of the larger one of the donors or acceptors. This concentration difference can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by the spreading resistance measurement (SR) can be used as the concentration of the donor or acceptor. In addition, in the case where the concentration distribution of the donor or acceptor has a peak, the peak value can be used as the concentration of the donor or acceptor in the region. In the case where the concentration of the donor or acceptor in the region where the donor or acceptor exists is roughly uniform, the average value of the donor concentration or acceptor concentration in the region can be used as the donor concentration or acceptor concentration.

[0039] Figure 1 An example of the arrangement of the components on the front side of the semiconductor device 100 of the embodiment is shown. The semiconductor device 100 includes a semiconductor substrate 10, a gate pad 50, a current sensing pad 172, a temperature sensing portion 178, an anode pad 174 and a cathode pad 176 electrically connected to the temperature sensing portion 178, a bidirectional diode portion 210, and an output comparison diode portion 220. The region where the current sensing pad 172, the anode pad 174, the cathode pad 176, the bidirectional diode portion 210, and the output comparison diode portion 220 are provided is sometimes collectively referred to as a pad region.

[0040] The semiconductor substrate 10 has an edge 102. In this specification, Figure 1The direction of one end side 102-1 of the semiconductor substrate 10 in a top view is set as the X-axis, and the direction perpendicular to the X-axis is set as the Y-axis. In this example, the X-axis is taken as the direction of the end side 102-1. In addition, the direction perpendicular to the X-axis direction and the Y-axis direction and in a right-hand system is called the Z-axis direction. The temperature sensing portion 178 of this example is set along the +Z-axis direction of the semiconductor substrate 10.

[0041] The semiconductor substrate 10 is provided by a semiconductor material such as silicon or a compound semiconductor. In the semiconductor substrate 10, the side provided with the temperature sensing portion 178 is referred to as the front side, and the surface on the opposite side is referred to as the back side. In this specification, the direction connecting the front side and the back side of the semiconductor substrate 10 is referred to as the depth direction. The semiconductor substrate 10 of this example has a substantially rectangular shape on the front side, but may have a different shape.

[0042] The semiconductor substrate 10 has an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the front surface and the back surface of the semiconductor substrate 10 when the semiconductor device 100 is turned on. A gate conductive portion 44 of the active portion 120, which will be described later, is electrically connected to a gate pad 50 via a gate wiring portion, which will be described later.

[0043] The active portion 120 may be configured to be divided into the active portion 120-1 and the active portion 120-2 when viewed from above. The active portion 120-1 and the active portion 120-2 of this example are separated in the Y-axis direction by a separation portion 90 that passes through the center Ac of the front surface of the semiconductor substrate 10 and extends in the Y-axis direction. Here, the center Ac of the active portion 120 refers to the geometric center of gravity of the active portion 120 when viewed from above. The active portion 120-1 and the active portion 120-2 may be provided with a pad region sandwiched therebetween.

[0044] The active portion 120 includes a transistor portion 70 including a transistor element such as an IGBT (insulated gate bipolar transistor) and a diode portion 80 including a diode element such as a FWD (freewheeling diode). The transistor portion 70 and the diode portion 80 form a RC-IGBT (Reverse Conducting IGBT).

[0045] exist Figure 1 In the active portion 120, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". The transistor portion 70 and the diode portion 80 of this example are arranged alternately along the X-axis direction in each region of the active portion 120. In the X-axis direction, the width of the transistor portion 70 is greater than or equal to 300 μm and less than or equal to 2000 μm, and the width of the diode portion 80 is greater than or equal to 200 μm and less than or equal to 2000 μm.

[0046] The semiconductor device 100 has an edge termination structure on the front side between the outer periphery of the active portion 120 and the edge 102. The edge termination structure includes, for example, a guard ring provided in an annular shape surrounding the active portion 120, a field plate, or a combination thereof.

[0047] The temperature sensing portion 178 may be disposed in the separation portion 90. The active portion 120 is not provided in the separation portion 90. If the active portion 120 of the semiconductor substrate 10 is integrated, the central portion of the semiconductor substrate 10 is easily heated by the heat generated by the switching element formed in the active portion 120. By providing the temperature sensing portion 178 in the separation portion 90 near the center, the temperature of the transistor portion 70 can be monitored. Thus, the transistor portion 70 can be prevented from being overheated by exceeding the junction temperature that is the normal operating temperature range.

[0048] The temperature sensing portion 178 may be provided by a temperature sensing diode. As an example, the temperature sensing portion 178 may be provided by a Schottky diode. Alternatively, the temperature sensing portion 178 may be provided by a PN junction diode formed of polysilicon provided above the semiconductor substrate 10 via an insulating film.

[0049] Anode wiring 180 and cathode wiring 182 made of metal are connected to the anode and cathode of the temperature sensing diode, respectively. Anode wiring 180 and cathode wiring 182 are wirings containing metal such as aluminum. Anode wiring 180 and cathode wiring 182 are examples of temperature sensing wirings. Anode wiring 180 and cathode wiring 182 are provided to extend in separation portion 90.

[0050] Cathode pad 176 is connected to temperature sensing unit 178 via cathode wiring 182. Anode pad 174 is connected to temperature sensing unit 178 via anode wiring 180. Cathode pad 176 and anode pad 174 are electrodes containing metal such as aluminum.

[0051] The current sensing pad 172 is electrically connected to the current sensing unit 110. The current sensing pad 172 is an example of a front electrode. The current sensing unit 110 has the same structure as the transistor unit 70 of the active unit 120, and simulates the operation of the transistor unit 70. A current proportional to the current flowing in the transistor unit 70 flows through the current sensing unit 110. Thus, the current flowing in the transistor unit 70 can be monitored.

[0052] It should be noted that unlike the transistor section 70, the emitter region 12 described later is not provided in the current sensing section 110. That is, the current sensing section 110 does not operate as a transistor. A gate trench section is provided in the current sensing section 110. The gate trench section of the current sensing section 110 is electrically connected to the gate wiring section.

[0053] The bidirectional diode unit 210 is disposed between the anode pad 174 and the cathode pad 176 on the front side of the semiconductor device 100. The bidirectional diode unit 210 includes a diode electrically connected in bidirectional series between the anode pad 174 and the cathode pad 176. The bidirectional diode unit 210 prevents the temperature sensing unit 178 from being damaged by electrostatic discharge (ESD).

[0054] The output comparison diode section 220 is provided between the anode pad 174 and the cathode pad 176. The output comparison diode section 220 is electrically connected to the anode pad 174 and the cathode pad 176. The output comparison diode section 220 includes an output comparison diode having a direction of a PN junction connected in reverse parallel with respect to the direction of a PN junction of the temperature sensing diode of the temperature sensing section 178.

[0055] The output comparison diode of the output comparison diode section 220 may have the same design as the diode of the temperature sensing section 178 except for the direction of the PN junction. When the semiconductor device 100 is operating, no current is conducted in the output comparison diode section 220. The output comparison operation is performed for each predetermined cycle. When the output comparison operation is performed, current is conducted in the output comparison diode section 220. Through the output comparison operation, the replacement period of the temperature sensing diode of the temperature sensing section 178 can be grasped.

[0056] A protection diode having the same forward direction as the output comparison diode 220 may be provided in parallel with the output comparison diode 220. When the temperature sensor 178 operates, the protection diode prevents an overvoltage from being applied to the temperature sensor 178 or an overcurrent from flowing due to noise or the like.

[0057] Figure 2 An example of the configuration of the emitter electrode 52 provided on the front surface of the semiconductor device 100 is shown. The emitter electrode 52 is provided by a metal conductor such as aluminum. The emitter electrode 52 of this example is set to an emitter potential which is a predetermined reference potential. Alternatively, the emitter potential may be set to a ground potential.

[0058] The emitter electrode 52 is formed of a conductive material containing a metal. For example, the emitter electrode 52 is formed of aluminum or an alloy having aluminum as a main component (such as aluminum-silicon, aluminum-silicon-copper alloy). The emitter electrode 52 is an example of a front electrode similar to the current sensing pad 172. Each electrode may have a barrier metal formed of titanium or a titanium compound or the like in a lower layer of a region formed of aluminum or the like.

[0059] exist Figure 2, the emitter electrode 52 is arranged in the region with oblique hatching. The emitter electrode 52 is not provided above the separation portion 90 that separates the active portion 120-1 and the active portion 120-2 from each other in the Y-axis direction. Similarly, the emitter electrode 52 is not provided above the pad region.

[0060] Figure 3 FIG. 1 shows an example of the configuration of the protective film 150 provided above the front surface of the semiconductor device 100. The protective film 150 of this example is formed of polyimide. Figure 3 In FIG. 5 , the outline of the region where the protective film 150 is disposed is shown by a dotted line and is hatched obliquely. The protective film 150 may be in contact with the upper surface of the emitter electrode 52 .

[0061] The protective film 150 of this example includes a protective film 150-1 covering the area where the gate pad 50 is provided, and a protective film 150-2 covering the pad area. The protective film 150-1 may have an opening that exposes a portion of the upper surface of the gate pad 50. In addition, the protective film 150-1 may also have an opening 153 that exposes a portion of the upper surface of the current sensing pad 172, and an opening 154 that exposes a portion of the upper surface of the anode pad 174 and the cathode pad 176. Thus, a wire or the like can be connected to the upper surface of the gate pad 50. In addition, similarly, a wire or the like can also be connected to the upper surfaces of the current sensing pad 172, the anode pad 174, and the cathode pad 176.

[0062] The protective film 150 may further include a protective film 150-3 provided between the outer periphery of the active portion 120 and the edge 102 (edges 102-1 to 102-4), and a protective film 150-4 covering the separation portion 90. That is, the emitter electrode 52 is divided into two regions surrounded by the protective films 150-1, 150-2, 150-3, and 150-4.

[0063] The protective film 150 of this example further includes a protective film 150-5 and a protective film 150-6 extending along the Y-axis direction on the upper surface of the emitter electrode 52. Figure 3 In the Y-axis direction, the protective film 150 - 5 is sandwiched between the protective film 150 - 2 and the protective film 150 - 3 , and the protective film 150 - 6 is sandwiched between the protective film 150 - 1 and the protective film 150 - 3 .

[0064] Unlike other protective films 150 provided on the front surface of the semiconductor substrate 10, the protective films 150-5 and 150-6 are provided on the upper surface of the emitter electrode 52. That is, among the protective films 150, only the protective films 150-5 and 150-6 are provided in the active portion 120. The active portion 120 has a protection area 151 provided with a protective film, and a non-protection area 152 not provided with a protective film. The active portion 120 of this example has a protection area 151-1 provided with a protective film 150-5 and a protection area 151-2 provided with a protective film 150-6, and non-protection areas 152-1, 152-2, and 152-3 not provided with a protective film.

[0065] Figure 4 Show Figure 3 An example of an a-a' cross section. The a-a' cross section is an XZ plane passing through the active portion 120-1. The active portion 120-1 of this example has a non-protection area 152-1 arranged near the center when viewed from above, and a non-protection area 152-2 and a non-protection area 152-3 located on both sides of the non-protection area 152-1 in the X-axis direction. The active portion 120-1 also has a protection area 151-1 sandwiched between the non-protection area 152-1 and the non-protection area 152-2, and a protection area 151-2 sandwiched between the non-protection area 152-1 and the non-protection area 152-3. A protective film 150-5 and a protective film 150-6 are provided in the protection area 151-1 and the protection area 151-2, respectively.

[0066] A plated portion 161 is provided on the upper surface of the emitter electrode 52. In one example, the plated portion 161 is Ni / Au obtained by laminating an Au layer on a Ni layer. The plated portion 161 is separated into a plated portion 161-1, a plated portion 161-2, and a plated portion 161-3 by the protective film 150-5 and the protective film 150-6. The plated portion 161-1, the plated portion 161-2, and the plated portion 161-3 are respectively provided in the non-protected area 152-2 and the non-protected area 152-3 located on both sides of the non-protected area 152-1.

[0067] exist Figure 4 In the embodiment, the protective film 150-5 is sandwiched between the plated portion 161-1 and the plated portion 161-2, and the protective film 150-6 is sandwiched between the plated portion 161-1 and the plated portion 161-3. The emitter electrode 52 extends below the protective films 150-5 and 150-6, and the plated portions 161-1, 161-2, and 161-3.

[0068] In the X-axis direction, the width W1 of the protection zone 151 - 1 and the width W2 of the protection zone 151 - 2 may be the same. In this example, the width W1 of the protection zone 151 - 1 and the width W2 of the protection zone 151 - 2 are greater than or equal to 100 μm and less than or equal to 1800 μm.

[0069] The thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 may be the same. Here, the thickness refers to the distance in the +Z axis direction based on the upper surface of the emitter electrode 52. In this example, the thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 are greater than the thickness d1 of the plated portion 161-1 sandwiched between the protective film 150-5 and the protective film 150-6. The thickness D1 of the protective film 150-5 and the thickness D2 of the protective film 150-6 are greater than 5 μm and less than 15 μm. The thickness d1 of the plated portion 161-1 is greater than 1 μm and less than 10 μm.

[0070] If you refer to it again Figure 2 , the area of ​​the non-protected area 152-1 is larger than the area of ​​each of the non-protected area 152-2 and the non-protected area 152-3 in a plan view. Therefore, when the semiconductor device 100 is mounted, the emitter electrode 52 can be easily electrically connected to the outside by bonding wiring such as a lead frame through a solder layer provided on the plated portion 161-1 of the non-protected area 152-1.

[0071] In addition, since the height of the protective film 150-5 and the protective film 150-6 is greater than the height of the plated portion 161-1, it is possible to suppress the solder layer and the like on the plated portion 161-1 of the non-protected area 152-1 from flowing out to the non-protected area 152-2 and the non-protected area 152-3. In addition, by arranging the non-protected area 152-2 and the non-protected area 152-3 on the opposite side with the non-protected area 152-1 as the center, it is possible to suppress the positional deviation of the solder layer and the like on the front surface of the semiconductor substrate 10.

[0072] Figure 4 Although the XZ plane passing through the active portion 120 - 1 is shown, the XZ plane passing through the active portion 120 - 2 also has the same structure, and thus the description thereof is omitted here.

[0073] Figure 5 An example of a top view of the semiconductor device 100 is shown. Figure 5 The vicinity of the negative end of the active portion 120 - 2 in the Y-axis direction is shown. The semiconductor device 100 includes a semiconductor substrate 10 having a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD).

[0074] The semiconductor device 100 of this example includes a gate trench 40, a dummy trench 30, a well region 130, an emitter region 12, a base region 14, and a contact region 15 provided inside the front surface side of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are each an example of a trench portion.

[0075] In addition, the semiconductor device 100 of this example includes a gate metal layer 48 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The gate metal layer 48 and the emitter electrode 52 are also examples of front electrodes. The gate metal layer 48 and the emitter electrode 52 are provided separately from each other. The gate metal layer 48 and the emitter electrode 52 are electrically insulated.

[0076] An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10 and between the gate metal layer 48 and the front surface of the semiconductor substrate 10. Figure 5 In the interlayer insulating film of this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. Figure 5 In the figure, each contact hole is marked with an oblique hatching line.

[0077] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 130, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56.

[0078] The gate metal layer 48 may be provided in a ring shape along the outer periphery of the active portion 120. The gate metal layer 48 of this example is provided along the outer periphery of each of the active portion 120-1 and the active portion 120-2. The gate metal layer 48 is connected to the gate conductive portion in the gate trench portion 40 through the contact hole 49.

[0079] The front electrodes such as the emitter electrode 52 and the gate metal layer 48 are formed of a conductive material containing a metal. For example, they are formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, etc., under the region formed of aluminum, etc.

[0080] Each electrode may have a plug made of tungsten or the like in the contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate 10, tungsten may be buried in contact with the barrier metal, and aluminum or the like may be formed on the tungsten.

[0081] It should be noted that the plug is provided in a contact hole connected to the contact region 15 or the base region 14. In addition, a P++ type plug region having a higher doping concentration than the contact region 15 may be provided below the contact hole of the plug. Thus, the contact resistance between the barrier metal and the contact region 15 can be improved. In addition, the depth of the plug region is about 0.1 μm or less, which is a region that is less than 10% of the depth of the contact region 15.

[0082] Since the plug region improves the contact resistance, the latch-up tolerance is improved in the operation of the transistor unit 70. On the other hand, in the operation of the diode unit 80, the increase of the conduction loss and the switching loss can be suppressed.

[0083] A connection portion 25 may be further provided to electrically connect the emitter electrode 52 or the front electrode such as the gate metal layer 48 to the semiconductor substrate 10. In one example, the connection portion 25 is provided in a region between the gate metal layer 48 and the gate conductive portion including the inside of the contact hole 49. The connection portion 25 may also be provided in a region between the emitter electrode 52 and the dummy conductive portion including the inside of the contact hole 56.

[0084] The connection portion 25 is a conductive material such as a metal such as tungsten or polysilicon doped with impurities. In addition, the connection portion 25 may also have a barrier metal such as titanium nitride. Here, the connection portion 25 is polysilicon doped with N-type impurities (N+). The connection portion 25 is arranged above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0085] The well region 130 is provided at a position closer to the front side of the semiconductor substrate 10 than the drift region 18 described later. The well region 130 of this example is of P+ type. The well region 130 of this example is provided in the edge termination structure portion and the separation portion 90. In addition, the well region 130 is provided from the periphery of the active portion 120-1 and the active portion 120-2 to the inside to a predetermined range. The well region 130 is electrically connected to the emitter electrode 52. The well region 130 is provided from the front side of the semiconductor substrate 10 to a position deeper than the lower end of the base region 14.

[0086] The transistor section 70 and the diode section 80 each have a plurality of groove sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged in the arrangement direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged in the arrangement direction.

[0087] In this example, the arrangement direction of the groove portion is the X-axis direction, and the extension direction perpendicular to the arrangement direction is the Y-axis direction. The gate groove portion 40 of this example may have two extension portions 39 extending along the extension direction (portions of the grooves that are linear along the extension direction), and a connection portion 41 connecting the two extension portions 39.

[0088] At least a portion of the connection portion 41 may be provided in a curved shape when viewed from above. Since the connection portion 41 connects the ends of the two extension portions 39 in the Y-axis direction to each other and the gate metal layer 48, it functions as a gate electrode for the gate trench portion 40. On the other hand, by providing the connection portion 41 in a curved shape, the electric field concentration at the end can be alleviated compared to when the connection portion 41 ends at the extension portion 39.

[0089] In the transistor portion 70, the dummy trench portion 30 is provided between the respective extension portions 39 of the gate trench portion 40. Figure 4 In the example of FIG. 1 , one dummy groove portion 30 is provided between each extending portion 39 , but two or more dummy groove portions 30 may be provided.

[0090] In addition, the dummy trench portion 30 may not be provided between the extension portions 39, and the gate trench portion 40 may be provided. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0091] The dummy trench portion 30 may have a linear shape extending in the extending direction, and may have an extending portion 29 and a connecting portion 31 similarly to the gate trench portion 40 . Figure 4 The semiconductor device 100 shown has only dummy trench portions 30 having connection portions 31 arranged therein, but in other examples, the semiconductor device 100 may also include dummy trench portions 30 having a linear shape and not having connection portions 31 .

[0092] The diffusion depth of the well region 130 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 130 in a plan view. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction (-Z-axis direction) is covered by the well region 130. Thus, the electric field concentration at the bottom of each trench portion can be alleviated.

[0093] In the arrangement direction, a mesa portion is provided between each groove portion. The mesa portion refers to a region sandwiched by the groove portion inside the semiconductor substrate 10. As an example, the depth position of the mesa portion extends from the front surface of the semiconductor substrate to the lower end of the groove portion.

[0094] The mesa portion of this example is provided so as to be sandwiched between adjacent groove portions in the X-axis direction, and extends in the extending direction (Y-axis direction) along the groove on the front surface of the semiconductor substrate 10 .

[0095] A base region 14 is provided in each mesa portion. In each mesa portion, at least one of an emitter region 12 and a contact region 15 may be provided in an area sandwiched by the base region 14 when viewed from above. The base region 14 in this example is of P-type, the emitter region 12 is of N+ type, and the contact region 15 is of P+ type. The base region 14 is provided in contact with the well region 130. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction. As an example, the dopant of the emitter region 12 is arsenic (As), phosphorus (P), antimony (Sb), etc.

[0096] The mesa portion of the transistor portion 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0097] The contact regions 15 and emitter regions 12 in the mesa portion are provided from one groove portion to the other groove portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extending direction of the groove portion (Y-axis direction).

[0098] In other examples, the contact area 15 and the emitter area 12 of the mesa portion may also be arranged in a stripe shape along the extension direction of the groove portion (Y-axis direction). For example, the emitter area 12 is arranged in the area connected to the groove portion, and the contact area 15 is arranged in the area sandwiched by the emitter area 12.

[0099] The emitter region 12 is not provided in the mesa portion of the diode portion 80. The base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be arranged on the entire mesa portion of the diode portion 80. The base region 14 of the diode portion 80 operates as an anode.

[0100] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched by the base region 14 in the extending direction (Y-axis direction). The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 can be arranged in the center of the mesa portion in the arrangement direction (X-axis direction).

[0101] In the diode portion 80, an N+ type cathode region 82 is provided on the back surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. Figure 5 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0102] Figure 6 The structure of the front surface of the semiconductor substrate 10 near the protection area 151-1 is schematically shown. Figure 6 In the figure, the emitter electrode 52 and the like disposed above the front surface of the semiconductor substrate 10 are omitted. Figure 6 The structure of the active portion 120 - 1 and the vicinity of the guard region 151 - 1 is illustrated, but the active portion 120 - 2 also has the same structure, so the description is omitted. In the diode portion 80 , a cathode region 82 is provided on the back surface of the semiconductor substrate 10 .

[0103] As described above, the non-protection area 152-1 is provided near the center of the active area 120-1, and the non-protection area 152-2 is provided between the pad area, the protection area 151-1, and the gate metal layer 48 on the positive side of the pad area in the Y-axis direction. The transistor area 70 and the diode area 80 are alternately provided in the non-protection area 152-1 and the non-protection area 152-2.

[0104] It should be noted that Figure 6 In the figure, for simplicity, one transistor unit 70 and one diode unit 80 are respectively shown in the non-protection area 152-1 and the non-protection area 152-2, but the present invention is not limited thereto. In the non-protection area 152-1 and the non-protection area 152-2, a plurality of transistor units 70 and diode units 80 may be alternately provided.

[0105] In the Y-axis direction, the length of the non-protection area 152-1 is greater than the length of the non-protection area 152-2. In other words, the non-protection area 152-2 is provided in the corner portion of the chip where the non-protection area 152-1 and the pad area are not provided, and by extending the active part 120-1 to such a portion, the area on the chip can be effectively used.

[0106] The protection area 151-1 is sandwiched between the non-protection area 152-1 and the non-protection area 152-2. In the protection area 151-1 of this example, only the transistor section 70 is provided, and the diode section 80 is not provided. The protection area 151-1 can be provided in the center of the transistor section 70.

[0107] Figure 7 Show Figure 6 The bb′ cross section is an example of the bb′ cross section. The bb′ cross section is an XZ plane passing through a part of the transistor section 70 and the diode section 80 , and passes through the emitter region 12 in the transistor section 70 .

[0108] The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a protective film 150-5, a plated portion 161-2, and a collector electrode 24 in the bb' cross section. The interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10, and the emitter electrode 52 is formed above the interlayer insulating film 38.

[0109] The drift region 18 is a region provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0110] The buffer region 20 is a region provided below the drift region 18. The buffer region 20 of this example is of the same conductivity type as the drift region 18, and is N-type as an example. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0111] The collector region 22 is a region of the transistor portion 70 provided below the buffer region 20 and having a conductivity type different from that of the drift region 18. The cathode region 82 is a region of the diode portion 80 provided below the buffer region 20 and having a conductivity type the same as that of the drift region 18. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80.

[0112] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0113] The base region 14 is a region of a conductivity type different from that of the drift region 18 and provided above the drift region 18 in the mesa portion. As an example, the base region 14 of this example is a P-type. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0114] The emitter region 12 is provided between the base region 14 and the front surface 21 of the semiconductor substrate 10. The emitter region 12 of this example is provided in the mesa portion of the transistor portion 70, and is not provided in the mesa portion of the diode portion 80. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0115] Although in Figure 6 Although not shown in the figure, the contact regions 15 are provided alternately with the emitter regions 12 in the mesa portion of the transistor portion 70. The contact regions 15 may be provided to a position deeper than the emitter regions 12 in the semiconductor substrate 10.

[0116] The accumulation region 16 is a region provided on the front surface 21 side of the semiconductor substrate 10 more than the drift region 18. The accumulation region 16 of this example is of the same conductivity type as the drift region 18, and is N+ type as an example. The accumulation region 16 of this example is provided only in the transistor portion 70, but may also be provided in the diode portion 80. In addition, the accumulation region 16 may be provided in a multi-layer manner.

[0117] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, thereby reducing the on-voltage of the transistor portion 70.

[0118] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21 of the semiconductor substrate 10. Each trench portion is provided from the front surface 21 of the semiconductor substrate 10 to the drift region 18. In a region where at least any one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18.

[0119] It should be noted that the method of forming the groove portion through the doped region is not limited to the method of forming the groove portion first and then the doped region. The method of forming the groove portion through the doped region is also included in the method of forming the groove portion through the doped region.

[0120] The gate groove portion 40 has a gate groove formed on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate groove. The gate conductive portion 44 is provided inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0121] The gate conductive portion 44 includes a region that is opposed to the base region 14 adjacent to the mesa portion side via the gate insulating film 42 in the depth direction (-Z axis direction) of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is in contact with the gate trench.

[0122] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 is covered by an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10.

[0123] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. The contact holes 55 and 56 may also be provided in a manner penetrating the interlayer insulating film 38 in the same manner.

[0124] A lifetime control region 85 containing a lifetime inhibitor is provided in the drift region 18 from the diode portion 80 to at least a portion of the transistor portion 70. The lifetime control region 85 is a crystal defect formed inside the semiconductor substrate 10 by injecting helium ions or the like into a predetermined depth position. The lifetime control region 85 promotes the recombination of holes generated in the base region 14 of the diode portion 80 and the transistor portion 70 and electrons injected from the cathode region 82 when the diode portion 80 is turned off, and promotes carrier annihilation, thereby suppressing the peak current during reverse recovery.

[0125] exist Figure 7 , the peak position of the lifetime inhibitor concentration distribution in the Z-axis direction is indicated by an "×" sign. In the Z-axis direction, the peak position of the lifetime inhibitor concentration distribution may be at the same depth as the bottom end of the well region 130, or may be deeper than the bottom end of the well region 130. The lifetime control region 85 may be formed to have a plurality of lifetime inhibitor concentration distribution peaks in the Z-axis direction.

[0126] The lifetime controlled region 85 of this example is formed by irradiating protons or helium from the front surface 21 of the semiconductor substrate 10. In one example, the lifetime controlled region 85 is formed by irradiating helium ions while masking a region where the lifetime controlled region 85 is not to be formed with a mask such as a resist.

[0127] The lifetime control region 85 of this example is provided only in the non-protection region 152, not in the protection region 151. The lifetime control region 85 is separated from the protection region 151, and a distance L1 between the protection region 151-1 and the lifetime control region 85 in the X-axis direction is 20 μm to 1800 μm.

[0128] As described above, in order to form the lifetime control region 85, helium ions are irradiated from the front surface 21 side of the semiconductor substrate 10. However, since helium ions are light ions, the range of the lifetime control region 85 varies in the protection area 151 provided with the protection film 150, and the depth direction position of the lifetime control region 85 deviates between the protection area 151 and the non-protection area 152.

[0129] Therefore, in this example, by irradiating helium ions only to the non-protected area 152 without irradiating the protected area 151, the depth direction position of the lifetime control area 85 is made uniform, and carrier annihilation is promoted when the diode part 80 is turned off, thereby suppressing the peak current during reverse recovery.

[0130] In the X-axis direction, the distance L2 that the lifetime control region 85 extends in the transistor portion 70 is greater than or equal to 80% and less than or equal to 250% of the thickness D0 of the semiconductor substrate 10. The thickness D0 of the semiconductor substrate 10 refers to the distance from the front surface 21 to the back surface 23 in the depth direction (-Z-axis direction) of the semiconductor substrate 10. The thickness D0 of the semiconductor substrate 10 in this example may be greater than or equal to 50 μm and less than or equal to 150 μm, or may be greater than or equal to 70 μm and less than or equal to 80 μm.

[0131] When the diode section 80 operates, carriers diffuse from the diode section 80 to the outside. In one example, the carriers move from the front surface 21 of the semiconductor substrate 10 at an angle of approximately 45° toward the back surface 23. In this example, by providing the lifetime control region 85 to extend toward the transistor section 70 by a distance L2, the carriers diffused from the diode section 80 can be captured.

[0132] In addition, in the X-axis direction, the distance between the protection area 151-1 and the diode unit 80 is greater than the thickness D0 of the semiconductor substrate 10. Although the polyimide is overetched to form the protection film 150, the deviation of the completed position is large. Therefore, by providing a margin, even if the deviation occurs, the influence on the performance can be suppressed.

[0133] In this way, the protection layer 151 of this example is provided inside the transistor portion 70 in a manner separated from the diode portion 80 and the lifetime control region 85. Thus, by providing the lifetime control region 85 without being affected by the protection film 150 and promoting carrier annihilation when the diode portion 80 is turned off, it is possible to suppress the peak current during reverse recovery.

[0134] Figure 8 An example of a method for manufacturing the semiconductor device 100 is shown. Figure 8 and Figure 7 Similarly, Figure 6 Taking the bb′ cross section of FIG. 1 as an example, the formation process of the lifetime control region 85 in the method for manufacturing the semiconductor device 100 is mainly described.

[0135] The manufacturing method of the semiconductor device 100 of this example includes forming an active portion 120 (in which transistor portions 70 and diode portions 80 are alternately arranged) on a semiconductor substrate 10. Figure 8 The step of forming a plurality of groove portions (in the semiconductor substrate 10) is as follows: Figure 8 The steps of: forming the gate trench portion 40 and the dummy trench portion 30 ; and forming the emitter electrode 52 above the front surface 21 of the semiconductor substrate 10 .

[0136] The step of forming the active portion 120 includes the step of injecting dopants into the semiconductor substrate 10 to form an impurity-injected region such as an emitter region 12, a base region 14, a contact region 15, and an accumulation region 16. The step of forming a plurality of groove portions includes the following steps: forming grooves by etching the front surface 21 of the semiconductor substrate 10, oxidizing or nitriding the semiconductor on the inner wall of the groove to form an insulating film (on the surface of the semiconductor substrate 10). Figure 8 The gate insulating film 42 and the dummy insulating film 32 are formed by filling the inner side of the insulating film with a conductive material such as polysilicon to form a conductive portion (in Figure 8 4 and dummy conductive portion 34). Any one of the step of forming the active portion 120 and the step of forming the plurality of trench portions may be performed first.

[0137] The step of forming the emitter electrode 52 includes the following steps: after an interlayer insulating film 38 is formed above the front surface 21 of the semiconductor substrate 10 using BPSG or the like, and a contact hole is formed by etching the interlayer insulating film 38, a film is formed on the front surface 21 of the semiconductor substrate 10 and the interlayer insulating film 38 using aluminum or an alloy having aluminum as a main component (such as an aluminum-silicon alloy, an aluminum-silicon-copper alloy, etc.).

[0138] The method for manufacturing the semiconductor device 100 further includes forming a protective film 150 of polyimide on the upper surface of the emitter electrode 52 (in Figure 8 After the polyimide coated on the front surface 21 of the semiconductor substrate 10 is spin-coated and cured, the non-protection area 152 (in the Figure 8 The polyimide in the non-protected area 152-2) is used, thereby in the protected area 151 (in Figure 8 A protection film 150 is formed in the protection area 151 - 1 .

[0139] In the non-protected area 152, a plated portion 161 may be formed on the upper surface of the emitter electrode 52 (at Figure 8 The plated portion 161 - 2 in FIG. 1 is a Ni / Au film formed by growing an Au film for preventing oxidation by immersion on a Ni film formed by electroless plating.

[0140] The diode portion 80 of this example is included in the non-protection area 152, and the protection area 151 is included in the transistor portion 70. In the X-axis direction, the distance between the diode portion 80 and the protection area 151 is greater than or equal to the thickness D0 of the semiconductor substrate 10. The thickness of the semiconductor substrate 10 may be greater than or equal to 50 μm and less than or equal to 150 μm, or may be greater than or equal to 70 μm and less than or equal to 80 μm.

[0141] The method for manufacturing the semiconductor device 100 further includes the step of irradiating the diode portion 80 with a lifetime inhibitor from the front surface 21 side of the semiconductor substrate 10 to form a lifetime control region 85. In one example, the lifetime inhibitor is helium or protons.

[0142] In this example, helium ions are irradiated through resist 190 disposed above protective film 150. The width of resist 190 in the X-axis direction is greater than that of protective film 150, and resist 190 is disposed to cover at least the entire protective film 150 in a plan view.

[0143] In the X-axis direction, a distance L1 between the end of the resist 190 and the end of the protective film 150 is greater than or equal to 0 μm and less than or equal to 1800 μm. In a plan view, the end of the resist 190 may coincide with the end of the lifetime control region 85 .

[0144] The resist 190 is disposed on the transistor portion 70 so as to be separated from the diode portion 80. In the X-axis arrangement direction, the distance between the diode portion 80 and the resist 190 is greater than or equal to 80% and less than or equal to 250% of the thickness D0 of the semiconductor substrate 10. After the lifetime control region 85 is formed, the resist 190 is removed using a developing solution.

[0145] Thus, according to the manufacturing method of the semiconductor device 100 of this example, the protection film 151 is formed inside the transistor portion 70 in a manner separated from the diode portion 80 and the lifetime control region 85. Thus, by forming the lifetime control region 85 without being affected by the protection film 150 and promoting carrier annihilation when the diode portion 80 is turned off, it is possible to suppress the peak current during reverse recovery.

[0146] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0147] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having an active portion in which transistor portions and diode portions are alternately provided, and having a plurality of groove portions extending along an extending direction of the transistor portions and the diode portions; an emitting electrode disposed above the front surface of the semiconductor substrate; as well as A protective film of polyimide, which is arranged on the upper surface of the emitter electrode, The diode portion has a lifetime control region, and the lifetime control region contains a lifetime inhibitor irradiated from the front side of the semiconductor substrate. The active portion includes a protection area where the protection film is provided and a non-protection area where the protection film is not provided. The diode section is included in the non-protection area, and the protection area is included in the transistor section.

2. The semiconductor device according to claim 1, wherein: The width of the transistor portion in the trench arrangement direction is greater than or equal to 300 μm and less than or equal to 2000 μm.

3. The semiconductor device according to claim 1, wherein: The width of the diode portion in the trench arrangement direction is greater than or equal to 200 μm and less than or equal to 2000 μm.

4. The semiconductor device according to claim 1, wherein: In the groove arrangement direction, the width of the protection zone is greater than or equal to 100 μm and less than or equal to 1800 μm.

5. The semiconductor device according to claim 1, wherein: In the trench arrangement direction, a distance between the protection area and the diode portion is greater than or equal to a thickness of the semiconductor substrate.

6. The semiconductor device according to claim 1, wherein: The lifetime control region is provided so as to extend from the diode portion to at least a portion of the transistor portion in the trench arrangement direction. In the trench arrangement direction, the lifetime control region extends in the transistor portion by a distance that is greater than or equal to 80% and less than or equal to 250% of the thickness of the semiconductor substrate.

7. The semiconductor device according to claim 5 or 6, characterized in that: The semiconductor substrate has a thickness of 50 μm or more and 150 μm or less.

8. The semiconductor device according to claim 1, wherein: The life control area is only set in the non-protection area, In the groove arrangement direction, the distance between the protection zone and the lifetime control zone is greater than or equal to 20 μm and less than or equal to 1800 μm.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a first plated portion and a second plated portion, wherein the first plated portion and the second plated portion are provided on the upper surface of the emitter electrode, and the protective film is sandwiched between the first plated portion and the second plated portion. The emitter electrode is extended below the protection film, the first plated portion, and the second plated portion.

10. The semiconductor device according to claim 9, wherein: The protective film includes a first protective film and a second protective film sandwiching the first plated portion. The thickness of the first protection film and the second protection film is greater than the thickness of the first plated portion.

11. The semiconductor device according to claim 1, wherein: The non-protected area includes a first non-protected area and a second non-protected area, and the protected area is sandwiched between the first non-protected area and the second non-protected area.

12. A method for manufacturing a semiconductor device, characterized in that: include: forming an active portion on a semiconductor substrate, wherein the active portion is alternately provided with a transistor portion and a diode portion; A step of forming a plurality of groove portions in the semiconductor substrate, wherein the plurality of groove portions extend along an extending direction of the transistor portion and the diode portion; A step of forming an emitter electrode above the front surface of the semiconductor substrate; forming a protective film of polyimide on the upper surface of the emitter electrode; as well as In the diode portion, a lifetime inhibitor is irradiated from the front side of the semiconductor substrate to form a lifetime control region, The active portion has a protection area provided with the protection film and a non-protection area not provided with the protection film when viewed from above. The diode section is included in the non-protection area, and the protection area is included in the transistor section.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: irradiating the lifetime inhibitor via a resist disposed above the protective film, In the trench arrangement direction, the width of the resist is larger than the width of the protection film.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The resist is configured to cover at least the entire protective film in a plan view.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: In the trench arrangement direction, a distance between an end portion of the resist and an end portion of the protective film is greater than or equal to 0 μm and less than or equal to 1800 μm.

16. The method for manufacturing a semiconductor device according to claim 13, wherein: The resist is arranged on the transistor portion so as to be separated from the diode portion. In the trench arrangement direction, a distance between the diode portion and the resist is greater than or equal to 80% and less than or equal to 250% of the thickness of the semiconductor substrate.

17. The method for manufacturing a semiconductor device according to claim 13, wherein: In the trench arrangement direction, the distance between the diode portion and the protection zone is greater than or equal to the thickness of the semiconductor substrate.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein: The semiconductor substrate has a thickness of 50 μm or more and 150 μm or less.

Images