Semiconductor device
By setting a carrier injection suppression area in the gate common wiring and pad area of the IGBT, using the low-concentration conductive layer material, the problem of damage caused by carrier concentration when the IGBT is turned off is solved, and the shutdown resistance is improved.
Patent Information
- Application Number
- CN202380040708.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-06-01
- Filing Date
- 2023-04-04
- Publication Date
- 2024-12-27
AI Technical Summary
During the shutdown process of the IGBT, the concentration of carriers near the gate common wiring area and the gate pad area causes damage. The prior art cannot effectively suppress such carrier injection, affecting the shutdown resistance.
In a semiconductor device, a carrier injection suppression region is designed, and a carrier injection suppression region is provided in the overlap region of the gate common wiring and the gate pad, and a low concentration of conductive layer material is used to suppress carrier injection. Ensure shutdown resistance.
The carrier concentration near the gate common wiring area and the gate pad area is effectively suppressed, and the IGBT is turned off withstandness and damage caused by carrier injection is avoided.
Smart Images
Figure CN119213569A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor devices. Background Art
[0002] In power semiconductors such as IGBTs, it is necessary to sufficiently ensure the turn-off tolerance (RBSOA (Reverse Bias Safe Operating Area) tolerance).
[0003] As a technology for improving the cutoff capability of an IGBT when it is turned off, there is, for example, Patent Document 1. The structures shown in paragraphs 0120 to 0123, Figures 32A and 32B of Patent Document 1 are structures for suppressing the injection of carriers from the collector side of the middle region 2 to the edge terminal region 5 of the IGBT, and describe, for example, the following contents: Figure 32A shows an IGBT in which the collector layer 16 is in contact with the metal 29 in the active cell region 1, and the n buffer layer 15 is in contact with the metal 29 in the middle region 2 and the edge terminal region 5; and Figure 32B shows an IGBT in which the p collector layer 16 is in contact with the metal 29 in the active cell region 1, and the low-concentration p collector layer 16' having an impurity concentration lower than that of the p collector layer 16 is in contact with the metal 29 in the middle region 2 and the edge terminal region 5. As a result, the structure has the following effects: during the shutdown operation, the electric field strength of the main junction pn junction existing in the middle region 2 is alleviated, the increase in local electric field strength is suppressed, and thermal destruction caused by local temperature increase caused by current concentration generated by impact ionization is suppressed.
[0004] Prior art literature
[0005] Patent Literature
[0006] Patent Document 1: International Publication No. 2017 / 115434 Summary of the invention
[0007] Problems to be solved by the invention
[0008] One of the factors causing IGBT destruction when turned off is that a large number of carriers such as holes are injected from the terminal region when turned off, so that carriers concentrate around the active region (especially corner regions), causing destruction due to electric field concentration.
[0009] According to the technology of Patent Document 1, since injection of carriers from the termination region is suppressed, it is possible to suppress damage in the peripheral portion of the active region during turn-off.
[0010] However, according to the research of the inventors of this application, carrier injection also occurs from the gate common wiring also called gate fingers and the lower part of the gate pad, causing carrier concentration in the active area near the gate common wiring area and the gate pad area, leading to destruction.
[0011] In Patent Document 1, in the gate common wiring equivalent to the gate common wiring, Figure 1 In the surface gate wiring portion 3, a structure for suppressing the injection of carriers from the collector side is not adopted, and this problem cannot be solved.
[0012] In addition, according to the research of the inventor of this application, regardless of whether there is a structure to suppress carrier injection in the terminal area, for example, when the switching speed is fast, carrier concentration occurs first in the active area near the gate common wiring area and the gate pad area compared to the peripheral part of the active area, thereby causing destruction.
[0013] use Figure 1 , Figure 2 , Figures 10 to 12 The reason will be explained.
[0014] Figure 1 is a top view of a semiconductor device, Figure 2 yes Figure 1 A magnified view of part A of a semiconductor device. Fig.10 is a BB' cross-sectional view of a conventional semiconductor device. Fig.11 is a DD' cross-sectional view of a conventional semiconductor device. Fig.12 It is a BB' cross-sectional view of a conventional semiconductor device.
[0015] like Fig.10 As shown in FIG. 1 , when the switching speed is slow, holes 20 in the gate common wiring region 6 and the terminal region 4 overlapping the gate common wiring 1 are injected into the active region 3, causing carrier concentration in the peripheral portion of the active region 3. Fig.11 As shown in FIG. 1 , in the gate common wiring region 6 sandwiched between the active regions 3, holes 20 are also injected into the active regions 3, and carriers are concentrated in the active regions 3 near the gate common wiring region 6. Fig.10 As shown, when the switching speed is slow, since a large amount of holes 20 are injected into the peripheral portion of the active region 3 , the peripheral portion of the active region 3 is easily destroyed.
[0016] On the other hand, Fig.12 As shown, in the case of a fast switching speed, before a portion of the holes 20 in the gate common wiring region 6 and the terminal region 4 reach the gate common wiring region 6 and the terminal region 4, as shown in FIG. Fig.11As shown, there is a case where the amount of holes 20 injected from the gate common wiring region 6 sandwiched by the active region 3 becomes dominant, which may cause damage to the active region 3 near the gate common wiring region 6. In addition, the structure of the gate pad region not shown is the same as that of the gate common wiring region 6, and similarly, it is possible to cause damage to the active region 3 near the gate pad region.
[0017] Therefore, it is understood that in order to ensure the turn-off withstand capability, a structure that suppresses the injection of carriers is required even in the gate common wiring region 6 and the gate pad region.
[0018] An object of the present invention is to provide a semiconductor device capable of suppressing carrier concentration in an active region near a gate common wiring region or a gate pad region and ensuring turn-off withstand capability.
[0019] Solutions to Solve Problems
[0020] In order to solve the above-mentioned problems, the semiconductor device of the present invention, for example, has multiple switching elements, a gate common wiring commonly connected to the gates of the above-mentioned multiple switching elements, and a gate pad that supplies power to the above-mentioned gate common wiring. The above-mentioned semiconductor device is characterized in that a carrier injection suppression region is provided in a gate common wiring area overlapping with the above-mentioned gate common wiring and a gate pad area overlapping with the gate pad.
[0021] Effects of the Invention
[0022] According to the semiconductor device of the present invention, it is possible to suppress the concentration of carriers in the active region near the gate common wiring region and the gate pad region, thereby ensuring turn-off resistance. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a top view of a semiconductor device.
[0024] Figure 2 yes Figure 1 An enlarged view of part A of a semiconductor device.
[0025] Figure 3 It is a cross-sectional view taken along the line BB′ of the semiconductor device of Example 1.
[0026] Figure 4 It is a cross-sectional view taken along the line CC′ of the semiconductor device of Example 1.
[0027] Figure 5 It is a cross-sectional view taken along the line DD′ of the semiconductor device according to the first embodiment.
[0028] Figure 6 It is a BB′ cross-sectional view of the semiconductor device of the second embodiment.
[0029] Figure 7 It is a cross-sectional view taken along the line DD′ of the semiconductor device according to the second embodiment.
[0030] Figure 8 It is a BB′ cross-sectional view of the semiconductor device of the third embodiment.
[0031] Fig. 9 It is a DD′ cross-sectional view of the semiconductor device of the third embodiment.
[0032] Fig.10 It is a BB' cross-sectional view of a conventional semiconductor device.
[0033] Fig.11 It is a DD' cross-sectional view of a conventional semiconductor device.
[0034] Fig.12 It is a BB' cross-sectional view of a conventional semiconductor device. DETAILED DESCRIPTION
[0035] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.
[0036] Example 1
[0037] Figure 1 is a top view of a semiconductor device, Figure 2 yes Figure 1 A magnified view of part A of a semiconductor device. Figure 3 is a BB' cross-sectional view of the semiconductor device of Example 1, Figure 4 is a CC' cross-sectional view of the semiconductor device of Example 1, Figure 5 It is a cross-sectional view taken along the line DD′ of the semiconductor device according to the first embodiment.
[0038] like Figure 1 as well as Figure 2 As shown, the semiconductor device 100 includes: an active region 3 in which a plurality of switching elements are formed; a gate common wiring 1 commonly connected to gates 5 of the plurality of switching elements; and a gate pad 2 for supplying power to the gate common wiring 1. The gate common wiring 1 includes a portion that divides the active region 3 and a portion formed at a boundary between the active region 3 and the terminal region 4.
[0039] In addition, Figure 1 The gate 5 is omitted in the figure. Figure 1 as well as Figure 2 In the figure, the gate electrode 13, the emitter electrode 14, and the field plate 15 are omitted.
[0040] like Figure 3As shown, the semiconductor device of the first embodiment has an IGBT as a switching element in the active region 3. Specifically, the semiconductor device of the first embodiment has: a first conductivity type (in Figure 3 a second conductivity type (in Figure 3 a main body layer 8 of p-type in the middle; a gate 5 and a gate insulating film 10 formed in the trench; an emitter layer 9 of the first conductivity type provided on the surface side of the main body layer 8; and a collector layer 17 of the second conductivity type provided on the back side of the drift layer 7.
[0041] Here, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the carriers are not the holes 20 but electrons.
[0042] In addition, the semiconductor device of Example 1 has: a first conductive type buffer layer 16 arranged between the drift layer 7 and the collector layer 17; a collector electrode 19 arranged on the back side of the collector layer 17; an interlayer insulating film 12 arranged on the surface side of the main layer 8 and the emitter layer 9; and an emitter electrode 14 that is in contact with the emitter layer 9 and the main layer 8 via a contact hole arranged in the interlayer insulating film 12.
[0043] The semiconductor device of Example 1 includes, in the termination region 4 , a second conductivity type well layer 11 provided on the surface side of the drift layer 7 , and a field plate 15 in contact with the well layer 11 via a contact hole provided in the interlayer insulating film 12 .
[0044] The semiconductor device of Example 1 includes a well layer 11, a gate common wiring 1, and a gate electrode 13 in contact with the gate common wiring 1 via a contact hole provided in an interlayer insulating film 12 in a gate common wiring region 6 overlapping with the gate common wiring 1. Although not shown in the figure, the structure of the gate pad region overlapping with the gate pad 2 is also substantially the same as that of the gate common wiring region 6.
[0045] like Figure 4 As shown, the gate 5 is connected to the gate common wiring 1 , and the gate common wiring 1 , the gate 5 , and the gate pad 2 are formed of, for example, polysilicon.
[0046] Here, if Figures 3 to 5 As shown, the semiconductor device of the first embodiment has a carrier injection suppression region 18 in the gate common wiring region 6 and the gate pad region (not shown). This can suppress carrier concentration in the active region 3 near the gate common wiring region 6 and the gate pad region, thereby ensuring turn-off resistance.
[0047] like Figure 4 as well as Figure 5As shown, it is ideal that the carrier injection suppression region 18 is also formed in the gate common wiring region 6 sandwiched between the divided active regions 3. This can suppress the concentration of carriers in the active regions 3 near the gate common wiring region 6 sandwiched between the divided active regions 3, thereby ensuring turn-off resistance.
[0048] In addition, if Figure 3 As shown, it is desirable that the carrier injection suppression region 18 is also formed in the terminal region 4. This ensures that carriers are concentrated in the peripheral portion of the active region 3 and that the turn-off tolerance is ensured. In addition, for example, when the switching speed is fast, when the hole injection from the terminal region 4 is not dominant, the carrier injection suppression region 18 may not be provided in the terminal region 4.
[0049] In Example 1, an example in which a layer having the same conductivity type as the collector layer 17 and a lower concentration than the collector layer 17 is used as the carrier injection suppression region 18 is shown.
[0050] In terms of the impurity concentration of each semiconductor layer, for example, the drift layer is of low-concentration n-type, the emitter layer 9 is of high-concentration n+ type, and the carrier injection suppression region 18 is of low-concentration p-type.
[0051] Example 2
[0052] Example 2 is a modified example of Example 1, and is different from Example 1 in the structure of the carrier injection suppressing region 18. Other aspects are the same as Example 1, and therefore duplicate descriptions are omitted.
[0053] Figure 6 is a BB' cross-sectional view of the semiconductor device of Example 2, Figure 7 It is a cross-sectional view taken along the line DD′ of the semiconductor device according to the second embodiment.
[0054] The carrier injection suppression region 18 of Example 2 is a region where there is no collector layer 17 and a layer (here, the buffer layer 16 ) having a conductivity type different from that of the collector layer 17 is in direct contact with the collector electrode 19 .
[0055] Compared with Example 1, there is no need to form a low-concentration p-type layer on the back side, so there is an advantage that the manufacturing is easy. Other than this, the same effects as those of Example 1 can be obtained.
[0056] Example 3
[0057] Example 3 is a modified example of Example 1, and is different from Example 1 in the structure of the carrier injection suppressing region 18. Other aspects are the same as Example 1, and therefore repeated descriptions are omitted.
[0058] Figure 8is a BB' cross-sectional view of the semiconductor device of Example 3, Fig. 9 It is a DD′ cross-sectional view of the semiconductor device of the third embodiment.
[0059] The carrier injection suppression region 18 of Example 3 becomes a short lifetime region of light ion irradiation. As the light ions, for example, protons, helium, etc. can be used.
[0060] In the third embodiment as well, the same effects as those of the first embodiment can be obtained.
[0061] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, part or all of the structures described in the embodiments can also be combined and applied.
[0062] Explanation of symbols
[0063] 1—gate common wiring, 2—gate pad, 3—active region, 4—terminal region, 5—gate, 6—gate common wiring region, 7—drift layer, 8—body layer, 9—emitter layer, 10—gate insulating film, 11—well layer, 12—interlayer insulating film, 13—gate electrode, 14—emitter electrode, 15—field plate, 16—buffer layer, 17—collector layer, 18—carrier injection suppression region, 19—collector electrode, 20—holes, 100—semiconductor device.
Claims
1. A semiconductor device comprising a plurality of switching elements, a gate common wiring connected to gates of the plurality of switching elements in common, and a gate pad for supplying power to the gate common wiring, The semiconductor device is characterized in that A carrier injection suppression region is provided in a gate common wiring region overlapping with the gate common wiring and a gate pad region overlapping with the gate pad.
2. The semiconductor device according to claim 1, wherein: An active region having the plurality of switching elements, The gate common wiring region has a portion that divides the active region. The carrier injection suppression region is formed in the gate common wiring region sandwiched between the divided active regions.
3. The semiconductor device according to claim 1, wherein: With terminal area, The terminal region also has the carrier injection suppression region.
4. The semiconductor device according to claim 1, wherein: having a collector layer provided on the back side, The carrier injection suppression region includes a layer having the same conductivity type as the collector layer and a lower concentration than the collector layer.
5. The semiconductor device according to claim 1, wherein: A collector layer is provided on the back side, and a collector electrode is connected to the collector layer. The carrier injection suppression region is a region where the collector layer is absent and a layer having a conductivity type different from that of the collector layer is in direct contact with the collector electrode.
6. The semiconductor device according to claim 1, wherein: The carrier injection suppression region is a low lifetime region of light ion irradiation.
7. The semiconductor device according to claim 1, wherein: The carrier injection suppressing region is a hole injection suppressing region.