Out-phase amplifier

Abstract

The out-phase amplifier is provided with: a first amplifier (10) that amplifies a first signal (Sia); a second amplifier (11) that amplifies the second signal (Sib); a synthesizer (16) that synthesizes the first signal (Soa) amplified by the first amplifier and the second signal (Sob) amplified by the second amplifier, and outputs the synthesized signal as an output signal (So); and a signal processor (20) that sets the amplitude (Ab) of the second signal to be greater than or equal to the amplitude (Aa) of the first signal when the output power of the output signal is set to be maximum, and sets the amplitude of the second signal to be smaller than the amplitude of the first signal when the output power is set to be minimum. The signal processor (20) sets the out-of-phase angle (theta) of the first signal and the second signal when the output power is set to be maximum to be larger than the out-of-phase angle when the output power is set to be minimum, and outputs the first signal and the second signal.

Description

Technical Field

[0001] The present disclosure relates to an out-of-phase amplifier. This application claims priority based on Japanese Patent Application No. 2022-093858 filed on June 9, 2022, and all the contents described in the Japanese Patent Application are incorporated herein by reference. Background Art

[0002] As an amplifier for amplifying high-frequency signals such as microwaves, an out-of-phase amplifier is known. The out-of-phase amplifier includes a signal processor, two amplifiers, and a synthesizer. The signal processor outputs two signals whose out-of-phase angles are changed based on the amplitude of the input signal. The two amplifiers amplify the two signals output from the signal processor respectively. The synthesizer includes a synthesizer that synthesizes the two output signals amplified by the two amplifiers into one output signal. It is known to use a Chireix synthesizer as a synthesizer (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-156023 Summary of the invention

[0006] One embodiment of the present disclosure is an out-of-phase amplifier, which includes: a first amplifier for amplifying a first signal; a second amplifier for amplifying a second signal; a synthesizer for synthesizing the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputting the synthesized signal as an output signal; and a signal processor for setting the amplitude of the second signal to be greater than or equal to the amplitude of the first signal when the output power of the output signal is set to a maximum, and setting the amplitude of the second signal to be less than the amplitude of the first signal when the output power is set to a minimum, the signal processor sets the out-of-phase angle between the first signal and the second signal when the output power is set to a maximum to be greater than the out-of-phase angle when the output power is set to a minimum, and outputs the first signal and the second signal.

[0007] One embodiment of the present disclosure is an out-of-phase amplifier, which includes: a first amplifier for amplifying a first signal; a second amplifier for amplifying a second signal; and a synthesizer for synthesizing the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputting the synthesized signal as an output signal, when the output power of the output signal is maximum, the amplitude of the second signal is greater than or equal to the amplitude of the first signal, when the output power is minimum, the amplitude of the second signal is less than the amplitude of the first signal, and the out-of-phase angle between the first signal and the second signal when the output power is maximum is greater than the out-of-phase angle when the output power is minimum. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram of the out-of-phase amplifier of Example 1.

[0009] Figure 2 This is a block diagram of the out-of-phase amplifier of Example 1.

[0010] Figure 3 2 is a block diagram of a different-phase amplifier of Comparative Example 1.

[0011] Figure 4 It is a Smith chart of impedance in Comparative Example 1.

[0012] Figure 5 is a Smith chart of impedance in Example 1.

[0013] Figure 6 3 is a diagram showing the out-of-phase angle θ with respect to the output power Po in Comparative Example 2.

[0014] Figure 7 1 is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in Comparative Example 2.

[0015] Fig. 8A It is a schematic diagram of the vector of the output power in Comparative Example 2.

[0016] Figure 8B It is a schematic diagram of the vector of the output power in Comparative Example 2.

[0017] Fig. 9 1 is a diagram showing the phase difference θ of the input signal with respect to the output power Po in the first embodiment.

[0018] Fig.10 It is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the first embodiment.

[0019] Fig.11A It is a schematic diagram of the vector of the output power in Example 1.

[0020] Fig. 11BIt is a schematic diagram of the vector of the output power in Example 1.

[0021] Fig. 11C It is a schematic diagram of the vector of the output power in Example 1.

[0022] Fig.12 1 is a diagram showing the out-of-phase angle θ with respect to the output power Po in the first modification of the first embodiment.

[0023] Fig.13 It is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the second modification of the first embodiment.

[0024] Fig.14 It is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the third modification of the first embodiment.

[0025] Fig.15 This is a block diagram of the out-of-phase amplifier of Example 2.

[0026] Fig.16 This is a graph showing the drain efficiency with respect to the output voltage in Example 1 and Comparative Example 1. DETAILED DESCRIPTION

[0027] [Problems to be Solved by the Present Disclosure]

[0028] By using a Chireix combiner, the impedance when looking from the amplifier to the combiner can be set to improve the characteristics. However, if the phase difference between the two signals deviates from the specified range, the high-frequency characteristics such as the drain efficiency of the two amplifiers will deteriorate. Therefore, if the phase difference between the two signals is set to a narrow range, the dynamic range will become smaller.

[0029] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to increase the dynamic range of a non-phasing amplifier.

[0030] [Effects of the present disclosure]

[0031] According to the present disclosure, the dynamic range of the out-phasing amplifier can be increased.

[0032] [Description of Embodiments of the Present Disclosure]

[0033] First, the contents of the embodiments of the present disclosure will be listed and described.

[0034] (1) One embodiment of the present disclosure is an out-of-phase amplifier, comprising: a first amplifier for amplifying a first signal; a second amplifier for amplifying a second signal; a synthesizer for synthesizing the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputting the synthesized signal as an output signal; and a signal processor for setting the amplitude of the second signal to be greater than or equal to the amplitude of the first signal when the output power of the output signal is set to a maximum, and setting the amplitude of the second signal to be less than the amplitude of the first signal when the output power is set to a minimum, the signal processor setting the out-of-phase angle between the first signal and the second signal when the output power is set to a maximum to be greater than the out-of-phase angle when the output power is set to a minimum, and outputting the first signal and the second signal. Thus, the dynamic range can be increased.

[0035] (2) In the above (1), the saturation power of the first amplifier may be smaller than the saturation power of the second amplifier.

[0036] (3) In the above (2), when the output power is set to a maximum, the signal processor may set the amplitude of the second signal to be larger than the amplitude of the first signal.

[0037] (4) In any of the above (1) to (3), it may be that when the output power is set within a first range, the signal processor sets the amplitude of the second signal to be larger than the amplitude of the first signal, and when the output power is set within a second range smaller than the first range, the signal processor sets the amplitude of the second signal in such a manner that the amplitude of the second signal decreases if the output power decreases.

[0038] (5) In any one of the above (1) to (4), the signal processor may set the amplitude of the first signal to a fixed value regardless of the output power.

[0039] (6) In the above (5), it may be that when the output power is set within a first range, the signal processor sets the amplitude of the second signal to a fixed value regardless of the output power, and when the output power is set within a second range smaller than the first range, the signal processor sets the amplitude of the second signal in such a manner that the amplitude of the second signal decreases as the output power decreases.

[0040] (7) In any one of the above (1) to (6), the signal processor may set the out-phase angle so that the out-phase angle becomes smaller as the output power becomes smaller.

[0041] (8) In any of the above (1) to (7), the synthesizer may be a Chireix synthesizer.

[0042] (9) In any of the above (1) to (8), the phase difference angle when the output power is set to the maximum may be less than 90°, and the phase difference angle when the output power is set to the minimum may be greater than 0°.

[0043] (10) One embodiment of the present disclosure is an out-of-phase amplifier, comprising: a first amplifier for amplifying a first signal; a second amplifier for amplifying a second signal; and a synthesizer for synthesizing the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputting the synthesized signal as an output signal, wherein when the output power of the output signal is maximum, the amplitude of the second signal is greater than or equal to the amplitude of the first signal, and when the output power is minimum, the amplitude of the second signal is less than the amplitude of the first signal, and the out-of-phase angle between the first signal and the second signal when the output power is maximum is greater than the out-of-phase angle when the output power is minimum. Thus, the dynamic range can be increased.

[0044] [Details of the embodiments of the present disclosure]

[0045] Hereinafter, specific examples of the out-of-phase amplifier according to the embodiment of the present disclosure will be described with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0046] Figure 1 is a block diagram of the out-of-phase amplifier of Example 1. Figure 1 As shown, in the out-of-phase amplifier 100, an amplifier 10 (first amplifier) ​​and an amplifier 11 (second amplifier) ​​are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input to the input terminal Tin as an input signal Si. When the out-of-phase amplifier 100 is used in a base station of mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. The signal processor 20 processes the input signal Si and outputs it as two signals, namely, a signal Sia (first signal) and a signal Sib (second signal).

[0047] The signal Sia is input to the amplifier 10 via the matching circuit 30. The matching circuit 30 matches the output impedance of the signal processor 20 with the input impedance of the amplifier 10. The amplifier 10 amplifies the signal Sia input via the matching circuit 30, and outputs the amplified signal Soa via the matching circuit 32. The signal Soa that has passed through the matching circuit 32 is input to the synthesizer 16. The matching circuit 32 matches the output impedance of the amplifier 10 with the input impedance of the synthesizer 16. The signal Sib is input to the amplifier 11 via the matching circuit 31. The matching circuit 31 matches the output impedance of the signal processor 20 with the input impedance of the amplifier 11. The amplifier 11 amplifies the signal Sib that has passed through the matching circuit 31, and outputs the amplified signal Sob via the matching circuit 33. The signal Sob that has passed through the matching circuit 33 is input to the synthesizer 16. The matching circuit 33 matches the output impedance of the amplifier 11 with the input impedance of the synthesizer 16. The synthesizer 16 synthesizes the signal Soa with the signal Sob. The synthesized signal is output from the output terminal Tout as the output signal So.

[0048] The bias circuit 34 supplies a bias voltage Vg1 to the gate G of the amplifier 10 and suppresses the signal Sia from leaking to the bias terminal. The bias circuit 36 ​​supplies a bias voltage Vd1 to the drain D of the amplifier 10 and suppresses the signal Soa amplified by the amplifier 10 from leaking to the bias terminal. The bias circuit 35 supplies a bias voltage Vg2 to the gate G of the amplifier 11 and suppresses the signal Sib from leaking to the bias terminal. The bias circuit 37 supplies a bias voltage Vd2 to the drain D of the amplifier 11 and suppresses the signal Sob amplified by the amplifier 11 from leaking to the bias terminal.

[0049] The amplifier 10 and the amplifier 11 are provided with, for example, FET (Field Effect Transistor) 18 and FET 19, respectively. The source S of FET 18 and FET 19 is grounded, the gate G is respectively input with the signal Sia and the signal Sib via the matching circuit 30 and the matching circuit 31, and the drain D is used to output the amplified signal. FET 18 and FET 19 are, for example, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or LDMOS (Laterally Diffused Metal Oxide Semiconductor). A plurality of FETs may be provided in the amplifier 10 and the amplifier 11, respectively. The size (for example, gate width) of FET 18 of the amplifier 10 is smaller than the size (for example, gate width) of FET 19 of the amplifier 11. The matching circuit 30, the matching circuit 31, the matching circuit 32, and the matching circuit 33 are designed, for example, so that high-frequency characteristics such as drain efficiency are optimized when the amplifier 10 and the amplifier 11 output saturation power. As a result, high-frequency characteristics such as drain efficiency when the amplifiers 10 and 11 amplify the signals Sia and Sib are improved.

[0050] The signal processor 20 is, for example, a signal processing unit (Signal Processing Unit), and the signal processor 20 performs digital processing on the input signal Si and outputs the signal Sia and the signal Sib. In the out-of-phase amplifier 100, the output signal So having an amplitude of output power corresponding to the amplitude of input power of the input signal Si is output. In order to output the output signal So depending on the amplitude of the input signal Si, the signal processor 20 sets the out-of-phase angle of the signal Sia and the signal Sib depending on the amplitude of the input signal Si.

[0051] Figure 2 is a block diagram of an out-of-phase amplifier of Example 1. Figure 2 In, with Figure 1 In contrast, the diagram omits the matching circuit 30, the matching circuit 31, the bias circuit 34, the bias circuit 35, the bias circuit 36, and the bias circuit 37, and only shows the configuration within the synthesizer 16. Figure 2 As shown, in the out-of-phase amplifier 100 of the first embodiment, the combiner 16 is, for example, a Chireix combiner. The combiner 16 includes an inductor L1, a capacitor C1, an impedance converter 14, and an impedance converter 15. The capacitor C1 is connected in a branch connection to a node N1 through which the signal Soa passes. The inductor L1 is connected in a branch connection to a node N2 through which the signal Sob passes.

[0052] The first ends of the impedance converter 14 and the impedance converter 15 are connected to the node N1 and the node N2, respectively, and the second ends are connected to the node N3. At the node N3, the signal Soa and the signal Sob are synthesized. The impedance converter 14 and the impedance converter 15 convert the output impedance of the matching circuit 32 and the matching circuit 33 into twice (100Ω) of the standard impedance (for example, 50Ω), respectively. Thus, the impedance when looking from the output terminal Tout to the node N3 is the standard impedance (50Ω). The impedance converter 14 and the impedance converter 15 are, for example, transmission lines with an electrical length of λ / 4. λ is the wavelength at the center frequency of the operating frequency band of the out-of-phase amplifier 100. The electrical length of the impedance converter 14 and the impedance converter 15 is, for example, greater than 3λ / 16 and less than 5λ / 16.

[0053] The phase difference between the signal Sia and the signal Sib output by the signal processor 20 is set to θ, and the amplitude of the power of the signal Sia and the signal Sib is set to Aa and Ab respectively. When the phase difference between the signal Sia and the signal Sib is 180°, the phase difference θ is 0°, and when the phase difference between the signal Sia and the signal Sib is 0°, the phase difference θ is 90°. When the amplifier 10 and the amplifier 11 amplify the signal Sia and the signal Sib respectively and output the signal Soa and the signal Sob, the phase difference between the signal Sia and the signal Sib is the same as the phase difference between the amplified signal Soa and the signal Sob. Therefore, for the signal Soa and the signal Sob, the phase difference is also θ. The power of the signal Soa and the signal Sob input to the synthesizer 16 from the matching circuit 32 and the matching circuit 33 is set to Pa and Pb respectively. The impedance when looking at the node N1 and the node N2 from the matching circuit 32 and the matching circuit 33 is set to Za and Zb respectively.

[0054] [Comparative Example 1]

[0055] Figure 3 is a block diagram of the out-of-phase amplifier of Comparative Example 1. Figure 3 As shown in FIG. 1 , in the out-of-phase amplifier 110 of the comparative example 1, the inductor L1 and the capacitor C1 are not provided in the synthesizer 16a. Thus, the synthesizer 16a is not a Chireix synthesizer. The other structures are the same as those of the embodiment 1. Figure 2 same.

[0056] Figure 4 is a Smith chart of impedance in Comparative Example 1, and is a Smith chart of impedance Za and impedance Zb when looking toward the combiner 16a from the matching circuit 32 and the matching circuit 33. Figure 4As shown in FIG. 5 , point 50 indicates when the phase difference angle θ is 0°, and point 51 indicates when the phase difference angle θ is 90°. When the phase difference angle θ changes from 0° to 90°, the impedance Za moves from point 50 to point 51 along the trajectory of the lower half of the arc as shown by arrow 52. The impedance Zb moves from point 50 to point 51 along the trajectory of the upper half of the arc as shown by arrow 53.

[0057] Matching circuits 32 and 33 transform the output impedances of amplifiers 10 and 11 so that the high-frequency characteristics of amplifiers 10 and 11 are optimal (for example, the drain efficiency is maximized) when impedance Za and impedance Zb are real numbers (for example, twice the standard impedance). Figure 4 In the example, when the impedance Za and the impedance Zb are real numbers, the characteristics of the amplifier 10 and the amplifier 11 are maximum. At the points 50 and 51, the impedance Za and the impedance Zb are real numbers. The range of the phase difference angle θ actually used is, for example, 20° or more and 70° or less. Within this range, the reactance components (imaginary components) of the impedance Za and the impedance Zb are large, and the load impedances of the amplifiers 10 and 11 deviate from the optimal values.

[0058] If the combiner 16 a other than the Chireix combiner is used as in Comparative Example 1, the load impedances of the amplifiers 10 and 11 deviate from the optimal values ​​within the range of the out-of-phase angle actually used, and thus the efficiency and other characteristics deteriorate.

[0059] [Chilex Synthesizer]

[0060] Figure 5 is the Smith chart of impedance in Embodiment 1, which is the Smith chart of impedance Za and impedance Zb when looking toward the synthesizer 16 from the matching circuit 32 and the matching circuit 33. Figure 5 As shown, by providing capacitor C1, impedance Za is kept in an overall arc shape, which is different from that of comparative example 1. Figure 4 By providing the inductor L1, the impedance Zb is shifted to the negative direction of the reactance component and rotates clockwise on the Smith chart of impedance compared to Comparative Example 1 while maintaining the overall arc shape.

[0061] The reactance component of the impedance Za at point 50a where the phase angle θ is 0° and point 51a where the phase angle θ is 90° is positive. Within the range of the phase angle θ actually used (for example, greater than 20° and less than 70°), the impedance Za approaches the real axis and the reactance component becomes smaller. Therefore, the load impedance of the amplifier 10 is close to the optimal value. The reactance component of the impedance Zb at point 50b where the phase angle θ is 0° and point 51b where the phase angle θ is 90° is negative. Within the range of the phase angle θ actually used (for example, greater than 20° and less than 70°), the impedance Zb approaches the real axis and the reactance component becomes smaller. Therefore, the load impedance of the amplifier 11 is close to the optimal value. As a result, high-frequency characteristics such as drain efficiency are improved.

[0062] [Operation of Comparative Example 2]

[0063] The operation of the out-of-phase amplifier in Comparative Example 2 will be described. In Comparative Example 2, the amplifier 10 and the amplifier 11 have substantially the same size (for example, gate width of FET). Therefore, the saturation power of the amplifier 10 and the amplifier 11 is substantially the same. Figure 6 3 is a diagram showing the out-of-phase angle θ with respect to the output power Po in Comparative Example 2. Figure 6 The horizontal axis is the output power Po, and the vertical axis is the phase difference angle θ. Figure 7 1 is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in Comparative Example 2. Figure 7 The horizontal axis represents the output power Po of the signal So output from the output terminal Tout, and the vertical axis represents the amplitude Aa of the signal Sia and the amplitude Ab of the signal Sib output from the signal processor 20 .

[0064] like Figure 6 As shown, in Comparative Example 2, the range Rθ in which the out-of-phase angle θ changes is the range between the maximum angle θ1 and the minimum angle θ2. Figure 5 In the range Rθ, the range Rθ is determined based on the range in which the reactance components of the impedance Za and the impedance Zb do not increase. Within the range Rθ, the load impedance of the amplifier 10 and the amplifier 11 is close to the optimal value, so the degradation of high-frequency characteristics such as the drain efficiency can be suppressed. The range RP for the output power Po to change is the range between the maximum power P4 and the minimum power P5. The range RP is determined based on the range Rθ of the phase difference angle θ. That is, the maximum power P4 is the output power Po when the phase difference angle θ is the maximum angle θ1. The minimum power P5 is the output power Po when the phase difference angle θ is the minimum angle θ2. When the output power Po is the maximum power P4, the signal processor 20 sets the phase difference angle θ to the maximum angle θ1, and when the output power Po is the minimum power P5, the signal processor 20 sets the phase difference angle θ to the minimum angle θ2 which is smaller than the angle θ1. As the output power Po approaches the power P5 from the power P4, the signal processor 20 gradually sets the phase difference angle θ to be smaller.

[0065] like Figure 7 As shown, within the range RP between the maximum power P4 and the minimum power P5, the signal processor 20 sets the amplitude Aa of the signal Sia and the amplitude Ab of the signal Sib to the amplitude A@sat. The amplitude A@sat is the amplitude of the signal Sia and the signal Sib that makes the output power Pa of the amplifier 10 and the output power Pb of the amplifier 11 become the saturation power. Since the saturation powers of the amplifiers 10 and 11 are substantially the same, the amplitudes Aa and Ab are substantially the same.

[0066] Fig. 8A and Figure 8B Schematic diagram of the vector of the output power in Comparative Example 2. First, the phase difference angle is explained. When the phase of the signal Soa is rotated by +θ and the phase of the signal Sob is rotated by -θ from the state of the signal Soa and the signal Sob having a phase difference of 180°, the angle θ is called the phase difference angle. When the phase difference angle θ is 0°, the phase difference between the signal Soa and the signal Sob is 180°, and when the phase difference angle θ is 90°, the phase difference between the signal Soa and the signal Sob is 0°.

[0067] like Fig. 8A As shown, when the output power Po is the maximum power P4, the power P4 is the composite vector of the power Pa and the power Pb. The amplitude Aa of the signal Sia and the amplitude Ab of the signal Sib are the amplitude A@sat. Therefore, the power Pa and the power Pb are the saturation power P@sat of the amplifier 10 and the amplifier 11. Figure 8B As shown, when the output power Po is the minimum power P5, the phase difference angle θ is an angle θ2 which is smaller than the angle θ1. The power P5 is the composite vector of the power Pa and the power Pb. Figure 8B The angle θ2 is less than Fig. 8A The power P5 is smaller than the power P4 because of the angle θ1. The amplifier 10 and the amplifier 11 are matched so that the drain efficiency and other characteristics are improved at the saturation power P@sat. Thus, the output power Po can be changed from the maximum power P4 to the minimum power P5 while maintaining the drain efficiency and other characteristics.

[0068] For example, the maximum power P4 is 48dBm, and the minimum power P5 is 38dBm. Thus, the minimum power P5 is 10dB lower than the maximum power P4, and the dynamic range is 10dB. The dynamic range is the fluctuation range of the output power Po. For example, in amplifiers used in base stations, it is required to further improve the dynamic range according to the modulation method. In Comparative Example 2, if the dynamic range is to be increased, the range Rθ of the phase difference angle θ will be expanded. However, if the range Rθ is expanded, Figure 5 In the embodiment of the present invention, a position where the reactance components of the impedance Za and the impedance Zb become large may occur at any portion within the range Rθ.

[0069] For example, if the capacitance of capacitor C1 and the inductance of inductor L1 are reduced, Figure 5 The impedance Za in Figure 4 The counterclockwise rotation will decrease. Figure 5 The impedance Zb in Figure 4 The clockwise rotation of will become smaller. Therefore, in the center of the range Rθ, the reactance components of impedance Za and impedance Zb will become larger, and the load impedance of amplifiers 10 and 11 will deviate from the optimal value. For example, if the capacitance of capacitor C1 and the inductance of inductor L1 are increased, then Figure 5 The impedance Za in Figure 4 The counterclockwise rotation will increase. Figure 5 The impedance Zb in Figure 4 The clockwise rotation of the output power Po increases. Therefore, at the ends of the range Rθ, the reactance components of the impedance Za and the impedance Zb increase, and the load impedance of the amplifier 10 and the amplifier 11 deviates from the optimal value. In this way, in Comparative Example 2, if the dynamic range is to be increased, the high-frequency characteristics such as the drain efficiency deteriorate at any part within the range RP of the output power Po.

[0070] [Working of Example 1]

[0071] The operation of the out-of-phase amplifier in Embodiment 1 will be described. In Embodiment 1, amplifier 10 is smaller than amplifier 11. For example, the gate width of FET 18 is smaller than the gate width of FET 19. Therefore, the saturation power of amplifier 10 is smaller than the saturation power of amplifier 11. Fig. 9 1 is a diagram showing the phase difference θ of the input signal with respect to the output power Po in the first embodiment. Fig. 9 The horizontal axis is the output power Po, and the vertical axis is the phase difference angle θ. Fig.10 It is a diagram showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the first embodiment.

[0072] Fig.10 The horizontal axis represents the output power Po of the signal So output from the out-of-phase amplifier 100 , and the vertical axis represents the amplitude Aa of the signal Sia and the amplitude Ab of the signal Sib output from the signal processor 20 .

[0073] like Fig. 9 As shown, the range Rθ of the phase difference angle θ is different from that in Comparative Example 2. Figure 6 The range Rθ is the same as that of the phase difference angle θ. The maximum angle θ1 and the minimum angle θ2 are the same as those of the maximum angle θ1 and the minimum angle θ2 of Comparative Example 2. As a result, the load impedance of amplifiers 10 and 11 is close to the optimal value, so that the degradation of high-frequency characteristics such as drain efficiency can be suppressed. The range RP of the output power Po is larger than that of Comparative Example 2. Figure 7The range RP is wide. The maximum power in the output power Po is P1, and the minimum power is P2.

[0074] The maximum power P1 and the minimum power P2 of Example 1 are not necessarily the same as those of Comparative Example 2. Figure 6 The maximum power P4 and the minimum power P5 are the same. For example, the maximum power P1 is the same as the maximum power P4 in Comparative Example 2, but the minimum power P2 is smaller than the minimum power P5 in Comparative Example 2. When the output power Po is the maximum power P1, the signal processor 20 sets the out-of-phase angle θ to the maximum angle θ1, and when the output power Po is the minimum power P2, the signal processor 20 sets the out-of-phase angle θ to the minimum angle θ2 which is smaller than the maximum angle θ1. As the output power Po approaches the minimum power P2 from the maximum power P1, the signal processor 20 gradually sets the out-of-phase angle θ to be smaller. When the output power Po is the intermediate power P3, the out-of-phase angle θ is the intermediate angle θ3. Fig. 9 In the embodiment, the phase difference angle θ changes linearly with respect to the output power Po, but it may also change in a curved line.

[0075] like Fig.10 As shown, in Embodiment 1, the range RP is divided into a range RP1 and a range RP2. The range RP1 is a range where the output power Po is between the maximum power P1 and the middle power P3, and the range RP2 is a range where the output power Po is between the middle power P3 and the minimum power P2. Within the range RP1, the signal processor 20 sets the amplitude Aa of the signal Sia to the amplitude Aa@sat, and sets the amplitude Ab of the signal Sib to the amplitude Ab@sat. The amplitude Aa@sat is the amplitude Aa that makes the output power Pa of the amplifier 10 become the saturated power, and the amplitude Ab@sat is the amplitude Ab that makes the output power Pb of the amplifier 11 become the saturated power.

[0076] Since the saturation power of amplifier 10 is less than the saturation power of amplifier 11, the amplitude Aa@sat is less than the amplitude Ab@sat. Within the range RP2, the signal processor 20 sets the amplitude Aa of the signal Sia to the amplitude Aa@sat. When the output power Po is reduced from the intermediate power P3 to the minimum power P2, the signal processor 20 gradually reduces the amplitude Ab of the signal Sib from the amplitude Ab@sat to the amplitude Ab2. When the output power Po is the minimum power P2, the amplitude Ab is less than the amplitude Aa. Fig.10 In the range RP2, the amplitude Ab changes linearly with respect to the output power Po, but may also change in a curve.

[0077] FIG. 11A to FIG. 11C is a schematic diagram of the vector of the output power in Example 1. Fig.11AAs shown, when the output power Po is the maximum power P1, the phase difference angle θ is the maximum angle θ1. The maximum power P1 is the composite vector of the power Pa and the power Pb. The power Pa is the saturation power Pa@sat of the amplifier 10, and the power Pb is the saturation power Pb@sat of the amplifier 11. Fig. 11B As shown, when the output power Po is the intermediate power P3, the phase difference angle θ is the intermediate angle θ3 which is smaller than the maximum angle θ1. The intermediate power P3 is the composite vector of the power Pa and the power Pb. The power Pa is the saturation power Pa@sat of the amplifier 10, and the power Pb is the saturation power Pb@sat of the amplifier 11. Fig. 11B The angle θ3 is less than Fig.11A The angle θ1 is θ2, so the intermediate power P3 is less than the maximum power P1. In the range RP1 of the output power Po, the power Pa and the power Pb are saturated power Pa@sat and saturated power Pb@sat, respectively. Therefore, the amplifier 10 and the amplifier 11 can operate under the matching condition of the maximum high-frequency characteristics such as the drain efficiency. In addition, in the range Rθ of the out-of-phase angle θ, the reactance components of the impedance Za and the impedance Zb are small, so the high-frequency characteristics such as the drain efficiency can be improved.

[0078] like Fig. 11C As shown, when the output power Po is the minimum power P2, the phase difference angle θ is the minimum angle θ2 which is smaller than the middle angle θ3. The minimum power P2 is the composite vector of the power Pa and the power Pb. The power Pa is the saturated power Pa@sat, and the power Pb is the power Pb2 ​​which is smaller than the saturated power Pb@sat. In addition to the minimum angle θ2 being smaller than the middle angle θ3, Fig. 11C The power Pb is also less than Fig. 11B Therefore, the minimum power P2 is smaller than the middle power P3. Fig. 11C In the embodiment, the output power Po is mainly the power Pa amplified by the amplifier 10. The power Pa is the saturated power Pa@sat, so in the amplifier 10, it can operate under the matching condition where the high-frequency characteristics such as the drain efficiency are maximized. In the amplifier 11, the power Pb is a power smaller than the saturated power Pb@sat. Therefore, in the amplifier 11, the high-frequency characteristics such as the drain efficiency are reduced. However, the power Pb output by the amplifier 11 is smaller than the power Pa output by the amplifier 10, so the reduction of the high-frequency characteristics such as the drain efficiency can be suppressed in the whole of the out-of-phase amplifier 100.

[0079] [Operation of Modification 1 of Embodiment 1]

[0080] Fig.12 1 is a diagram showing the phase difference θ with respect to the output power Po in the first modification of the first embodiment. Fig. 9 Same. Fig.12 As shown in FIG. 1 , when the output power Po is the maximum power P1 and the intermediate power P3, the signal processor 20 sets the phase difference angle θ to the maximum angle θ1 and the minimum angle θ2, respectively. When the output power Po is within the range RP1, the signal processor 20 sets the phase difference angle θ in such a way that the phase difference angle θ decreases as the output power Po decreases. Fig.10 Thus, within the range RP1, the signal processor 20 sets the amplitude Aa and the amplitude Ab to the amplitude Aa@sat and the amplitude Ab@sat, respectively. Thus, within the range RP1, the output power Po can be reduced from the maximum power P1 to the intermediate power P3 as in the first embodiment.

[0081] Within the range RP2, the signal processor 20 sets the out-of-phase angle θ to a fixed minimum angle θ2. Fig.10 In this way, within the range RP2, as the output power Po approaches the minimum power P2 from the middle power P3, the signal processor 20 reduces the amplitude Ab from the amplitude Aa@sat to the amplitude Ab2. Therefore, within the range RP2, even if the phase difference angle θ is fixed, the output power Po can be reduced from the middle power P3 to the minimum power P2. Fig.12 In the range RP1, the phase difference angle θ changes linearly with respect to the output power Po, but may also change in a curve.

[0082] [Operation of Modification 2 of Embodiment 1]

[0083] Fig.13 : is a graph showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the second modification of the first embodiment. The relationship between the phase difference angle θ and the output power Po is the same as that of the first embodiment. Fig. 9 or a modification 1 of the embodiment 1 Fig.12 Same. Fig.13 As shown, it is also possible that, as the output power Po approaches the minimum power P2 from the maximum power P1, the signal processor 20 gradually decreases the amplitude Ab from the amplitude Ab@sat to the amplitude Ab2. In the second modification of the first embodiment, except when the output power Po is the maximum power P1, the amplitude Ab of the signal Sib deviates from the amplitude Ab@sat. Therefore, compared with the first embodiment and its modification 1, the high-frequency characteristics such as the drain efficiency of the amplifier 11 are worse. However, it is also possible to make the output power Po when the phase difference angle θ is the minimum angle θ2 to be the minimum power P2 which is smaller than the minimum power P5 in the second comparative example. Therefore, the dynamic range can be increased.

[0084] [Operation of Modification 3 of Embodiment 1]

[0085] Fig.14: is a graph showing the amplitude Aa and the amplitude Ab with respect to the output power Po in the third modification of the first embodiment. The relationship between the phase difference angle θ and the output power Po is the same as that of the first embodiment. Fig. 9 or a modification 1 of the embodiment 1 Fig.12 Same. Fig.14 As shown, the signal processor 20 may gradually reduce the amplitude Aa from the amplitude Aa@sat to the amplitude Aa2 as the output power Po approaches the minimum power P2 from the maximum power P1. In the modified example 3 of the embodiment 1, the amplitude Aa of the signal Sia deviates from the amplitude Aa@sat except when the output power Po is the maximum power P1. Therefore, the high-frequency characteristics such as the drain efficiency of the amplifier 10 are worse than those of the modified example 2 of the embodiment 1. However, the output power Po when the phase difference angle θ is the minimum angle θ2 may be the minimum power P2 which is smaller than the minimum power P5 in the comparative example 2. Therefore, the dynamic range can be increased.

[0086] [Example 2]

[0087] Fig.15 is a block diagram of the out-of-phase amplifier of Example 2. Fig.15 As shown, in the out-of-phase amplifier 102 of the second embodiment, in the synthesizer 16, an inductor L1 is connected in a branch at the node N1, and a capacitor C1 is connected in a branch at the node N2. The signal processor 20 reverses the phase of the signal Sia with respect to the phase of the signal Sia in the first embodiment and its modified example, and reverses the phase of the signal Sib with respect to the phase of the signal Sib in the first embodiment and its modified example. Thus, the out-of-phase amplifier of the second embodiment can operate in the same manner as the out-of-phase amplifier of the first embodiment and its modified example. The other configurations are the same as those of the first embodiment and its modified example, and the description thereof is omitted.

[0088] According to Embodiment 1 and its variations, the signal processor 20 sets the output power Po of the output signal So within a range RP between the maximum power P1 and the minimum power P2. When the output power Po is set to the maximum power P1, the amplitude Ab is set to be greater than or equal to the amplitude Aa. When the output power Po is set to the minimum power P2, the amplitude Ab is set to be less than the amplitude Aa. For example, the amplitude Ab is set to be smaller than the amplitude Aa by more than 0.1 dB or more than 0.5 dB. The phase difference angle θ1 when the output power Po is set to the maximum power P1 is set to be greater than the phase difference angle θ2 when the output power Po is set to the minimum power P2. For example, the angle θ1 is set to be greater than the angle θ2 by more than 10° or more than 20°. Thus, when the phase difference angle θ is set to the angle θ2 at which the reactance components of the impedance Za and the impedance Zb are small and the load impedance of the amplifier 10 and the amplifier 11 does not deviate significantly from the optimal value, the minimum power P2 can be smaller than the minimum power P5 in Comparative Example 2. Therefore, the dynamic range can be increased without deteriorating high-frequency characteristics such as drain efficiency.

[0089] The drain efficiency DE is taken as an example for explanation. Fig.16 This is a graph showing the drain efficiency with respect to the output voltage in Example 1 and Comparative Example 2. Fig.16 The horizontal axis is the output power Po, and the vertical axis is the drain efficiency DE. The dotted line represents Comparative Example 2, and the solid line represents Example 1. Fig.16 As shown, in Example 1 and Comparative Example 2, the maximum power P1 and the maximum power P4 in the output power Po are about the same. In Comparative Example 2, if the output power Po becomes less than the minimum power P5, the drain efficiency decreases. This is because the phase difference angle θ becomes smaller than the minimum angle θ2, the reactance components of the impedance Za and the impedance Zb become larger, and the load impedance of the amplifier 10 and the amplifier 11 deviates from the optimal value. In Example 1, even when the output power Po is the minimum power P2 smaller than the minimum power P5 in Comparative Example 2, the drain efficiency DE hardly decreases. This is because even if the phase difference angle θ is set to the minimum angle θ2, the output power Po can be set to the minimum power P2 smaller than the minimum power P5 in Comparative Example 2.

[0090] The saturation power Pa@sat of the amplifier 10 and the saturation power Pb@sat of the amplifier 11 may be substantially the same. In this case, when the phase difference angle θ is set to the minimum angle θ2, the amplitude Ab is also set to be smaller than the amplitude Aa. Thus, the output power Po can be made smaller than the minimum power P5 in Comparative Example 2. Therefore, compared with Comparative Example 2, the dynamic range can be further increased.

[0091] like Fig.10Thus, the saturation power Pa@sat of the amplifier 10 is smaller than the saturation power Pb@sat of the amplifier 11. For example, the saturation power Pa@sat is smaller than the saturation power Pb@sat by more than 1 dB. Thus, when the phase difference angle θ is made the smallest angle θ2, the output power Po can be further reduced. Therefore, the dynamic range can be further increased.

[0092] At this time, when the output power Po is set to the maximum power P1, the amplitude Ab of the signal Sob is set to be larger than the amplitude Aa of the signal Soa. Thus, when the phase difference angle θ is set to the minimum angle θ2, the output power Po can be further reduced. Therefore, the dynamic range can be further increased.

[0093] like Fig.10 and Fig.13 In this way, the signal processor 20 sets the amplitude Aa to a fixed value regardless of the output power Po. Thus, by setting the load impedance of the amplifier 10 in a manner that optimizes the high-frequency characteristics when the amplitude Aa is a fixed value, the high-frequency characteristics of the amplifier 10 can be improved. It should be noted that the amplitude Aa is fixed (or substantially fixed) as long as the amplitude Aa is fixed within a controllable range, for example, a variation of about ±1 dB of the amplitude Aa is allowed. The fixed value of the amplitude Aa can be set to a value at which the output power Po becomes a saturated power. Thus, the output power Po can be increased.

[0094] like Fig.10 In this way, when the output power Po is set within the range RP1 (first range), the signal processor 20 sets the amplitude Ab to a fixed value regardless of the output power Po. When the output power Po is set within the range RP2 (second range) smaller than the range RP1, the signal processor 20 sets the amplitude Ab in such a way that the amplitude Ab becomes smaller if the output power Po becomes smaller. Thus, by setting the load impedance of the amplifier 11 in such a way that the high-frequency characteristics are optimal when the amplitude Ab is a fixed value, the high-frequency characteristics of the amplifier 11 can be improved within the range RP2. It should be noted that, with respect to the amplitude Ab being fixed (or substantially fixed), it is sufficient as long as the amplitude Ab is fixed within a controllable range, for example, a variation of the amplitude Ab of about ±1dB is allowed. The fixed value of the amplitude Ab can be set to a value at which the output power Po becomes a saturated power. Thus, the output power Po can be increased.

[0095] Furthermore, when the output power Po is set within the range RP1, the signal processor 20 sets the amplitude Ab to be larger than the amplitude Aa. When the output power Po is set within the range RP2, the signal processor 20 sets the amplitude Ab in such a way that the amplitude Ab becomes smaller as the output power Po becomes smaller. Thus, within the range RP1, the amplifier 10 and the amplifier 11 can be operated under conditions close to the optimal operating conditions. Within the range RP2, although the amplifier 11 deviates from the optimal operating conditions compared to the amplifier 10, the output power Pb of the amplifier 11 is smaller than the output power Pa of the amplifier 10, so the degradation of the high frequency characteristics can be suppressed.

[0096] like Fig. 9 and Fig.12 In this way, the signal processor 20 sets the phase difference angle θ so that the phase difference angle θ decreases as the output power Po decreases. Thus, the output power Po can be controlled by the phase difference angle θ. Fig. 9 In this way, if the output power Po decreases, the phase difference angle θ gradually decreases. Fig.12 In this way, the out-of-phase angle θ is fixed within a part of the range RP (eg, the range RP2).

[0097] The maximum angle θ1 when the output power Po is set to the maximum power P1 is less than 90°, and the minimum angle θ2 when the output power Po is set to the minimum power P2 is greater than 0°. Thus, the reactance components of the impedance Za and the impedance Zb can be reduced within the range between the maximum angle θ1 and the minimum angle θ2. The maximum angle θ1 can be set to 80° or less, or 70° or less. The minimum angle θ2 can be set to 10° or more, or 20° or more.

[0098] The synthesizer 16 is a Chireix synthesizer, but it may not be a Chireix synthesizer. Figure 6 As described in , the drain efficiency and other characteristics can be improved.

[0099] The embodiments disclosed herein are illustrative in all aspects and are not restrictive. The scope of the present disclosure is indicated not by the above meaning but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0100] Description of Reference Numerals

[0101] Sia, Sib: signal (first signal, second signal);

[0102] Si: input signal;

[0103] Soa, Sob: signal;

[0104] So: output signal;

[0105] Po: output power;

[0106] P1, P2, P3, P4, P5: power;

[0107] Tin: input terminal;

[0108] Tout: output terminal;

[0109] θ: out-of-phase angle;

[0110] θ1, θ2, θ3: angle;

[0111] Aa, Ab: amplitude;

[0112] 10, 11: amplifiers (first amplifier, second amplifier);

[0113] 14, 15: Impedance transformer;

[0114] 16, 16a: Synthesizer;

[0115] 18, 19: FET;

[0116] 20: signal processor;

[0117] 30, 31, 32, 33: matching circuit;

[0118] 34, 36: bias circuit;

[0119] 50, 50a, 50b, 51, 51a, 51b: points;

[0120] 52, 53: arrows;

[0121] 100: Out-of-phase amplifier.

Claims

1. An out-of-phase amplifier, comprising: A first amplifier amplifies the first signal; a second amplifier, amplifying the second signal; a synthesizer that synthesizes the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputs the synthesized signal as an output signal; and A signal processor, which sets the amplitude of the second signal to be greater than or equal to the amplitude of the first signal when the output power of the output signal is set to a maximum, and sets the amplitude of the second signal to be less than the amplitude of the first signal when the output power is set to a minimum. The signal processor sets the out-of-phase angle between the first signal and the second signal when the output power is set to a maximum to be greater than the out-of-phase angle when the output power is set to a minimum, and outputs the first signal and the second signal.

2. The out-of-phase amplifier according to claim 1, wherein: The saturation power of the first amplifier is less than the saturation power of the second amplifier.

3. The out-phasing amplifier according to claim 2, wherein: When the output power is set to a maximum, the signal processor sets the amplitude of the second signal to be greater than the amplitude of the first signal.

4. The out-phasing amplifier according to any one of claims 1 to 3, wherein: When the output power is set within a first range, the signal processor sets the amplitude of the second signal to be greater than the amplitude of the first signal, and when the output power is set within a second range smaller than the first range, the signal processor sets the amplitude of the second signal in such a manner that the amplitude of the second signal decreases if the output power decreases.

5. The out-phasing amplifier according to any one of claims 1 to 4, wherein: The signal processor sets the amplitude of the first signal to a fixed value regardless of the output power.

6. The out-phasing amplifier of claim 5, wherein: When the output power is set within a first range, the signal processor sets the amplitude of the second signal to a fixed value regardless of the output power, and when the output power is set within a second range smaller than the first range, the signal processor sets the amplitude of the second signal in such a manner that the amplitude of the second signal decreases if the output power decreases.

7. The out-phasing amplifier according to any one of claims 1 to 6, wherein: The signal processor sets the out-phase angle in such a manner that the out-phase angle becomes smaller as the output power becomes smaller.

8. The out-phasing amplifier according to any one of claims 1 to 6, wherein: The synthesizer is a Chireix synthesizer.

9. The out-phasing amplifier according to any one of claims 1 to 6, wherein: The out-of-phase angle when the output power is set to the maximum is less than 90°, and the out-of-phase angle when the output power is set to the minimum is greater than 0°.

10. An out-of-phase amplifier, comprising: A first amplifier amplifies the first signal; a second amplifier, amplifying the second signal; and a synthesizer that synthesizes the first signal amplified by the first amplifier and the second signal amplified by the second amplifier, and outputs the synthesized signal as an output signal, When the output power of the output signal is maximum, the amplitude of the second signal is greater than or equal to the amplitude of the first signal, when the output power is minimum, the amplitude of the second signal is less than the amplitude of the first signal, and the out-of-phase angle between the first signal and the second signal when the output power is maximum is greater than the out-of-phase angle when the output power is minimum.

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