Concurrent frame buffer synthesis scheme

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as a GPU or DPU. The apparatus may configure a plurality of concurrent frame buffers for a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with a same frame of a plurality of frames in a scenario of the display processing operation. The apparatus may also obtain a set of display layers associated with the plurality of frames in the scene of the display processing operation. In addition, the apparatus may identify a composite mapping scheme based on the plurality of concurrent frame buffers and the display layer set. The device may also perform synthesis of one or more display layers in the set of display layers based on the synthesis mapping scheme.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize a GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and can issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0003] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0004] The following presents the summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0005] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a graphics processing unit (GPU), a display processing unit (DPU), or any device that can perform display processing. The device may receive a list of multiple concurrent frame buffers for display processing operations. The device may also configure multiple concurrent frame buffers for display processing operations, wherein all concurrent frame buffers in the multiple concurrent frame buffers are associated with the same frame of multiple frames in the scene of the display processing operation. Additionally, the device may obtain a display layer set associated with the multiple frames in the scene of the display processing operation. The device may also identify a synthesis mapping scheme based on the multiple concurrent frame buffers and the display layer set. In addition, the device may perform synthesis of one or more display layers in the display layer set based on the synthesis mapping scheme. The device may also send data associated with one or more of the following based on the synthesis of the one or more display layers: at least one display layer in the display layer set or at least one concurrent frame buffer in the multiple concurrent frame buffers.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 An example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example layer composition scheme for display processing.

[0012] Figure 6 is a diagram illustrating an example layer composition scheme for display processing.

[0013] Figure 7 is a diagram illustrating an example layer composition scheme for display processing.

[0014] Figure 8 is a diagram illustrating an example layer composition scheme for display processing.

[0015] Fig. 9 is a diagram illustrating an example layer composition scheme for display processing.

[0016] Fig.10 is a communication flow diagram illustrating example communications between a GPU, a display processing component, and a DPU.

[0017] Fig.11 is a flowchart illustrating a method of display processing.

[0018] Fig.12 is a flow chart showing an example method of processing. DETAILED DESCRIPTION

[0019] Some aspects of display processing may utilize a frame buffer to cache or store the composite output of the GPU. For example, after being synthesized at the GPU, the display layer may be cached or stored in a frame buffer. In some aspects, the synthesis hardware (HW) or software (SW) stack may use a frame buffer target to cache the synthesis output (e.g., GPU synthesis output or CPU synthesis output). The cached synthesis output may then be transmitted to another processor (e.g., DPU) as an input layer. In some cases, if the frame layer does not use a specific synthesis (e.g., GPU or client synthesis), the frame buffer may be ignored. Moreover, the layer (e.g., a frame layer or display layer associated with display processing) may be directly extracted and synthesized. For example, a DPU or hardware synthesizer may directly extract the layer and then synthesize the layer. In some aspects, certain types of frame buffers may correspond to reduced display quality (e.g., poor synthesis performance, poor power performance, poor color management, and / or poor visual quality). For example, certain types of frame buffer synthesis may not match certain power / performance specifications of certain displays (e.g., high frame rates, high layer complexity, frame geometry, standard dynamic range (SDR) / high dynamic range (HDR)), such as color management of certain displays and mobile system performance / power specifications. Some types of layer formats may lose details of certain types of synthesis (e.g., color and geometry details). For example, if 4 bytes are maintained and the 32-bit buffer alignment is not changed, the alpha channel may not be sufficient to maintain a certain level of detail. Additionally, if direct changes are made to the frame buffer, the power / performance cost may be high. In some aspects, if the frame buffer is marked as SDR, it may not meet the HDR layer synthesis specification. Moreover, if the frame buffer is marked as HDR, it may not meet the SDR layer synthesis specification, and result in poor power / performance. As indicated herein, a frame buffer that handles a certain type of layer format may not be able to fully process all layers in the synthesis. This may result in insufficient layer synthesis allocations, and the generation of certain layers that are not synthesized. Aspects of the present disclosure may utilize frame buffers that may be able to handle all types of layer formats. For example, when performing layer composition allocation, aspects of the present disclosure may utilize multiple different types of frame buffers. For example, aspects of the present disclosure may cache or store different types of layers at multiple different types of frame buffers. Additionally, in some examples, aspects of the present disclosure may utilize a composition mapping scheme to map different layers to different frame buffers during the composition process. That is, aspects presented herein may provide a composition mapping scheme for caching or storing different types of layers at multiple different types of frame buffers.

[0020] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0021] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure and do not limit the present disclosure, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0022] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0024] Therefore, in one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available medium that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0025] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0026] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. For another example, the display processing unit may be configured to synthesize, mix or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been mixed together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently mixed.

[0028] Figure 11 is a block diagram illustrating an exemplary content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this may be referred to as split rendering.

[0029] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in the graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor (such as a display processor 127) to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before being presented by one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0030] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0031] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0032] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0033] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0034] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0035] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. In addition, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0037] Reference again Figure 1 In some aspects, the processing unit 120 may include a synthesis component 198 configured to receive a list of multiple concurrent frame buffers for display processing operations. The synthesis component 198 may also be configured to configure multiple concurrent frame buffers for display processing operations, wherein all concurrent frame buffers in the multiple concurrent frame buffers are associated with the same frame in the multiple frames in the scene of the display processing operation. The synthesis component 198 may also be configured to obtain a display layer set associated with multiple frames in the scene of the display processing operation. The synthesis component 198 may also be configured to identify a synthesis mapping scheme based on the multiple concurrent frame buffers and the display layer set. The synthesis component 198 may also be configured to perform synthesis of one or more display layers in the display layer set based on the synthesis mapping scheme. The synthesis component 198 may also be configured to send data associated with one or more of the following based on the synthesis of the one or more display layers: at least one display layer in the display layer set or at least one concurrent frame buffer in the multiple concurrent frame buffers. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0038] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an onboard computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0039] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shaders, or constant data, which can adjust how the graphics context will be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0040] The context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in the pipeline based on the context register definition of the mode or state. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changed mode or state.

[0041] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220-238, but GPU 200 may include multiple additional processing units. In addition, processing units 220-238 are only examples, and any combination or order of processing units may be used in accordance with the present disclosure of the GPU. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0042] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0043] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. In addition, some types of GPUs may allow both tile rendering and direct rendering.

[0044] Figure 3 is a block diagram 300 illustrating an example display framework including a processing unit 120 , a system memory 124 , a display processor 127 , and a display 131 , as may be identified in connection with device 104 .

[0045] The GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by the CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 at the same time. The processing technology may be performed by outputting frames via the processing unit 120 over a physical or wireless communication channel.

[0046] System memory 124, which may be executed by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. The application framework may include a framework used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. Kernel space 325 may further include a display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize a frame and send data of the frame to a display.

[0047] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 may be configured to manipulate functions of display 131 (e.g., based on input received from display driver 330). Display control block 335 may be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of processing unit 120 on system memory 124.

[0048] The display interface 340 may be configured to cause the display 131 to display an image frame. The display interface 340 may output image data to the display 131 according to an interface protocol such as, for example, MIPIDSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display 131 may be configured according to the MIPIDSI standard. The MIPIDSI standard supports a video mode and a command mode. In an example where the display 131 operates in the video mode, the display processor 127 may continuously refresh the graphics content of the display 131. For example, the entire graphics content may be refreshed at each refresh cycle (e.g., line by line). In an example where the display 131 operates in the command mode, the display processor 127 may write the graphics content of the frame to the buffer 350.

[0049] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use vertical synchronization (Vsync) pulses to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse may indicate that current graphics content has been rendered at buffer 350.

[0050] Based on the display controller 345, the display client 355, and the buffer 350, the frame is displayed at the display 131. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0051] The display client 355 may be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel may output a signal to the display controller 345 indicating which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 may use the sensor output to determine the manner in which the user is interacting with the display 131. The display 131 may further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0052] Some processing techniques of device 104 may be performed through three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing technique may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process a content buffer based on the execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., display 131) that displays the frame.

[0053] Instructions (e.g., software instructions) executed by a CPU or instructions executed by a display processor may cause the CPU or display processor to search and / or generate a synthesis strategy for synthesizing a frame based on dynamic priorities and runtime statistics associated with one or more synthesis strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. In addition, the synthesis of a frame may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining multiple layers into a frame, the frame may be provided to a display panel for display on the display panel. The process of combining each layer in a plurality of layers into a frame may be referred to as synthesis, frame synthesis, synthesis procedure, synthesis process, etc.

[0054] The frame synthesis procedure or synthesis strategy may correspond to a technique for synthesizing different layers in a plurality of layers into a single frame. The plurality of layers may be stored in a double data rate (DDR) memory. Each layer in the plurality of layers may further correspond to a separate buffer. A synthesizer or hardware synthesizer (HWC) associated with a block or function may determine the input of each layer / buffer and execute the frame synthesis procedure to generate an output indicating a synthesized frame. That is, the input may be a layer, and the output may be a frame synthesis procedure for synthesizing a frame to be displayed on a display panel.

[0055] Some aspects of display processing may utilize different types of mask layers, such as shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​a mask layer may correspond to an area of ​​a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of the display area. In addition, for certain portions of the display area, the contents of different mask layers may overlap with each other. Accordingly, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0056] Figure 44 is a diagram illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that can represent portions of a display panel. Figure 4 As shown, diagram 400 includes a mask layer 402, which includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. Figure 4 As depicted, mask layer 402 may represent different areas displayed on the display panel.

[0057] Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer may reshape the display frame to provide a more optimized visual shape at the display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). In addition, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in display driver integrated circuits (DDICs) or bridge chips). In some aspects, these types of mask layers (e.g., shape mask layers) may be based on a certain unit, such as a pixel. That is, the shape generation base unit of the shape mask layer may be a single pixel.

[0058] Some aspects of display processing can utilize frame buffers to cache or store the composite output of the GPU. For example, after synthesis at the GPU, the display layer can be cached or stored in a frame buffer. In some aspects, the synthesis hardware (HW) or software (SW) stack can use a frame buffer target to cache the synthesis output (e.g., GPU synthesis output or CPU synthesis output). The cached synthesis output can then be transmitted to another processor (e.g., DPU) as an input layer. The frame buffer can have multiple different color formats, such as red (R) green (G) blue (B) α (A) (RGBA) format (e.g., RGBA8888 format). Moreover, the frame buffer can have a specific size (e.g., 32-bit triple buffer). For example, at the beginning of the display / graphics subsystem design, the frame buffer can be created as an RGBA8888 format and a 32-bit triple buffer. In some cases, if the frame layer does not use a specific synthesis (e.g., GPU or client synthesis), the frame buffer can be ignored. Moreover, the layer (e.g., a frame layer or display layer associated with the display process) can be directly extracted and synthesized. For example, a DPU or hardware synthesizer may extract the layers directly and then synthesize the layers.

[0059] Figure 5 5 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 500 depicts layer composition of display layers, where some layers (e.g., layers of a particular composition) are cached in a frame buffer and some layers are fetched and composed directly by the DPU. Figure 5 As shown, diagram 500 includes layer 510 , layer 511 , layer 512 , layer 513 , a frame buffer 530 (eg, an RGBA8888 format frame buffer), a DPU 540 , and a display 550 . Figure 5 It is depicted that layers synthesized at the GPU (i.e., layers associated with GPU synthesis) can be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 can be synthesized at the GPU and then cached / stored at frame buffer 530. Alternatively, layers that are not synthesized at the GPU (i.e., layers associated with non-GPU synthesis) can be directly extracted and synthesized at the DPU. For example, layer 513 can be directly extracted and synthesized at DPU 540. That is, layer 510, layer 511, and layer 512 can be a particular type of synthesis (e.g., GPU synthesis), while layer 513 can be another type of synthesis (non-GPU synthesis). After being cached / stored in frame buffer 530, layer 510, layer 511, and layer 512 can be transmitted to DPU 540. Further, after processing at DPU 540, layers 510 to 513 can be transmitted to display 550.

[0060] In some aspects, certain types of frame buffers (e.g., single format 32-bit RGBA8888 frame buffers) may correspond to reduced display quality (e.g., poor composition performance, poor power performance, poor color management and / or poor visual quality). For example, certain types of frame buffer composition (e.g., single format 32-bit RGBA8888 frame buffer composition) may not match certain power / performance specifications of certain displays (e.g., high frame rates, high layer complexity, frame geometry, standard dynamic range (SDR) / high dynamic range (HDR)), such as color management of certain displays and mobile system performance / power specifications. Some types of layer formats (e.g., floating point 16-bit (FP16) format, integer 12-bit (INT12) format, integer 10-bit (INT10) format) may lose details (e.g., color and geometry details) of certain types of composition (e.g., 32-bit RGBA8888 GPU composition). For example, if 4 bytes are maintained and the 32-bit buffer alignment is not changed (e.g., RGBA1010102 buffer), the alpha channel (e.g., 2-bit alpha channel) may not be sufficient to maintain a certain level of detail. Additionally, if a direct change is made to the frame buffer (e.g., to RGBA FP16161616 8-byte format), the power / performance cost may be high. In some aspects, if the frame buffer is marked as SDR, it may not meet the HDR layer composition specification. Moreover, if the frame buffer is marked as HDR, it may not meet the SDR layer composition specification and result in poor power / performance.

[0061] Figure 6 600 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 600 depicts layer composition of certain types of display layers (e.g., layers of a certain composition) and other types of display layers (e.g., layers of another composition). Figure 6As shown, diagram 600 includes a plurality of layers, such as layer 610 (e.g., 10-bit luminance (Y) chrominance (UV) (YUV) HDR format), layer 611 (e.g., 10-bit RGB protocol 3 (P3) format), layer 612 (e.g., 10-bit RGB P3 format), layer 613 (e.g., 10-bit RGB HDR format), layer 614 (e.g., FP16 RGB P3 format), layer 615 (e.g., 8-bit standard RGB (sRGB) format), and layer 616 (e.g., FP16 RGB HDR format). Diagram 600 also includes a plurality of frame buffers, such as frame buffer 630 (e.g., RGBA8888 format frame buffer), frame buffer 631 (e.g., RGBA16161616 format frame buffer), frame buffer 632 (e.g., RGBA1010102 format frame buffer), frame buffer 633 (e.g., SDR format frame buffer), and frame buffer 634 (e.g., HDR format frame buffer). In addition, Figure 6 Diagram 600 in includes a DPU 640 and a display 650 (eg, a 10-bit 1440×3200, 120 Hz, 1800 nits, HDR, organic light emitting diode (OLED) display). Figure 6 It is depicted that some frame buffers (e.g., frame buffers 630 to 634) may be sufficient for certain types of layer formats (e.g., the first layer format of layers 610 to 615), but may be insufficient for other types of layer formats (e.g., the second layer format of layer 616). As a result, the frame buffers may not be able to handle all layers in the display process, and thus layer composition may not be able to fully allocate all layers to the frame buffers. That is, frame buffers 630 to 634 may not be able to handle layer 616, and thus layer composition may not be able to fully allocate all layers 610 to 616 to frame buffers 630 to 634.

[0062] As indicated herein, a frame buffer that handles a certain type of layer format may not be able to fully handle all layers in a composition. This may result in insufficient layer composition allocations, as well as producing certain layers that are not composited. Based on the above, it may be beneficial to utilize a frame buffer that may be able to handle all types of layer formats. For example, it may be beneficial to utilize multiple different types of frame buffers when performing layer composition allocations. For example, it may be beneficial to cache or store different types of layers at multiple different types of frame buffers.

[0063] Aspects of the present disclosure may utilize frame buffers that may be capable of handling all types of layer formats. For example, when performing layer composition allocation, aspects of the present disclosure may utilize multiple different types of frame buffers. For example, aspects of the present disclosure may cache or store different types of layers at multiple different types of frame buffers. Additionally, in some instances, aspects of the present disclosure may utilize a composition mapping scheme to map different layers to different frame buffers during the composition process. That is, aspects presented herein may provide a composition mapping scheme for caching or storing different types of layers at multiple different types of frame buffers.

[0064] In some instances, aspects of the present disclosure may utilize a dynamic composition strategy including concurrent frame buffers (e.g., frame buffers that cache or store information concurrently) with separate formats and / or separate color spaces / ranges. For example, aspects presented herein may create several frame buffers (e.g., double or triple buffers) or frame buffer targets (FBTs) with different formats / color spaces / ranges. For example, a frame buffer or FBT may be created during the launch or runtime of an operating system (OS). For each display in a plurality of display devices, a frame buffer or FBT may be created separately. In addition, when applicable (e.g., based on device-specific random access memory (RAM) capabilities), frame buffers or FBTs of different formats may share a physical memory buffer. Additionally, in some instances, if a frame buffer or FBT is not created during booting, aspects presented herein may dynamically create a new frame buffer or FBT during OS runtime. Some types of frame buffers or FBTs may be configured or created during the launch or runtime of an OS. For example, an RGBA8888 display P3 / sRGB triple buffer format frame buffer may be configured or created during the launch or runtime of an OS. Moreover, a RGBA12121212 display P3 / sRGB triple buffer format frame buffer may be configured or created during launch or runtime of the OS. Additionally, a RGBA16161616 FP16 / HDR double buffer may be configured or created during launch or runtime of the OS to save memory.

[0065] In some aspects, for example, during the runtime of the OS, the aspects presented herein can dynamically determine the synthesis mapping scheme for the layer and the frame buffer / FBT. The synthesis mapping scheme (including multiple frame buffers / FBTs) can be divided into several categories. The aspects presented herein can select the best or most suitable frame buffer / FBT from the list of frame buffers / FBTs, and then use the best or most suitable frame buffer / FBT to cache GPU synthesis output (for example, if GPU synthesis is involved). The synthesis mapping strategy or the selected frame buffer / FBT can be based on multiple different categories (for example, RGB bits, color space, HDR or SDR and / or DPU hardware specifications for each layer). For example, if a certain format (for example, RGBA16161616FP16 format) is selected, the DPU can synthesize the frame buffer / FBT with other layers, or the frame buffer / FBT can be the only DPU input. Additionally, aspects presented herein may select two or more frame buffers / FBTs, and these frame buffers / FBTs (e.g., if GPU compositing is involved) may be used for the same frame compositing based on several different categories (e.g., RGB bits per layer, color space, HDR or SDR, and / or DPU hardware specifications). For example, if a certain format is selected (e.g., RGBA8888 display P3 / sRGB format or RGBA16161616 FP16 format), the DPU may composite those two concurrent frame buffers / FBTs with other layers. In addition, aspects presented herein may select one frame buffer / FBT for each window display (e.g., in a split-screen display format). For example, aspects presented herein may select a first format (e.g., RGBA8888 display P3 / sRGB format) for a first display and a second format (e.g., RGBA12121212 display P3 / sRGB format) for a second display.

[0066] Additionally, in some aspects, a compositor (e.g., an OS service compositor) may negotiate a composition mapping scheme (i.e., a frame buffer / FBT selection strategy) with a GPU or DPU via an application program interface (API) (e.g., a hardware compositor API). The compositor may transmit a list of available frame buffers / FBTs to the GPU or DPU together with a list of layers. The GPU or DPU may then determine a final composition mapping scheme or frame buffer / FBT strategy. For example, the GPU or DPU may determine or identify which frame buffer / FBT will be used for the current frame composition. Moreover, the GPU or DPU may select to determine or identify a list of layers to be synthesized for each specific frame buffer / FBT. In addition, the aspects presented herein may determine or identify a final pipeline allocation strategy for content layers and frame buffers / FBTs.

[0067] Figure 7700 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 700 depicts the composition of certain display layers (e.g., certain composited layers) at a frame buffer / FBT. Figure 7 As shown, diagram 700 includes layer 710 (e.g., 10-bit luminance (Y) chrominance (UV) (YUV) HDR format) and layer 711 (e.g., 8-bit RGB P3 format). Diagram 700 also includes frame buffer 730 (e.g., RGBA8888 format frame buffer), frame buffer 731 (e.g., RGBA12121212 format frame buffer), and frame buffer 732 (e.g., RGBA16161616 FP16 format frame buffer). In addition, Figure 7 Diagram 700 in FIG. 7 includes a DPU 740 and a display 750 (eg, a 10-bit 1440×3200 120 Hz 1800 nits HDR OLED display). Figure 7 It is depicted that layer 710 and layer 711 may be allocated to frame buffer 731. For example, a composition of layer 710 and layer 711 may be cached or stored at frame buffer 731. Figure 7 One type of composition mapping scheme for distributing the composition of one or more layers at a single frame buffer or a single FBT is shown.

[0068] Figure 8 8 is a diagram 800 illustrating an example of a layer composition scheme for display processing. More specifically, diagram 800 depicts the composition of certain display layers (e.g., certain composited layers) at different frame buffers / FBTs. Figure 8 As shown, diagram 800 includes layer 810 (e.g., 10-bit YUV HDR format), layer 811 (e.g., FP16 RGB format), layer 812 (e.g., 8-bit RGB P3 animation format), and layer 813 (e.g., 8-bit RGB P3 format). Diagram 800 also includes frame buffer 830 (e.g., RGBA12121212 format frame buffer), frame buffer 831 (e.g., RGBA16161616 FP16 format frame buffer), and frame buffer 832 (e.g., RGBA8888 format frame buffer). In addition, Figure 8 Diagram 800 in includes a DPU 840 and a display 850 (eg, a 10-bit 1440×3200 120 Hz 1800 nits HDR OLED display). Figure 8 It is depicted that layers 810 and 811 may be allocated to frame buffer 831. For example, a composite of layers 810 and 811 may be cached or stored at frame buffer 831. Additionally, layers 812 and 813 may be allocated to frame buffer 832. That is, a composite of layers 812 and 813 may be cached or stored at frame buffer 832. Figure 8One type of composition mapping scheme for allocating composition of multiple layers to multiple frame buffers or FBTs is shown.

[0069] Fig. 9 900 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 900 depicts the composition of certain display layers (e.g., certain composed layers) corresponding to different windows (e.g., windows in a split-screen display format) at different frame buffers / FBTs. Fig. 9 As shown, diagram 900 includes layer 910 (e.g., 10-bit RGB HDR format), layer 911 (e.g., 8-bit RGB animation format), layer 912 (e.g., 8-bit RGB format with blur effect), layer 913 (e.g., 8-bit RGB animation format), layer 914 (e.g., 10-bit YUV HDR format) and layer 915 (e.g., FP16 animation format). Fig. 9 It is shown that layers 910 and 911 correspond to window 920 (e.g., a window in a split screen display format), layers 912 and 913 correspond to window 921 (e.g., a window in a split screen display format), and layers 914 and 915 correspond to window 922 (e.g., a window in a split screen display format). Diagram 900 also includes a frame buffer 930 (e.g., an RGBA12121212 format frame buffer), a frame buffer 931 (e.g., an RGBA8888 format frame buffer), and a frame buffer 932 (e.g., an RGBA16161616 FP16 format frame buffer). In addition, Fig. 9 Diagram 900 in includes a DPU 940 and a display 950 (e.g., a 10-bit 1440×3200, 120 Hz, 1800 nits, HDR OLED display). Fig. 9 It is depicted that layers 910 and 911 (corresponding to window 920) may be allocated to frame buffer 930. For example, the composition of layers 910 and 911 may be cached or stored at frame buffer 930. Moreover, layers 912 and 913 (corresponding to window 921) may be allocated to frame buffer 931. That is, the composition of layers 912 and 913 may be cached or stored at frame buffer 931. In addition, layers 914 and 915 (corresponding to window 922) may be allocated to frame buffer 932 (that is, the composition of layers 914 and 915 may be cached or stored at frame buffer 932). Fig. 9 One type of composition mapping scheme for allocating composition of multiple layers (corresponding to different windows) to multiple frame buffers or FBTs is shown.

[0070] Aspects of the present disclosure may include several benefits or advantages. For example, the aspects presented herein may reduce or optimize the amount of memory allocated for layer synthesis. This reduced amount of memory may be suitable for current mobile devices. For example, the aspects presented herein may reduce the amount of memory storage used for layer synthesis allocation by 20MB or 100MB. Moreover, layer synthesis allocation may improve the relevant power, performance and / or visual quality at a processing unit (e.g., a processing unit for a mobile device). In addition, the aspects presented herein may improve the synthesis power, performance and / or visual quality at a GPU or DPU. That is, the aspects presented herein may balance the synthesis power, performance and visual quality at a GPU or DPU with the flexibility of selecting the best or most suitable frame buffer / FBT from multiple candidates of a frame buffer / FBT.

[0071] Fig.10 FIG. 1 is a communication flow diagram 1000 showing a process according to one or more techniques of the present disclosure. Fig.10 As shown, diagram 1000 includes example communications between a GPU 1002, a display processing component 1004 (eg, a component involved in a display processing operation), and a DPU 1006 (or other display processor) in accordance with one or more techniques of this disclosure.

[0072] At 1010, GPU 1002 may receive a list of multiple concurrent frame buffers for display processing operations (eg, receiving buffers 1012 from display processing component 1004). The list of multiple concurrent frame buffers may be received from at least one component associated with the display processing operation.

[0073] At 1020, GPU 1002 may configure a plurality of concurrent frame buffers for display processing operations, wherein all of the plurality of concurrent frame buffers are associated with the same frame of a plurality of frames in a scene of the display processing operation. In some instances, configuring the plurality of concurrent frame buffers may include selecting the plurality of concurrent frame buffers from a list of the plurality of concurrent frame buffers. Each of the plurality of concurrent frame buffers (e.g., frame buffers that cache or store information concurrently) may be associated with one of a plurality of color formats or a plurality of color coordinates. The plurality of color formats may include at least one of: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format, or luminance (Y) chrominance (UV) (YUV) color format, and the plurality of color coordinates may include one or more XYZ color coordinates. Additionally, the plurality of concurrent frame buffers may be dynamically configured during runtime of an operating system (OS) associated with the display processing operation. Furthermore, configuring the plurality of concurrent frame buffers for the display processing operation may include generating the plurality of concurrent frame buffers for the display processing operation at a graphics processing unit (GPU). In addition, the plurality of concurrent frame buffers may correspond to a plurality of frame buffer targets (FBTs) or a plurality of concurrent FBTs.

[0074] At 1030, GPU 1002 may obtain a set of display layers associated with a plurality of frames in a scene of a display processing operation. In some aspects, obtaining the set of display layers associated with the plurality of frames may include receiving the set of display layers associated with the plurality of frames from at least one rendering component associated with the display processing operation.

[0075] At 1040, GPU 1002 may identify a composition mapping scheme based on the multiple concurrent frame buffers and the display layer set. The composition mapping scheme may be a frame buffer target (FBT) composition mapping scheme. Moreover, identifying the composition mapping scheme may include negotiating the composition mapping scheme with at least one component in an operating system (OS) associated with a display processing operation. In addition, negotiating the composition mapping scheme with at least one component in the OS may include sending one or more layer lists to at least one component in the OS, wherein the composition mapping scheme is negotiated based on the one or more layer lists. In addition, the composition mapping scheme may map at least two display layers in the display layer set to a first concurrent frame buffer in the multiple concurrent frame buffers.

[0076] At 1050 , GPU 1002 may perform composition of one or more display layers in the display layer set based on the composition mapping scheme.

[0077] At 1060, GPU 1002 may send data associated with one or more of: at least one display layer in the display layer set or at least one concurrent frame buffer in the plurality of concurrent frame buffers based on the composition of the one or more display layers (e.g., sending data 1062 to DPU 1006). The at least one display layer may not be included in the one or more display layers. Moreover, the at least one concurrent frame buffer may include all concurrent frame buffers in the plurality of concurrent frame buffers.

[0078] Fig.11 1100 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a GPU (or other graphics processor), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10 The examples are performed using any device that displays the process.

[0079] At 1104, the GPU may configure a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with the same frame of a plurality of frames in a scene of the display processing operation, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in 1020 of the embodiment, GPU 1002 may configure multiple concurrent frame buffers for display processing operations, wherein all concurrent frame buffers in the multiple concurrent frame buffers are associated with the same frame in the multiple frames in the scene of the display processing operation. In addition, step 1104 may be performed by Figure 1, executed by the processing unit 120 in . In some instances, configuring multiple concurrent frame buffers may include: selecting multiple concurrent frame buffers from a list of multiple concurrent frame buffers. Each concurrent frame buffer in the multiple concurrent frame buffers (e.g., frame buffers that cache or store information concurrently) may be associated with one of multiple color formats or multiple color coordinates. The multiple color formats may include at least one of the following: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format, or luminance (Y) chrominance (UV) (YUV) color format, and the multiple color coordinates may include one or more XYZ color coordinates. Additionally, the multiple concurrent frame buffers may be dynamically configured during runtime of an operating system (OS) associated with the display processing operation. Furthermore, configuring multiple concurrent frame buffers for display processing operations may include generating multiple concurrent frame buffers for display processing operations at a graphics processing unit (GPU). In addition, the multiple concurrent frame buffers may correspond to multiple frame buffer targets (FBTs) or multiple concurrent FBTs.

[0080] At 1106, the GPU may obtain a set of display layers associated with a plurality of frames in a scene of display processing operations, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in step 1030, GPU 1002 may obtain a display layer set associated with multiple frames in a scene of a display processing operation. In addition, step 1106 may be performed by Figure 1 In some aspects, obtaining the display layer set associated with the plurality of frames may include: receiving the display layer set associated with the plurality of frames from at least one rendering component associated with the display processing operation.

[0081] At 1108, the GPU may identify a composition mapping scheme based on multiple concurrent frame buffers and display layer sets, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in 1040 of , GPU 1002 may identify a synthesis mapping scheme based on multiple concurrent frame buffers and display layer sets. In addition, step 1108 may be performed by Figure 1The processing unit 120 in the display processing unit 120 is executed. The synthesis mapping scheme may be a frame buffer target (FBT) synthesis mapping scheme. Moreover, identifying the synthesis mapping scheme may include: negotiating the synthesis mapping scheme with at least one component in an operating system (OS) associated with the display processing operation. In addition, negotiating the synthesis mapping scheme with at least one component in the OS may include: sending one or more layer lists to at least one component in the OS, wherein the synthesis mapping scheme is negotiated based on the one or more layer lists. In addition, the synthesis mapping scheme may map at least two display layers in the display layer set to a first concurrent frame buffer in a plurality of concurrent frame buffers.

[0082] At 1110, the GPU may perform composition of one or more display layers in the display layer set based on a composition mapping scheme, such as in combination with Figures 1 to 10 For example, as described in Fig.10 As described in 1050 of the embodiment, GPU 1002 may perform synthesis of one or more display layers in the display layer set based on the synthesis mapping scheme. In addition, step 1110 may be performed by Figure 1 The processing unit 120 in is executed.

[0083] Fig.12 1200 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a GPU (or other graphics processor), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10 The examples are performed using any device that displays the process.

[0084] At 1202, the GPU may receive a list of multiple concurrent frame buffers for display processing operations, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in 1010 of the embodiment, GPU 1002 may receive a list of multiple concurrent frame buffers for display processing operations. In addition, step 1202 may be performed by Figure 1 The processing unit 120 in the embodiment of the present invention is executed. The list of multiple concurrent frame buffers may be received from at least one component associated with the display processing operation.

[0085] At 1204, the GPU may configure a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with the same frame of a plurality of frames in a scene of the display processing operation, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10As described in 1020 of the embodiment, GPU 1002 may configure multiple concurrent frame buffers for display processing operations, wherein all concurrent frame buffers in the multiple concurrent frame buffers are associated with the same frame in the multiple frames in the scene of the display processing operation. In addition, step 1204 may be performed by Figure 1 , executed by the processing unit 120 in . In some instances, configuring multiple concurrent frame buffers may include: selecting multiple concurrent frame buffers from a list of multiple concurrent frame buffers. Each concurrent frame buffer in the multiple concurrent frame buffers (e.g., frame buffers that cache or store information concurrently) may be associated with one of multiple color formats or multiple color coordinates. The multiple color formats may include at least one of the following: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format, or luminance (Y) chrominance (UV) (YUV) color format, and the multiple color coordinates may include one or more XYZ color coordinates. Additionally, the multiple concurrent frame buffers may be dynamically configured during runtime of an operating system (OS) associated with the display processing operation. Furthermore, configuring multiple concurrent frame buffers for display processing operations may include generating multiple concurrent frame buffers for display processing operations at a graphics processing unit (GPU). In addition, the multiple concurrent frame buffers may correspond to multiple frame buffer targets (FBTs) or multiple concurrent FBTs.

[0086] At 1206, the GPU may obtain a set of display layers associated with a plurality of frames in a scene of display processing operations, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in step 1030, GPU 1002 may obtain a display layer set associated with multiple frames in a scene of a display processing operation. In addition, step 1206 may be performed by Figure 1 In some aspects, obtaining the display layer set associated with the plurality of frames may include: receiving the display layer set associated with the plurality of frames from at least one rendering component associated with the display processing operation.

[0087] At 1208, the GPU may identify a composition mapping scheme based on multiple concurrent frame buffers and display layer sets, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in 1040 of , GPU 1002 may identify a synthesis mapping scheme based on multiple concurrent frame buffers and display layer sets. In addition, step 1208 may be performed by Figure 1The processing unit 120 in the display processing unit 120 is executed. The synthesis mapping scheme may be a frame buffer target (FBT) synthesis mapping scheme. Moreover, identifying the synthesis mapping scheme may include: negotiating the synthesis mapping scheme with at least one component in an operating system (OS) associated with the display processing operation. In addition, negotiating the synthesis mapping scheme with at least one component in the OS may include: sending one or more layer lists to at least one component in the OS, wherein the synthesis mapping scheme is negotiated based on the one or more layer lists. In addition, the synthesis mapping scheme may map at least two display layers in the display layer set to a first concurrent frame buffer in a plurality of concurrent frame buffers.

[0088] At 1210, the GPU may perform composition of one or more display layers in the display layer set based on a composition mapping scheme, such as in combination with Figures 1 to 10 For example, as described in Fig.10 As described in 1050 of FIG. 1 , GPU 1002 may perform synthesis of one or more display layers in the display layer set based on the synthesis mapping scheme. In addition, step 1210 may be performed by Figure 1 The processing unit 120 in is executed.

[0089] At 1212, the GPU may send data associated with one or more of: at least one display layer in a display layer set or at least one concurrent frame buffer in a plurality of concurrent frame buffers based on the composition of the one or more display layers, such as in conjunction with Figures 1 to 10 For example, as described in Fig.10 As described in 1060 of , GPU 1002 may send data associated with one or more of the following based on the composition of one or more display layers: at least one display layer in the display layer set or at least one concurrent frame buffer in the plurality of concurrent frame buffers. In addition, step 1212 may be performed by Figure 1 The processing unit 120 in the embodiment of the present invention is executed. At least one display layer may not be included in the one or more display layers. Moreover, at least one concurrent frame buffer may include all concurrent frame buffers in the plurality of concurrent frame buffers.

[0090] In various configurations, a method or apparatus for display processing is provided. The apparatus may be a GPU (or other graphics processor), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within a device 104 or another device. The apparatus (e.g., processing unit 120) may include a component for configuring a plurality of concurrent frame buffers for display processing operations, wherein all of the plurality of concurrent frame buffers are associated with the same frame of a plurality of frames in a scene of a display processing operation. The apparatus (e.g., processing unit 120) may also include a component for obtaining a display layer set associated with a plurality of frames in a scene of a display processing operation. The apparatus (e.g., processing unit 120) may also include a component for identifying a synthesis mapping scheme based on a plurality of concurrent frame buffers and a display layer set. The apparatus (e.g., processing unit 120) may also include a component for performing synthesis of one or more display layers in a display layer set based on a synthesis mapping scheme. The device (e.g., processing unit 120) may also include means for sending data associated with one or more of: at least one display layer in the display layer set or at least one concurrent frame buffer in the plurality of concurrent frame buffers based on the composition of the one or more display layers. The device (e.g., processing unit 120) may also include means for receiving a list of the plurality of concurrent frame buffers for display processing operations.

[0091] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing techniques described can be used by a GPU, a CPU, a DPU, a display processor, or some other processor that can perform display processing to implement the concurrent frame buffer synthesis techniques described herein. Compared with other display processing techniques, this can also be implemented at a low cost. Moreover, the display processing techniques of this article can improve or accelerate data processing or execution. In addition, the display processing techniques of this article can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize concurrent frame buffer synthesis techniques to improve memory bandwidth efficiency and / or increase processing speed at a GPU or DPU.

[0092] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged based on design preferences. Further, some blocks can be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0093] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0094] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," "device," etc. cannot replace the word "component." Therefore, no claim element will be understood as a component plus function unless the element is explicitly stated using the phrase "component for..."

[0095] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent on a computer-readable medium as one or more instructions or codes.

[0096] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used with some features disclosed herein but not others, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0097] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0098] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Additionally, these techniques may be fully implemented in one or more circuits or logic elements.

[0099] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with suitable software and / or firmware. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0100] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0101] Aspect 1 is a device for display processing, comprising: a memory; and at least one processor, the at least one processor being coupled to the memory, and being configured, at least in part based on information stored in the memory, to: configure multiple concurrent frame buffers for display processing operations, wherein all concurrent frame buffers in the multiple concurrent frame buffers are associated with the same frame among multiple frames in a scene of the display processing operation; obtain a display layer set associated with the multiple frames in the scene of the display processing operation; identify a synthesis mapping scheme based on the multiple concurrent frame buffers and the display layer set; and perform synthesis of one or more display layers in the display layer set based on the synthesis mapping scheme.

[0102] Aspect 2 is a device according to Aspect 1, wherein the at least one processor is further configured to: send data associated with one or more of the following based on the synthesis of the one or more display layers: at least one display layer in the display layer set or at least one concurrent frame buffer among the multiple concurrent frame buffers.

[0103] Aspect 3 is an apparatus according to any one of Aspects 1 and 2, wherein the at least one display layer is not included in the one or more display layers, and wherein the at least one concurrent frame buffer includes all concurrent frame buffers of the plurality of concurrent frame buffers.

[0104] Aspect 4 is an apparatus according to any one of aspects 1 to 3, wherein the synthesis mapping scheme maps at least two display layers in the display layer set to a first concurrent frame buffer in the plurality of concurrent frame buffers.

[0105] Aspect 5 is a device according to any one of Aspects 1 to 4, wherein the at least one processor is further configured to: receive a list of the multiple concurrent frame buffers used for the display processing operation, and wherein in order to configure the multiple concurrent frame buffers, the at least one processor is configured to: select the multiple concurrent frame buffers from the list of the multiple concurrent frame buffers.

[0106] Aspect 6 is an apparatus according to any one of aspects 1 to 5, wherein the list of the plurality of concurrent frame buffers is received from at least one component associated with the display processing operation.

[0107] Aspect 7 is an apparatus according to any one of aspects 1 to 6, wherein the composition mapping scheme is a frame buffer target (FBT) composition mapping scheme.

[0108] Aspect 8 is an apparatus according to any one of Aspects 1 to 7, wherein, in order to identify the synthetic mapping scheme, the at least one processor is configured to: negotiate the synthetic mapping scheme with at least one component in an operating system (OS) associated with the display processing operation.

[0109] Aspect 9 is a device according to any one of Aspects 1 to 8, wherein in order to negotiate the synthetic mapping scheme with the at least one component in the OS, the at least one processor is configured to: send one or more layer lists to the at least one component in the OS, wherein the synthetic mapping scheme is negotiated based on the one or more layer lists.

[0110] Aspect 10 is the apparatus of any one of aspects 1 to 9, wherein each concurrent frame buffer of the plurality of concurrent frame buffers is associated with one of a plurality of color formats or a plurality of color coordinates.

[0111] Aspect 11 is a device according to any one of Aspects 1 to 10, wherein the multiple color formats include at least one of the following: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format or luminance (Y) chrominance (UV) (YUV) color format, and wherein the multiple color coordinates include one or more XYZ color coordinates.

[0112] Aspect 12 is a device according to any one of Aspects 1 to 11, wherein in order to obtain the display layer set associated with the multiple frames, the at least one processor is configured to: receive the display layer set associated with the multiple frames from at least one rendering component associated with the display processing operation.

[0113] Aspect 13 is an apparatus according to any one of aspects 1 to 12, wherein the plurality of concurrent frame buffers are dynamically configured during runtime of an operating system (OS) associated with the display processing operation.

[0114] Aspect 14 is a device according to any one of Aspects 1 to 13, wherein in order to configure the multiple concurrent frame buffers for the display processing operation, the at least one processor is configured to: generate the multiple concurrent frame buffers for the display processing operation at a graphics processing unit (GPU).

[0115] Aspect 15 is an apparatus according to any one of aspects 1 to 14, wherein the plurality of concurrent frame buffers corresponds to a plurality of concurrent frame buffer targets (FBTs).

[0116] Aspect 16 is an apparatus according to any one of aspects 1 to 15, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

[0117] Aspect 17 is a method for implementing the display processing of any one of aspects 1 to 16.

[0118] Aspect 18 is an apparatus for display processing, comprising means for implementing any one of aspects 1 to 16.

[0119] Aspect 19 is a computer-readable medium (eg, non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 16.

Claims

1. A device for display processing, the device comprising: Memory; and at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: configuring a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with a same frame of a plurality of frames in a scene of the display processing operation; obtaining a set of display layers associated with the plurality of frames in the scene of the display processing operation; identifying a composition mapping scheme based on the plurality of concurrent frame buffers and the set of display layers; as well as Composition of one or more display layers in the set of display layers is performed based on the composition mapping scheme.

2. The apparatus of claim 1 , wherein the at least one processor is further configured to: Data associated with one or more of: at least one display layer in the set of display layers or at least one concurrent frame buffer in the plurality of concurrent frame buffers is sent based on the composition of the one or more display layers.

3. The apparatus of claim 2, wherein the at least one display layer is not included in the one or more display layers, and wherein the at least one concurrent frame buffer comprises all concurrent frame buffers of the plurality of concurrent frame buffers. 4 . The apparatus of claim 1 , wherein the composition mapping scheme maps at least two display layers in the set of display layers to a first concurrent frame buffer in the plurality of concurrent frame buffers.

5. The apparatus of claim 1 , wherein the at least one processor is further configured to: A list of the plurality of concurrent frame buffers for the display processing operation is received, and wherein to configure the plurality of concurrent frame buffers, the at least one processor is configured to select the plurality of concurrent frame buffers from the list of the plurality of concurrent frame buffers.

6. The apparatus of claim 5, wherein the list of the plurality of concurrent frame buffers is received from at least one component associated with the display processing operation.

7. The apparatus of claim 1, wherein the composition mapping scheme is a frame buffer target (FBT) composition mapping scheme.

8. The apparatus of claim 1, wherein to identify the composite mapping scheme, the at least one processor is configured to: negotiate the composite mapping scheme with at least one component in an operating system (OS) associated with the display processing operation.

9. An apparatus according to claim 8, wherein, in order to negotiate the synthetic mapping scheme with the at least one component in the OS, the at least one processor is configured to: send one or more layer lists to the at least one component in the OS, wherein the synthetic mapping scheme is negotiated based on the one or more layer lists.

10. The device of claim 1, wherein each concurrent frame buffer of the plurality of concurrent frame buffers is associated with one of a plurality of color formats or a plurality of color coordinates.

11. The device of claim 10, wherein the plurality of color formats comprises at least one of: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format, or luminance (Y) chrominance (UV) (YUV) color format, and wherein the plurality of color coordinates comprises one or more XYZ color coordinates.

12. The apparatus of claim 1, wherein, in order to obtain the display layer set associated with the plurality of frames, the at least one processor is configured to: receive the display layer set associated with the plurality of frames from at least one rendering component associated with the display processing operation.

13. The apparatus of claim 1, wherein the plurality of concurrent frame buffers are dynamically configured during runtime of an operating system (OS) associated with the display processing operation.

14. The apparatus of claim 1, wherein to configure the plurality of concurrent frame buffers for the display processing operation, the at least one processor is configured to: generate the plurality of concurrent frame buffers for the display processing operation at a graphics processing unit (GPU).

15. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, and wherein the plurality of concurrent frame buffers corresponds to a plurality of concurrent frame buffer targets (FBTs).

16. A method of display processing, the method comprising: configuring a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with a same frame of a plurality of frames in a scene of the display processing operation; obtaining a set of display layers associated with the plurality of frames in the scene of the display processing operation; identifying a composition mapping scheme based on the plurality of concurrent frame buffers and the set of display layers; as well as Composition of one or more display layers in the set of display layers is performed based on the composition mapping scheme.

17. The method according to claim 16, further comprising: Data associated with one or more of: at least one display layer in the set of display layers or at least one concurrent frame buffer in the plurality of concurrent frame buffers is sent based on the composition of the one or more display layers.

18. The method of claim 17, wherein the at least one display layer is not included in the one or more display layers, and wherein the at least one concurrent frame buffer includes all concurrent frame buffers of the plurality of concurrent frame buffers.

19. The method of claim 16, wherein the composition mapping scheme maps at least two display layers in the set of display layers to a first concurrent frame buffer in the plurality of concurrent frame buffers.

20. The method of claim 16, further comprising: A list of the plurality of concurrent frame buffers for the display processing operation is received, and wherein configuring the plurality of concurrent frame buffers comprises selecting the plurality of concurrent frame buffers from the list of the plurality of concurrent frame buffers.

21. The method of claim 20, wherein the list of the plurality of concurrent frame buffers is received from at least one component associated with the display processing operation.

22. The method of claim 16, wherein the composition mapping scheme is a frame buffer target (FBT) composition mapping scheme.

23. The method of claim 16, wherein identifying the composite mapping scheme comprises: The composition mapping scheme is negotiated with at least one component in an operating system (OS) associated with the display processing operation.

24. The method of claim 23, wherein negotiating the composite mapping scheme with the at least one component in the OS comprises: One or more layer lists are sent to the at least one component in the OS, wherein the composite mapping scheme is negotiated based on the one or more layer lists.

25. The method of claim 16, wherein each concurrent frame buffer of the plurality of concurrent frame buffers is associated with one of a plurality of color formats or a plurality of color coordinates.

26. A method according to claim 25, wherein the multiple color formats include at least one of the following: red (R), green (G), blue (B), alpha (A) (RGBA) color format, RGBA8888 color format, RGBA12121212 color format, RGBA16161616 color format, high dynamic range (HDR) color format, RGB color format or luminance (Y) chrominance (UV) (YUV) color format, and wherein the multiple color coordinates include one or more XYZ color coordinates.

27. The method of claim 16, wherein obtaining the set of display layers associated with the plurality of frames comprises: The set of display layers associated with the plurality of frames is received from at least one rendering component associated with the display processing operation, and wherein the plurality of concurrent frame buffers are dynamically configured during runtime of an operating system (OS) associated with the display processing operation.

28. The method of claim 16, wherein configuring the plurality of concurrent frame buffers for the display processing operation comprises generating the plurality of concurrent frame buffers for the display processing operation at a graphics processing unit (GPU), and wherein the plurality of concurrent frame buffers correspond to a plurality of concurrent frame buffer targets (FBTs).

29. An apparatus for display processing, the apparatus comprising: means for configuring a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with a same frame of a plurality of frames in a scene of the display processing operation; means for obtaining a set of display layers associated with the plurality of frames in the scene of the display processing operation; means for identifying a composition mapping scheme based on the plurality of concurrent frame buffers and the set of display layers; and Means for performing composition of one or more display layers in the set of display layers based on the composition mapping scheme.

30. A computer readable medium storing computer executable code for display processing, the code when executed by a processor causing the processor to: configuring a plurality of concurrent frame buffers for use in a display processing operation, wherein all of the plurality of concurrent frame buffers are associated with a same frame of a plurality of frames in a scene of the display processing operation; obtaining a set of display layers associated with the plurality of frames in the scene of the display processing operation; identifying a composition mapping scheme based on the plurality of concurrent frame buffers and the set of display layers; as well as Composition of one or more display layers in the set of display layers is performed based on the composition mapping scheme.

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