Printed circuit board including first portion and second portion having pillar extending from first portion

Abstract

A printed circuit board (100) for an electronic device, comprising: a first portion (110) comprising an upper plate (112) having a first width (w1) in a lateral direction of the upper plate (112); and a second portion (120) integrally formed with the first portion (110) as a single body, the second portion (120) comprising one or more struts (122) extending vertically from the first portion (110) and disposed in a lateral direction between a first end (114) of the upper plate (112) and a second end (116) of the upper plate (112). Each of the one or more struts (122) has a second width (w2) in the lateral direction that is narrower (w1) than the first width.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a printed circuit board structure including the printed circuit board (PCB). The printed circuit board structure can be implemented in an electronic device such as a wearable computing device, a smart phone, a camera, etc. Background Art

[0002] Various methods can be used to accommodate electronic components (such as printed circuit board structures) inside the body of an electronic device. For example, some methods include providing an interposer board that uses a connector to connect to a main logic board. However, the connector has several limitations. For example, since more signals need to be carried to the main logic board, the connector must be made longer. In addition, the mating height of some connectors (e.g., board-to-board (BTB) connectors or zero insertion force (ZIF) connectors) may be limited in terms of the mating heights that can be selected from. The connector also requires screws to fix the interposer board. Another method for accommodating a printed circuit board structure inside the body of an electronic device includes a sandwich stacked PCB design. However, this configuration requires precise alignment of the individual components. Additionally, the manufacturing process for sandwich stacked PCBs is complex because multiple individual components must be precisely aligned when forming the sandwich stacked PCB and fastening elements (such as screws) are required to secure the components together. Summary of the invention

[0003] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the description which follows, or may be learned from the description, or may be learned through practice of example embodiments.

[0004] In one or more example embodiments, a printed circuit board includes: a first portion, the first portion including an upper plate, the upper plate having a first width in a widthwise direction of the upper plate; and a second portion, the second portion is integrally formed with the first portion as a single body, the second portion including one or more pillars, the one or more pillars extending vertically from the first portion and arranged between a first end of the upper plate and a second end of the upper plate in the widthwise direction. Each of the one or more pillars has a second width in the widthwise direction, the second width being narrower than the first width.

[0005] In some implementations of the printed circuit board, the one or more pillars include a pillar disposed at a central portion of the upper board in a lateral direction.

[0006] In some implementations of the printed circuit board, the second portion includes a plurality of pillars, the plurality of pillars including a first pillar disposed adjacent to the first end of the upper plate and a second pillar disposed adjacent to the second end of the upper plate. In some implementations, the plurality of pillars includes a third pillar disposed in a central portion of the upper plate between the first pillar and the second pillar in a lateral direction.

[0007] In some implementations of the printed circuit board, the printed circuit board can be coupled to a main logic board such that when the printed circuit board is coupled to the main logic board, the first pillar is coupled to the main logic board at an angle inclined relative to the second pillar, and the first pillar and the second pillar are coupled to the main logic board at corresponding angles inclined relative to the third pillar.

[0008] In some implementations of the printed circuit board, each of the one or more pillars has a vertical height from an end of the pillar extending vertically from the first portion to a distal end of the pillar that is less than or equal to about 3.0 mm.

[0009] In some implementations of the printed circuit board, the printed circuit board includes at least ten layers, the upper plate includes at least four layers of the at least ten layers, and the one or more pillars include at least six layers of the at least ten layers.

[0010] In some implementations of the printed circuit board, the distal end of each of the one or more pillars includes at least fifty pins, and the second width is less than about 9 mm.

[0011] In one or more example embodiments, an electronic device includes: a main body; and a printed circuit board structure, the printed circuit board structure being disposed within the main body. The printed circuit board structure includes a main logic board and a printed circuit board. The printed circuit board includes: a first portion, the first portion including an upper plate, the upper plate having a first width in a lateral direction of the upper plate; and a second portion, the second portion being integrally formed with the first portion as a single body, the second portion including one or more pillars, the one or more pillars being coupled to the main logic board, extending vertically between the main logic board and the first portion, and being disposed in a lateral direction between a first end of the upper plate and a second end of the upper plate, wherein each of the one or more pillars has a second width in a lateral direction, the second width being narrower than the first width.

[0012] In some implementations of the electronic device, the one or more pillars include a pillar disposed at a central portion of the upper plate in a lateral direction.

[0013] In some implementations of the electronic device, the second portion includes a plurality of pillars, the plurality of pillars including a first pillar disposed adjacent to the first end of the upper plate and a second pillar disposed adjacent to the second end of the upper plate. In some implementations, the plurality of pillars includes a third pillar disposed in a central portion of the upper plate between the first pillar and the second pillar in a lateral direction.

[0014] In some implementations of the electronic device, the first support leg is coupled to the main logic board at an angle oblique to the second support leg, and the first support leg and the second support leg are coupled to the main logic board at respective angles oblique to the third support leg.

[0015] In some implementations of the electronic device, each of the one or more posts extends a vertical height from the main logic board to the first portion that is less than or equal to approximately 3.0 mm.

[0016] In one or more example embodiments, a method for manufacturing a printed circuit board structure includes: providing a laminated structured core, the laminated structured core including a first plurality of layers, a second plurality of layers, and one or more cores disposed between the first plurality of layers and the second plurality of layers; removing a first portion of the second plurality of layers at a first position of the laminated structured core; and removing a second portion of the second plurality of layers at a second position of the laminated structured core, such that the portion of the second plurality of layers located between the first position and the second position forms at least a portion of a pillar extending vertically from the portion of the laminated structured core including the first plurality of layers.

[0017] In some embodiments, providing a laminated structured core includes: providing a structured core including a first plurality of layers; applying a release layer to at least a portion of an upper surface of the structured core; and laminating a second plurality of layers onto the upper surface of the structured core to which at least the portion of the upper surface of the structured core has been applied the release layer, to obtain a laminated structured core.

[0018] In some implementations of the method, removing a first portion of the second plurality of layers at a first location of the laminated structural core and removing a second portion of the second plurality of layers at a second location of the laminated structural core are performed by a mechanical milling process or a de-cap process.

[0019] In some implementations of the method, each of the first portion of the second plurality of layers and the second portion of the second plurality of layers extends to the release layer.

[0020] In some implementations, the method further includes coupling the support leg to a main logic board.

[0021] In some implementations of the method, a vertical height of the support pillar extending from the primary logic board to the portion of the laminated structural core including the first plurality of layers is less than or equal to about 3.0 mm.

[0022] These and other features, aspects and advantages of various embodiments of the present disclosure will be better understood with reference to the following description, drawings and appended claims.The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, serve to explain the relevant principles. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] A detailed discussion of example embodiments for persons of ordinary skill in the art is set forth in this specification with reference to the accompanying drawings, in which:

[0024] Figure 1 depicts an example printed circuit board according to one or more example embodiments of the present disclosure;

[0025] FIG. 2A to FIG. 2B depicts an example board-to-board connector according to one or more example embodiments of the present disclosure;

[0026] Figure 2C depicts an example printed circuit board according to one or more example embodiments of the present disclosure;

[0027] FIG. 3A to FIG. 3B Depicts an example printed circuit board structure and pin configuration of a printed circuit board according to one or more example embodiments of the present disclosure;

[0028] FIG. 4A to FIG. 4B Depicts an example printed circuit board structure and pin configuration of a printed circuit board according to one or more example embodiments of the present disclosure;

[0029] FIG. 5A to FIG. 5B Depicts an example printed circuit board structure and pin configuration of a printed circuit board according to one or more example embodiments of the present disclosure;

[0030] 6A to 6F An example method for manufacturing a printed circuit board by a milling decapping process according to one or more example embodiments of the present disclosure is depicted;

[0031] 7A to 7F An example method for manufacturing a printed circuit board by a laser decapping process according to one or more example embodiments of the present disclosure is depicted;

[0032] FIG. 8A to FIG. 8C An example method for manufacturing a printed circuit board by a milling process according to one or more example embodiments of the present disclosure is depicted;

[0033] 9A to 9CAn example via configuration according to one or more example embodiments of the present disclosure is depicted in plan view;

[0034] FIG. 10A to FIG. 10D Example impedance simulation results relating to various via configurations according to one or more example embodiments of the present disclosure;

[0035] FIG. 11A to FIG. 11C depicts an example stacked layer structure of a printed circuit board according to one or more example embodiments of the present disclosure;

[0036] Fig.12 depicts an example cross-section of a stacked layer structure of a printed circuit board according to one or more example embodiments of the present disclosure;

[0037] Fig.13 depicts a plan view of an example pin array configuration for a printed circuit board according to one or more example embodiments of the present disclosure;

[0038] Fig.14 A flow chart illustrating an example non-limiting method for manufacturing a laminated structural core according to one or more example embodiments of the present disclosure;

[0039] Fig.15 A flowchart illustrating an example non-limiting method for manufacturing a printed circuit board according to one or more example embodiments of the present disclosure; and

[0040] FIG. 16 depicts an example view of an electronic device having a printed circuit board structure according to one or more example embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] Reference will now be made to embodiments of the present disclosure, one or more examples of which are illustrated in the accompanying drawings, wherein similar reference numerals represent similar elements. Each example is provided by way of explanation of the present disclosure, and is not intended to limit the present disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations may be made to the present disclosure without departing from the scope or spirit of the present disclosure. For example, a feature shown or described as part of one embodiment may be used together with another embodiment to produce yet another embodiment. Therefore, the present disclosure is intended to encompass such modifications and variations within the scope of the appended claims and their equivalents.

[0042] The terms used herein are used to describe example embodiments and are not intended to limit and / or constrain the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. In the present disclosure, terms such as "including", "having", "comprising", etc. are used to specify features, numbers, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more of the features, elements, steps, operations, elements, components, or combinations thereof.

[0043] It should be understood that although the terms first, second, third, etc. can be used to describe various elements in this article, the elements should not be limited by these terms. Instead, these terms are used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and the second element can be referred to as the first element.

[0044] It will be understood that when an element is referred to as being “connected” to another element, the expression encompasses examples of direct connection or direct coupling as well as connections or couplings with one or more other elements interposed therebetween.

[0045] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. For example, the scope of the expression or phrase "A and / or B" includes the item "A", the item "B" and the combination of the items "A and B".

[0046] In addition, the scope of the expression or phrase "at least one of A or B" is intended to include all of the following: (1) at least one of A; (2) at least one of B; and (3) at least one of A and at least one of B. Similarly, the scope of the expression or phrase "at least one of A, B, or C" is intended to include all of the following: (1) at least one of A; (2) at least one of B; (3) at least one of C; (4) at least one of A and at least one of B; (5) at least one of A and at least one of C; (6) at least one of B and at least one of C; and (7) at least one of A, at least one of B, and at least one of C.

[0047] According to example embodiments, a printed circuit board structure according to the present disclosure may be coupled to a main logic board. The printed circuit board structure may be accommodated in an electronic device having a relatively small size and / or space constraints. In addition, the design of the printed circuit board structure described herein may vary depending on the internal structure and / or space constraints of the electronic device and the number of signals required, rather than relying on a connector shape.

[0048] In some implementations, the printed circuit board structure includes a main logic board and a printed circuit board. The printed circuit board includes: a first portion, the first portion includes an upper plate, the upper plate having a first width in a lateral direction of the upper plate; and a second portion, the second portion includes one or more pillars, the one or more pillars vertically extending or protruding from the first portion and arranged between a first end of the upper plate and a second end of the upper plate in a lateral direction. The second portion is integrally formed with the first portion as a single body. Each of the one or more pillars has a second width in a lateral direction, and the second width is narrower than the first width.

[0049] One or more pillars have a first end extending or protruding vertically from the first portion and a second end (distal end) that can be coupled to the main logic board. Each of the one or more pillars is disposed between the first end of the upper plate and the second end of the upper plate in the lateral direction of the upper plate. The upper plate has a first width in the lateral direction, and each pillar has a second width in the lateral direction, the first width being larger (e.g., wider) than the second width. The upper plate and the one or more pillars are integrally formed into a single body to form a printed circuit board, as will be discussed according to various manufacturing methods disclosed herein.

[0050] In an example embodiment, the printed circuit board includes a plurality of pillars, and the total width of the pillars (i.e., the second width multiplied by the number of pillars provided) is also less than the first width. In an example embodiment, the printed circuit board includes a single pillar, the appearance of the printed circuit board has a mushroom-like shape, and the single pillar can be arranged to extend from a central portion of the first portion (e.g., the upper plate).

[0051] An example configuration of a printed circuit board structure includes a printed circuit board having a first pillar disposed adjacent to a first end of an upper plate in a lateral direction and a second pillar disposed adjacent to a second end of the upper plate in a lateral direction. For example, the first pillar and the second pillar may be oriented parallel to each other in the same direction. For example, the first pillar and the second pillar may be aligned with each other in a length direction of the upper plate (which is perpendicular to the width direction and the vertical (height) direction).

[0052] Another example configuration of a printed circuit board structure includes a printed circuit board having a first pillar disposed adjacent to a first end of an upper board in a lateral direction, a second pillar disposed adjacent to a second end of the upper board, and a third pillar disposed in a central portion of the upper board in a lateral direction. For example, the first pillar can be coupled to a main logic board at an angle inclined to the second pillar, and the first pillar and the second pillar can be coupled to the main logic board at respective angles inclined to the third pillar. For example, the first pillar, the second pillar, and the third pillar are not oriented parallel to each other in the same direction. For example, the first pillar and the second pillar can be aligned with each other in the length direction, and the third pillar can be offset (spaced apart) from the first pillar and the second pillar in the length direction.

[0053] According to an example embodiment of the present disclosure, the printed circuit board includes a plurality of layers. For example, in some embodiments, the printed circuit board may include ten or more layers. However, in alternative embodiments, the printed circuit board may include less than ten layers. For example, the printed circuit board may include a first plurality of layers in the upper plate and a second plurality of layers in the pillars. One or more core sections may be disposed between the first plurality of layers and the second plurality of layers. The width of the first plurality of layers in the upper plate in the lateral direction may be greater than the width of the second plurality of layers in the pillars.

[0054] According to an example embodiment of the present disclosure, each layer of the PCB (e.g., including the first plurality of layers and the second plurality of layers) may include a combination of a signal layer and a ground (GND) layer and various vias. Each layer of the PCB may include a conductive material (e.g., copper foil) and an insulating material (e.g., a dielectric material such as a prepreg).

[0055] According to an exemplary embodiment of the present disclosure, the vertical height of each pillar may be any height greater than 0 mm to about 3 mm. For example, the height of the upper plate may be about 0.5 mm.

[0056] According to an example embodiment of the present disclosure, each pillar includes a plurality of pins to be connected to a main logic board. For example, the plurality of pins may be greater than 50 pins. For example, when a printed circuit board is coupled to the main logic board, the plurality of pins are arranged at the bottom side or bottom surface of the pillar facing the main logic board. For example, the plurality of pins are arranged in multiple rows, such as four rows, with thirteen pins in each row. The pins can be electrically connected to various components of an electronic device in which a PCB structure is provided. Compared with the pin arrangement according to the example disclosed herein, a B2B connector may have only two rows, with twenty-six pins in each row, resulting in a longer length of the B2B connector compared to the pillar disclosed herein. For example, a B2B connector having 52 pins and a spacing of 0.35 millimeters (mm) between the pins has a length of about 11.35 mm, and a B2B connector having 52 pins and a spacing of 0.40 mm between the pins has a length of about 12.60 mm. In contrast, according to an example embodiment, a pillar having 52 pins arranged in an array of four rows with thirteen pins in each row has a length of 8 mm to 9 mm (e.g., approximately 8.8 mm), which is a reduction of approximately 23% and 30%, respectively, compared to the example B2B connector described above.

[0057] The printed circuit board structures described herein may be manufactured according to one or more example methods of the present disclosure.

[0058] In an embodiment, a method for manufacturing a printed circuit board structure includes providing a laminated structured core, the laminated structured core including a first plurality of layers, a second plurality of layers, and a core disposed between the first plurality of layers and the second plurality of layers. The method also includes: removing a first portion of the second plurality of layers at a first position of the laminated structured core; and removing a second portion of the second plurality of layers at a second position of the laminated structured core, so that the portion of the second plurality of layers located between the first position and the second position forms at least a portion of a pillar extending vertically from the portion of the laminated structured core including the first plurality of layers. The method may also include coupling the pillar to a main logic board to form a printed circuit board structure. For example, the pillar may be coupled to the main logic board by a gluing method (e.g., using epoxy, soldering, underfill, or a combination thereof).

[0059] In an embodiment, a laminated structured core may be obtained by providing a structured core comprising a first plurality of layers; applying a peeling layer to at least a portion of an upper surface of the structured core; and laminating a second plurality of layers onto the upper surface of the structured core to which at least the portion of the upper surface of the structured core has been applied the peeling layer, to obtain a laminated structured core. A first portion of the second plurality of layers at a first position of the laminated structured core and a second portion of the second plurality of layers at a second position of the laminated structured core may be removed by a mechanical milling process or a decapping process. For example, each of the first portion of the second plurality of layers and the second portion of the second plurality of layers may be removed by applying a decapping process so as to cut away the first portion and the second portion of the second plurality of layers until the peeling layer is reached. For example, each of the first portion of the second plurality of layers and the second portion of the second plurality of layers may be removed by applying a milling tool so as to cut away the first portion and the second portion of the second plurality of layers until the peeling layer is reached.

[0060] The vertical height of the pillar extending from the main logic board to the portion of the laminated structural core including the first plurality of layers is greater than 0.0 mm and less than or equal to about 3.0 mm. The vertical height of the pillar corresponds to the vertical height of each of the first portion of the second plurality of layers and the second portion of the second plurality of layers, the first portion and the second portion being removed.

[0061] According to example embodiments of the present disclosure, vertical impedance control and signal stability / quality can be improved with the aid of the structure of the example printed circuit boards disclosed herein. For example, compared to the impedance value mismatch of known connectors, the mismatch between the impedance value at the lower layer and the impedance value at the upper layer of the printed circuit board is lower. For example, a via configuration including ground vias and signal vias arranged in one, two, or three rows may have a deviation of less than 5 ohms for a 50 ohm impedance value, which is an acceptable range for a 10% tolerance value. In contrast, due to the limited spacing (distance between vias) of known connectors (e.g., having a spacing of 0.35 mm or 0.40 mm), the ground vias cannot be positioned close to the signal vias, resulting in poor signal integrity and impedance deviations greater than 5 ohms.

[0062] Example aspects of the present disclosure provide several technical effects, benefits and / or improvements in printed circuit board and electronic device (e.g., wearable computing device) technologies. For example, as described above, a printed circuit board structure according to the examples disclosed herein can be accommodated in an electronic device with a smaller size and / or space constraints to accommodate electronic components. The design of the printed circuit board structure described herein can vary according to the internal structure and / or space constraints of the electronic device and the number of signals required, rather than relying on the connector shape. For example, according to an example embodiment of the printed circuit board structure, the signal array can be arranged in more than two rows.

[0063] The printed circuit board structure according to the examples disclosed herein can maximize the main logic board component placement area, is more flexible for the desired total number of available signals, and is more flexible for current transmission restrictions (for example, B2B connectors are typically limited to 200mA per signal pin). In addition, since the printed circuit board structure is integrally formed as a single body, the connection between the printed circuit board structure and the main logic board is stronger than the connection between the interposer and the main logic board via the connector. In addition, since the printed circuit board structure is integrally formed as a single body, alignment problems are avoided compared to stacked circuit boards composed of multiple parts assembled together. Therefore, the printed circuit board structure has improved reliability. According to the example embodiments disclosed herein, the impedance control of high-speed signals can be improved by vertically configuring different signal / ground (GND) via distributions. Vertical plated through holes (PTH) or laser vias can also provide better GND shielding than B2B connectors. Therefore, the printed circuit board structure is less susceptible to or not subject to electromagnetic interference. In addition, the pillar height of the printed circuit board structure according to the examples disclosed herein can vary between 0 mm and about 3.0 mm, and there is no need to worry about connector mating height restrictions.

[0064] Now referring to the accompanying drawings, Figure 1 An example printed circuit board 100 according to one or more example embodiments of the present disclosure is depicted. The printed circuit board 100 includes a first portion 110 including an upper plate 112 having a first width w1 in a lateral direction (e.g., y direction) of the upper plate 112, and a second portion 120 including a single pillar 122 extending or protruding vertically (e.g., in the z direction) from the first portion 110 and disposed between a first end 114 of the upper plate 112 and a second end 116 of the upper plate 112 in the lateral direction. The second portion 120 is integrally formed with the first portion 110 as a single body. For example, the upper plate 112 is integrally formed with the pillar 122 as a single body to form the printed circuit board 100. The pillar 122 has a second width w2 in the lateral direction, which is narrower than the first width w1.

[0065] The pillar 122 has a vertical height d1, which is equal to the end 124 where the pillar 122 vertically extends or protrudes from the first portion 110 and the pillar 122 can be coupled to the main logic board ( Figure 1In some embodiments, the pillar 122 may be centrally disposed in the lateral direction between the first end 114 of the upper plate 112 and the second end 116 of the upper plate 112. The upper plate 112 has a vertical height d2 that spans the first end (upper distal end) 118 of the upper plate 112 and the second end (lower end 119) of the upper plate 112 facing the second portion 120 in the z direction. The total height of the printed circuit board 100 corresponds to the sum of the vertical heights d1 and d2.

[0066] FIG. 2A to FIG. 2B An example board-to-board connector is depicted in accordance with one or more example embodiments of the present disclosure. Figure 2A A first board-to-board (BTB) connector 200 is shown, and Figure 2B A second BTB connector 200 ′ is shown.

[0067] refer to Figure 2A , the connector 200 has a width W bb1 and length L bb1 . Pitch P bb1 The length L of the first BTB connector 200 corresponds to the distance between the pins 210. As mentioned above, since more signals need to be carried to the main logic board, the BTB connector must be made longer. For example, when the number of pins is fifty or more, the length L of the first BTB connector 200 is bb1 The width W of the first BTB connector 200 may be about 11 to 12 mm. bb1 The area of ​​the first BTB connector 200 may be approximately 22 mm. 2 Up to 24mm 2 The spacing P between pins 210 bb1 It can be about 0.3mm to 0.4mm.

[0068] refer to Figure 2B , the connector 200' has a width W bb2 and length L bb2 . Pitch P bb2 As mentioned above, since more signals need to be carried to the main logic board, the BTB connector must be made longer. For example, when the number of pins is fifty or more, the length L of the second BTB connector 200' is bb2 The width W of the second BTB connector 200 ′ may be about 12 mm to 13 mm. bb2 The area of ​​the second BTB connector 200' may be about 36mm 2 Up to 52mm 2 The spacing P between the pins 210' bb2 It can be about 0.4 mm.

[0069] Figure 2C An example printed circuit board is depicted according to one or more example embodiments of the present disclosure. Figure 2A and Figure 2B Compared with the BTB connector of the present disclosure, the exemplary embodiment of the present disclosure can Figure 2C The length of the support 122 shown is shorter. Figure 2C , the support 122 has a length L p and width W p (It can be combined with Figure 1 As an example, when the pillar 122 includes fifty or more pins, the width W of the pillar 122 is p The length L of the support 122 may be about 2 mm to 3 mm. p The area of ​​the support 122 may be about 16 mm. 2 To about 27mm 2 For example, in some embodiments, the area of ​​the support 122 may be approximately 23 mm. 2 According to various implementations described herein, the spacing between the pins (not shown in FIG. 2 ) disposed on the pillar 122 may be between about 0.5 mm and 1 mm, for example, 0.7 mm. FIG. 2A to FIG. 2B In terms of the reduction in length compared to the B2B connector, in some implementations, the pillar 122 may be about 27% to 38% shorter, for example, 23% to 30% shorter. In addition, some known connectors have a mating height of about 0.6 mm to about 0.8 mm. In contrast, according to the example embodiments disclosed herein, the height d1 of the pillar 122 can be about 2.0 mm to about 3.0 mm, wherein the height d2 of the upper plate is about 0.5 mm. In some implementations, the height of the pillar 122 can vary from a value greater than 0 mm to about 3.0 mm.

[0070] FIG. 3A to FIG. 3B Depicted are example printed circuit board structures and pin configurations for printed circuit boards according to one or more example embodiments of the present disclosure. Figure 3A, the printed circuit board structure 300 includes a printed circuit board 100, which has a first portion 110 including an upper plate 112 and a second portion 120 including a single pillar 122, which extends or protrudes vertically (e.g., in the z-direction) from the first portion 110. The printed circuit board structure 300 also includes a main logic board 370, to which the printed circuit board 100 is mounted or coupled. For example, the printed circuit board 100 can be mounted or coupled to the main logic board 370 via solder balls 380. For example, the pillar 122 can be mounted or coupled to the main logic board 370 by a gluing method (e.g., using epoxy resin, soldering, bottom fill glue, or a combination thereof).

[0071] refer to Figure 3B , shows a plan view of a pin array 390 disposed on the bottom surface of the pillar 122. Figure 3B In the example of , the pin array 390 includes three columns of sixteen pins, for a total of 48 pins. However, it should be understood that the present disclosure is not limited to this example embodiment. For example, in alternative embodiments, the pin array 390 may include more than 48 pins or less than 48 pins (e.g., an array of four columns with thirteen pins in each column).

[0072] FIG. 4A to FIG. 4B Depicted are example printed circuit board structures and pin configurations for printed circuit boards according to one or more example embodiments of the present disclosure. Figure 4A , the printed circuit board structure 400 includes a printed circuit board 100', which has a first portion 110' including an upper plate 112' and two second portions 120a' and 120b', wherein the second portion 120a' includes a pillar 122a' extending or protruding vertically (e.g., in the z-direction) from the first portion 110' and the second portion 120b' includes a pillar 122b' extending or protruding vertically (e.g., in the z-direction) from the first portion 110'. The printed circuit board structure 400 also includes a main logic board 470, to which the printed circuit board 100' is mounted or coupled. For example, the printed circuit board 100' can be mounted or coupled to the main logic board 470 via solder balls 480. For example, the pillars 122a' and the pillars 122b' can be mounted or coupled to the main logic board 470 by a gluing method (e.g., using epoxy resin, welding, bottom fill glue, or a combination thereof).

[0073] The upper plate 112' has a first width w1' in the lateral direction (e.g., y direction) of the upper plate 112', and the pillars 122a' and the pillars 122b' extend or protrude vertically (e.g., in the z direction) from the first portion 110' and are disposed between the first end 114' of the upper plate 112' and the second end 116' of the upper plate 112' in the lateral direction. The second portion 120a' and the second portion 120b' are integrally formed with the first portion 110' as a single body. For example, the upper plate 112', the pillars 122a', and the pillars 122b' are integrally formed as a single body to form the printed circuit board 100'. Each of the pillars 122a' and 122b' has a second width w2' in the lateral direction, which is narrower (smaller) than the first width w1'. The total width of the pillars (i.e., twice w2') is less than the width w1' of the upper plate 112'.

[0074] according to Figure 4A In the example configuration of the printed circuit board structure 400, the printed circuit board 100' includes a first pillar (pillar 122a') arranged adjacent to the first end 114' of the upper board 112' in the lateral direction of the upper board 112' and a second pillar (pillar 122b') arranged adjacent to the second end 116' of the upper board 112' in the lateral direction.

[0075] refer to Figure 4B , shows a plan view of a pin array 490a disposed on the bottom surface of a support 122a' and a pin array 490b disposed on the bottom surface of a support 122b'. Figure 4B In the example of , pin array 490a and pin array 490b each include three columns of eight pins, for a total of 24 pins. It should be understood that the present disclosure is not limited to this example embodiment. For example, in alternative embodiments, the pin array of each pillar may include more than 24 pins or less than 24 pins (e.g., a three-column array with sixteen pins in each column; a four-column array with thirteen pins in each column, etc.). For example, the first pillar and the second pillar (pillar 122a' and pillar 122b') can be oriented in the same direction to be parallel to each other (e.g., in the x-direction). For example, as Figure 4B As shown, the first and second struts (struts 122a' and struts 122b') may be aligned with each other in the length direction (x-direction) such that they are not offset from each other.

[0076] FIG. 5A to FIG. 5B Depicted are example printed circuit board structures and pin configurations for printed circuit boards according to one or more example embodiments of the present disclosure. Figure 5AThe printed circuit board structure 500 includes a printed circuit board 100", which has a first part 110" including an upper board 112" and three second parts 120a", 120b" and 120c', wherein the second part 120a" includes a pillar 122a" extending or protruding vertically (for example, in the z direction) from the first part 110", the second part 120b" includes a pillar 122b" extending or protruding vertically (for example, in the z direction) from the first part 110", and the second part 120c" includes a pillar 122c" extending or protruding vertically (for example, in the z direction) from the first part 110". The printed circuit board structure 500 also includes a main logic board 570, and the printed circuit board 100" is mounted or coupled to the main logic board. For example, the printed circuit board 100" can be mounted or coupled to the main logic board 570 via solder balls 580. For example, pillars 122a", 122b", and 122c" may be mounted or coupled to main logic board 570 by a gluing method (eg, using epoxy, soldering, underfill, or a combination thereof).

[0077] The upper plate 112" has a first width w1" in a lateral direction (e.g., y direction) of the upper plate 112", and the pillars 122a", 122b", and 122c" extend or protrude vertically (e.g., in the z direction) from the first portion 110" and are arranged in the lateral direction between the first end 114" of the upper plate 112" and the second end 116" of the upper plate 112". The second portion 120a", 120b", and the second portion 120c" are integrally formed with the first portion 110" as a single body. For example, the upper plate 112", the pillars 122a", 122b", and 122c" are integrally formed as a single body to form a printed circuit board 100". Pillar 122a", pillar 122b" and pillar 122c" each have a second width w2" in the lateral direction, and the second width is narrower (smaller) than the first width w1". The total width of the pillars (i.e., three times w2") is smaller than the width w1" of the upper plate 112".

[0078] according to Figure 5A In an example configuration of the printed circuit board structure 500, the printed circuit board 100" includes a first pillar (pillar 122a") disposed adjacent to a first end 114" of the upper board 112" in a lateral direction of the upper board 112", a second pillar (pillar 122b") disposed adjacent to a second end 116" of the upper board 112", and a third pillar (pillar 122c") disposed in a central portion of the upper board in the lateral direction.

[0079] refer to Figure 5B, showing a plan view of a pin array 590a disposed on the bottom surface of a pillar 122a", a pin array 590b disposed on the bottom surface of a pillar 122b", and a pin array 590c disposed on the bottom surface of a pillar 122c". Figure 5B In the example of , pin array 590a, pin array 590b, and pin array 590c each include three columns of eight pins, for a total of 24 pins. However, it should be understood that the present disclosure is not limited to this example embodiment. For example, in alternative embodiments, the pin array of each pillar may include more than 24 pins or less than 24 pins (e.g., a three-column array with sixteen pins in each column; a four-column array with thirteen pins in each column, etc.). For example, the first pillar (pillar 122a") can be coupled to the main logic board 570 at an angle inclined to the second pillar (pillar 122b"), and the first and second pillars (pillars 122a" and pillars 122b") can be coupled to the main logic board 570 at respective angles inclined to the third pillar (pillar 122c"). For example, the first pillar, the second pillar, and the third pillar (pillars 122a", pillars 122b", and pillars 122c") may not all be oriented in the same direction to be parallel to each other (e.g., in the x-direction or the y-direction). For example, the first and second pillars (pillars 122a" and 122b") can be aligned with each other in the length direction (x direction), and the third pillar (pillar 122c") can be offset (spaced apart) from the first and second pillars (pillars 122a" and 122b") in the length direction (e.g., a distance d 偏移 ).

[0080] 6A to 6F An example method for manufacturing a printed circuit board by a milling decapping process is depicted according to one or more example embodiments of the present disclosure.

[0081] In the example method, Fig. 6A In the method for manufacturing a printed circuit board structure, at 610, a structured core 612 including a plurality of layers 614 is provided. For example, the structured core 612 may include a plurality of vias 616. The method further includes Figure 6B At 620 in the embodiment, a release layer 622 is applied to at least a portion of an upper surface 624 of the structured core 612, the upper surface 624 of the structured core 612 being the upper surface of the plurality of layers 614. For example, the release layer 622 may not be applied to one or more regions of the upper surface 624 of the structured core 612. The one or more regions of the upper surface 624 of the structured core 612 may correspond to the location of one or more regions to be formed according to the method.

[0082] The method further comprises Figure 6CAt 630 in the embodiment, one or more layers 632 are laminated to the upper surface 624 of the structured core 612 to which at least the portion of the upper surface 624 of the structured core 612 to which the release layer 622 has been applied. Fig.6D At 640 in FIG. 6, additional layers 642 are laminated to complete the formation of a laminated structured core 644. The laminated structured core 644 may include a first plurality of layers 646, a second plurality of layers 648, and a core 649. For example, at least some portions of the first plurality of layers 646 may be separated from the second plurality of layers 648 and / or the core 649 by a peel layer 622.

[0083] The method further comprises Fig. 6E A milling tool 652 is applied at 650 in order to cut off a first portion 654 including a second plurality of layers 648 and a core 649 and a second portion 656 including a second plurality of layers 648 and a core 649. For example, the milling tool 652 may be applied to cut off the first portion 654 and the second portion 656 until the peeling layer 622 is reached so that the first portion 654 and the second portion 656 can be easily removed from the peeling layer. The peeling layer 622 is a substance other than prepreg or glue and is not intended to permanently bond the layers together. After cutting off the first portion 654 and the second portion 656, the remaining portion including the second plurality of layers 648 and the core 649 (which is disposed between the first portion 654 and the second portion 656) forms at least a portion of a pillar 658 extending from the first plurality of layers 646. For example, the pillar 658 may correspond to the pillar 122, or any one of the pillars 122a', 122b', 122a", and 122b". The support 658 may include a second plurality of layers 648, a core 649 (e.g., similar to Figure 1 The core 150 of the embodiment of the present invention and one or more of the first plurality of layers 646. In some implementations, the support 658 can include the second plurality of layers 648 and the core 649, but does not include the first plurality of layers 646.

[0084] exist Fig. 6F At 660 in FIG. 1 , the method includes finalizing the printed circuit board 662 (e.g., by removing any remaining portion of the peeling layer 622). The printed circuit board 662 includes the pillars 658 and the upper plate 664, for example, having a similar structure to the printed circuit board 100. However, in other embodiments, the printed circuit board 662 may be modified. 6A to 6F The method of forming a plurality of pillars from the structured core 612 (e.g., by applying a release layer to a plurality of locations, wherein the plurality of locations are disposed between locations of the release layer corresponding to the locations of the pillars to be formed by using the milling tool 652). 6A to 6FAlthough not shown, the method may further include coupling the pillar 658 to a main logic board (e.g., main logic board 370) to form a printed circuit board structure (e.g., printed circuit board structure 300). For example, the pillar 658 may be coupled to the main logic board by a gluing method (e.g., using epoxy, solder, underfill, or a combination thereof).

[0085] 7A to 7F An example method for manufacturing a printed circuit board by a laser decapping process according to one or more example embodiments of the present disclosure is described. In the example method, Fig. 7A In the method for manufacturing a printed circuit board structure, at 710, a structured core 712 including a plurality of layers 714 is provided. For example, the structured core 712 may include a plurality of vias 716. The method further includes Figure 7B A release layer 722 is applied at 720 to at least a portion of an upper surface 724 of the structured core 712, the upper surface 724 of the structured core 712 being the upper surface of the plurality of layers 714. For example, the release layer 722 may not be applied to one or more regions of the upper surface 724 of the structured core 712. The one or more regions of the upper surface 724 of the structured core 712 may correspond to the location of one or more regions to be formed according to the method.

[0086] The method further comprises Figure 7C At 730 in, one or more layers 732 are laminated to the upper surface 724 of the structured core 712 to which at least the portion of the upper surface 724 of the structured core 712 to which the release layer 722 has been applied. Fig.7D At 740, additional layers 742 are laminated to complete the formation of a laminated structured core 744. Fig.7D , the laminated structural core 744 may include a first plurality of layers 746, a second plurality of layers 748, and a core 749. For example, at least some portions of the first plurality of layers 746 may be separated from the second plurality of layers 748 and / or the core 749 by a peeling layer 722.

[0087] The method further comprises Fig. 7E750 in the figure, so as to cut off the first portion 754 including the second plurality of layers 748 and the core 749 and the second portion 756 including the second plurality of layers 748 and the core 749. For example, the laser tool 752 can be applied to cut off the first portion 754 and the second portion 756 until the peeling layer 722 is reached, so that the first portion 754 and the second portion 756 can be easily removed from the peeling layer 722. The peeling layer 722 is a substance other than prepreg or glue, and is not intended to permanently bond the layers together. After cutting off the first portion 754 and the second portion 756, the remaining portion including the second plurality of layers 748 and the core 749 (which is disposed between the first portion 754 and the second portion 756) forms at least a portion of a pillar 758 extending from the first plurality of layers 746. For example, the pillar 758 can correspond to the pillar 122, or any one of the pillars 122a', 122b', 122a", and 122b". The support 758 may include a second plurality of layers 748, a core 749 (e.g., similar to Figure 1 The core 150 of the embodiment of the present invention and one or more of the first plurality of layers 746. In some implementations, the support 758 can include the second plurality of layers 748 and the core 749, but does not include the first plurality of layers 746.

[0088] exist Figure 7F At 760 in the method, the method includes finalizing the printed circuit board 762 (e.g., by removing any remaining portion of the peeling layer 722). The printed circuit board 762 includes the pillars 758 and the upper plate 764, for example, having a similar structure to the printed circuit board 100. However, in other embodiments, the printed circuit board 762 may be modified. 7A to 7F The method of forming a plurality of pillars from the structured core 712 (e.g., by applying a release layer to a plurality of locations, wherein the plurality of locations are disposed between locations of the release layer corresponding to the locations of the pillars to be formed by using the laser tool 752). 7A to 7F Although not shown, the method may further include coupling the pillar 758 to a main logic board (e.g., main logic board 370) to form a printed circuit board structure (e.g., printed circuit board structure 300). For example, the pillar 758 may be coupled to the main logic board by a gluing method (e.g., using epoxy, solder, underfill, or a combination thereof).

[0089] FIG. 8A to FIG. 8C An example method for manufacturing a printed circuit board through a milling process according to one or more example embodiments of the present disclosure is depicted.

[0090] In the example method, Fig. 8AIn the method for manufacturing a printed circuit board structure, at 810, a laminated structured core 812 is provided. The laminated structured core 812 can be similar to the laminated structured cores 644, 744. In some implementations, the laminated structured core 812 can include no release layer. Fig. 8A , the laminated structural core 812 may include a first plurality of layers 814 , a second plurality of layers 816 , and a core 818 .

[0091] The method further comprises Figure 8B A milling tool 822 is applied at 820 in order to cut away the first and second portions including the second plurality of layers 816 and the core 818, similar to the above with respect to Fig. 6E For example, the milling tool 822 may be applied to cut away the first portion and the second portion until the peeling layer is reached so that the first portion and the second portion can be easily removed. However, in some implementations, a peeling layer may not be provided. Figure 8C , after the first and second portions are cut away, the remaining portion including the second plurality of layers 816 and the core 818 (which is disposed between the first and second portions) forms at least a portion of the second portion 834 including a support 835 extending from the first portion 836 including an upper plate 837 including the first plurality of layers 814. For example, support 835 can correspond to support 122, or any of support 122a', 122b', 122a", and 122b". Support 835 can include the second plurality of layers 816, the core 818 (e.g., similar to the support from Figure 1 In some implementations, the support 835 may include the second plurality of layers 816 and the core 818, but not the first plurality of layers 814. In some implementations, a laser tool may be used instead of a milling tool to perform the FIG. 8A to FIG. 8C Laser tools may be more precise than milling tools, however, the strength of laser tools may be limited such that the height of the pillars that can be obtained using the laser tool may be less than the height of the pillars that can be obtained using the milling tool.

[0092] refer to Figure 8C The resulting printed circuit board 832 includes a first portion 836 having an upper plate 837 and a second portion 834 having a support 835, for example, having a structure similar to that of the printed circuit board 100. However, in other embodiments, the FIG. 8A to FIG. 8C The method of forming a plurality of pillars from the laminated structured core 812. Although FIG. 8A to FIG. 8CAlthough not shown, the method may further include coupling the pillar 835 to a main logic board (e.g., main logic board 370) to form a printed circuit board structure (e.g., printed circuit board structure 300). For example, the pillar 835 may be coupled to the main logic board by a gluing method (e.g., using epoxy, soldering, underfill, or a combination thereof).

[0093] 9A to 9C An example via configuration according to one or more example embodiments of the present disclosure is depicted in plan view.As discussed above, a printed circuit board may include a plurality of vias. 9A to 9C The illustrated via configuration may be implemented in any of the printed circuit boards disclosed herein (eg, printed circuit boards 100, 400, 500, etc.). Fig. 9A , the first via configuration 900 includes: a first row of vias, the first row of vias including ground vias 910 disposed on opposite sides of the signal vias 920; and ground vias 910 disposed in a second row. Fig. 9B , the second via configuration 900' includes: a first row of vias, the first row of vias including ground vias 930 disposed on the opposite side of the signal via 940; and ground vias 930 disposed in the second and third rows. Fig. 9C , the third via configuration 900" includes: a first row of vias, the first row of vias including signal vias 960; and ground vias 950 arranged in the second row and the third row. For example, the distance d between adjacent signal vias 940 in the x direction is 信号 may be greater than the distance d′ between adjacent signal vias 960 in the x direction 信号 As an example value, the distance d 信号 It can be about 1.3 mm, and the distance d' 信号 It can be about 1.0 mm.

[0094] FIG. 10A to FIG. 10D Example impedance simulation results related to various via configurations according to one or more example embodiments of the present disclosure. According to the example printed circuit board structures disclosed herein (e.g., printed circuit board structures 300, 400, 500), vertical impedance control and signal stability / quality can be improved with the structure of the example printed circuit board disclosed herein. For example, as shown in FIG. FIG. 10A to FIG. 10DExplain that, compared to the impedance value mismatch of known connectors, the mismatch between the impedance value at a lower layer (e.g., at a main logic board) and the impedance value at an upper layer (e.g., at an upper board) of a printed circuit board structure is lower. For example, a via configuration including ground vias and signal vias arranged in one, two, or three rows may have a deviation of less than 5 ohms for a 50 ohm impedance value, which is an acceptable range for a 10% tolerance value. In contrast, known connectors have limited spacing (e.g., a distance between vias of about 0.35 mm to about 0.40 mm), and therefore the ground vias are positioned close to the signal vias, resulting in signal reflections and causing signal degradation, which may lead to logic errors and / or a higher impedance mismatch between the upper layer and the lower layer.

[0095] refer to Fig. 10A , shows impedance simulation results 1000 for applying 50 ohm impedance to three via configurations. For example, the first via configuration ( Fig. 10B ) provides a first output 1010 of 49.83 ohms. For example, the second via configuration ( Fig. 10C ) provides a second output 1020 of 47.78 ohms. For example, the third via configuration ( Fig. 10D ) provides a third output 1030 of 46.08 ohms. Thus, in each case, the impedance mismatch is less than 5 ohms, with each output meeting a 10% tolerance value (ie, the mismatch is less than 5 ohms when a 50 ohm impedance is applied).

[0096] refer to Fig. 10B , the first via configuration 1060 includes a single row of vias including ground vias 1050 disposed on opposite sides of the signal via 1040. Fig. 10B In the example, the signal via 1040 has an inner diameter d 内 and outer diameter d 外 The spacing (the distance between the centers of the ground via 1050 and the signal via 1040) and d 间距 As an example value, d 内 It can be about 0.25 mm, d 外 can be about 0.45 mm, and d 间距 It may be about 0.70 mm. Therefore, the pitch according to example embodiments may be greater than that of known connectors. Therefore, the ground via is not positioned very close to the signal via, resulting in less signal reflection and improved signal integrity.

[0097] refer to Fig. 10CThe second via configuration 1060' includes: a first row of vias 1070', the first row of vias including ground vias 1050' disposed on the opposite side of the signal via 1040'; and ground vias 1050' disposed in a second row 1080'. Fig. 10C In the example, the pitch (the distance between the centers of the vias across the rows) is proportional to d' 间距 As an example value, d' 间距 It may be about 0.50 mm. Therefore, the pitch according to example embodiments may be greater than that of known connectors. Therefore, the ground via is not located very close to the signal via, resulting in less signal reflection and improved signal integrity.

[0098] refer to Fig. 10D , the third via configuration 1060" includes: a first row of vias 1070", the first row of vias including a ground via 1050" disposed on an opposite side of the signal via 1040"; a ground via 1050' disposed in a second row 1080"; and a ground via 1050" disposed in a third row 1090". Fig. 10D In the example of Fig. 10C The same as in . Therefore, the pitch according to the example embodiment can be larger than the pitch of the known connector. Therefore, the ground via is not located very close to the signal via, resulting in less signal reflection and improved signal integrity.

[0099] According to the example embodiments disclosed herein, impedance control of high-speed signals can be improved by vertically configuring different signal / ground (GND) via distributions. As discussed above, in each of the different configurations, the impedance mismatch is less than 5 ohms, where each output meets a 10% tolerance value (i.e., when a 50 ohm impedance is applied, the mismatch is less than 5 ohms). Therefore, vertical signal integrity is improved in the printed circuit board disclosed herein.

[0100] FIG. 11A to FIG. 11C An example stacked layer structure of a printed circuit board according to one or more example embodiments of the present disclosure is depicted. FIG. 11A to FIG. 11C The stacked layer structure shown can be implemented in any of the printed circuit boards disclosed herein (e.g., printed circuit boards 100, 400, 500, etc.). For example, in some embodiments, the printed circuit board can include ten or more layers. However, in alternative embodiments, the printed circuit board can include less than ten layers.

[0101] refer to Fig.11A, the example printed circuit board 1100 includes a plurality of layers L1 to L10. For example, one or more of the layers L1 to L10 may include a top layer, a bottom layer, a conductor 1120 (e.g., a conductive material such as copper foil), and / or a prepreg (PP) 1130 (e.g., an insulating or dielectric material). A solder mask (SM) may also be applied to each of the top layer and the bottom layer. Fig.11A In the embodiment of the present invention, the core 1110 is disposed between layers L5 and L6. Generally, the thickness of the core 1110 is greater than the thickness of each layer.

[0102] refer to Fig. 11B , the example printed circuit board 1100' includes a plurality of layers L1 to L10. For example, one or more of the layers L1 to L10 may include a top layer, a bottom layer, a conductor 1120' (e.g., a conductive material such as copper foil), and / or a prepreg (PP) 1130' (e.g., an insulating or dielectric material). A solder mask layer (SM) may also be applied to each of the top layer and the bottom layer. Fig. 11B , the first core 1140 is disposed between layers L4 and L5, and the second core 1150 is disposed between layers L6 and L7. Generally, the thickness of each of the first core 1140 and the second core 1150 is greater than the thickness of each layer.

[0103] refer to Fig. 11C , the example printed circuit board 1100" includes a plurality of layers L1 to L10. For example, one or more of the layers L1 to L10 may include a top layer, a bottom layer, a conductor 1120" (e.g., a conductive material such as copper foil), and / or a prepreg (PP) 1130" (e.g., an insulating or dielectric material). A solder mask (SM) may also be applied to each of the top layer and the bottom layer. Fig. 11C , the first core 1160 is disposed between layers L3 and L4, the second core 1170 is disposed between layers L5 and L6, and the third core 1180 is disposed between layers L7 and L8. Generally, the thickness of each of the first core 1160, the second core 1170, and the third core 1180 is greater than the thickness of each layer.

[0104] Fig.12 Depicted are example cross-sections of a stacked layer structure of a printed circuit board according to one or more example embodiments of the present disclosure. Fig.12 The stacked layer structure shown can be implemented in any of the printed circuit boards disclosed herein (e.g., printed circuit boards 100, 400, 500, etc.). For example, in some embodiments, the printed circuit board can include ten or more layers. However, in alternative embodiments, the printed circuit board can include less than ten layers.

[0105] refer to Fig.12, the example printed circuit board 1200 includes a plurality of layers L1 to L10. For example, one or more of the layers L1 to L10 may include a foil 1210 (e.g., copper foil or other conductive material) and / or a prepreg (PP) 1220 (e.g., insulating or dielectric material). Fig.12 In the embodiment of the present invention, the core 1230 is disposed between the layers L5 and L6. Generally, the thickness of the core 1230 is greater than the thickness of each layer. The printed circuit board 1200 further includes a plurality of vias (eg, via 1240 and via 1250).

[0106] Fig.13 A plan view of an example pin array configuration of a printed circuit board according to one or more example embodiments of the present disclosure is depicted. According to an example embodiment of the present disclosure, each pillar includes a plurality of pins that can be connected to a main logic board. For example, the plurality of pins can be greater than 50 pins. For example, when the printed circuit board is coupled to the main logic board, the plurality of pins can be arranged at a bottom side or bottom surface of the pillar facing the main logic board. Reference Fig.13 , the plurality of pins are arranged in a plurality of rows, for example, four rows, with thirteen pins in each row, on the bottom surface 1330 of the pillar. When the pillar is coupled to a main logic board to form a printed circuit board structure disposed inside an electronic device, the pins can be electrically connected to various components of the electronic device. For example, the pins may include a plurality of ground pins 1310 and a plurality of signal pins 1320. The present disclosure is not limited to Fig.13 Example configurations of ground pins and signal pins shown. For example, ground pins and signal pins can be configured differently (e.g., a signal pin can be replaced by a ground pin, and vice versa). Signal pin 1320 can be used as, for example, a mobile industry processor interface (MIPI), a four-wire serial peripheral interface (QSPI), a power grid, etc. Compared to the example arrangement of pins as disclosed herein, a known B2B connector with more than 50 pins may have only two rows, with twenty-six pins in each row, resulting in a longer length of the B2B connector compared to the pillars disclosed herein. For example, a B2B connector with 52 pins and a spacing of 0.35 mm between the pins has a length of about 11.35 mm, and a B2B connector with 52 pins and a spacing of 0.40 mm between the pins has a length of about 12.60 mm. In contrast, according to an exemplary embodiment, a pillar having 52 pins arranged in an array of four rows with thirteen pins in each row has a length of 8 mm to 9 mm (e.g., approximately 8.8 mm), which is a reduction of approximately 23% and 30% in length, respectively, compared to a B2B connector.

[0107] Fig.14 A flow chart illustrating an example non-limiting method for manufacturing a laminated structural core according to one or more example embodiments of the present disclosure is shown. Fig.14, method 1400 includes the following 6A to 7F At 1410, the method includes providing a structured core (e.g., structured core 612, 712) including a plurality of layers (e.g., layers 614, 714). At 1420, the method 1400 includes applying a release layer (e.g., release layer 622, 722) to at least a portion of an upper surface (e.g., upper surface 624, 724) of the structured core. At 1430, the method 1400 includes laminating each layer (e.g., layers 632, 642, 732, 742) onto the upper surface of the structured core to which at least the portion of the upper surface of the structured core has been applied the release layer to obtain a laminated structured core (e.g., laminated structured core 644, 744).

[0108] Fig.15 A flowchart of an example non-limiting method for manufacturing a printed circuit board according to one or more example embodiments of the present disclosure is shown. Fig.15 , method 1500 includes the following 6A to 8C For example, at 1510, a method 1500 for manufacturing a printed circuit board structure includes providing a laminated structured core (e.g., a laminated structured core 644, 744, 812), the laminated structured core including a first plurality of layers (e.g., a first plurality of layers 646, 846, 814), a second plurality of layers (e.g., a second plurality of layers 648, 848, 816), and one or more cores (e.g., one or more cores 649, 749, 818) disposed between the first plurality of layers and the second plurality of layers. At 1520, the method 1500 includes removing a first portion of the second plurality of layers at a first location of the laminated structured core. At 1530, the method 1500 includes removing a second portion of the second plurality of layers at a second location of the laminated structured core. For example, the first portion of the second plurality of layers and the second portion of the second plurality of layers may be removed by a mechanical milling process or a decapping cutting process. For example, each of the first and second portions of the second plurality of layers can be removed via a decapping process by applying a milling tool or a laser to cut away the first and second portions of the second plurality of layers until the peeling layer is reached. The first and second portions are removed so that the portion of the second plurality of layers located between the first position and the second position forms at least a portion of a pillar extending vertically from a portion of the laminated structured core including the first plurality of layers to obtain a printed circuit board having an upper plate and pillars extending vertically from the upper plate. At operation 1540, method 1500 includes mounting the printed circuit board to a main logic board. For example, one or more pillars of the printed circuit board can be mounted to the main logic board by a gluing method (e.g., using epoxy, soldering, underfill, or a combination thereof).

[0109] FIG. 16 depicts an example view of an electronic device having a printed circuit board structure according to one or more example embodiments of the present disclosure. Referring to FIG. 16 , the electronic device 1600 corresponds to a wearable computing device that can be worn, for example, on a user's arm (e.g., wrist). The band 1620 can be used to secure the electronic device 1600 to the user's arm (e.g., wrist). For example, the electronic device 1600 may include a body 1610 having a cavity 1612, in which one or more electronic components (e.g., disposed on one or more printed circuit boards) are disposed. The electronic device 1600 may include a cover 1614, for example, to protect the display of the electronic device 1600 from being scratched or damaged. For example, the electronic device 1600 may include a printed circuit board 1640 disposed in the cavity 1612 of the body 1610. For example, the printed circuit board 1640 may be mounted on the main logic board 1630 and may correspond to any of the printed circuit boards disclosed herein. In addition, one or more electronic components may be disposed on the printed circuit board 1640. The electronic device 1600 may also include one or more batteries and one or more sensors (not shown) disposed within a cavity 1612 defined by the body 1610. The electronic device 1600 may be a device other than a wearable computing device, such as a smart phone, a tablet computer, a laptop computer, a camera, etc.

[0110] Each frame of the flow chart may represent a unit, module, fragment or part of a code, and the code includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions mentioned in the frame may occur out of order. For example, two frames shown in succession may actually be executed substantially concurrently (simultaneously), or the frames may sometimes be executed in reverse order, depending on the functionality involved.

[0111] Although the present disclosure has been described with respect to various example embodiments, each example is provided by way of explanation, not limitation of the present disclosure. Those skilled in the art, after understanding the foregoing, can easily produce modifications, variations, and equivalents of such embodiments. Therefore, the present disclosure does not exclude such modifications, variations, and / or additions to the disclosed subject matter that would be apparent to those of ordinary skill in the art. For example, a feature shown or described as part of one embodiment can be used together with another embodiment to produce yet another embodiment. Therefore, the present disclosure is intended to cover such modifications, variations, and equivalents.

Claims

1. A printed circuit board, comprising: a first portion, the first portion comprising an upper plate having a first width in a lateral direction of the upper plate; as well as A second part, the second part is integrally formed with the first part as a single body, the second part includes one or more pillars, the one or more pillars vertically extend from the first part and are arranged between the first end of the upper plate and the second end of the upper plate in the lateral direction, wherein each of the one or more pillars has a second width in the lateral direction, and the second width is narrower than the first width. 2 . The printed circuit board of claim 1 , wherein the one or more pillars include a pillar disposed at a central portion of the upper plate in the lateral direction.

3. The printed circuit board of claim 1, wherein the second portion comprises a plurality of pillars including a first pillar disposed adjacent to the first end of the upper plate and a second pillar disposed adjacent to the second end of the upper plate. 4 . The printed circuit board of claim 3 , wherein the plurality of pillars include a third pillar disposed in a central portion of the upper board between the first pillar and the second pillar in the lateral direction.

5. The printed circuit board as claimed in claim 4, wherein The printed circuit board can be coupled to the main logic board, so that when the printed circuit board is coupled to the main logic board, the first pillar is coupled to the main logic board at an angle inclined to the second pillar, and the first pillar and the second pillar are coupled to the main logic board at corresponding angles inclined to the third pillar.

6. The printed circuit board according to claim 1, wherein Each of the one or more struts has a vertical height from an end of the strut extending vertically from the first portion to a distal end of the strut that is less than or equal to about 3.0 mm.

7. The printed circuit board of claim 1, wherein the printed circuit board comprises at least ten layers, the upper plate comprises at least four of the at least ten layers, and the one or more pillars comprise at least six of the at least ten layers.

8. The printed circuit board according to claim 1, wherein The distal end of each of the one or more struts includes at least fifty pins, and The second width is less than about 9 mm.

9. An electronic device comprising: main body; as well as A printed circuit board structure, wherein the printed circuit board structure is arranged in the main body, and the printed circuit board structure comprises: The main logic board, and A printed circuit board, the printed circuit board comprising: a first portion including an upper plate having a first width in a lateral direction of the upper plate, and A second part, the second part is integrally formed with the first part as a single body, the second part includes one or more pillars, the one or more pillars are coupled to the main logic board, vertically extend between the main logic board and the first part, and are arranged between the first end of the upper board and the second end of the upper board in the lateral direction, wherein each of the one or more pillars has a second width in the lateral direction, and the second width is narrower than the first width. 10 . The electronic device of claim 9 , wherein the one or more pillars include a pillar provided at a central portion of the upper plate in the lateral direction.

11. The electronic device of claim 9, wherein the second portion comprises a plurality of pillars including a first pillar disposed adjacent to the first end of the upper plate and a second pillar disposed adjacent to the second end of the upper plate. 12 . The electronic device of claim 11 , wherein the plurality of pillars include a third pillar disposed in a central portion of the upper plate between the first pillar and the second pillar in the lateral direction.

13. The electronic device as claimed in claim 12, wherein The first support is coupled to the main logic board at an angle inclined to the second support, and The first support and the second support are coupled to the main logic board at respective angles inclined to the third support.

14. The electronic device of claim 9, wherein a vertical height of each of the one or more pillars extending from the main logic board to the first portion is less than or equal to about 3.0 mm.

15. A method for manufacturing a printed circuit board structure, comprising: providing a laminated structured core comprising a first plurality of layers, a second plurality of layers, and one or more cores disposed between the first plurality of layers and the second plurality of layers; removing a first portion of the second plurality of layers at a first location of the laminated structural core; as well as A second portion of the second plurality of layers is removed at a second position of the laminated structural core such that the portion of the second plurality of layers between the first position and the second position forms at least a portion of a strut extending vertically from the portion of the laminated structural core including the first plurality of layers.

16. The method for manufacturing the printed circuit board structure of claim 15, wherein providing the laminated structured core comprises: providing a structured core comprising said first plurality of layers; applying a release layer to at least a portion of the upper surface of the structured core; as well as The second plurality of layers is laminated onto the upper surface of the structured core to which at least the portion of the upper surface of the structural core has been applied the release layer to obtain the laminated structured core.

17. A method for manufacturing the printed circuit board structure as described in claim 15, wherein removing the first portion of the second plurality of layers at the first position of the laminated structural core and removing the second portion of the second plurality of layers at the second position of the laminated structural core are performed by a mechanical milling process or a decapping process.

18. The method for manufacturing the printed circuit board structure of claim 16, wherein each of the first portion of the second plurality of layers and the second portion of the second plurality of layers extends to the release layer.

19. The method for manufacturing the printed circuit board structure of claim 15, further comprising coupling the support posts to a main logic board.

20. The method for manufacturing the printed circuit board structure of claim 19, wherein the vertical height of the pillar extending from the main logic board to the portion of the laminated structural core comprising the first plurality of layers is less than or equal to about 3.0 mm.

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