Flexible active neural electrode and preparation method thereof

Abstract

The invention relates to a flexible active neural electrode and a preparation method thereof. The flexible neural electrode comprises a flexible substrate; a thin film transistor located on the flexible substrate; a control signal line connected to the gate of the thin film transistor for applying a control signal to the gate of the thin film transistor; the electrode site is used for collecting an electric signal and is connected with a source electrode of the thin film transistor; the neural signal line is connected with the drain electrode of the thin film transistor so as to be used for transmitting an electric signal, and the neural signal line receives the electric signal through the thin film transistor under the condition that the control signal enables the thin film transistor to be conducted.

Description

Technical Field

[0001] The present disclosure relates to the technical field of brain-computer interface, and more specifically, to a flexible neural electrode and a preparation method thereof. Background Art

[0002] As an interface for recording the electrical signals of neurons or transmitting electrical signals to external devices, neural electrodes are an important component of brain-computer interfaces, neural regulation and other systems. Among them, flexible neural electrodes have a Young's modulus closer to that of the brain than traditional silicon-based electrodes. After implantation, they can greatly reduce the mechanical damage caused by micro-movements between neural electrodes and brain tissue, making long-term use of neural electrodes possible. High-channel neural electrodes can improve the recording of neural activity with higher resolution, reveal more sophisticated neural network structures and functions, achieve more sophisticated brain-computer interactions, and promote the development of basic neuroscience. Summary of the invention

[0003] A brief overview of the disclosure is given below in order to provide a basic understanding of some aspects of the disclosure. However, it should be understood that this overview is not an exhaustive overview of the disclosure. It is not intended to identify the key or important parts of the disclosure, nor is it intended to limit the scope of the disclosure. Its purpose is simply to give some concepts of the disclosure in a simplified form as a prelude to a more detailed description given later.

[0004] According to a first aspect of the present disclosure, there is provided a flexible neural electrode, comprising: a flexible substrate; a thin film transistor located on the flexible substrate; a control signal line, the control signal line being connected to a gate of the thin film transistor for applying a control signal to the gate of the thin film transistor; an electrode site, the electrode site being used to collect an electrical signal and being connected to a source of the thin film transistor; and a neural signal line, the neural signal line being connected to a drain of the thin film transistor for transmitting an electrical signal, wherein when the control signal turns on the thin film transistor, the neural signal line receives the electrical signal via the thin film transistor.

[0005] According to a second aspect of the present disclosure, a method for preparing a flexible neural electrode is provided, comprising: providing a flexible substrate; forming a thin film transistor located on the flexible substrate; forming a control signal line, the control signal line is connected to the gate of the thin film transistor; forming an electrode site, the electrode site is connected to the source of the thin film transistor; forming a neural signal line, the neural signal line is connected to the drain of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The foregoing and other features and advantages of the present disclosure will become apparent from the following description of the embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are incorporated herein and form a part of the specification, and are further used to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. Among them:

[0007] Figure 1 shows a schematic cross-sectional view of a flexible neural electrode according to some embodiments of the present disclosure;

[0008] Figure 2 shows a schematic cross-sectional view of a flexible neural electrode according to some embodiments of the present disclosure;

[0009] Figure 3 shows a schematic cross-sectional view of a flexible neural electrode according to some embodiments of the present disclosure;

[0010] Figure 4 shows a schematic cross-sectional view of a flexible neural electrode according to some embodiments of the present disclosure;

[0011] Figure 5 A schematic partially exploded perspective view of a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0012] Figure 6 shows an exemplary circuit diagram of a flexible neural electrode according to some embodiments of the present disclosure;

[0013] Figure 7 An exemplary circuit diagram of a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0014] Figure 8 shows an exemplary circuit diagram of a flexible neural electrode according to some embodiments of the present disclosure;

[0015] Fig. 9 A schematic partially exploded perspective view of a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0016] Fig.10 A flow chart showing a method for preparing a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0017] Fig.11 A flow chart showing a method for preparing a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0018] Fig.12 Schematic cross-sectional views of flexible neural electrodes corresponding to corresponding steps of a non-limiting example process for preparing a flexible neural electrode according to some embodiments of the present disclosure are shown;

[0019] Fig.13A flow chart showing a method for preparing a flexible neural electrode according to some embodiments of the present disclosure is shown;

[0020] Fig.14 Schematic cross-sectional views of a flexible neural electrode corresponding to respective steps of a non-limiting example process for preparing a flexible neural electrode according to some embodiments of the present disclosure are shown.

[0021] Note that in the embodiments described below, sometimes the same reference numerals are used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In some cases, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0022] For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the present disclosure is not limited to the position, size, range, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0024] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0025] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0026] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0027] It can be understood that the "longitudinal direction" mentioned in this article refers to the length direction of the flexible neural electrode, the "transverse direction" refers to the width direction of the flexible neural electrode, the "longitudinal" and "transverse" together define the plane where the flexible neural electrode is located, and the "vertical direction" refers to the thickness direction of the flexible neural electrode and is perpendicular to the plane where the flexible neural electrode is located.

[0028] One electrode site of a flexible neural electrode can collect neural signals (usually in the form of electrical signals) from a corresponding neural site. Therefore, in order to obtain higher-resolution neural activity records, more electrode sites need to be arranged to collect electrical signals from more neural sites. After the electrode site of the flexible neural electrode collects the electrical signal, it is necessary to transmit the electrical signal to the external circuit via the corresponding channel. Usually, one channel is used to transmit the electrical signal from one electrode site. That is to say, as the number of electrode sites of the flexible neural electrode increases, the number of channels used to transmit electrical signals will also increase. For example, for a wireless implant system, in order to collect electrical signals from 1024 neural sites, 1024 electrode sites need to be arranged accordingly, and then 1024 channels need to be equipped to transmit these electrical signals respectively, and 1024 channel acquisition chips need to be set up to process these electrical signals. Therefore, increasing the number of channels will undoubtedly increase the power consumption of the wireless implant system, causing the endurance of the wireless implant system to decrease and fail to meet the use requirements. In addition, if these channels are arranged in the same layer in the flexible neural electrode with intervals from each other in the horizontal direction, the lateral size of the flexible neural electrode will increase, resulting in a higher risk of implant damage. If these channels are distributed in multiple vertically stacked layers in the flexible neural electrode, although it is possible to avoid the lateral size of the flexible neural electrode being too large, it will also increase the vertical size of the flexible neural electrode, which is still not conducive to use in some cases.

[0029] To this end, the present disclosure provides a flexible neural electrode, which sets a thin-film transistor (TFT) between each electrode site and the corresponding signal acquisition and processing channel, so that the electrode site can be gated by controlling the on and off of the thin-film transistor with a control signal. The flexible neural electrode according to the present disclosure can be a flexible active neural electrode, which has a signal gating function. The flexible neural electrode according to the present disclosure can allow multiple electrode sites to share a signal acquisition and processing channel in a time-division multiplexing manner, so that a smaller number of channels can be used when the number of neural sites to be measured is constant. In other words, more neural sites can be measured when the number of channels used is constant. The flexible neural electrode provided by the present disclosure has high-resolution signal acquisition capabilities and low system resource requirements, and can be used, for example but not limited to, as an implantable neural electrode and a cerebral cortex electrode.

[0030] The following will describe in detail the flexible neural electrodes according to some embodiments of the present disclosure in conjunction with the accompanying drawings. It is understood that the actual flexible neural electrode may have other components, and in order to avoid blurring the main points of the present disclosure, the accompanying drawings do not show and the present invention does not discuss other components. In addition, for the sake of simplicity, the components are depicted in some drawings in the form of legends.

[0031] Figure 1 A schematic cross-sectional view of a flexible neural electrode 100 according to some embodiments of the present disclosure is shown. The cross-sectional views of the present disclosure are all taken at the location of the electrode site of the flexible neural electrode. In some embodiments, the thickness t1 of the flexible neural electrode 100 is 1 micrometer (um) to 100um. Specifically, for example, the thickness of the flexible neural electrode can be 1um, 2um, 5um, 10um, 20um, 50um or 100um.

[0032] like Figure 1 As shown, the flexible neural electrode 100 includes a flexible substrate. The flexible substrate can be made of a biocompatible material with a low Young's modulus (e.g., close to or even lower than the Young's modulus of the brain). In some embodiments, the flexible substrate includes but is not limited to any one of polyimide (PI), SU8 (a photoresist), hydrogel, and polyparaxylene, or a combination thereof.

[0033] The flexible neural electrode 100 further includes a thin film transistor located on the flexible substrate, specifically, the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode.

[0034] The gate is used to control the switching state of the thin film transistor and is usually made of a conductive material. In this article, for example, one or more highly biocompatible metals such as but not limited to gold, platinum, titanium, etc. or a combination thereof may be used.

[0035] The gate insulating layer is located between the gate and the active layer to prevent current leakage, and is generally made of an oxide material, such as but not limited to silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, or a combination thereof.

[0036] The active layer may include one or more semiconductor materials, and specific examples of the materials include but are not limited to amorphous silicon semiconductor materials, polycrystalline silicon semiconductor materials, metal oxide semiconductor materials (such as but not limited to indium tin oxide, indium gallium zinc oxide, etc.), organic semiconductor materials, etc., or combinations thereof. In particular, the active layer may be an indium gallium zinc oxide (IGZO) thin film. Compared with thin film transistors with thin films of other materials as active layers, thin film transistors with IGZO thin films as active layers (hereinafter referred to as IGZO thin film transistors) have a larger switching ratio (i.e., the ratio of the current of the thin film transistor in the on state to the current in the off state) and a lower leakage current, and may have lower power consumption. Since neural signals are small signals in the microvolt (μV) range, IGZO thin film transistors are able to collect neural signals with a better signal-to-noise ratio by virtue of their larger switching ratio. In addition, IGZO thin film transistors are not prone to interfere with neural signals due to their smaller leakage current.

[0037] The source and drain are usually made of conductive materials, and one or more highly biocompatible metals can be used herein, such as but not limited to gold, platinum, titanium, etc. or a combination thereof. The present disclosure does not impose any particular restrictions on the materials of the various components of the thin film transistor, as long as it is suitable for forming components therein for realizing the corresponding functions. When a suitable voltage is applied to the gate, an electric field is generated between the gate and the source, which can control the carriers in the active layer to flow from the source to the drain, thereby forming a conducting state. When the voltage applied to the gate is too low, the carriers cannot be transmitted from the source to the drain through the active layer, thereby forming a cut-off state.

[0038] Understandably, Figure 1 The structure of the thin film transistor shown is only exemplary and not restrictive. Figure 1 The thin film transistor shown has only a single gate, but in some embodiments, a thin film transistor with a double gate may also be provided. Figure 2 As shown, the flexible neural electrode 100' is different from the flexible transistor 100 in that the thin film transistor of the flexible neural electrode 100' includes a double gate, specifically, a top gate and a bottom gate. For example, the thin film transistor of the flexible neural electrode 100' may be as follows: Figure 2 (a) as shown in the top contact structure (i.e., the source and drain are located on the top side of the active layer) or as shown in Figure 2(b) shows the bottom contact structure (i.e., the source and drain are located on the bottom side of the active layer). Compared with single-gate thin-film transistors, dual-gate thin-film transistors can have a larger switching ratio, resulting in better electrode site gating capability, and can collect neural signals with better signal-to-noise ratio. Compared with dual-gate thin-film transistors, single-gate thin-film transistors can have a simpler structure, smaller size, and lower power consumption. The number of gates of the thin-film transistor can be determined according to actual conditions. For example, dual-gate thin-film transistors can be advantageous in cases of higher electrode site gating switching frequencies or higher requirements for the signal-to-noise ratio of the collected neural signals. Single-gate thin-film transistors can be advantageous in cases where volume requirements or power consumption requirements are more stringent.

[0039] In addition, although Figure 1 The thin film transistor shown is a bottom gate top contact structure (i.e., the gate is located at the bottom side of the active layer, and the source and drain are located at the top side of the active layer), but in some embodiments, the thin film transistor may alternatively be any one of a bottom gate bottom contact (i.e., the gate is located at the bottom side of the active layer, and the source and drain are located at the bottom side of the active layer), a top gate bottom contact (i.e., the gate is located at the top side of the active layer, and the source and drain are located at the bottom side of the active layer), and a top gate top contact (i.e., the gate is located at the top side of the active layer, and the source and drain are located at the top side of the active layer). Specifically, for example, Figure 3 As shown: the difference between the flexible neural electrode 100A and the flexible transistor 100 is that the thin film transistor in the flexible neural electrode 100A has a bottom gate and a bottom contact; the difference between the flexible neural electrode 100B and the flexible transistor 100 is that the thin film transistor in the flexible neural electrode 100B has a top gate and a bottom contact; the difference between the flexible neural electrode 100C and the flexible transistor 100 is that the thin film transistor in the flexible neural electrode 100C has a top gate and a top contact.

[0040] The flexible neural electrode 100 further includes: a control signal line connected to the gate of the thin film transistor for applying a control signal to the gate of the thin film transistor; an electrode site for collecting electrical signals and connected to the source of the thin film transistor; and a neural signal line connected to the drain of the thin film transistor for transmitting electrical signals. When the control signal turns on the thin film transistor, the neural signal line receives the electrical signal via the thin film transistor.

[0041] Since the electrode site is connected to the source of the thin film transistor, the electrical signal collected by the electrode site can be transmitted to the source of the thin film transistor. When the voltage applied to the gate of the thin film transistor via the control signal is lower than the threshold voltage of the thin film transistor, the thin film transistor is turned off, so that the electrical signal cannot be transmitted to the neural signal line. When the voltage applied to the gate of the thin film transistor via the control signal is higher than the threshold voltage of the thin film transistor, the thin film transistor is turned on, so that the electrical signal can be transmitted to the neural signal line via the thin film transistor. Thus, the conduction or shutdown of the thin film transistor can be controlled by adjusting the control signal, thereby controlling the selection of the electrode site and the transmission of the electrical signal.

[0042] The control signal line and the neural signal line can each be formed of a single layer or multiple layers of highly biocompatible metal. In some embodiments, the control signal line and the neural signal line each include, but are not limited to, any one of gold, platinum, titanium, or a combination thereof. In some embodiments, the thickness t2 of the control signal line is 50 nanometers (nm) to 2um. In some embodiments, the thickness t3 of the neural signal line is 50nm to 2um. For example, the thickness of the control signal line and the neural signal line can each be 50nm, 60nm, 70nm, 100nm, 200nm, 500nm, 1um, 1.5um, or 2um.

[0043] The electrode sites can also be formed by a single layer or multiple layers of highly biocompatible metals. In some embodiments, the electrode sites include but are not limited to any one of gold, platinum, titanium or a combination thereof.

[0044] Although Figure 1 The gate, source, and drain of the thin film transistor are depicted as separate components from the control signal line, the electrode site, and the neural signal line, respectively, but this is merely exemplary and not restrictive. For example, a portion of the control signal line can form the gate of the thin film transistor. Additionally or alternatively, a portion of the neural signal line can form the drain of the thin film transistor. Additionally or alternatively, a portion or all of the electrode site can form the source of the thin film transistor. In other words, the source of the thin film transistor can be directly used as an electrode site.

[0045] refer to Figure 4 , which shows a schematic cross-sectional view of a flexible neural electrode according to some embodiments of the present disclosure. Figure 4 As shown, the difference between the flexible neural electrode 100D and the flexible neural electrode 100 is that a portion of the control signal line of the flexible neural electrode 100D forms the gate of the thin film transistor. Figure 4 As shown, the difference between the flexible neural electrode 100E and the flexible neural electrode 100 is that a portion of the neural signal line of the flexible neural electrode 100E forms the drain of the thin film transistor. Figure 4As shown, the difference between the flexible neural electrode 100F and the flexible neural electrode 100 is that the electrode site of the flexible neural electrode 100F forms the source of the thin film transistor.

[0046] In the process of preparing flexible neural electrodes, since the control signal line and the gate, the neural signal line and the drain, and the electrode site and the source can use the same conductive material and are in contact with each other, in some cases, a part of the control signal line can be formed as the gate of the thin film transistor while the control signal line is formed, and / or a part of the neural signal line can be formed as the drain of the thin film transistor while the neural signal line is formed, and / or a part or all of the electrode site can be formed as the source of the thin film transistor while the electrode site is formed, thereby simplifying the process steps, improving the efficiency of preparing flexible neural electrodes, and reducing the complexity of the structure of the flexible neural electrode and reducing the volume of the flexible neural electrode.

[0047] In some embodiments, continue to refer to Figure 1 The flexible neural electrode 100 may also include an electrode site modification layer located on the electrode site to reduce the interface impedance between the electrode site and the nerve, thereby improving the signal-to-noise ratio of the electrical signal collected by the electrode site and improving the quality of the electrical signal. For example, the electrode site modification layer may include a single layer or multiple layers of biocompatible materials. In some embodiments, the electrode site modification layer includes but is not limited to any one of platinum, titanium nitride, iridium oxide, poly (3,4-ethylenedioxythiophene) (PEDOT) or a combination thereof.

[0048] In some embodiments, the flexible neural electrode 100 includes a welding layer for connecting the end of the control signal line away from the thin film transistor and the end of the neural signal line away from the thin film transistor to an external circuit respectively. Figure 5 , which shows a schematic partial exploded perspective view of a flexible neural electrode 100 according to some embodiments of the present disclosure. Specifically, Figure 5 The portion of the flexible neural electrode 100 that is close to the external circuit and far from the implanted object (also referred to as the distal portion in this article) is shown. Figure 5As shown, the end 1022 of the neural signal line 102 away from the thin film transistor (not shown) and the end 1042 of the control signal line 104 away from the thin film transistor (not shown) are respectively connected to the corresponding welding layer 106 and then connected to the external circuit (not shown). In some embodiments, the external circuit can be a printed circuit board (PCB, Printed Circuit Board), a flexible circuit board (FPC, Flex Printed Circuit Board), a chip, etc. For example, the external circuit can be a multi-channel acquisition chip, so that the control signal can be transmitted to the gate of the thin film transistor used to select the target electrode site in the flexible neural electrode 100 via the control signal line 104 to turn on the thin film transistor, thereby receiving the electrical signal collected by the target electrode site via the neural signal line 102 for further processing. It can be understood that although Figure 5 It seems that the neural signal line 102 and the control signal line 104 each have only one bundle, but in fact they may each include many signal lines.

[0049] The flexible neural electrode 100 may include a plurality of thin film transistors and a corresponding plurality of control signal lines, a plurality of neural signal lines and a plurality of electrode sites. The thin film transistors and the electrode sites may be arranged in a one-to-one correspondence so that the gating of the corresponding electrode sites can be controlled by controlling each thin film transistor, so that the area of ​​interest can be flexibly selected and the electrical signal can be collected in a targeted manner. The thin film transistors may be arranged in a one-to-one correspondence with the control signal lines and / or the neural signal lines, respectively. Preferably, the thin film transistors may be arranged in a many-to-one configuration with the control signal lines and / or the neural signal lines, respectively, that is, a plurality of thin film transistors may share a control signal line, and / or a plurality of thin film transistors may share a neural signal line. The following describes the connection relationship between these thin film transistors and the control signal lines and the neural signal lines when the flexible neural electrode includes a plurality of thin film transistors in combination with various embodiments.

[0050] For ease of description, a certain thin film transistor in the flexible neural electrode is referred to as a first thin film transistor (it can be any thin film transistor in the flexible neural electrode, such as Figure 1 ), the control signal line connected to the first thin film transistor is referred to as a first control signal line, and the neural signal line connected to the first thin film transistor is referred to as a first neural signal line.

[0051] In some embodiments, the flexible neural electrode may further include one or more second thin film transistors located on the flexible substrate, and the gates of the one or more second thin film transistors and the gate of the first thin film transistor are connected to the first control signal line. Figure 6 , which shows an exemplary circuit diagram 200 of a flexible neural electrode according to some embodiments of the present disclosure. Figure 6 As shown, the gate of the first thin film transistor 202 and the gates of the three second thin film transistors 204 are connected to a control signal line, and the drain of the first thin film transistor 202 and the drain of the three second thin film transistors 204 are connected to the neural signal lines 1, 2, 3, and 4 respectively. Thus, four thin film transistors can be controlled simultaneously through one control signal line. It can be understood that Figure 6 This is merely exemplary and not restrictive, and one control signal line can be used to control the gates of two, three, four, five or more thin film transistors. Multiple thin film transistors whose gates are commonly connected to the same control signal line will be turned on or off simultaneously according to the control signal. At this time, the electrical signal at the electrode site to which each of these thin film transistors is connected can be transmitted by using different neural signal lines, thereby achieving separate collection of the electrode sites.

[0052] In some embodiments, the flexible neural electrode further comprises one or more third thin film transistors located on the flexible substrate, and the drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the first neural signal line. Figure 7 , which shows an exemplary circuit diagram 300 of a flexible neural electrode according to some embodiments of the present disclosure. Figure 7 As shown, the drain of the first thin film transistor 302 and the drains of the three third thin film transistors 304 are connected to one neural signal line, and the gate of the first thin film transistor 302 and the gates of the three third thin film transistors 304 are connected to control signal lines 1, 2, 3, and 4 respectively. Thus, one neural signal line can be used to collect electrical signals from four electrode sites. It can be understood that Figure 7 It is merely exemplary and not restrictive. One neural signal line can be connected to the drains of two, three, four, five or more thin film transistors to be used as a shared signal acquisition channel by the corresponding two, three, four, five or more electrode sites. At this time, the on and off of these thin film transistors can be controlled by different control signal lines, so that only one of the thin film transistors is turned on at the same time and the other thin film transistors are turned off, so as to transmit the electrical signal collected by the electrode site connected to the turned-on thin film transistor via the neural signal line. One neural signal line can be used to transmit electrical signals collected by multiple electrode sites by time division multiplexing. Therefore, compared with traditional flexible neural electrodes, flexible neural electrodes with such circuit configuration can have higher resolution signal acquisition capabilities.

[0053] The flexible neural electrode may include a plurality of thin film transistors located on a flexible substrate, the plurality of thin film transistors including, for example, a first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors. The flexible neural electrode may include a plurality of control signal lines, the plurality of control signal lines including, for example, a first control signal line. The flexible neural electrode may include a plurality of neural signal lines, the plurality of neural signal lines including, for example, a first neural signal line. In some embodiments, the gate of the one or more second thin film transistors and the gate of the first thin film transistor are connected to the first control signal line, and the drain of each of the one or more second thin film transistors and the first thin film transistor are respectively connected to a corresponding one of the plurality of neural signal lines. In addition, in these embodiments, the drain of the one or more third thin film transistors and the drain of the first thin film transistor are connected to the first neural signal line, and the gate of each of the one or more third thin film transistors and the first thin film transistor are respectively connected to a corresponding one of the plurality of control signal lines.

[0054] refer to Figure 8 , which shows an exemplary circuit diagram 400 of a flexible neural electrode according to some embodiments of the present disclosure. Figure 8 As shown, the gate of the first thin film transistor 402 and the gates of the seven second thin film transistors 404 are commonly connected to the control signal line 1 (i.e., the first control signal line), and the drain of the first thin film transistor 402 and the drains of the seven second thin film transistors 404 are respectively connected to the neural signal lines 1 to 8. In addition, the drain of the first thin film transistor 402 and the drains of the three third thin film transistors 406 are commonly connected to the neural signal line 1 (i.e., the first neural signal line), and the gate of the first thin film transistor 402 and the gates of the three third thin film transistors 406 are respectively connected to the control signal lines 1 to 4. It can be understood that although the first thin film transistor 402 is depicted as Figure 8 The first thin film transistor 402 may be a thin film transistor at the first row and the first column in FIG. Figure 8 The second thin film transistor 404 may be any thin film transistor in the same column as the thin film transistor, and the third thin film transistor 406 may be any thin film transistor in the same row as the thin film transistor.

[0055] Therefore, from the perspective of the circuit configuration of the flexible neural electrode, by arranging multiple thin-film transistors in the flexible neural electrode in the form of an m×n array, the drain of each row of thin-film transistors is connected to the same neural signal line, and the gate of each column of thin-film transistors is connected to the same control signal line, so that the signal acquisition control of m×n electrode sites can be realized with m neural signal lines and n control signal lines. Therefore, with a limited number of channels, the signal acquisition capability of the flexible neural electrode is significantly improved, and each electrode site can be addressed individually. Exemplarily, the values ​​of m and n can depend on the desired number of electrode sites and channels. For example, if it is desired to set 1024 electrode sites and use a 256-channel acquisition chip, then the number of neural signal lines can be 256, and the number of control signal lines can be 4, that is, m=256, n=4.

[0056] In some embodiments, the plurality of control signal lines are arranged together at a first height from the flexible substrate, the plurality of neural signal lines are arranged together at a second height from the flexible substrate, and the plurality of control signal lines are separated from the plurality of neural signal lines by an insulating layer. Fig. 9 , which shows a schematic partial exploded perspective view of a flexible neural electrode 100 according to some embodiments of the present disclosure. Specifically, Fig. 9 FIG. 2 shows a portion of the flexible neural electrode 100 that is away from the external circuit and close to the implanted object (hereinafter, may also be referred to as the proximal portion). Fig. 9 As shown, a plurality of control signal lines 104 are arranged together at a first height from the flexible substrate 114, and a plurality of neural signal lines 102 are arranged together at a second height from the flexible substrate 114. That is, a plurality of control signal lines 104 are arranged together in one wiring layer, and a plurality of neural signal lines 102 are arranged together in another wiring layer. In addition, an insulating layer 108 is arranged between the two wiring layers to separate the plurality of control signal lines 104 and the plurality of neural signal lines 102. It can be understood that when the thin film transistor adopts a bottom gate configuration (such as Figure 1 The flexible neural electrode 100 shown, Figure 2 The flexible neural electrode 100 ′ shown Figure 3 The flexible neural electrode 100A shown, Figure 4 When the flexible neural electrodes 100D, 100E, 100F, etc. are shown in the figure, the first height may be less than the second height, that is, the wiring layer where the plurality of control signal lines 104 are located is closer to the flexible substrate 114 than the wiring layer where the plurality of neural signal lines 102 are located, for example, Fig. 9 When the thin film transistor adopts a top-gate configuration (such as Figure 3When the flexible neural electrode 100B, 100C, etc. is shown in the figure, the first height can be greater than the second height, that is, the wiring layer where the multiple control signal lines 104 are located is farther away from the flexible substrate 114 than the wiring layer where the multiple neural signal lines 102 are located. Arranging the multiple control signal lines 104 and the multiple neural signal lines 102 in different wiring layers is conducive to reducing the lateral size of the flexible neural electrode, thereby reducing the risk of implantation loss.

[0057] Further, in some embodiments, a plurality of control signal lines are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, a plurality of neural signal lines are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and a plurality of thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

[0058] like Fig. 9 As shown, the arrow indicates the longitudinal direction of the flexible neural electrode 100. It can be seen that multiple control signal lines 104 extend along the longitudinal direction of the flexible neural electrode 100, multiple neural signal lines 102 extend along the longitudinal direction of the flexible neural electrode 100, and multiple thin film transistors 112 are linearly arranged along the longitudinal direction of the flexible neural electrode 100.

[0059] Combination Figure 5 It can be understood that the multiple control signal lines 104 and the multiple neural signal lines 102 extend along the longitudinal direction of the flexible neural electrode 100 to form their respective aforementioned ends 1042, 1022 away from the thin film transistor, thereby respectively connecting to the welding layer 106 for connection to an external circuit.

[0060] It can also be understood that in the circuit configuration, the plurality of thin film transistors in the flexible neural electrode 100 can be in the form of an m×n array (e.g., Figure 8 8×4 array shown in the figure), but in the actual structure, these thin film transistors can be arranged linearly along the longitudinal direction of the flexible neural electrode 100. Specifically, in the actual structure, the m×n array of thin film transistors can be unfolded, for example, these thin film transistors can be arranged linearly in the longitudinal direction of the flexible neural electrode 100 row by row or column by column. It can be understood that the m×n array of thin film transistors can be linearly unfolded and arranged in the longitudinal direction of the flexible neural electrode 100 in any order, but unfolding row by row or column by column can be beneficial to simplify circuit connection.

[0061] like Fig. 9 As shown, each of the four thin film transistors may correspond to Figure 8 For example, Fig. 9 The thin film transistors 112-1, 112-2, 112-3, and 112-4 in Figure 8 If every four thin film transistors are regarded as a group of thin film transistors, then Fig. 9 The 32 thin film transistors in the can be divided into 8 groups of thin film transistors, each group of thin film transistors corresponding to Figure 8 The drains of the four thin film transistors (e.g., 112-1, 112-2, 112-3, 112-4) in each group of thin film transistors are connected to the same neural signal line 102, and the thin film transistors (e.g., 112-1, 112-2, 112-3, 112-4) in each group of thin film transistors are connected to different control signal lines 104. In addition, the i-th thin film transistor (e.g., 112-i, i is 1, 2, 3, 4) in each group of thin film transistors corresponds to Figure 8 A corresponding column of the four columns of thin film transistors in the TFT array is connected to the same control signal line 104 .

[0062] By linearly arranging multiple thin-film transistors in the longitudinal direction of the flexible neural electrode and making these thin-film transistors share control signal lines or neural signal lines in the manner described above, it is possible to achieve improved signal acquisition capabilities with a limited number of channels and reduce the lateral size of the flexible neural electrode to facilitate subsequent implantation.

[0063] like Fig. 9 As shown, a plurality of thin film transistors 112 linearly arranged in the longitudinal direction of the flexible neural electrode may have a common gate insulating layer 110. In other words, the gate insulating layer 110 may extend continuously across the gates 120 of the plurality of thin film transistors 112, so that the portion thereof above the gate 120 of each thin film transistor 112 may be used as the gate insulating layer of the thin film transistor 112. This is conducive to simplifying the manufacturing process.

[0064] Also like Fig. 9 As shown, a through hole 122 can be formed in the insulating layer 108 above the selected position of the corresponding control signal line 104 and filled with a conductive material for preparing the gate 120 of the corresponding thin film transistor 112 or providing a conductive connection portion for connecting the corresponding control signal line 104 to the gate 120. In addition, the flexible neural electrode 100 can be encapsulated with an encapsulation layer 124, so that the control signal line 104, the thin film transistor 112, and the neural signal line 102 are wrapped between the flexible substrate 104 and the encapsulation layer 124. A through hole 128 can be formed in the encapsulation layer 124 above the source of the corresponding thin film transistor 112 to expose the source of the thin film transistor 112 as an electrode site, or a conductive material can be filled therein to prepare the corresponding electrode site or provide a conductive connection portion for connecting the corresponding source to the electrode site. An electrode site modification layer 126 can also be provided above each electrode site to improve the interface impedance between the electrode site and the nerve.

[0065] The present disclosure also provides a method for preparing a flexible neural electrode. The method for preparing a flexible neural electrode according to some embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It is understood that the actual method may have other steps, and in order to avoid blurring the main points of the present disclosure, the accompanying drawings are not shown and the present invention does not discuss other steps.

[0066] refer to Fig.10 , which shows a flow chart of a method 500 for preparing a flexible neural electrode according to some embodiments of the present disclosure. Fig.10 As shown, method 500 includes: at step S502, providing a flexible substrate; at step S504, forming a thin film transistor located on the flexible substrate; at step S506, forming a control signal line, the control signal line is connected to the gate of the thin film transistor; at step S508, forming an electrode site, the electrode site is connected to the source of the thin film transistor; at step S510, forming a neural signal line, the neural signal line is connected to the drain of the thin film transistor.

[0067] The thin film transistor in the flexible neural electrode prepared based on method 500 can be a single-gate structure or a double-gate structure, a top-gate structure or a bottom-gate structure, a top-contact structure or a bottom-contact structure, depending on the order and quantity of forming the gate, active layer, source and drain in the specific preparation process.

[0068] The flexible neural electrode according to any of the above embodiments can be obtained by the method 500. Various embodiments of the method 500 can be similar to the various embodiments described above regarding the flexible neural electrode, and will not be described in detail here.

[0069] refer to Fig.11 , which shows a flow chart of a method 600 for preparing a flexible neural electrode according to some embodiments of the present disclosure. As an exemplary implementation of method 500, method 600 can be used to prepare a flexible neural electrode including a thin film transistor with a bottom gate structure.

[0070] Specifically, Fig.11As shown, method 600 includes: at step S602, forming a flexible substrate layer (to provide a flexible substrate); at step S604, forming a first wiring layer on the flexible substrate layer, the first wiring layer including a control signal line; at step S606, forming an insulating layer on the first wiring layer; at step S608, forming a thin film transistor on the insulating layer, the control signal line is connected to the gate of the thin film transistor; at step S610, forming a second wiring layer on the thin film transistor, the second wiring layer including a neural signal line, the neural signal line is connected to the drain of the thin film transistor; at step S612, forming an electrode site layer on the thin film transistor, the electrode site layer including an electrode site, the electrode site is connected to the source of the thin film transistor. The thin film transistor in the flexible neural electrode prepared based on method 600 is a bottom gate structure, for example, it may include a bottom gate top contact and a bottom gate bottom contact.

[0071] It can be understood that in some embodiments, a portion of the control signal line can form the gate of the thin film transistor, in such an embodiment, step S608 can be at least partially included in step S604, or vice versa. In some embodiments, a portion of the neural signal line can form the drain of the thin film transistor, in such an embodiment, step S608 can be at least partially included in step S610, or vice versa. In some embodiments, a portion or all of the electrode sites can form the source of the thin film transistor, in such an embodiment, step S608 can be at least partially included in step S612, or vice versa.

[0072] For ease of description, the thin film transistor formed in the aforementioned method 600 may be referred to as a first thin film transistor, the control signal line may be referred to as a first control signal line, and the neural signal line may be referred to as a first neural signal line.

[0073] In some embodiments, the method 600 includes: forming one or more second thin film transistors on the insulating layer, wherein gates of the one or more second thin film transistors and a gate of the first thin film transistor are commonly connected to the first control signal line.

[0074] In some embodiments, method 600 includes: forming one or more third thin film transistors on the insulating layer, wherein drains of the one or more third thin film transistors and a drain of the first thin film transistor are commonly connected to the first neural signal line.

[0075] In some embodiments, method 600 includes: forming a first wiring layer on a flexible substrate layer, the first wiring layer including a plurality of control signal lines, the plurality of control signal lines including a first control signal line; forming a plurality of thin film transistors on an insulating layer, the plurality of thin film transistors including a first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors; forming a second wiring layer on the plurality of thin film transistors, the second wiring layer including a plurality of neural signal lines, the plurality of neural signal lines including a first neural signal line. In this embodiment, the gates of the one or more second thin film transistors and the gate of the first thin film transistor are connected to the first control signal line, and the drains of the one or more second thin film transistors and each of the first thin film transistors are connected to a corresponding one of the plurality of neural signal lines. And, in this embodiment, the drains of the one or more third thin film transistors and the drain of the first thin film transistor are connected to the first neural signal line, and the gates of the one or more third thin film transistors and each of the first thin film transistors are connected to a corresponding one of the plurality of control signal lines.

[0076] In some embodiments, multiple control signal lines in the first wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, multiple neural signal lines in the second wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and multiple thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

[0077] In some embodiments, method 600 includes: forming a packaging layer to package the flexible neural electrode. Further, in some embodiments, method 600 includes at least one of the following: etching the packaging layer to expose the electrode site and forming an electrode site modification layer on the electrode site to reduce the interface impedance between the electrode site and the nerve; etching the packaging layer to expose the end of the neural signal line away from the thin film transistor and forming a first welding layer on the exposed end of the neural signal line for connection to an external circuit; etching the packaging layer and the insulating layer to expose the end of the control signal line away from the thin film transistor and forming a second welding layer on the exposed end of the control signal line for connection to an external circuit.

[0078] Various embodiments of method 600 may be similarly described with reference to the various embodiments of the flexible neural electrode described above, and will not be described in detail here.

[0079] Combine the following Fig.12A schematic cross-sectional view of a flexible neural electrode corresponding to corresponding steps of a non-limiting exemplary process 700 for preparing a flexible neural electrode. In this article, the corresponding film layer can be formed by various suitable means, such as but not limited to spin coating, spray coating, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc., and any suitable means can be used to form the corresponding grooves, through holes, etc., including but not limited to dry etching or wet etching, etc., which will not be described in detail here.

[0080] like Fig.12 As shown in (a), a flexible substrate layer is formed.

[0081] For example, a polyimide film can be spin-coated on a carrier to make a flexible substrate layer, and a vacuum oven can be used for heating and curing. Prior to this, a carrier suitable for micro-nano processing (such as glass or silicon wafer) can be selected according to the size requirements of the flexible neural electrode and the carrier can be cleaned with an organic solvent (such as acetone) (for example, by immersion, etc., and ultrasound can be applied if necessary), and then the carrier can be rinsed with deionized water and dried (for example, blown dry with nitrogen, or dried by heating, etc.). Next, a double layer of glue can be prepared on the carrier using a uniform glue and photolithography process, a sacrificial layer (not shown) can be deposited on the carrier using an evaporation process, and acetone and a developer can be used, for example, for stripping and degumming. A flexible substrate layer can be prepared on top of the sacrificial layer.

[0082] like Fig.12 As shown in (b), a control signal line is formed on the flexible substrate layer.

[0083] For example, a double layer of glue (which provides the desired control signal line pattern) can be prepared on the cured polyimide film flexible substrate layer using a coating and photolithography process, and 100 nm of gold can be deposited on the flexible substrate layer as the control signal line using an evaporation process, and then stripped and debonded using, for example, acetone and a developer.

[0084] like Fig.12 As shown in (c), an insulating layer is formed on the control signal line, and a through hole is formed in the insulating layer above a selected position of the control signal line for connecting the control signal line to a gate of a subsequently formed thin film transistor. It can be understood that although only one through hole is depicted in the figure, multiple through holes for multiple thin film transistors can actually be formed simultaneously.

[0085] For example, a polyimide film can be spin-coated on the carrier again as an insulating layer and heated and cured in a vacuum oven. Then, the position of the through hole connecting the control signal line and the gate of the thin film transistor can be defined by using a coating and photolithography process, and the polyimide film can be etched by a dry etching device to form a through hole, and the coating can be removed after the etching is completed.

[0086] like Fig.12As shown in (d), a gate of a thin film transistor connected to a control signal line is formed in the through hole, and a gate insulating layer, an active layer, and a source and drain of the thin film transistor are formed in sequence. It can be understood that what is shown here is a top contact structure. If a bottom contact structure is to be realized, the preparation order of the active layer and the source and drain can be reversed. The source electrode can be directly used as an electrode site, and the drain electrode can be formed integrally with the neural signal line. It can be understood that although only one thin film transistor is depicted in the figure, in fact, multiple gates, multiple gate insulating layers, multiple active layers, and multiple source and drain electrodes for multiple thin film transistors can be formed simultaneously in each step.

[0087] For example, a double-layer glue (which provides the desired gate pattern) can be prepared using a photolithography process, and a 100nm gold can be deposited on the insulating layer using an evaporation process as a gate (the gate can be formed as part of the control signal line), and acetone and a developer can be used for stripping and degumming. Then, chemical vapor deposition can be used to deposit, for example, 100nm silicon dioxide on the gate as a gate insulating layer, and after the position of the gate insulating layer is defined using a photolithography process, a dry etching device is used to etch the silicon dioxide and degumming is performed after the etching is completed. Then, a thin film of indium gallium zinc oxide is deposited on the gate insulating layer using magnetron sputtering as an active layer, and after the active layer area is defined using a photolithography process, a nitric acid mixture is used to etch the indium gallium zinc oxide, and degumming is performed after the etching is completed. Then, a double layer of glue (which provides the desired source (electrode site) / drain (neural signal line) pattern) can be prepared using a photolithography process, and a vapor deposition process can be used to deposit, for example, 100 nm of gold on the active layer as electrode sites (a portion of which contacts the active layer to form the source) and neural signal lines (a portion of which contacts the active layer to form the drain), and acetone and a developer can be used for stripping and de-bonding.

[0088] like Fig.12 As shown in (e), a packaging layer is formed to encapsulate the flexible neural electrode, and a through hole is formed in the packaging layer above the electrode site for connecting the electrode site with the electrode site modification layer formed subsequently. It can be understood that although only one through hole is depicted in the figure, multiple through holes for multiple electrode sites can actually be formed simultaneously. Although not shown, through holes can also be formed in the packaging layer above the distal ends of the neural signal line and the control signal line respectively for connecting the corresponding signal lines with the welding layer formed subsequently.

[0089] For example, a polyimide film can be spin-coated as an encapsulation layer and heated and cured in a vacuum oven. Then, the overall contour of the flexible neural electrode, the through-hole position connecting the electrode site modification layer to the electrode site (the source of the thin-film transistor), and the through-hole position connecting the welding layer to the control signal line and the neural signal line can be defined using a coating and photolithography process. The polyimide film is etched using a dry etching device, and acetone and a developer are used for stripping and debonding.

[0090] like Fig.12 As shown in (f), an electrode site modification layer is formed on the electrode site to reduce the interface impedance between the electrode site and the nerve. Although not shown, welding layers can also be formed on the distal ends of the nerve signal line and the control signal line for connection to an external circuit.

[0091] For example, a double layer of glue can be prepared by using photolithography process, and the electrode site modification layer and the welding layer can be prepared by using magnetron sputtering or evaporation. The electrode site modification layer is connected to the source (electrode site) of the thin film transistor, and the welding layer is connected to the distal end of the control signal line and the distal end of the neural signal line respectively.

[0092] Finally, the sacrificial layer can be removed (e.g., by an etching process) to release the flexible neural electrode.

[0093] refer to Fig.13 , which shows a flow chart of a method 800 for preparing a flexible neural electrode according to some other embodiments of the present disclosure. As an exemplary implementation of method 500, method 800 can be used to prepare a flexible neural electrode including a thin film transistor with a top gate structure.

[0094] Specifically, Fig.13 As shown, method 800 includes: at step S802, forming a flexible substrate layer (to provide a flexible substrate); at step S804, forming a first wiring layer on the flexible substrate layer, the first wiring layer including a neural signal line; at step S806, forming a thin film transistor on the first wiring layer, the neural signal line is connected to the drain of the thin film transistor; at step S808, forming an insulating layer on the thin film transistor; at step S810, forming a second wiring layer on the insulating layer, the second wiring layer including a control signal line, the control signal line is connected to the gate of the thin film transistor; at step S812, forming an electrode site layer on the thin film transistor, the electrode site layer including an electrode site, the electrode site is connected to the source of the thin film transistor. The thin film transistor in the flexible neural electrode prepared based on method 800 is a top gate structure, for example, it may include a top gate top contact and a top gate bottom contact.

[0095] It can be understood that in some embodiments, a portion of the control signal line can form the gate of the thin film transistor, in such an embodiment, step S806 can be at least partially included in step S810, or vice versa. In some embodiments, a portion of the neural signal line can form the drain of the thin film transistor, in such an embodiment, step S806 can be at least partially included in step S804, or vice versa. In some embodiments, a portion or all of the electrode sites can form the source of the thin film transistor, in such an embodiment, step S806 can be at least partially included in step S812, or vice versa.

[0096] For ease of description, the thin film transistor formed in the aforementioned method 800 may be referred to as a first thin film transistor, the control signal line may be referred to as a first control signal line, and the neural signal line may be referred to as a first neural signal line.

[0097] In some embodiments, the method 800 includes: forming one or more second thin film transistors on the first wiring layer, wherein gates of the one or more second thin film transistors and a gate of the first thin film transistor are commonly connected to the first control signal line.

[0098] In some embodiments, method 800 includes: forming one or more third thin film transistors on the first wiring layer, wherein drains of the one or more third thin film transistors and a drain of the first thin film transistor are commonly connected to the first neural signal line.

[0099] In some embodiments, method 800 includes: forming a first wiring layer on a flexible substrate layer, the first wiring layer including a plurality of neural signal lines, the plurality of neural signal lines including a first neural signal line; forming a plurality of thin film transistors on the first wiring layer, the plurality of thin film transistors including a first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors; forming a second wiring layer on an insulating layer, the second wiring layer including a plurality of control signal lines, the plurality of control signal lines including a first control signal line. In this embodiment, the gates of the one or more second thin film transistors and the gate of the first thin film transistor are connected to the first control signal line, and the drains of the one or more second thin film transistors and each thin film transistor in the first thin film transistor are respectively connected to a corresponding one of the plurality of neural signal lines. And, in this embodiment, the drains of the one or more third thin film transistors and the drain of the first thin film transistor are connected to the first neural signal line, and the gates of the one or more third thin film transistors and each thin film transistor in the first thin film transistor are respectively connected to a corresponding one of the plurality of control signal lines.

[0100] In some embodiments, a plurality of neural signal lines in a first wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, a plurality of control signal lines in a second wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and a plurality of thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

[0101] In some embodiments, method 800 includes: forming a packaging layer to package the flexible neural electrode. Further, in some embodiments, method 800 includes: etching the packaging layer to expose the electrode site and forming an electrode site modification layer on the electrode site to reduce the interface impedance between the electrode site and the nerve; etching the packaging layer to expose the end of the control signal line away from the thin film transistor and forming a first welding layer on the exposed end of the control signal line for connection to an external circuit; etching the packaging layer and the insulating layer to expose the end of the neural signal line away from the thin film transistor and forming a second welding layer on the exposed end of the neural signal line for connection to an external circuit.

[0102] Various embodiments of method 800 may be similar to various embodiments described above with respect to flexible neural electrodes, and will not be described in detail here. In addition, the main difference between method 600 and method 800 is that the former is used to form a thin film transistor with a bottom gate structure and the latter is used to form a thin film transistor with a top gate structure, so they are similar in other aspects and can be referenced to each other.

[0103] Combine the following Fig.14 Schematic cross-sectional views of a flexible neural electrode corresponding to respective steps of a non-limiting example process 900 for preparing a flexible neural electrode.

[0104] like Fig.14 As shown in (a), a flexible substrate layer is formed.

[0105] For example, a polyimide film can be spin-coated on a carrier to make a flexible substrate layer, and a vacuum oven can be used for heating and curing. Prior to this, a carrier suitable for micro-nano processing (such as glass or silicon wafer) can be selected according to the size requirements of the flexible neural electrode and the carrier can be cleaned with an organic solvent (such as acetone) (for example, by immersion, etc., and ultrasound can be applied if necessary), and then the carrier can be rinsed with deionized water and dried (for example, blown dry with nitrogen, or dried by heating, etc.). Next, a double layer of glue can be prepared on the carrier using a uniform glue and photolithography process, a sacrificial layer (not shown) can be deposited on the carrier using an evaporation process, and acetone and a developer can be used, for example, for stripping and degumming. A flexible substrate layer can be prepared on top of the sacrificial layer.

[0106] like Fig.14As shown in (b), electrode sites (serving as sources of thin-film transistors to be formed subsequently) and neural signal lines (part of which serves as drains of thin-film transistors to be formed subsequently) are formed on the flexible substrate layer.

[0107] For example, a double layer of glue (which provides the desired source (electrode site) / drain (neural signal line) pattern) can be prepared using a photolithography process, and a vapor deposition process can be used to deposit, for example, 100 nm of gold on the flexible substrate layer as electrode sites (serving as the source of the subsequently formed thin-film transistor) and neural signal lines (part of which serves as the drain of the subsequently formed thin-film transistor), and then acetone and a developer can be used for stripping and de-bonding.

[0108] like Fig.14 As shown in (c), the active layer, gate insulating layer and gate of the thin film transistor are formed in sequence on the source and drain. It can be understood that the bottom contact structure is shown here. If a top contact structure is to be realized, the preparation order of the active layer and the source and drain electrodes can be reversed. It can be understood that although only one thin film transistor is depicted in the figure, in fact, multiple source and drain electrodes, multiple active layers, multiple gate insulating layers and multiple gates for multiple thin film transistors can be formed simultaneously in each step.

[0109] For example, magnetron sputtering can be used to deposit an indium gallium zinc oxide thin film on a flexible substrate layer as an active layer, and after using a photoresist and photolithography process to define the active layer area, a nitric acid mixture is used to etch the indium gallium zinc oxide, and after the etching is completed, the photoresist is removed. Then, chemical vapor deposition can be used to deposit, for example, 100nm of silicon dioxide as a gate insulating layer on the active layer, and after using a photoresist and photolithography process to define the position of the gate insulating layer, a dry etching device is used to etch the silicon dioxide, and after the etching is completed, the photoresist is removed. Then, a double-layer photoresist (which provides the desired gate pattern) can be prepared using a photoresist and photolithography process, and a 100nm of gold can be deposited on the gate insulating layer using an evaporation process as the gate of a thin film transistor, and acetone and a developer are used for stripping and photoresist removal.

[0110] like Fig.14 As shown in (d), an insulating layer is formed on the thin film transistor.

[0111] For example, a polyimide film can be spin-coated on a thin film transistor as an insulating layer and heated and cured using a vacuum oven.

[0112] like Fig.14 As shown in (e), a through hole is formed in the insulating layer above the corresponding gate to connect the gate to a control signal line formed subsequently. It can be understood that although only one through hole is depicted in the figure, multiple through holes for multiple thin film transistors can actually be formed simultaneously.

[0113] For example, the position of the through hole connecting the control signal line and the gate can be defined by using a photolithography process, and the polyimide film can be etched using a dry etching device to expose the gate, and the photolithography process can be performed after the etching is completed.

[0114] like Fig.14 As shown in (f), a control signal line connected to the gate of the thin film transistor is formed in the through hole and on the insulating layer.

[0115] For example, a double layer of glue (which provides the desired control signal line pattern) can be prepared on the cured polyimide film insulating layer using a photolithography process, and a vapor deposition process can be used to deposit, for example, 100 nm of gold on the insulating layer as a control signal line to connect to the gate, and then acetone and a developer can be used for stripping and de-gluing.

[0116] like Fig.14 As shown in (g), a packaging layer is formed to encapsulate the flexible neural electrode, and a through hole is formed in the packaging layer above the electrode site for connecting the electrode site with the electrode site modification layer formed subsequently. It can be understood that although only one through hole is depicted in the figure, multiple through holes for multiple electrode sites can actually be formed simultaneously. Although not shown, through holes can also be formed in the packaging layer above the distal ends of the neural signal line and the control signal line respectively for connecting the corresponding signal lines with the welding layer formed subsequently.

[0117] For example, a polyimide film can be spin-coated as an encapsulation layer and heated and cured in a vacuum oven. Then, the overall contour of the flexible neural electrode, the through-hole position connecting the electrode site modification layer to the electrode site (the source of the thin-film transistor), and the through-hole position connecting the welding layer to the control signal line and the neural signal line can be defined using a coating and photolithography process. The polyimide film is etched using a dry etching device, and acetone and a developer are used for stripping and debonding.

[0118] like Fig.14 As shown in (h), an electrode site modification layer is formed on the electrode site to reduce the interface impedance between the electrode site and the nerve. Although not shown, welding layers can also be formed on the distal ends of the nerve signal line and the control signal line for connection to an external circuit.

[0119] For example, a double layer of glue can be prepared by using photolithography process, and the electrode site modification layer and the welding layer can be prepared by using magnetron sputtering or evaporation. The electrode site modification layer is connected to the source (electrode site) of the thin film transistor, and the welding layer is connected to the distal end of the control signal line and the distal end of the neural signal line respectively.

[0120] Finally, the sacrificial layer can be removed (e.g., by an etching process) to release the flexible neural electrode.

[0121] The flexible neural electrode disclosed in the present invention is integrated with a flexible circuit that uses thin-film transistors to realize the electrode site selection function, and can use limited signal acquisition and processing channels to acquire and process neural signals from a large number of sites in a time-division multiplexing manner, thereby achieving higher-resolution signal acquisition while reducing the demand for system resources such as acquisition chips.

[0122] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be otherwise oriented (rotated 90 degrees or at other orientations), and the relative spatial relationships will be interpreted accordingly.

[0123] In the specification and claims, when an element is said to be "above", "attached" to, "connected" to, "coupled" to, "coupled to", or "in contact with" another element, the element may be directly above, directly attached to, directly connected to, directly coupled to, directly coupled to, or directly in contact with another element, or one or more intermediate elements may be present. In contrast, when an element is said to be "directly" "above", "directly attached" to, "directly connected" to, "directly coupled" to, "directly coupled to", or "in direct contact with" another element, there will be no intermediate elements. In the specification and claims, a feature is arranged "adjacent" to another feature, which may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is above or below an adjacent feature.

[0124] As used herein, the word "exemplary" means "used as an example, instance or illustration", rather than as a "model" to be exactly copied. Any implementation described exemplarily herein is not necessarily to be construed as being preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any stated or implied theory given in the technical field, background technology, content of the invention or specific embodiments. In addition, for reference purposes only, "first", "second" and similar terms may also be used herein, and are therefore not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second" and other such numerical words referring to structures or elements do not imply an order or sequence. It should also be understood that when the word "include / comprises" is used herein, it indicates the presence of the indicated features, wholes, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0125] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0126] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0127] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A flexible neural electrode, comprising: Flexible substrate; a thin film transistor located on the flexible substrate; a control signal line, the control signal line being connected to the gate of the thin film transistor to apply a control signal to the gate of the thin film transistor; An electrode site, the electrode site is used to collect an electrical signal and is connected to a source electrode of the thin film transistor; a neural signal line connected to the drain of the thin film transistor for transmitting the electrical signal, Wherein, when the control signal turns on the thin film transistor, the neural signal line receives the electrical signal via the thin film transistor.

2. The flexible neural electrode according to claim 1, wherein: The thin film transistor is a first thin film transistor, The flexible neural electrode further includes one or more second thin film transistors located on the flexible substrate, and the gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the control signal line.

3. The flexible neural electrode according to claim 1, wherein: The thin film transistor is a first thin film transistor, The flexible neural electrode further comprises one or more third thin film transistors located on the flexible substrate, and the drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the neural signal line.

4. The flexible neural electrode according to claim 1, wherein: The thin film transistor is a first thin film transistor, the control signal line is a first control signal line, and the neural signal line is a first neural signal line. The flexible neural electrode includes a plurality of thin film transistors located on the flexible substrate, and the plurality of thin film transistors include the first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors. The flexible neural electrode includes a plurality of control signal lines and a plurality of neural signal lines, the plurality of control signal lines include the first control signal line, and the plurality of neural signal lines include the first neural signal line. The gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the first control signal line, and the drains of the one or more second thin film transistors and each of the first thin film transistors are respectively connected to a corresponding one of the plurality of neural signal lines. The drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the first neural signal line, and the gate of each thin film transistor in the one or more third thin film transistors and the first thin film transistor is respectively connected to a corresponding one of the multiple control signal lines.

5. The flexible neural electrode according to claim 4, wherein: The plurality of control signal lines are arranged together at a first height from the flexible substrate, the plurality of neural signal lines are arranged together at a second height from the flexible substrate, and the plurality of control signal lines are separated from the plurality of neural signal lines by an insulating layer.

6. The flexible neural electrode according to claim 5, wherein: The multiple control signal lines are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, the multiple neural signal lines are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and the multiple thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

7. The flexible neural electrode according to claim 1, wherein: The flexible substrate includes any one of polyimide, SU8, hydrogel, and polyparaxylene, or a combination thereof.

8. The flexible neural electrode according to claim 1, wherein: The thickness of the flexible neural electrode is 1 um to 100 um.

9. The flexible neural electrode according to claim 1, wherein: The control signal line and the neural signal line each include any one of gold, platinum, titanium or a combination thereof.

10. The flexible neural electrode according to claim 1, wherein: The thickness of the control signal line and the neural signal line are respectively 50nm to 2um.

11. The flexible neural electrode according to claim 1, wherein: The thin film transistor includes a single gate or a double gate.

12. The flexible neural electrode according to claim 1, wherein: A portion of the control signal line forms a gate of the thin film transistor.

13. The flexible neural electrode according to claim 1, wherein: A portion of the neural signal line forms a drain of the thin film transistor.

14. The flexible neural electrode according to claim 1, wherein: A part or all of the electrode sites forms the source of the thin film transistor.

15. The flexible neural electrode according to claim 1, further comprising: The electrode site modification layer located on the electrode site is used to reduce the interface impedance between the electrode site and the nerve.

16. The flexible neural electrode according to claim 15, wherein: The electrode site modification layer includes any one of platinum, titanium nitride, iridium oxide, poly (3,4-ethylenedioxythiophene) or a combination thereof. 17 . The flexible neural electrode according to claim 1 , comprising a welding layer for connecting an end of the control signal line away from the thin film transistor and an end of the neural signal line away from the thin film transistor to an external circuit, respectively.

18. The flexible neural electrode according to claim 1, wherein: The active layer of the thin film transistor includes an indium gallium zinc oxide thin film.

19. A method for preparing a flexible neural electrode, comprising: providing a flexible substrate; forming a thin film transistor on the flexible substrate; forming a control signal line, wherein the control signal line is connected to the gate of the thin film transistor; forming an electrode site, wherein the electrode site is connected to a source electrode of the thin film transistor; A neural signal line is formed, wherein the neural signal line is connected to the drain of the thin film transistor.

20. The method according to claim 19, comprising: forming a flexible substrate layer to provide the flexible substrate; forming a first wiring layer on the flexible substrate layer, wherein the first wiring layer includes the control signal line; forming an insulating layer on the first wiring layer; forming the thin film transistor on the insulating layer, wherein the control signal line is connected to the gate of the thin film transistor; forming a second wiring layer on the thin film transistor, wherein the second wiring layer includes the neural signal line, and the neural signal line is connected to the drain electrode of the thin film transistor; An electrode site layer is formed on the thin film transistor, wherein the electrode site layer includes the electrode site, and the electrode site is connected to the source of the thin film transistor.

21. The method according to claim 20, wherein: The thin film transistor is a first thin film transistor, and the method includes: One or more second thin film transistors are formed on the insulating layer, and gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the control signal line.

22. The method according to claim 20, wherein: The thin film transistor is a first thin film transistor, and the method includes: One or more third thin film transistors are formed on the insulating layer, and the drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the neural signal line.

23. The method according to claim 20, wherein: The thin film transistor is a first thin film transistor, the control signal line is a first control signal line, the neural signal line is a first neural signal line, and the method includes: forming a first wiring layer on the flexible substrate layer, wherein the first wiring layer includes a plurality of control signal lines, and the plurality of control signal lines includes the first control signal line; forming a plurality of thin film transistors on the insulating layer, wherein the plurality of thin film transistors include the first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors; forming a second wiring layer on the plurality of thin film transistors, the second wiring layer including a plurality of neural signal lines, the plurality of neural signal lines including the first neural signal line, The gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the first control signal line, and the drains of the one or more second thin film transistors and each of the first thin film transistors are respectively connected to a corresponding one of the plurality of neural signal lines. The drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the first neural signal line, and the gate of each thin film transistor in the one or more third thin film transistors and the first thin film transistor is respectively connected to a corresponding one of the multiple control signal lines.

24. The method according to claim 23, wherein: The multiple control signal lines in the first wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, the multiple neural signal lines in the second wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and the multiple thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

25. The method according to claim 20, wherein: The electrode site forms a source of the thin film transistor.

26. The method according to claim 20, comprising forming an encapsulation layer to encapsulate the flexible neural electrode, and comprising at least one of the following: Etching the encapsulation layer to expose the electrode site and forming an electrode site modification layer on the electrode site to reduce the interface impedance between the electrode site and the nerve; Etching the packaging layer to expose the end of the neural signal line away from the thin film transistor and forming a first welding layer on the exposed end of the neural signal line for connecting to an external circuit; The encapsulation layer and the insulating layer are etched to expose the end of the control signal line away from the thin film transistor and a second welding layer is formed on the exposed end of the control signal line for connection to an external circuit.

27. The method of claim 19, comprising: forming a flexible substrate layer to provide the flexible substrate; forming a first wiring layer on the flexible substrate layer, wherein the first wiring layer includes the neural signal line; forming the thin film transistor on the first wiring layer, wherein the neural signal line is connected to the drain of the thin film transistor; forming an insulating layer on the thin film transistor; forming a second wiring layer on the insulating layer, wherein the second wiring layer includes the control signal line, and the control signal line is connected to the gate of the thin film transistor; An electrode site layer is formed on the thin film transistor, wherein the electrode site layer includes the electrode site, and the electrode site is connected to the source of the thin film transistor.

28. The method according to claim 27, wherein: The thin film transistor is a first thin film transistor, and the method includes: One or more second thin film transistors are formed on the first wiring layer, and gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the control signal line.

29. The method according to claim 27, wherein: The thin film transistor is a first thin film transistor, and the method includes: One or more third thin film transistors are formed on the first wiring layer, and the drains of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the neural signal line.

30. The method of claim 27, wherein: The thin film transistor is a first thin film transistor, the control signal line is a first control signal line, the neural signal line is a first neural signal line, and the method includes: forming a first wiring layer on the flexible substrate layer, wherein the first wiring layer includes a plurality of neural signal lines, and the plurality of neural signal lines includes the first neural signal line; forming a plurality of thin film transistors on the first wiring layer, the plurality of thin film transistors including the first thin film transistor, one or more second thin film transistors, and one or more third thin film transistors; forming a second wiring layer on the insulating layer, wherein the second wiring layer includes a plurality of control signal lines, and the plurality of control signal lines includes the first control signal line, The gates of the one or more second thin film transistors and the gate of the first thin film transistor are commonly connected to the first control signal line, and the drains of the one or more second thin film transistors and each of the first thin film transistors are respectively connected to a corresponding one of the plurality of neural signal lines. The drain of the one or more third thin film transistors and the drain of the first thin film transistor are commonly connected to the first neural signal line, and the gate of each thin film transistor in the one or more third thin film transistors and the first thin film transistor is respectively connected to a corresponding one of the multiple control signal lines.

31. The method according to claim 30, wherein: The multiple neural signal lines in the first wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, the multiple control signal lines in the second wiring layer are spaced apart from each other and extend together along the longitudinal direction of the flexible neural electrode, and the multiple thin film transistors are linearly arranged along the longitudinal direction of the flexible neural electrode.

32. The method of claim 27, wherein: The electrode site forms a source of the thin film transistor.

33. The method of claim 27, comprising forming an encapsulation layer to encapsulate the flexible neural electrode, and comprising at least one of: Etching the encapsulation layer to expose the electrode site and forming an electrode site modification layer on the electrode site to reduce the interface impedance between the electrode site and the nerve; Etching the encapsulation layer to expose the end of the control signal line away from the thin film transistor and forming a first welding layer on the exposed end of the control signal line for connecting to an external circuit; The encapsulation layer and the insulating layer are etched to expose an end of the neural signal line away from the thin film transistor and a second welding layer is formed on the exposed end of the neural signal line for connection to an external circuit.

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