Device for measuring power current delivered by power FET

Abstract

The disclosure relates to an apparatus for measuring a power current delivered by a power FET. The present disclosure relates to an apparatus for measuring a power current supplied by a main power FET. The apparatus comprises: a current measurement power FET, the current measurement power FET being coupled with the main power FET; and a first FET and a second FET, gates of the first and second FETs being coupled to each other, the first FET being coupled to the current measuring FET, where a source / drain terminal of the second FET is coupled to a source / drain terminal of the first FET, and where a source / drain terminal of the second FET is coupled to a source / drain terminal of the first FET. Or the source / drain terminal of the second FET is coupled with the source / drain terminal of the main power FET or to a voltage source or a load external to the device, and the source / drain terminals of the first and second FETs are coupled to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French Application No. 23 / 06826, filed on June 28, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description generally relates to apparatus for measuring power current supplied by a power FET. Background Art

[0004] Measuring the current supplied by a power FET driving an electrical load may be performed, in particular, to efficiently drive the load, diagnose problems with the load, or protect the load and the circuit to which it belongs.

[0005] In order to measure the current supplied by a power FET driving an electrical load, another power FET dedicated to this measurement can be used, which is coupled in a branch of the circuit in parallel with the circuit including the main power FET.

[0006] In order to ensure that the current supplied by the measuring FET is very low compared to the current supplied by the main power FET, the measuring FET is designed to occupy a semiconductor surface area that is much smaller than the semiconductor surface area occupied by the main power FET. In particular, the value of the ratio between the semiconductor surface area of ​​the main power FET and the semiconductor surface area of ​​the measuring FET can be selected according to the function to be realized by the power circuit in which the main power transistor is located and the expected value of the power current.

[0007] The characteristics of the measurement FET, in particular the form factor, can be optimized in each region of the measurement FET to avoid problems encountered with power transistors that are too small, in particular problems caused by edge effects and form factor variations at the edges and corner cells of the transistor (differences in dynamic behavior from the expected dynamic behavior, changes in transistor response with operating temperature). Summary of the invention

[0008] It would be advantageous to provide a means for measuring the power current supplied by a main power FET without the disadvantages of existing solutions.

[0009] Particular embodiments address at least some of these issues and provide an apparatus for measuring a power current intended to be supplied by a main power FET, the apparatus comprising at least: a current measuring power FET comprising a first source or drain terminal configured to be coupled to a first source or drain terminal of the main power FET; a first FET and a second FET, the gates of the first FET and the second FET being electrically coupled to each other, the first source or drain terminal of the first FET being coupled to the second source or drain terminal of the current measuring power FET, wherein the first source or drain terminal of the second FET is coupled to the first source or drain terminal of the first FET, or wherein the first source or drain terminal of the second FET is configured to be coupled to the second source or drain terminal of the main power FET or to a voltage source or load external to the apparatus, and the second source or drain terminals of the first FET and the second FET are electrically coupled to each other.

[0010] According to a specific embodiment, the semiconductor surface of the current measuring power FET and the channel widths of the first FET and the second FET are such that the value of the ratio between the charging current intended to be supplied at the second source or drain terminal of the main power FET and the output current intended to be supplied at the second source or drain terminal of the first FET is different from the value of the ratio between the semiconductor surface of the main power FET and the semiconductor surface of the current measuring power FET.

[0011] According to a specific embodiment, the current measuring power FET is of VDMOSFET type, and the first FET and the second FET are of MOSFET type.

[0012] According to a specific embodiment, the first FET and the second FET have different channel widths.

[0013] According to a specific embodiment, the device also includes a comparator having a first input terminal configured to be coupled to the second source or drain terminal of the main power FET, a second input terminal coupled to the second source or drain terminal of the current measurement power FET, and an output terminal coupled to the gates of the first FET and the second FET.

[0014] According to a specific embodiment, the device also includes at least one third FET, the gate of which is coupled to the gates of the first FET and the second FET, and the first source or drain terminal of the third FET is coupled to the first source or drain terminal of the first FET or to the second source or drain terminal of the main power FET.

[0015] According to a specific embodiment, the device also includes: a fourth FET, a first source or drain terminal of the fourth FET is coupled to the second source or drain terminal of the current measurement power FET, and the second source or drain terminal of the fourth FET is coupled to the first source or drain terminal of the first FET; a comparator, the comparator having a first input terminal coupled to the second source or drain terminal of the current measurement power FET, a second input terminal configured to be coupled to the second source or drain terminal of the main power FET, and an output terminal coupled to the gate of the fourth FET.

[0016] According to a specific embodiment, the first FET and the second FET are mounted as a current mirror.

[0017] According to a specific embodiment, the first FET and the second FET are of P-type. The gates of the first FET and the second FET are coupled to the second source or drain terminal of the first FET, and the first source or drain terminal of the second FET is coupled to the first source or drain terminal of the first FET.

[0018] According to a specific embodiment, the first FET and the second FET are N-type; the gates of the first FET and the second FET are coupled to the first source or drain terminal of the first FET; and the second source or drain terminals of the first FET and the second FET are electrically coupled to each other.

[0019] A specific embodiment provides a power control circuit for controlling an electrical load, the power control circuit comprising at least: a main power FET, the main power FET comprising a first source or drain terminal configured to be coupled to an electrical power source and a second source or drain terminal configured to be coupled to a terminal of the electrical load; and a device as described above, the device being used to measure the power current supplied by the main power FET.

[0020] According to a specific embodiment, the main power FET and the current measurement power FET have the same conductivity type.

[0021] A specific embodiment provides a method for making a power control circuit for controlling an electrical load, the method comprising at least: making a main power FET, the main power FET comprising a first source or drain terminal configured to be coupled to an electrical power source and a second source or drain terminal configured to be coupled to a terminal of the electrical load; and making a device as described above, the device being used to measure the power current supplied by the main power FET.

[0022] According to a specific embodiment, the method further comprises the following steps: before manufacturing the main power FET and the device for measuring the power current supplied by the main power FET, determining the semiconductor surface of the current measuring power FET of the device for measuring the power current supplied by the main power FET and the channel widths of the first FET and the second FET, so that the value of the ratio between the charging current intended to be supplied at the second source or drain terminal of the main power FET and the output current intended to be supplied at the second source or drain terminal of the first FET is different from the value of the ratio between the semiconductor surface of the main power FET and the semiconductor surface of the current measuring power FET; and wherein, then, based on the previously determined semiconductor surface of the current measuring power FET and the channel widths of the first FET and the second FET, at least the current measuring power FET and the first FET and the second FET of the device are manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above features and advantages and others will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1 schematically illustrates an example arrangement for measuring a power current supplied by a main power FET according to a first embodiment;

[0025] Figure 2 schematically illustrates an alternative implementation of the apparatus for measuring the power current supplied by the main power FET according to the first embodiment;

[0026] Figure 3 schematically illustrates an example arrangement for measuring a power current supplied by a main power FET according to a second embodiment;

[0027] Figure 4 schematically illustrates an example arrangement for measuring a power current supplied by a main power FET according to a third embodiment;

[0028] Figure 5 schematically illustrates an example arrangement for measuring a power current supplied by a main power FET according to a fourth embodiment;

[0029] Figure 6 schematically illustrates a variation of the apparatus for measuring the power current supplied by the main power FET according to the fourth embodiment; and

[0030] Figure 7 The schematic illustrates the steps in making a device for measuring the power current supplied by the main power FET. DETAILED DESCRIPTION

[0031] In the various drawings, similar features have been designated by similar reference symbols. In particular, common structural and / or functional features between various embodiments may have the same reference symbols and may be arranged in the same structure, size and material properties.

[0032] For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein have been illustrated and described in detail. Specifically, various transistors and comparators for measuring power current are not described in detail. Those skilled in the art will be able to implement these elements in detail from the functional description given here.

[0033] Unless otherwise indicated, when two elements are connected, this means they are directly connected without intermediate elements other than conductors. When two elements are coupled together, this means the two elements may be connected or coupled via one or more other elements.

[0034] Unless otherwise specified, the terms "about," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0035] In all the described embodiments, for each transistor, the first source or drain terminal and the second source or drain terminal correspond to two mutually different terminals of the same transistor, one corresponding to the source terminal and the other corresponding to the drain terminal.

[0036] against Figure 1 , described below is a first example of an apparatus 100 for measuring a power current supplied by a main power FET 102 according to a first embodiment.

[0037] In this first example, the transistor 102 supplies an electrical load 104, thereby supplying a load current called “I_load”. For example, the electrical load 104 corresponds to a motor, a lamp or any other electrical component designed to be supplied by an electrical power current. The term “electrical power current” applied to the load current supplied by the transistor 102 specifies, for example, a current whose intensity is between a few milliamperes and tens of amperes, which value varies with the size of the transistor 102.

[0038] For example, transistor 102 and device 100 form part of a power control circuit 1000 and are Figure 1 Other components (converters, regulators, etc.) are not shown. Figure 1In the example shown in , the power control circuit 1000 is of the "high side" type, i.e. corresponds to a power control circuit inserted between an electrical load 104 and a positive supply potential of this electrical load 104. Thus, the transistor 102 comprises a first source or drain terminal 106 coupled to the supply potential "+V" and a second source or drain terminal 108 coupled to a terminal of the electrical load 104 supplied with the current I_load. The transistor 102 is designed to receive on its gate a signal controlling the supply of power to the load 104.

[0039] exist Figure 1 In the first example embodiment shown in , the transistor 102 is of N-type. Therefore, the first terminal 106 corresponds to the drain of the transistor 102 and the second terminal 108 corresponds to the source of the transistor 102.

[0040] The device 100 comprises a current measuring power FET 110 comprising a first source or drain terminal 112 coupled to the first terminal 106 of the transistor 102 and thus to the power supply potential +V. The transistor 110 is designed to receive at its gate the same signal as that applied to the gate of the transistor 102. Thus, the transistors 102 and 110 are switched on or off at the same time.

[0041] exist Figure 1 In the example embodiment shown in , transistor 110 is of N-type and thus of the same type as transistor 102. Thus, first terminal 112 corresponds to the drain of transistor 110.

[0042] The device 100 also includes first and second FETs, respectively designated 114 and 116, which are not power transistors, unlike the transistors 102 and 110. A first source or drain terminal 118 of the transistor 114 is coupled to a second source or drain terminal 120 of the transistor 110, i.e., in the embodiment described herein, to the source of the transistor 110.

[0043] exist Figure 1 In the example embodiment shown in , a first source or drain terminal 122 of transistor 116 is coupled to a first terminal 118 of transistor 114. Transistor 114 also has a second source or drain terminal 124 intended to be supplied with a measurement current referred to as "Isense". Transistor 116 also includes a second source or drain terminal 126 intended to supply a current whose characteristics will be described in more detail below.

[0044] exist Figure 1In the example embodiment shown in , the transistors 114 , 116 are of P-type, so the first terminals 118 , 122 correspond to sources of these transistors 114 , 116 , and the second terminals 124 , 126 correspond to drains of these transistors 114 , 116 .

[0045] In this first example embodiment, the apparatus 100 further comprises a comparator 128 having a first input 130 coupled to the second terminal 108 of the transistor 102, a second input 132 coupled to the second terminal 120 of the transistor 110, and an output 134 coupled to the gates of the transistors 114 and 116, the gates of the transistors 114, 116 being thus electrically coupled to each other. In this configuration, the voltage V GS are the same.

[0046] Transistors 110 , 114 , 116 of device 100 are designed such that the semiconductor surface of transistor 110 and the channel widths of transistors 114 , 116 are such that the ratio K_target=I_load / Isense has a value different from the ratio Kref between the semiconductor surface of transistor 102 and the semiconductor surface of transistor 110 .

[0047] exist Figure 1 In the example embodiment shown in FIG. 1 , transistors 110, 114 and 116 are dimensioned such that the value of ratio K_target is greater than the value of ratio Kref between semiconductor surfaces of transistors 102 and 110. Therefore, transistor 110 outputs a current Isense_ref=I_load / Kref at its second terminal 120 having a value greater than the value of current Isense.

[0048] The current Isense can be obtained from the current Isense_ref by the fact that both transistors 114, 116 receive the current Isense_ref as input at their first terminals 118, 122 and output a portion of the current Isense_ref at their second terminals 124, 126. The transistor 114 has a channel width called "W1" and the transistor 116 has a channel width called "W2", such that W2 = K*W1, where K is a real number greater than 0. Figure 1 In the example embodiment shown in , K corresponds to an integer greater than or equal to 1. According to a specific example embodiment, the transistors 114 , 116 may have channel widths different from each other, which means that the value of K is different from 1, and is, for example, greater than 1.

[0049] Therefore, the current Isense supplied to the second terminal 124 of the transistor 114 is such that Isense=I_load / K_target, where K_target=Kref*(1+K), and the current supplied to the second terminal 126 of the transistor 116 is therefore equal to K*Isense. These currents satisfy the relationship Isense_ref=(1+K)*Isense.

[0050] Based on the measured current Isense obtained and knowing the value of the ratio Kref and K, the value of the current I_load can be determined. The measured current Isense and the calculated current I_load can be obtained by Figure 1 The process is performed by elements of the device 100 which are not shown.

[0051] In this manner, transistor 110 is fabricated to have a larger semiconductor surface area than would enable transistor 110 alone to supply current Isense if transistors 114 , 116 were not present.

[0052] In a specific example embodiment, the current K*Isense supplied to the second terminal 126 of the transistor 116 may be reused for applications other than measuring the current I_load.

[0053] The following is for Figure 2 A modification of the device 100 according to the first embodiment is described.

[0054] The device 100 according to this variant comprises the previously described Figure 1 All elements and components of the device 100 are described.

[0055] in addition, Figure 2 The device 100 shown in FIG. 1 comprises at least one third FET 136 having its gate coupled to the output 134 of the comparator 128 and thus also to the gates of the transistors 114, 116. A first source or drain terminal 138 of the transistor 136 is coupled to the first terminal 118 of the transistor 114 (which in turn is coupled to the first terminal 122 of the transistor 116 and the second terminal 120 of the transistor 110).

[0056] In the example described here, transistor 136 is of the same type as transistors 114 , 116 , ie, P-type. Thus, first terminal 138 corresponds to the source of transistor 136 , and second terminal 140 corresponds to the drain of transistor 136 .

[0057] exist Figure 2In the variation shown in , transistors 114 , 116 , 136 are such that transistor 114 has a channel width W1 and outputs a current Isense1 at its second terminal 124 ; transistor 116 has a channel width W2 and outputs a current Isense2 at its second terminal 126 ; and transistor 136 has a channel width W3 and outputs a current Isense3 at its second source or drain terminal 140 .

[0058] exist Figure 2 In the example shown in , the transistors 114, 116, 136 receive the current Isense_ref at their first terminals 118, 122, 138 and output a portion of the current Isense_ref at their second terminals 124, 126, 140. Therefore, the currents Isense1, Isense2 and Isense3 supplied to the second terminals 124, 126, 140 of these transistors 114, 116, 136 satisfy the following relationship:

[0059] Isense_ref=Isense1+Isense2+Isense3;

[0060] Isense1=(W1 / (W1+W2+W3))*Isense_ref;

[0061] Isense2=(W2 / (W1+W2+W3))*Isense_ref; and

[0062] Isense3=(W3 / (W1+W2+W3))*Isense_ref.

[0063] The different currents Isense1 , Isense2 and Isense3 may be used, for example, for different functions: load 104 diagnostics, protection of an electrical harness coupled to transistor 102 , protection against current peaks, etc.

[0064] According to another variant, the device 100 may comprise a plurality of FETs comprising a first source or drain terminal thereof coupled to the second terminal 120 of the transistor 110 and a second source or drain terminal thereof at which the measurement current is obtained.

[0065] The following is for Figure 3 An example apparatus 100 for measuring the power current output by a main power FET 102 according to a second embodiment is described.

[0066] The device 100 according to the second embodiment comprises the previously described Figure 1 All elements and components of the device 100 are described.

[0067] Compared to the device 100 according to the first embodiment, the first terminal 122 of the transistor 116 is not coupled to the first terminal 118 of the transistor 114 but to the second terminal 108 of the transistor 102. Furthermore, the second terminals 124, 126 of the transistors 114, 116 are electrically coupled to each other.

[0068] Therefore, unlike the first embodiment in which the current Isense supplied by the second transistor 114 is lower than the current Isense_ref supplied by the transistor 110, the current supplied by the second transistor 114 is equal to Isense_ref, which is added to the current supplied at the second terminal 126 of the transistor 116 at the junction of the second terminals 124, 126. Therefore, the device 100 according to the second embodiment makes it possible to obtain a current Isense_target greater than the current Isense_ref output by the transistor 110 at the junction of the second terminals 124, 126 of the transistors 114, 116.

[0069] In this second embodiment, comparator 128 adjusts the current flowing through transistor 110 so that the potential at the second terminal 120 of transistor 110 is similar to or substantially equal to the potential at the second terminal 108 of transistor 102. Therefore, the potential at the first terminal 118 of transistor 114 (which is equal to the potential at the second terminal 120 of transistor 110) is similar to or substantially equal to the potential at the first terminal 122 of transistor 116 (which is equal to the potential at the second terminal 108 of transistor 102). Because of the presence of comparator 128, the voltage V of transistors 114, 116 GS Similar or substantially equal, so the values ​​of the currents supplied by transistors 114, 116 are proportional to their respective sizes.

[0070] Therefore, considering the channel width W1 of transistor 114 and the channel width W2 of transistor 116 such that W2=K*W1, since the current supplied to the second terminal 124 of transistor 114 is equal to Isense_ref and the current supplied to the second terminal 126 of transistor 116 is equal to K*Isense_ref, the current Isense_target supplied to the junction of the second terminals 124, 126 of transistors 114, 116 makes Isense_target=I_sense_ref*(1+K).

[0071] In this second embodiment, because the second terminals 118, 122 of the transistors 114, 116 are not electrically coupled to each other, the potentials applied to the second terminals 118, 122 may not be completely equal. Therefore, a potential difference, for example equal to several mV, may appear at the inputs 130, 132 of the comparator 128, resulting in a variation in the current output by the transistor 116 relative to the current output by the transistor 114. However, the various components of the device 100 are dimensioned and optimized (in particular, the offset of the comparator 128 and the ratio of the sizes of the transistors 114 and 116) to minimize this possible potential difference as much as possible.

[0072] The following is for Figure 4 An example of the apparatus 100 for measuring the power current supplied by the main power FET 102 according to the third embodiment is described.

[0073] The device 100 according to the third embodiment includes the Figure 1 All elements and components of the device 100 are described.

[0074] in addition, Figure 4 The device 100 shown in FIG. 1 comprises a third FET 136 having its gate coupled to the output 134 of the comparator 128 and thus also to the gates of the transistors 114, 116. A first source or drain terminal 138 of the transistor 136 is coupled to the second terminal 108 of the transistor 102.

[0075] As in the first embodiment, both transistors 114, 116 receive the current Isense_ref at their first terminals 118, 122 and output a portion of the current Isense_ref at their second terminals 124, 126. Therefore, the currents Isense1 and Isense2 supplied to the second terminals 124, 126 of these transistors 114, 116 satisfy the following relationship:

[0076] Isense_ref=Isense1+Isense2;

[0077] Isense1=(W1 / (W1+W2))*Isense_ref;

[0078] Isense2 = (W2 / (W1+W2))*Isense_ref; and

[0079] Where W1 corresponds to the channel width of transistor 114 , and W2 corresponds to the channel width of transistor 116 .

[0080] Transistor 136 also outputs a current Isense3 at its second terminal 140 that is proportional to current I_load.

[0081] Alternatively, the second terminal 140 of the transistor 136 may be coupled to the second terminal 124 , 126 of one of the transistors 114 , 116 so as to obtain a current corresponding to the sum of the current Isense3 and one of the currents Isense1 or Isense2 at the junction of the two second terminals coupled to each other.

[0082] Alternatively, the apparatus 100 may include one or more further FETs whose first source or drain terminals are coupled to the first terminal 118 of the first transistor 114 .

[0083] The following is for Figure 5 An example of the apparatus 100 for measuring the power current output by the main power FET 102 according to the fourth embodiment is described.

[0084] The device 100 according to the fourth embodiment includes the previously described Figure 1 All elements and components of the device 100 are described.

[0085] The device 100 according to this fourth embodiment further comprises a further FET 142, a first source or drain terminal 144 of which is coupled to the second terminal of the transistor 110, and a second source or drain terminal 146 of which is coupled to the first terminals 118, 122 of the transistors 114, 116 which are electrically coupled to each other. Figure 5 In the example embodiment shown in , the transistor 142 is of P-type, wherein the first terminal 144 corresponds to the source of the transistor 142 and the second terminal 146 corresponds to the drain of the transistor 142 .

[0086] Unlike the previously described example embodiments, the output 134 of the comparator 128 is not electrically coupled to the gates of the transistors 114 , 116 , but is instead electrically coupled to the gate of the transistor 142 .

[0087] The transistors 114, 116 are current mirrored. Therefore, the gates of the transistors 114, 116 are electrically coupled to each other and to the second terminal 124 of the transistor 114. The current Isense1 is supplied to the second terminal 124 of the transistor 114, and the current Isense2 is supplied to the second terminal 126 of the transistor 116.

[0088] As in the first embodiment, transistor 114 has a channel width W1, and transistor 116 has a channel width W2, such that W2=K*W1, where K is a real number greater than 0. Figure 1 In the example embodiment shown in , K corresponds to an integer greater than or equal to 1. According to a specific example embodiment, the transistors 114 , 116 may have channel widths different from each other, which means that the value of K is different from 1, and is, for example, greater than 1.

[0089] As in the first embodiment, both transistors 114, 116 receive the current Isense_ref at their first terminals 118, 122 and output a portion of the current Isense_ref at their second terminals 124, 126. Therefore, the currents Isense1 and Isense2 supplied to the second terminals 124, 126 of these current mirror transistors 114, 116 satisfy the following relationship:

[0090] Isense_ref=Isense1+Isense2;

[0091] Isense1=(W1 / (W1+W2))*Isense_ref; and

[0092] Isense2=(W2 / (W1+W2))*Isense_ref.

[0093] The following is for Figure 6 A variation of the device 100 according to the fourth embodiment is described. The device 100 according to this variation includes the device 100 previously described for Figure 5 All elements and components of the device 100 described herein. Figure 6 In the device 100 shown in FIG. 1 , the transistors 114, 116 (in the form of current mirrors) are of N-type, their first terminals 118, 122 correspond to the drains of these transistors 114, 116, and their second terminals 124, 126 correspond to the sources of these transistors 114, 116. The gates of the transistors 114, 116 are electrically coupled to each other and to the first terminal 118 of the transistor 114. The first terminal 122 of the transistor 116 is electrically coupled to a voltage source or load (at Figure 6 The second terminals 124, 126 of the transistors 114, 116 are electrically coupled to each other.

[0094] In this variation, current Isense_target is equal to current K*Isense_ref flowing in first terminal 122 of transistor 116, and current Isense1 is equal to current Isense_ref flowing in first terminal 118 of transistor 114. As in the previous example, transistor 114 has a channel width W1, and transistor 116 has a channel width W2, such that W2=K*W1.

[0095] In all of the above-described embodiments, examples and variations, the current measurement accuracy achieved by the device 100 is, for example, less than or equal to 5% of the nominal value of the current I_load over the entire operating temperature range of the device 100 .

[0096] The proposed circuit makes it possible to use current measuring power FETs of larger dimensions than existing solutions, thus avoiding problems encountered with transistors of too small dimensions such as differences in the dynamic behavior compared to the expected dynamic behavior or variations in the response of the measuring transistor with the operating temperature (the effects of which will be similar to the variations in the value of the ratio K_target with the operating temperature). The behavior of the current measuring power FETs is also closer to that of the main power FETs, regardless of factors such as temperature or the voltage V applied to these transistors. GS What are the values ​​of external parameters such as .

[0097] In all embodiments, examples and variations, the size of the transistor is determined according to the desired values ​​of the various ratios K_target, Kref and K, which themselves are functions of the characteristics and functionality of the electrical environment in which the device 100 and circuit 1000 are used. For example, the value of the ratio K_target (which can be set according to the application of the device 100) can be greater than or equal to 1000, or, for example, equal to one of the following values: 1,000, 2,000, 10,000, 40,000. For example, the value of the ratio K_target can be 4 to 10 times the value of the ratio Kref.

[0098] In all embodiments, examples and variations, the main power FET 102 and the current measuring power FET may be, for example, VDMOSFETs (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistors).

[0099] In all embodiments, examples and variations, the FETs 114, 116, 136, 142 may be, for example, MOSFET type transistors. In addition, these FETs 114, 116, 136, 142 may be N-type or P-type transistors.

[0100] In all embodiments, examples and variations, the FETs 114 , 116 , 136 , 142 form an output stage, enabling a desired ratio of measurement current to load current to be obtained at the output.

[0101] In all embodiments and variations, the main power FET 102 and / or the current measurement power FET 110 are the same N-type or P-type.

[0102] As an alternative to the above-described example embodiments, the transistor 102 and the device 100 may form part of a “low-side” power control circuit 1000, i.e. a control circuit interposed between the electrical load 104 and an electrical reference potential of the electrical load 104. In this case, the first terminals of the power transistors 102, 110 are not coupled to a power supply terminal potential but to one of the terminals of the electrical load 104, and the second terminal 108 of the transistor 102 is coupled to the reference potential.

[0103] The measuring device 100 and the control circuit 1000 can be designed as independent modules, or can be integrated into a chip or integrated circuit with other functions, for example using the technology of integrating power components and CMOS components and / or bipolar (analog), CMOS (digital) and DMOS (double diffused MOS, which is a power component) components.

[0104] Figure 7 Steps in an example method for manufacturing a power control circuit 1000 for controlling an electrical load 104 are schematically illustrated.

[0105] In a first step 200, the semiconductor area of ​​transistor 110 and the channel widths of transistors 114, 116 are determined so that the value of the ratio K_target between the load current I_load and the output current Isense is different from the value of the ratio Kref between the semiconductor area of ​​transistor 102 and the semiconductor area of ​​transistor 110. In this step, any other elements or components of device 100 are also sized according to the desired characteristics of device 100.

[0106] In step 300, main power FET 102 and various components of device 100 are then formed. In particular, transistors 110, 114, and 116 are formed according to the surface areas and channel widths previously determined.

[0107] The measuring device 100 and the control circuit 1000 can be advantageously used in the automotive field, for example, in a power distribution and management circuit of a vehicle. The measuring device 100 and the control circuit 1000 can also be used in other fields, for example, in the industrial field.

[0108] In an embodiment, the current path terminal refers to the source terminal, the drain terminal, or both of the FET.

[0109] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0110] Finally, based on the functional description provided above, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

Claims

1. A device for measuring a power current to be supplied by a main power field effect transistor FET, the device comprising: a current measuring power FET comprising a first current path terminal coupleable to a first current path terminal of the main power FET; and a first FET and a second FET, wherein a gate terminal of the first FET is electrically coupled to a gate terminal of the second FET, wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measuring power FET, or wherein the first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET, the second current path terminal of the main power FET, a voltage source, or a load external to the device, and the second current path terminal of the first FET is electrically coupled to the second current path terminal of the second FET.

2. The device according to claim 1, wherein: The semiconductor surface of the current measuring power FET and the channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET is different from a ratio between the semiconductor surface of the main power FET and the semiconductor surface of the current measuring power FET.

3. The device according to claim 1, wherein: The current measuring power FET is a vertical double diffused metal oxide semiconductor FET (VDMOSFET) type, and wherein the first FET and the second FET are MOSFET types.

4. The device according to claim 1, wherein: A channel width of the first FET is different from a channel width of the second FET.

5. The apparatus of claim 1 , further comprising a comparator having a first input capable of being coupled to a second current path terminal of the main power FET, a second input of the comparator capable of being coupled to a second current path terminal of the current measurement power FET, and an output of the comparator capable of being coupled to a gate terminal of the first FET and a gate terminal of the second FET.

6. The apparatus of claim 1, further comprising a third FET, wherein: The gate terminal of the third FET is coupled to the gate terminal of the first FET and the gate terminal of the second FET, and wherein the first current path terminal of the third FET is coupled to the first current path terminal of the first FET or the second current path terminal of the main power FET.

7. The apparatus according to claim 1, further comprising: a fourth FET, wherein a first current path terminal of the fourth FET is coupled to a second current path terminal of the current measuring power FET and a second current path terminal of the fourth FET is coupled to a first current path terminal of the first FET; and a comparator having a first input coupled to the second current path terminal of the current measuring power FET, a second input of the comparator coupleable to the second current path terminal of the main power FET, and an output of the comparator coupled to the gate terminal of the fourth FET.

8. The device according to claim 7, wherein: The first FET and the second FET are arranged as a current mirror.

9. The device according to claim 8, wherein: The first FET and the second FET are P-type, wherein a gate terminal of the first FET and a gate terminal of the second FET are coupled to a second current path terminal of the first FET, and wherein a first current path terminal of the second FET is coupled to a first current path terminal of the first FET.

10. The device according to claim 8, wherein: The first FET and the second FET are N-type, wherein a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first current path terminal of the first FET, and wherein a second current path terminal of the first FET and a second current path terminal of the second FET are electrically coupled.

11. A power control circuit for controlling an electrical load, the power control circuit comprising: a main power field effect transistor FET comprising a first current path terminal coupleable to a source of electrical power, a second current path terminal of said main power FET coupleable to a terminal of an electrical load; and a measurement circuit configured to measure a power current to be supplied by the main power FET, the measurement circuit comprising: a current measuring power FET comprising a first current path terminal coupleable to a first current path terminal of the main power FET; and a first FET and a second FET, wherein a gate terminal of the first FET is electrically coupled to a gate terminal of the second FET, wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measuring power FET, or wherein the first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET, the second current path terminal of the main power FET, a voltage source, or an electrical load, and the second current path terminal of the first FET is electrically coupled to the second current path terminal of the second FET.

12. The power control circuit according to claim 11, wherein: The main power FET and the current measuring power FET have the same conductivity type.

13. The power control circuit according to claim 11, wherein: The semiconductor surface of the current measuring power FET and the channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET is different from a ratio between the semiconductor surface of the main power FET and the semiconductor surface of the current measuring power FET.

14. The power control circuit according to claim 11, wherein: The measurement circuit also includes a comparator having a first input capable of being coupled to a second current path terminal of the main power FET, a second input of the comparator capable of being coupled to a second current path terminal of the current measurement power FET, and an output of the comparator capable of being coupled to a gate terminal of the first FET and a gate terminal of the second FET.

15. A method for measuring a power current to be supplied by a main power field effect transistor (FET) in a device, the method comprising: receiving a control signal at a gate terminal of a current measuring power FET, the gate terminal of the current measuring power FET being coupled to the gate terminal of the main power FET and the first current path terminal of the current measuring power FET being coupled to the first current path terminal of the main power FET; and adjusting a first potential at a second terminal of the current measuring power FET to be equal to a second potential at a second terminal of the main power FET by a comparator, wherein a gate terminal of the first FET is electrically coupled to a gate terminal of the second FET, wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measuring power FET, or wherein the first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET, the second current path terminal of the main power FET, a voltage source, or an external electrical load, and the second current path terminal of the first FET is electrically coupled to the second current path terminal of the second FET.

16. The method according to claim 15, wherein: The semiconductor surface of the current measuring power FET and the channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET is different from a ratio between the semiconductor surface of the main power FET and the semiconductor surface of the current measuring power FET.

17. The method according to claim 15, wherein: The comparator includes a first input coupled to a second current path terminal of the main power FET, a second input of the comparator coupled to a second current path terminal of the current measurement power FET, and an output of the comparator coupled to gate terminals of the first FET and the second FET.

18. The method according to claim 15, wherein: A gate terminal of a third FET is coupled to a gate terminal of the first FET and a gate terminal of the second FET, and wherein a first current path terminal of the third FET is coupled to a first current path terminal of the first FET or a second current path terminal of the main power FET.

19. The method according to claim 15, wherein: The current measuring power FET is a vertical double diffused metal oxide semiconductor FET (VDMOSFET) type, and wherein the first FET and the second FET are MOSFET types.

20. The method according to claim 15, in, The first FET and the second FET are of P-type, wherein a gate terminal of the first FET and a gate terminal of the second FET are coupled to a second current path terminal of the first FET, and wherein a first current path terminal of the second FET is coupled to a first current path terminal of the first FET, or wherein the first FET and the second FET are N-type, wherein the gate terminal of the first FET and the gate terminal of the second FET are coupled to a first current path terminal of the first FET, and wherein the second current path terminal of the first FET and the second current path terminal of the second FET are electrically coupled.

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