IGBT (Insulated Gate Bipolar Translator) defect detection method and device based on gate current signal in opening process

Abstract

The invention provides an IGBT defect detection method and device based on a gate current signal in a turn-on process, and the method comprises the steps: obtaining a target stage current waveform during the actual work of an IGBT based on the gate current signal in the turn-on process of the IGBT; according to the current waveform of the target stage when the IGBT actually works, calculating to obtain the charging charge quantity of the gate capacitor at the target stage when the IGBT actually works; and analyzing and judging whether the current IGBT has gate emitter loop defects or not according to the charging charge quantity of the gate capacitor at the target stage when the IGBT actually works. According to the invention, the change of the charging charge quantity of the grid electrode is analyzed through the grid electrode current waveform in the opening process of the IGBT so as to judge whether the IGBT has the grid emitter loop defect or not, and the detection efficiency is improved. When the IGBT has defects, the number of the packaging chips with the defects of the IGBT can be known by adopting the technical scheme of the invention, and quantitative detection can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to an IGBT defect detection method and device based on a gate current signal during a turn-on process. Background Art

[0002] Insulate-Gate Bipolar Transistor (IGBT) devices have the advantages of fast switching speed of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices and low conduction loss of bipolar devices. They are widely used in new energy converters, flexible DC transmission equipment, dynamic reactive power compensation equipment, etc. IGBT is a three-terminal device, including: gate, collector and emitter. However, in practical applications, it is difficult to detect the internal gate-emitter loop defect state of IGBT. Summary of the invention

[0003] The main purpose of the embodiments of the present invention is to provide an IGBT defect detection method and device based on the gate current signal of the turn-on process. The gate current waveform of the IGBT turn-on process is used to analyze the change in the gate charging charge to determine whether the IGBT has a gate-emitter loop defect. The present invention has certain guiding significance for IGBT status detection.

[0004] In order to achieve the above object, an embodiment of the present invention provides an IGBT defect state detection method, comprising: Based on the gate current signal of the IGBT turn-on process in the commutation circuit to be measured, the current waveform of the target stage when the IGBT is actually working is obtained; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode. The second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the gate of the IGBT is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor; According to the current waveform of the target stage when the IGBT is actually working, the charge amount of the gate capacitance in the target stage when the IGBT is actually working is calculated; According to the charge amount of the gate capacitor in the target stage when the IGBT is actually working, it is analyzed and determined whether there is a gate-emitter loop defect in the IGBT in the commutation circuit to be tested, and the gate-emitter loop defect includes a gate defect and an emitter defect.

[0005] In one embodiment, the calculating the charge amount of the gate capacitance in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working comprises: Obtaining the gate current at each moment of the target phase when the IGBT is actually working from the current waveform of the target phase when the IGBT is actually working; The gate capacitance charge during the target phase of the actual operation of the IGBT is calculated by using the gate current at each moment during the target phase of the actual operation of the IGBT.

[0006] In one embodiment, when the IGBT is actually working, the gate capacitance charging charge Q G Calculated by the following formula: ; Where n is the total number of IGBT packaged chips, i G is the gate current at each moment of the target phase when the IGBT is actually working, t 0 is the starting time of the target phase, t 1 The target phase ends.

[0007] In one embodiment, analyzing and determining whether the current IGBT has a defect according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working includes: When the amount of charge charged on the gate capacitance in the target phase during the actual operation of the IGBT is less than a threshold value, the current IGBT has a gate-emitter loop defect.

[0008] In one embodiment, the threshold value is the charge amount of the gate capacitance in the target phase when the current IGBT is working normally.

[0009] In one embodiment, the method further includes: if the current IGBT has a gate-emitter loop defect, the number of defective chips in the IGBT is calculated based on the charge amount of the gate capacitor in the target stage.

[0010] In one embodiment, the number m of defective chips in the IGBT is calculated by the following formula: ; Where n is the total number of IGBT package chips, Q G It is the charge amount of gate capacitance in the target phase when IGBT is actually working. It is the charge amount of the gate capacitance in the target stage when the IGBT is working normally.

[0011] The embodiment of the present invention further provides an IGBT defect detection device based on a gate current signal during a turn-on process, comprising: The acquisition module is used to acquire the current waveform of the target stage when the IGBT is actually working based on the gate current signal of the IGBT turn-on process in the commutation circuit to be measured; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode circuit one end, the second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the gate of the IGBT is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor; A calculation module, used for calculating the charge amount of the gate capacitance in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working; The judgment module is used to analyze and judge whether there is a gate-emitter loop defect of the IGBT in the commutation circuit to be tested according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working, and the gate-emitter loop defect includes a gate defect and an emitter defect.

[0012] An embodiment of the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements any of the above methods when executing the computer program.

[0013] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above methods when executed by a processor.

[0014] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0015] The embodiment of the present invention provides an IGBT defect detection method and device based on the gate current signal of the turn-on process. The present invention obtains the current waveform of the target stage when the IGBT is actually working based on the gate current signal of the IGBT turn-on process; calculates the gate capacitance charging charge of the target stage when the IGBT is actually working according to the current waveform of the target stage when the IGBT is actually working; and analyzes and determines whether the current IGBT has a gate-emitter loop defect according to the gate capacitance charging charge of the target stage when the IGBT is actually working. Compared with the prior art, the present invention analyzes the change of the gate charging charge through the gate current waveform of the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter loop defect, which can easily detect the defective state of the IGBT and improve the detection efficiency. When there is a defect in the IGBT, the technical solution of the present invention can also know the number of packaged chips with specific defects in the IGBT, and quantitative detection can be achieved, which has certain guiding significance for IGBT state detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a schematic diagram of a commutation circuit structure provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the internal structure of an IGBT provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of an IGBT turn-on transient process provided by an embodiment of the present invention; Figure 4 It is a flow chart of an IGBT defect detection method based on a gate current signal during a turn-on process provided by an embodiment of the present invention; Figure 5 It is a structural schematic diagram of an IGBT defect detection device based on a gate current signal during a turn-on process provided by an embodiment of the present invention; Figure 6 It is a structural block diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Those skilled in the art know that the embodiments of the present invention can be implemented as a system, device, apparatus, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0020] It is difficult to detect the internal defect state of IGBT in the prior art. In order to solve the problems in the prior art, the present invention analyzes the change of gate charge through the gate current waveform of the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter loop defect, which can easily detect the defect state of the IGBT and improve the detection efficiency. When there is a defect in the IGBT, the technical solution of the present invention can also be used to know the specific number of defective packaged chips in the IGBT, which has certain guiding significance for IGBT state detection.

[0021] In order to facilitate understanding of the technical solution provided by this application, the research background of the technical solution of this application is briefly described below.

[0022] Figure 1 It is a schematic diagram of a commutation circuit structure provided by an embodiment of the present invention. Figure 1 It is the circuit structure model of power electronic commutation device. Most commutation devices (such as dynamic reactive power compensation equipment, flexible DC equipment, wind power converter, traction converter, etc.) can be used. Figure 1 The topology shown is analyzed. Figure 1 The commutation circuit shown mainly includes the DC bus capacitor C 0 、Insulated Gate Bipolar Transistor IGBT (gate-emitter capacitance C GE 、Miller capacitance C GC , Collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter), freewheeling diode FWD and other structures, the reference direction of voltage and current is already in Figure 1 Winning bid. Figure 1 middle L load is the load inductance, L s,1 is the parasitic inductance of the IGBT circuit, L s,2 is the parasitic inductance of the FWD loop; u chip,F is the voltage of the chip inside the freewheeling diode, us,F is the parasitic inductance voltage inside the freewheeling diode package, u F is the voltage across the freewheeling diode, u s,2 is the parasitic inductance of the FWD loop L s,2 Voltage; u GE is the gate voltage of IGBT, u CE is the collector-emitter voltage of the IGBT, u chip,CE is the collector-emitter voltage of the IGBT internal chip, and the collector-emitter voltage u CE =u chip,CE ,u CG is the collector-gate voltage of the IGBT; i C is the collector current, i G is the gate current, i GE For flow through C GE The current, i GC For flow through C GC The current, I L is the current flowing through the load inductor L load The current. L s,F and L s,CE They represent the parasitic parameters of the FWD and IGBT internal packaging main circuits, respectively. s,F Including the parasitic inductance of the FWD anode and cathode sides, L s,CE Including L s,C , L s,E Two parts, L s,C is the parasitic inductance on the collector side of the IGBT, L s,E is the parasitic inductance on the emitter side of the IGBT; in addition, R G,on is the gate turn-on resistance, R G,off is the gate turn-off resistance, U G,on Turn on the control voltage for the drive power supply, U G,off The present invention is mainly used to detect Figure 1 Is there a defect in the gate emitter loop (GE)?

[0023] Figure 2 Schematic diagram of the internal structure of an IGBT provided by an embodiment of the present invention. The insulated gate bipolar transistor IGBT includes a gate-emitter capacitor C GE 、Miller capacitance C GC , collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter, L s,C is the collector side parasitic inductance, L s,E is the parasitic inductance on the emitter side, L s,Gis the parasitic inductance on the gate side. In the figure, n is the total number of IGBT internal package chips, and each IGBT internal package chip includes a gate-emitter capacitor C GE 、Miller capacitance C GC , collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter, and the collector side parasitic inductance L s,C , emitter side parasitic inductance L s,E , gate side parasitic inductance L s,G , the collector side parasitic inductance L of each IGBT internal package chip s,C The second end is connected to the IGBT collector C. The emitter side parasitic inductance L of each IGBT internal package chip s,E The first end is connected to the IGBT emitter E, and the gate side parasitic inductance L of each IGBT internal package chip s,G The first end is connected to the IGBT gate G. IGBT packaging defects can be divided into three categories: gate defects ( Figure 2 Marking ①), collector defect ( Figure 2 Marking②), emitter defect ( Figure 2 The present invention is mainly used to detect whether ① and ③ have gate-emitter loop defects, that is, whether the IGBT has gate-emitter loop defects.

[0024] Figure 3 Schematic diagram of an IGBT turn-on transient process provided by an embodiment of the present invention. From the start time t0 of the IGBT turn-on process in the commutation circuit to be tested, the gate current i G and gate voltage u GE The voltage of the DC bus capacitor starts to rise. U DC Basically remain unchanged, the collector-emitter voltage u of the IGBT internal chip chip,CE and the collector-emitter voltage u of the IGBT CE Also unchanged; at time t1, the gate voltage u GE Rising to the threshold voltage U T , at this time the collector current i C The collector-emitter voltage u of the IGBT internal chip starts to rise. chip,CE and the collector-emitter voltage u of the IGBT CE starts to decrease; at time t2, the collector current i C Rising to the load current I L ; At time t3, the reverse recovery voltage of the freewheeling diode chip is -u chip,F and the reverse recovery voltage flowing through the freewheeling diode -u F At time t4, the collector current i C Reach peak ICP , correspondingly, the reverse recovery current i of the freewheeling diode F Also reached peak I FP At time t5, the opening process is basically completed. 0 ~t 1 The stage is the target stage of the present invention.

[0025] In order to achieve the above object, an embodiment of the present invention provides an IGBT defect detection method based on a gate current signal during a turn-on process. Figure 4 1 is a flow chart of an IGBT defect detection method based on a gate current signal during a turn-on process provided by an embodiment of the present invention, comprising: S1. Based on the gate current signal of the IGBT turn-on process in the commutation circuit to be tested, the current waveform of the target stage when the IGBT is actually working is obtained; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode The second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the IGBT gate is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor.

[0026] Specifically, obtaining the current waveform through the current signal requires the following steps, including signal acquisition, processing and display. The following is a basic process provided by an embodiment of the present invention: 1. Current signal acquisition stage, including equipment selection, connection and configuration of equipment.

[0027] The present invention can select a suitable current sensor to collect current signals according to the size and type of current (DC or AC). Common current sensors include shunts, Hall effect sensors, etc. After selecting a suitable current sensor, it is necessary to correctly connect the current sensor to the circuit to be tested and ensure that the connection between the sensor and the data acquisition system is stable and reliable.

[0028] Connect the signal output by the current sensor (which may be an analog signal or a digital signal) to a data acquisition system (such as a data acquisition card, oscilloscope, or microcontroller), and then configure the parameters of the data acquisition system, such as sampling rate, range, etc., to ensure that the current signal can be accurately captured.

[0029] 2. Current signal processing stage, including filtering, amplification and attenuation, conversion and other operations.

[0030] Due to the presence of various noises in the actual environment, the collected current signal may contain high-frequency noise. Therefore, it is necessary to remove these noises through a filter (such as a low-pass filter) to obtain a clearer current waveform.

[0031] If the current signal is weak, it may need to be amplified by an amplifier; if the signal is too strong, it may need to be attenuated by an attenuator to ensure that the current signal is within the range of the data acquisition system.

[0032] If the current sensor outputs an analog signal and the data acquisition system is a digital system, an analog-to-digital conversion (ADC) is required.

[0033] 3. The current waveform display stage includes selecting appropriate display software, displaying the current waveform, analyzing the current waveform, etc.

[0034] In the commutation circuit, the insulated gate bipolar transistor IGBT and the freewheeling diode FWD are connected in series, and the freewheeling diode FWD is connected to the load inductor. L load In parallel, DC bus capacitor C 0 The collector of the insulated gate bipolar transistor IGBT is connected to the parasitic inductance L on the collector side of the IGBT. s,C First terminal (positive pole), IGBT collector side parasitic inductance L s,C The second end (negative pole) is connected to the FWD loop parasitic inductance L s,2 First terminal (positive), load inductance L load The second end (negative pole), FWD loop parasitic inductance L s,2 The second end (negative pole) is connected to the FWD parasitic inductance L s,F First terminal (positive), FWD parasitic inductance L s,F The second end (negative pole) is connected to the first end (positive pole) of FWD, and the second end (negative pole) of FWD is connected to the load inductor L load The first terminal (positive pole) and the parasitic inductance L of the IGBT loop s,1The first terminal (positive pole), IGBT loop parasitic inductance L s,1 The second end (negative pole) is connected to the DC bus capacitor C 0 The first terminal (positive), DC bus capacitor C 0 The second end (negative pole) is connected to the parasitic inductance L on the emitter side of the IGBT. s,E The first terminal (positive electrode), gate turn-on resistance R G,on The second terminal (negative pole), gate turn-off resistor R G,off The second end (negative pole), IGBT emitter side parasitic inductance L s,E The second end (negative pole) is connected to the IGBT emitter, and the IGBT gate is connected to the gate turn-on resistor R G,on First terminal (positive electrode), gate turn-off resistor R G,off First terminal (positive terminal).

[0035] The present invention can use the built-in display software of the oscilloscope to receive, process and display the current waveform. The processed current signal data is imported into the display software, and a current waveform diagram is generated through the drawing function. Different time axis and vertical axis (current) scales can be set to observe the waveform more clearly. On the waveform diagram, the current change trend, peak value, cycle and other characteristics can be observed. Based on these characteristics, the working state of the circuit can be analyzed and evaluated.

[0036] In one embodiment, the gate voltage signal of the IGBT turn-on process to be tested can be collected by a current signal detector, and then the current signal can be transmitted to the waveform drawing software. Alternatively, the current signal can be directly captured and the current waveform can be displayed by an oscilloscope or other electronic measuring instrument.

[0037] S2. Calculate the gate capacitance charge amount in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working.

[0038] In one embodiment, the calculating the charge amount of the gate capacitance in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working comprises: S201. Obtaining the gate current at each moment of the target phase when the IGBT is actually working from the current waveform of the target phase when the IGBT is actually working; S202. Calculate the charge amount of the gate capacitance in the target stage when the IGBT is actually working by using the gate current at each moment in the target stage when the IGBT is actually working.

[0039] In one embodiment, the gate capacitance charging charge amount of the IGBT in the target stage when the IGBT is actually working can be obtained by integrating the gate current at each moment of the target stage when the IGBT is actually working in the current waveform diagram of the target stage when the IGBT is actually working. The gate capacitance charging charge amount Q of the IGBT in the target stage when the IGBT is actually working can be obtained. G Calculated by the following formula: ; Where n is the total number of IGBT packaged chips, i G is the gate current at each moment of the target phase when the IGBT is actually working, t 0 is the starting time of the target phase, t 1 The target phase ends.

[0040] Specifically, during the IGBT turn-on transient, the gate-emitter capacitance (C GE ) and Miller capacitance (C GC ) The current direction is Figure 1 shown.

[0041] 1) For C GE , if the voltage reference direction is G→E, then the process C GE Charging, gate-emitter voltage u GE rise.

[0042] 2) For C CG , if the voltage reference direction is C→G, then the process C CG Discharge, u CG and u CE reduce.

[0043] Gate current i G There is the following relationship with the voltage (Q G Discharge amount for gate of a single chip): ; If the collector-gate voltage u is taken into account CG ≈gate-emitter voltage u CE ,exist: ; C GE is a constant (not changing with u GE changes), while C CG is a variable (variable with u CG Or u CE Considering t 0 ~t 1 Stage, u GE changes, and u CG Or u CE does not change, so CCG No changes occur during the process.

[0044] The stage before the collector current starts to rise (t 0 ~t 1 stage), whether the voltage and capacitance change is summarized in Table 1: Table 1

[0045] Considering the changes in voltage and capacitance at different stages, i G It can be expressed as: .

[0046] In summary, 0 ~t 1 Phase gate voltage u GE The waveform can be used to analyze gate emitter (GE) loop defects, including gate defects ( Figure 2 Marking ①), emitter defect ( Figure 2 In another embodiment, it is also possible to use t 0 ~t 1 Phase gate voltage u GE Calculate t 0 ~t 1 Phase gate current i G , and then through the gate current i G By performing integral calculation, the charge amount of the gate capacitance during the target phase when the IGBT is actually working can be obtained.

[0047] Define the gate-emitter loop time of a single chip τ 0 It can be calculated by the following formula: τ 0 =R G,on C GE .

[0048] In the formula, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance.

[0049] Overall gate loop time constant τ It can be calculated by the following formula: τ = n × τ 0 =R G,on × nC GE .

[0050] In the formula, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance, n is the total number of IGBT packaged chips.

[0051] t 0 ~ t During gate discharge, the following relationship is satisfied: ; In the formula, u GE is the gate voltage at each moment of the target stage when the IGBT is actually working, n is the total number of IGBT packaged chips, U G,on Turn on the control voltage for the drive power supply, U G,off Shuts down the control voltage for the driver power supply.

[0052] If the gate (G) or emitter (E) contact defect occurs in the gate-emitter loop, the gate loop discharge time constant will become smaller.

[0053] In one embodiment, the gate voltage u GE from U G,on Raise to U T process (i.e. t 0 ~ t 1 ) The gate charge can be calculated using the following formula: ; In the formula, C GE is the gate-emitter capacitance, U G,off To turn off the control voltage for the drive power supply, U T It is the IGBT gate threshold voltage. When the gate voltage is greater than this value, the gate channel is turned on and the collector current begins to rise.

[0054] S3. Analyze and determine whether there is a gate-emitter loop defect in the IGBT in the commutation circuit to be tested according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working. The gate-emitter loop defect includes a gate defect and an emitter defect.

[0055] In one embodiment, analyzing and determining whether the current IGBT has a defect according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working includes: When the amount of charge charged on the gate capacitance in the target phase during the actual operation of the IGBT is less than a threshold value, the current IGBT has a gate-emitter loop defect.

[0056] In one embodiment, the threshold is the charge amount of the gate capacitor in the target phase when the current IGBT is working normally. The charge amount of the gate capacitor in the target phase when the IGBT is working normally can also be calculated by referring to the above method, which will not be repeated here.

[0057] In one embodiment, the method further includes: S4. If the current IGBT has a gate-emitter loop defect, the number of defective chips in the IGBT is calculated based on the charge amount of the gate capacitance in the target stage.

[0058] In one embodiment, the number m of defective chips in the IGBT is calculated by the following formula: ; Where n is the total number of IGBT package chips, Q G It is the charge amount of gate capacitance in the target phase when IGBT is actually working. It is the charge amount of the gate capacitance in the target stage when the IGBT is working normally.

[0059] Specifically, at a known gate voltage u GE from U G,on (The driving power supply turns on the control voltage, which is also the starting time of the target stage t 0 The corresponding gate voltage) increases to U T (IGBT gate threshold voltage, which is the end time of the target stage t 1 When the gate charging charge changes during the process of the corresponding gate voltage), the number of defective chips in the IGBT can be calculated by the above formula.

[0060] Specifically, when there is m The gate or emitter contact of the IGBT chip packaging structure is abnormal, and the gate circuit time Calculated by the following formula: ; In the above case, the gate voltage u GE from U G,on Raise toU T process (i.e. t 0 ~ t 1 ) Gate charge Q G,fault Calculated by the following formula: ; Among them, n is the total number of IGBT packaged chips, C GE is the gate-emitter capacitance, U G,off To turn off the control voltage for the drive power supply, U T is the IGBT gate threshold voltage, which is also the end time of the target stage t 1 The corresponding gate voltage.

[0061] From the above formula, we can see that Δ Q G =Q G,fault — Q G <0; Gate voltage u GE from U G,on Raise to U T process (i.e. t 0 ~ t 1 ), the gate capacitance charge Q G A decrease in the voltage indicates that a gate-emitter (GE) circuit defect has occurred in the IGBT.

[0062] In a specific embodiment, taking a wind power converter as an example, an IGBT defect detection method based on a gate current signal of a turn-on process provided by the present invention is used to detect whether there is a defect in the gate-emitter loop (GE) inside the IGBT of the wind power converter. First, an oscilloscope is used to collect the gate current signal of the IGBT turn-on process and display the current waveform of the target stage when the IGBT is actually working. Then, the current waveform of the target stage when the IGBT is actually working is transmitted to an analyzer for analysis and processing. The analyzer obtains the gate current of the target stage when the IGBT is actually working from the current waveform of the target stage when the IGBT is actually working. The gate current of the gate capacitor at each moment of the target stage when the IGBT is actually working is calculated by the gate current of each moment of the target stage when the IGBT is actually working. When the gate capacitor charge amount of the target stage when the IGBT is actually working is less than the gate capacitor charge amount of the target stage when the current IGBT is working normally, the current IGBT has a gate-emitter loop defect. The present application can improve the defect detection efficiency of the IGBT. Furthermore, if the current IGBT has a gate-emitter loop defect, the number of defective chips in the IGBT can also be calculated based on the gate capacitor charge amount of the target stage. The analyzer can detect whether the current IGBT has gate-emitter loop defects in real time based on the current waveform of the target phase when the IGBT is actually working, and issue an early warning to remind the operation and maintenance personnel to perform maintenance, thereby improving the efficiency of later maintenance and reducing the operation and maintenance costs. At the same time, it can also display how many packaged chips in the IGBT are faulty, which can further improve the operation and maintenance efficiency.

[0063] Compared with the prior art, the present invention analyzes the change in gate charge through the gate current waveform during the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter loop defect, which can easily detect the defective state of the IGBT and improve the detection efficiency. In particular, when there is a defect in the IGBT, the technical solution of the present invention can also be used to know the number of packaged chips with specific defects in the IGBT, and quantitative detection can be achieved, which has certain guiding significance for IGBT state detection.

[0064] Based on the same inventive concept, an embodiment of the present invention further provides an IGBT defect detection device based on a gate current signal during a turn-on process. Figure 5 1 is a schematic diagram of the structure of an IGBT defect detection device based on a gate current signal during a turn-on process provided by an embodiment of the present invention, comprising: The acquisition module is used to acquire the current waveform of the target stage when the IGBT is actually working based on the gate current signal of the IGBT turn-on process in the commutation circuit to be measured; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode circuit one end, the second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the gate of the IGBT is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor; The acquisition module includes a collection module and a drawing module; The acquisition module is used to collect the gate current signal of the IGBT turn-on process; The drawing module is used to draw a current waveform diagram of the IGBT when it is actually working according to the gate current signal of the IGBT turn-on process, and extract the current waveform of the IGBT in the target stage when it is actually working from the current waveform diagram of the IGBT when it is actually working for the next step of processing.

[0065] A calculation module, used for calculating the charge amount of the gate capacitance in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working; The computing module includes a first unit and a second unit; The first unit is used to obtain the gate current at each moment of the target phase when the IGBT is actually working from the current waveform of the target phase when the IGBT is actually working; The second unit is used to calculate the charge amount of the gate capacitance in the target stage when the IGBT is actually working through the gate current at each moment of the target stage when the IGBT is actually working.

[0066] The target phase gate capacitance charge Q when the IGBT is actually working G Calculated by the following formula: ; Where n is the total number of IGBT packaged chips, i G is the gate current at each moment of the target phase when the IGBT is actually working, t 0 is the starting time of the target phase, t 1The target phase ends.

[0067] The judgment module is used to analyze and judge whether there is a gate-emitter loop defect of the IGBT in the commutation circuit to be tested according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working, and the gate-emitter loop defect includes a gate defect and an emitter defect.

[0068] The judgment module includes a third unit and a fourth unit; The third unit is used to obtain a threshold value; the threshold value is the charge amount of the gate capacitance in the target stage when the current IGBT is working normally.

[0069] The fourth unit is used to compare the gate capacitance charging charge amount in the target stage when the IGBT is actually working with the threshold value obtained by the third unit. When the gate capacitance charging charge amount in the target stage when the IGBT is actually working is less than the threshold value, it is considered that the current IGBT has a gate-emitter loop defect.

[0070] The quantitative detection module is used to calculate the number of defective chips in the IGBT according to the charge amount of the gate capacitor in the target stage when the judgment result sent by the judgment module is that the current IGBT has a gate-emitter loop defect.

[0071] The number m of defective chips in the IGBT is calculated by the following formula: ; Where n is the total number of IGBT package chips, Q G It is the charge amount of gate capacitance in the target phase when IGBT is actually working. It is the charge amount of the gate capacitance in the target stage when the IGBT is working normally.

[0072] The remaining embodiments of the device can be implemented in one-to-one correspondence with the aforementioned method embodiments, and will not be described in detail here.

[0073] The embodiment of the present invention also provides a computer device, such as Figure 6 The figure is a structural block diagram of a computer device provided by an embodiment of the present invention, including a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor implements any of the above methods when executing the computer program.

[0074] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above methods when executed by a processor.

[0075] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0076] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0077] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0078] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0079] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0080] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An IGBT defect detection method based on a gate current signal during a turn-on process, characterized in that: include: Based on the gate current signal of the IGBT turn-on process in the commutation circuit to be measured, the current waveform of the target stage when the IGBT is actually working is obtained; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode. The second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the gate of the IGBT is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor; According to the current waveform of the target stage when the IGBT is actually working, the charge amount of the gate capacitance in the target stage when the IGBT is actually working is calculated; According to the charge amount of the gate capacitor in the target stage when the IGBT is actually working, it is analyzed and determined whether there is a gate-emitter loop defect in the IGBT in the commutation circuit to be tested, and the gate-emitter loop defect includes a gate defect and an emitter defect.

2. The method according to claim 1, characterized in that: The calculating, according to the current waveform of the target stage when the IGBT is actually working, the charge amount of the gate capacitance in the target stage when the IGBT is actually working comprises: Obtaining the gate current at each moment of the target phase when the IGBT is actually working from the current waveform of the target phase when the IGBT is actually working; The gate capacitance charge during the target phase of the actual operation of the IGBT is calculated by using the gate current at each moment during the target phase of the actual operation of the IGBT.

3. The method according to claim 2, characterized in that: The target phase gate capacitance charge Q when the IGBT is actually working G Calculated by the following formula: ； Where n is the total number of IGBT packaged chips, i G It is the gate current at each moment of the target phase when the IGBT is actually working, t0 is the starting moment of the target phase, and t1 is the ending moment of the target phase.

4. The method according to any one of claims 1 to 3, characterized in that: The analyzing and judging whether the current IGBT has a defect according to the charge amount of the gate capacitance in the target stage when the IGBT is actually working includes: When the amount of charge charged on the gate capacitance in the target phase during the actual operation of the IGBT is less than a threshold value, the current IGBT has a gate-emitter loop defect.

5. The method according to claim 4, characterized in that: The threshold value is the charge amount of the gate capacitance in the target phase when the current IGBT is working normally.

6. The method according to claim 4, characterized in that: The method also includes: if the current IGBT has a gate-emitter loop defect, the number of defective chips in the IGBT is calculated based on the charge amount of the gate capacitor in the target phase.

7. The method according to claim 6, characterized in that: The number m of defective chips in the IGBT is calculated by the following formula: ； Where n is the total number of IGBT package chips, Q G It is the charge amount of gate capacitance in the target phase when IGBT is actually working. It is the charge amount of the gate capacitance in the target stage when the IGBT is working normally.

8. An IGBT defect detection device based on a gate current signal during a turn-on process, characterized in that: include: The acquisition module is used to acquire the current waveform of the target stage when the IGBT is actually working based on the gate current signal of the IGBT turn-on process in the commutation circuit to be measured; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; the collector of the IGBT is connected to the first end of the parasitic inductance on the collector side of the IGBT, the second end of the parasitic inductance on the collector side of the IGBT is respectively connected to the first end of the parasitic inductance of the freewheeling diode circuit and the second end of the load inductance, and the second end of the parasitic inductance of the freewheeling diode circuit is connected to the first end of the parasitic inductance of the freewheeling diode circuit one end, the second end of the parasitic inductance of the freewheeling diode is connected to the first end of the freewheeling diode, the second end of the freewheeling diode is respectively connected to the first end of the load inductance and the first end of the parasitic inductance of the IGBT loop, the second end of the parasitic inductance of the IGBT loop is connected to the first end of the DC bus capacitor, the second end of the DC bus capacitor is respectively connected to the first end of the parasitic inductance on the emitter side of the IGBT, the second end of the gate turn-on resistor, and the second end of the gate turn-off resistor, the second end of the parasitic inductance on the emitter side of the IGBT is connected to the emitter of the IGBT, and the gate of the IGBT is respectively connected to the first end of the gate turn-on resistor and the first end of the gate turn-off resistor; A calculation module, used for calculating the charge amount of the gate capacitance in the target stage when the IGBT is actually working according to the current waveform in the target stage when the IGBT is actually working; The judgment module is used to analyze and judge whether there is a gate-emitter loop defect of the IGBT in the commutation circuit to be tested according to the charge amount of the gate capacitor in the target stage when the IGBT is actually working, and the gate-emitter loop defect includes a gate defect and an emitter defect.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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