Detection circuit

Abstract

The invention provides a detection circuit. The detection circuit comprises a counter circuit, a sensing circuit, a monitoring circuit, a sampling circuit and a judging circuit, the counter circuit executes a counting operation according to the first initial value and the second initial value to generate a first counting value and a second counting value respectively. The sensing circuit provides a first sensing channel and a second sensing channel. The monitoring circuit generates at least one control signal according to the first count value and the second count value. The sampling circuit samples a first sensing signal of the first sensing channel and a second sensing signal of the second sensing channel in a polling mode according to at least one control signal so as to obtain a first sensing sampling value and a second sensing sampling value respectively. The judgment circuit judges whether at least one protection starting event occurs or not according to the first sensing sampling value and the second sensing sampling value so as to control at least one protection operation. According to the invention, whether a protection starting event occurs or not can be detected according to different time requirements, and the protection function can be controlled.

Description

Technical Field

[0001] The present invention relates to a detection circuit, and more particularly to a detection circuit which can detect whether a protection start event occurs and control the protection function according to different time requirements. Background Art

[0002] Generally speaking, the protection circuit in the chip can determine whether to perform protection operation according to multiple system parameters (voltage, current, temperature, etc.) In order to meet various protection conditions and requirements of the system, the protection circuit needs to be equipped with multiple comparators, which increases the size of the chip. Summary of the invention

[0003] The present invention provides a detection circuit, which includes a counter circuit, a sensing circuit, a monitoring circuit, a sampling circuit, and a judgment circuit. The counter circuit performs a counting operation according to a first initial value and a second initial value to generate a first counting value and a second counting value respectively. The sensing circuit provides a first sensing channel and a second sensing channel. The monitoring circuit is coupled to the counter circuit and generates at least one control signal according to the first counting value and the second counting value. The sampling circuit is coupled to the sensing circuit and the monitoring circuit, and samples a first sensing signal of the first sensing channel and a second sensing signal of the second sensing channel in a polling manner according to at least one control signal to obtain a first sensing sampling value and a second sensing sampling value respectively. The judgment circuit is coupled to the sampling circuit to receive the first sensing sampling value and the second sensing sampling value, and determines whether at least one protection start event occurs according to the first sensing sampling value and the second sensing sampling value, thereby controlling at least one protection operation.

[0004] The present invention can adapt to the conditions and requirements of the system for different protection operations by setting the threshold values ​​TH30-TH34 and the preset values ​​of the matching counters, without using a large number of comparators to avoid increasing the size of the detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 4 shows a detection circuit according to an embodiment of the present invention.

[0006] Figure 2 According to an embodiment of the present invention, Figure 1 The counter circuit in the detection circuit and the overload control circuit.

[0007] Figure 3 According to an embodiment of the present invention, Figure 1 The sensing circuit and the judgment circuit in the detection circuit.

[0008] Figure 4 According to an embodiment of the present invention, Figure 1The protection control circuit in the detection circuit.

[0009] Reference Numbers

[0010] 1: Detection circuit

[0011] 10: Memory

[0012] 11: Counter circuit

[0013] 12: Heavy load control circuit

[0014] 13: Sensing circuit

[0015] 14: Monitoring circuit

[0016] 15: Sampling circuit

[0017] 16: Judgment circuit

[0018] 17: Protection control circuit

[0019] 30: Matching counter circuit

[0020] 31: Output circuit

[0021] 32: External temperature sensor

[0022] 40~44:OR gate

[0023] 45-48: AND gate

[0024] 49~52:Driver

[0025] 53: Transistor

[0026] 54: Resistor

[0027] 55: Transistor

[0028] 120~126: Buffer (BUF)

[0029] 127-129: AND gate

[0030] 130, 131: Resistors

[0031] 132: Operational Amplifier

[0032] 133, 134: Resistors

[0033] 135: Internal temperature sensor

[0034] 150: Multiplexer

[0035] 151: Analog-to-digital converter (ADC)

[0036] 152: Demultiplexer

[0037] 160~164: Buffer (BUF)

[0038] 165-169: AND gate

[0039] CM30~CM34: Comparator

[0040] E30~E34: Enable signal

[0041] F30~F34: Flag signal

[0042] GND: Ground

[0043] MC30~MC34:matching counter

[0044] N30: Node

[0045] S12: Control signal

[0046] S13: Sensing signal

[0047] S13_30~S13_34: Sensing signal

[0048] S14A, S14B, S14C: control signal

[0049] S16A: Protection start signal

[0050] S16A_30~S16A_34: Protection start signal

[0051] S16B: Status signal

[0052] S16C: Continuous detection signal

[0053] S30~S34: Comparison signal

[0054] S150: Output signal

[0055] T30~T34:Input terminal

[0056] TH30~TH34: critical value

[0057] V10: Initial value

[0058] V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, V10_EADC: initial values

[0059] V11: count value

[0060] V11_20~V11_26: count value

[0061] V151: Sampling value

[0062] V152: Sensing sampling value

[0063] V152_30~V152_34: Sensing sampling value DETAILED DESCRIPTION

[0064] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

[0065] Figure 1 FIG. 2 is a diagram showing a detection circuit according to an embodiment of the present invention. Figure 1 The detection circuit 1 includes a memory 10, a counter circuit 11, a reload control circuit 12, a sensing circuit 13, a monitoring circuit 14, a sampling circuit 15, a judgment circuit 16, and a protection control circuit 17. The memory 10 stores at least two initial values ​​V10. During the operation of the detection circuit 1, the at least two initial values ​​V10 are loaded into the counter circuit 11. The counter circuit 11 performs a counting operation starting from the at least two initial values ​​V10 to generate at least two count values ​​V11 respectively. The reload control circuit 12 is coupled to the counter circuit 11 to receive all the count values ​​V11. When all the count values ​​V11 are equal to zero, the reload control circuit 12 controls the memory 10 to reload the at least two initial values ​​V10 into the counter circuit 11.

[0066] The sensing circuit 13 detects the environmental parameters of the system where the detection circuit 1 is located and / or the internal temperature of the detection circuit 1 with at least two sensing channels. For example, the environmental parameters of the system can be a voltage or voltage from the system, or the temperature of the system. The sensing circuit 13 generates at least two sensing signals S13 according to the sensing results. The monitoring circuit 14 is coupled to the counter circuit 11, and generates control signals S14A and S14B according to the above-mentioned at least two initial values ​​V10. In this embodiment, the system can be a power management system.

[0067] The sampling circuit 15 can perform a sampling operation on the sensing signals S13 of the at least two sensing channels of the sensing circuit 13 in a polling manner during at least one sampling period to obtain at least two sensing sampling values ​​V152. Figure 1The sampling circuit 15 includes a multiplexer 150, an analog-to-digital converter (ADC) 151, and a demultiplexer 152. The multiplexer 150 has at least two input terminals and an output terminal. The at least two input terminals of the multiplexer 150 correspond to the at least two sensing channels mentioned above. The multiplexer 150 receives a control signal S14A, and is controlled by the control signal S14A to select a sensing signal S13 of one of the at least two sensing channels each time, and outputs the selected sensing signal S13 through the output terminal as an output signal S150. Therefore, it can be known that through the control signal S14A, the multiplexer 150 selects a sensing signal S13 as an output signal S150 each time in a polling manner during a sampling period. In this embodiment, the at least two initial values ​​V10 determine the preset number of times that the at least two sensing channels are scanned (selected) during a sampling period. The at least two initial values ​​V10 can be adjusted according to system requirements. In other words, the sampling period is determined by the period required for completing the predetermined number of scans for each of the at least two sensing channels.

[0068] The analog-to-digital converter 151 is coupled to the multiplexer 150 and receives the output signal S150. The analog-to-digital converter 151 performs a digital-to-analog conversion operation on the analog output signal S150. Through the polling of the at least two sensing channels by the multiplexer 150, the analog-to-digital converter 151 performs a digital-to-analog conversion operation on the analog output signal S150 at least two times in a sampling period to generate a sampling value V151. The demultiplexer 152 has an input terminal and a plurality of output terminals. The demultiplexer 152 receives the control signal S14B and is controlled by the control signal S14B to selectively transmit the currently obtained sampling value V151 to one of the at least two output terminals as a sensing sampling value V152 each time. According to the above, the analog-to-digital converter 151 performs a digital-to-analog conversion operation on the output signal S150 at least two times, so that the output terminal of the demultiplexer 152 outputs at least two sensing sampling values ​​V152 correspondingly. In this embodiment, at least two input terminals of the multiplexer 150 correspond to at least two output terminals of the demultiplexer 152. Therefore, the control signals S14A and S14B are signals corresponding to each other. Therefore, the selection operations of the multiplexer 150 and the demultiplexer 152 correspond to each other.

[0069] The judgment circuit 16 is coupled to at least two output terminals of the demultiplexer 152 to receive the at least two sensing sample values ​​V152 at different times. The judgment circuit 16 judges whether at least one protection activation event occurs according to the at least two sensing sample values ​​V152 to generate at least one protection activation signal S16A. The protection control circuit 17 receives the at least one protection activation signal S16A and controls at least one protection operation according to the at least one protection activation signal S16A. In this embodiment, the at least one protection operation includes at least one of an overcurrent protection operation, an underpower protection operation, an overcurrent protection operation, and a short circuit protection operation.

[0070] According to the above-mentioned embodiment, the detection circuit 1 of the present invention can determine a sampling period by setting at least two initial count values, and detect whether a protection start event occurs by taking a sampling period as a unit.

[0071] Figure 2 1 is a diagram showing a counter circuit 11 and a reload control circuit 12 according to an embodiment of the present invention. In order to clearly explain the operation of the counter circuit 11 and the reload control circuit 12, Figure 2 Simultaneous display memory 10. Figure 2 , the counter circuit 11 includes at least two counters. In this embodiment, the counter circuit 11 includes seven counters DC20-DC26 as an example. Based on the seven counters DC20-DC26, the memory 10 stores seven initial values ​​V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, and V10_EADC. During the operation of the detection circuit 1, the initial values ​​V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, and V10_EADC are loaded into the counters DC20-DC26, respectively. In this embodiment, the counters DC20-DC26 are implemented as down counters. Counters DC20-DC26 respectively start to perform down counting operation from initial values ​​V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, and V10_EADC to generate count values ​​V11_20-V11_26 respectively. For example, the initial values ​​V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, and V10_EADC are 255, 255, 255, 255, 1, 0, 0 respectively, but the present invention is not limited thereto.

[0072] The reload control circuit 12 includes buffers (BUF) 120-126 and AND gates 127-129. The input terminals of the buffers 120-126 are respectively coupled to the counters DC20-DC26. The three input terminals of the AND gate 127 are respectively coupled to the output terminals of the buffers 120-122, that is, the count values ​​V11_20-V11_22 are respectively transmitted to the AND gate 127 through the buffers 120-122. The three input terminals of the AND gate 128 are respectively coupled to the output terminals of the buffers 124-126, that is, the count values ​​V11_24-V11_26 are respectively transmitted to the AND gate 128 through the buffers 124-126. The AND gate 129 has three input terminals. The first input terminal of the AND gate 129 is coupled to the output terminal of the buffer 123, that is, the count value V11_23 is respectively transmitted to the first input terminal of the AND gate 129 through the buffer 123. The second and third input terminals of the AND gate 129 are respectively coupled to the output terminals of the AND gates 127 and 128. The output terminal of the AND gate 129 is coupled to the counter circuit 11.

[0073] According to the circuit architecture of the reload control circuit 12, when all the count values ​​V11_20 to V11_26 are equal to zero, the AND gate 129 outputs the control signal S12 to control all the down counters DC20 to DC26 of the counter circuit 11 to read their initial values ​​from the memory 10 again, that is, the seven initial values ​​are reloaded into the down counters DC20 to DC2 respectively. Therefore, the counters DC20 to DC26 start to perform down counting operations again from the initial values ​​V10_OVP, V10_UVP, V10_OCP, V10_SCP, V10_NTC, V10_IT, and V10_EADC respectively.

[0074] In this embodiment, the count values ​​V11_20 ˜ V11_26 generated by the counters DC20 ˜ DC26 are also transmitted to the monitoring circuit 14 .

[0075] Figure 3 1 is a diagram showing a sensing circuit 13 and a judging circuit 16 according to an embodiment of the present invention. In order to clearly explain the operation of the sensing circuit 13 and the judging circuit 16, Figure 3 The monitoring circuit 14 and the sampling circuit 15 are also shown. In an embodiment of the present invention, the sensing circuit 13 includes a circuit for detecting or sensing the environmental parameters of the system where the detection circuit 1 is located and / or the internal temperature of the detection circuit 1. For example, in this embodiment, the sensing circuit 13 includes resistors 130 and 131 to form a voltage detector for detecting the voltage VIN of the input terminal T30. In this embodiment, the voltage VIN can be a power output path, a power input path, or a voltage on a critical path on the system where the detection circuit 1 is located. See Figure 3The resistors 130 and 131 are connected in series between the input terminal T30 and the ground GND to form a voltage divider circuit structure. According to the operation of the voltage divider circuit structure, a sensing signal S13_30 is generated at the node N30 between the resistors 130 and 131, which indicates the magnitude of the voltage VIN.

[0076] The sensing circuit 13 further includes an operational amplifier 132 and resistors 133 and 134 to form a current detector for detecting the current flowing through a specific component or device in the system through input terminals T31 and T32. Figure 3 The positive input terminal (+) of the operational amplifier 132 is coupled to the input terminal T31, and the resistor 133 is coupled between the input terminal T32 and the negative input terminal (-) of the operational amplifier 132. The resistor 134 is coupled between the negative input terminal (-) and the output terminal of the operational amplifier 132. Through the operation of this current detector, the operational amplifier 132 generates a sensing signal S13_31 at its output terminal, which represents the magnitude of the detected current.

[0077] The input terminal T33 of the sensing circuit 13 is coupled to an external temperature sensor 32 of the detection circuit 1. The external temperature sensor 32 senses the temperature of the system in which the detection circuit 1 is located (or, the external environment temperature of the detection circuit 1), and generates a sensing signal S13_32, which represents the detected external temperature. The input terminal T33 receives the sensing signal S13_32. The sensing circuit 13 includes an internal temperature sensor 135. The internal temperature sensor 135 senses the internal temperature of the detection circuit 1 to generate a sensing signal S13_33, which represents the detected internal temperature. The input terminal T34 of the sensing circuit 13 can be coupled to other sensors in the system for sensing environmental parameters to generate a corresponding sensing signal S13_34. The input terminal T34 receives the sensing signal S13_34.

[0078] According to the operation of the sensing circuit 13, the sampling circuit 15 receives the sensing signals S13_30 to S13_34 through five sensing channels, wherein the first sensing channel CH0 is a voltage sensing channel, the second sensing channel CH1 is a current sensing channel, the third sensing channel CH2 is an external temperature sensing channel, the fourth sensing channel CH3 is an internal temperature sensing channel, and the fifth sensing channel CH4 is an environmental parameter sensing channel.

[0079] In this embodiment, the multiplexer 150 has five input terminals, which receive the sensing signals S13_30 to S13_34 through the five sensing channels. Through the control signal S14A, the multiplexer 150 selects one sensing signal as the output signal S150 in a polling manner during a sampling period. In detail, the monitoring circuit 14 controls the multiplexer 150 to select the sensing signal S13_30 of the sensing channel CH0 according to the count values ​​V11_20 and V11_21 and through the control signal S14A; the monitoring circuit 14 controls the multiplexer 150 to select the sensing signal S13_31 of the sensing channel CH1 according to the count values ​​V11_22 and V11_23 and through the control signal S14A; the monitoring circuit 14 controls the multiplexer 150 to select the sensing signal S13_32 of the sensing channel CH2 according to the count value V11_24 and through the control signal S14A; the monitoring circuit 14 controls the multiplexer 150 to select the sensing signal S13_33 of the sensing channel CH3 according to the count value V11_25 and through the control signal S14A; the monitoring circuit 14 controls the multiplexer 150 to select the sensing signal S13_34 of the sensing channel CH4 according to the count value V11_26 and through the control signal S14A. During the polling process, the multiplexer 150 selects the sensing signals S13_30-S13_34 from the five sensing channels CH0-CH4 in a specific order as the output signal S150. In one embodiment, the specific order is from the sensing signal S13_30 to the sensing signal S13_34, that is, from the sensing channel CH0 to the sensing channel CH4.

[0080] The analog-to-digital converter 151 performs a digital-to-analog conversion operation on the output signal S150 to generate a sample value V151. For example, when the multiplexer 150 selects the sensing signal S13_30 as the output signal S150 according to the control signal S14A (that is, when the sampling circuit 15 scans the sensing channel CH0), the sample value V151 corresponds to the sensing signal S13_30 to indicate the magnitude of the current voltage VIN. The sampling operation of the sensing signal S13_30 is implemented through the operation of the multiplexer 150 and the analog-to-digital converter 151. For another example, when the multiplexer 150 selects the sensing signal S13_31 as the output signal S150 according to the control signal S14A (that is, when the sampling circuit 15 scans the sensing channel CH1), the sample value V151 corresponds to the sensing signal S13_31 to indicate the magnitude of the current current. Through the operation of the multiplexer 150 and the analog-to-digital converter 151 , the sampling operation of the sensing signal S13_31 is implemented.

[0081] The demultiplexer 152 has five output terminals, which correspond to the five input terminals of the multiplexer 150, that is, the five sensing channels CH0-CH4. The demultiplexer 152 selectively transmits the currently obtained sample value V151 to one of the five output terminals according to the control signal S14B as one of the sensing sample values ​​V152_30-V152_34. For example, when the multiplexer 150 selects the sensing signal S13_30 as the output signal S150 according to the control signal S14A, the demultiplexer 152 outputs the sample value V151 as the sensing sample value V152_30 according to the control signal S14B. For another example, when the multiplexer 150 selects the sensing signal S13_31 as the output signal S150 according to the control signal S14A, the demultiplexer 152 outputs the sample value V151 as the sensing sample value V152_31 according to the control signal S14B. Similarly, based on the operation of the multiplexer 150, the demultiplexer 152 can also output the sensing sample values ​​V152_32 to V152_34, which respectively correspond to the sensing signals S13_32 to S13_34.

[0082] See also Figure 3 , the judgment circuit 16 includes buffers (BUF) 160-164, comparators CM30-CM34, a matching counter circuit 30, and an output circuit 31. The buffers 160-164 are coupled to the demultiplexer 152 to respectively receive and temporarily store the sensing sample values ​​V152_30-V152_34. The comparator CM30 is coupled to the buffer 160 to receive the sensing sample value V152_30 and the threshold value TH30. By comparing the sensing sample value V152_30 with the threshold value TH30 by the comparator CM30, it can be determined whether an over-voltage event occurs to generate a comparison signal S30. For example, when the sensing sample value V152_30 is greater than (>) or equal to (=) the threshold value TH30, the comparator CM30 enables the comparison signal S30 to indicate whether an over-voltage event occurs in the system; otherwise, the comparator CM30 disables the comparison signal S30.

[0083] The comparator CM31 is coupled to the buffer 160 to receive the sensed sample value V152_30 and the threshold value TH31. By comparing the sensed sample value V152_30 with the threshold value TH31, the comparator CM31 can determine whether an undervoltage event occurs to generate a comparison signal S31. For example, when the sensed sample value V152_30 is less than (<) or equal to (=) the threshold value TH31, the comparator CM31 enables the comparison signal S31 to indicate whether an undervoltage event occurs in the system; otherwise, the comparator CM31 disables the comparison signal S31.

[0084] The comparator CM32 is coupled to the buffer 161 to receive the sensed sample value V152_31 and the threshold value TH32. By comparing the sensed sample value V152_31 with the threshold value TH32 by the comparator CM32, it is possible to determine whether an overcurrent event occurs to generate a comparison signal S32. For example, when the sensed sample value V152_31 is greater than (>) or equal to (=) the threshold value TH32, the comparator CM32 enables the comparison signal S32 to indicate whether an overcurrent event occurs in the system; otherwise, the comparator CM32 disables the comparison signal S31.

[0085] The comparator CM33 is coupled to the buffer 161 to receive the sensed sample value V152_31 and the threshold value TH33. By comparing the sensed sample value V152_31 with the threshold value TH33, the comparator CM33 can determine whether a short circuit event occurs to generate a comparison signal S33. For example, when the sensed sample value V152_31 is greater than (>) or equal to (=) the threshold value TH33, the comparator CM33 enables the comparison signal S33 to indicate whether a short circuit event occurs in the system; otherwise, the comparator CM33 disables the comparison signal S33.

[0086] The comparator CM34 is coupled to the buffer 162 to receive the sensed sample value V152_32 and the threshold value TH34. By comparing the sensed sample value V152_32 with the threshold value TH34, the comparator CM34 can determine whether an over-temperature or under-temperature event occurs to generate a comparison signal S34. For example, when the sensed sample value V152_32 is greater than (>) or equal to (=) the threshold value TH34, the comparator CM34 enables the comparison signal S34 to indicate whether an over-temperature or under-temperature event occurs in the system; otherwise, the comparator CM34 disables the comparison signal S34.

[0087] As described above, the buffers 163 and 164 receive and temporarily store the sensing sample values ​​V152_33 and V152_34 respectively. The sensing sample values ​​V152_33 and V152_34 can be used by the detection circuit 1 or other circuits or devices of the system to perform protection functions or system control.

[0088] The match counter circuit 30 includes match counters MC30-MC34. In this embodiment, the match counters MC30-MC34 are implemented as down counters. The match counters MC30-MC34 have respective preset values ​​and start to count down from their respective preset values ​​during a sampling period. The output circuit 31 includes AND gates 165-169, which are respectively coupled to the match counters MC30-MC34.

[0089] See also Figure 3, the match counter MC30 is coupled to the comparator CM30 to receive the comparison signal S30. During a sampling period, the match counter MC30 counts down from the corresponding preset value toward zero. Whenever the comparison signal S30 is enabled, the match counter MC30 counts down once (i.e., the count value of the match counter MC30 is reduced by "1"). When the count value of the match counter MC30 is equal to zero, it indicates that a protection activation event related to overvoltage occurs, and the match counter MC30 enables the flag signal F30. The AND gate 165 receives the flag signal F30 and the enable signal E30 for overvoltage protection, and generates a protection activation signal S16A_30. When the flag signal F30 and the enable signal E30 are both enabled (at a high voltage level), the AND gate 165 enables the protection activation signal S16A_30 to indicate that the detection circuit 1 wants to activate the overvoltage protection operation. In this embodiment, the preset value of the match counter MC30 is, for example, 3.

[0090] The match counter MC31 is coupled to the comparator CM31 to receive the comparison signal S31. During a sampling period, the match counter MC31 counts down from the corresponding preset value toward zero. Whenever the comparison signal S31 is enabled, the match counter MC31 counts down once (i.e., the count value of the match counter MC31 is reduced by "1"). When the count value of the match counter MC31 is equal to zero, it indicates that a protection activation event related to undervoltage occurs, and the match counter MC31 enables the flag signal F31. The AND gate 166 receives the flag signal F31 and the enable signal E31 for undervoltage protection, and generates a protection activation signal S16A_31. When the flag signal F31 and the enable signal E31 are both enabled, the AND gate 166 enables the protection activation signal S16A_31 to indicate that the detection circuit 1 wants to activate the undervoltage protection operation. In this embodiment, the preset value of the match counter MC31 is, for example, 3.

[0091] The match counter MC32 is coupled to the comparator CM32 to receive the comparison signal S32. During a sampling period, the match counter MC32 counts down from the corresponding preset value toward zero. Whenever the comparison signal S32 is enabled, the match counter MC32 counts down once (i.e., the count value of the match counter MC32 is reduced by "1"). When the count value of the match counter MC32 is equal to zero, it indicates that a protection activation event related to overcurrent occurs, and the match counter MC32 enables the flag signal F32. The AND gate 167 receives the flag signal F32 and the enable signal E32 for overcurrent protection, and generates a protection activation signal S16A_32. When the flag signal F32 and the enable signal E32 are both enabled, the AND gate 167 enables the protection activation signal S16A_32 to indicate that the detection circuit 1 intends to activate the overcurrent protection operation.

[0092] The match counter MC33 is coupled to the comparator CM33 to receive the comparison signal S33. During a sampling period, the match counter MC33 counts down from the corresponding preset value toward zero. Whenever the comparison signal S33 is enabled, the match counter MC33 counts down once (i.e., the count value of the match counter MC33 is reduced by "1"). When the count value of the match counter MC33 is equal to zero, it indicates that a protection activation event related to a short circuit occurs, and the match counter MC33 enables the flag signal F33. The AND gate 168 receives the flag signal F33 and the enable signal E33 for short circuit protection, and generates a protection activation signal S16A_33. When the flag signal F33 and the enable signal E33 are both enabled, the AND gate 168 enables the protection activation signal S16A_33 to indicate that the detection circuit 1 intends to activate the short circuit protection operation.

[0093] The match counter MC34 is coupled to the comparator CM34 to receive the comparison signal S34. During a sampling period, the match counter MC34 counts down from the corresponding preset value toward zero. Whenever the comparison signal S34 is enabled, the match counter MC34 counts down once (i.e., the count value of the match counter MC34 is reduced by "1"). When the count value of the match counter MC34 is equal to zero, it indicates that a protection activation event related to over-temperature / under-temperature occurs, and the match counter MC34 enables the flag signal F34. The AND gate 169 receives the flag signal F34 and the enable signal E34 for over-temperature / under-temperature protection, and generates a protection activation signal S16A_34. When the flag signal F34 and the enable signal E34 are both enabled, the AND gate 169 enables the protection activation signal S16A_34 to indicate that the detection circuit 1 intends to activate the over-temperature / under-temperature protection operation.

[0094] According to the above operation, the buffer 160, the comparators CM30 and CM31, the matching counters MC30 and MC31, and the AND gates 165 and 166 operate according to the sensing signal S13_30 of the voltage sensing channel CH0; the buffer 161, the comparators CM32 and CM33, the matching counters MC32 and MC33, and the AND gates 167 and 168 operate according to the sensing signal S13_31 of the current sensing channel CH1; the buffer 162, the comparator CM34, the matching counter MC34, and the AND gate 169 operate according to the sensing signal S13_32 of the external temperature sensing channel CH2; the buffer 163 operates according to the sensing signal S13_33 of the internal temperature sensing channel CH3; and the buffer 164 operates according to the sensing signal S13_34 of the environmental parameter sensing channel CH4.

[0095] According to an embodiment of the present invention, the detection circuit 1 can receive a continuous detection signal S16C. During a sampling period, when the comparison signal of the comparator corresponding to a sensing channel indicates the occurrence of a specific event for the first time (i.e., the count value of the match counter is reduced by "1" for the first time), the detection circuit 1 can make the corresponding match counter operate continuously to determine whether a protection start event occurs. The continuous detection signal S16C indicates the match counter that can operate continuously.

[0096] See also Figure 2 and Figure 3For example, when the continuous detection signal S16C indicates that the matching counter MC30 of the corresponding voltage sensing channel CH0 can operate continuously, when the comparison signal S30 of the comparator CM30 first indicates the occurrence of a specific event (i.e., the count value of the matching counter MC30 is reduced by "1" for the first time), the monitoring circuit 14 controls the counters DC20 and DC21 of the corresponding voltage sensing channel CH0 to continue the down counting operation according to the continuous detection signal S16C through the control signal S14C, and controls the counters DC22~DC26 corresponding to other sensing channels CH1~CH4 to stop the down counting operation. In addition, the monitoring circuit 14 generates a control signal S14A to control the multiplexer 150 to continuously select the sensing signal S13_30 (i.e., to continuously scan the voltage sensing channel CH0) according to the continuous detection signal S16C, and generates a control signal S14B to continuously control the demultiplexer 152 to continuously output the sampling value V151 as the sensing sampling value V152_30. At this time, the match counter circuit 30 controls the match counter MC30 to operate continuously according to the continuous detection signal S16C, and controls the other match counters MC31-MC34 to stop operating. In one case, during the continuous operation of the match counter MC30, when its count value is continuously reduced by "1" and finally equals to zero, the match counter circuit 30 determines that an overvoltage protection start event occurs, and notifies the monitoring circuit 14 of the count state of the match counter MC30 through the state signal S16B. In another case, during the continuous operation of the match counter MC30, when its count value is continuously reduced by "1" and finally equals to zero, the match counter circuit 30 determines that an overvoltage protection start event occurs, and notifies the monitoring circuit 14 of the count state of the match counter MC30 through the state signal S16B. During the continuous operation of 0, when its count value stops decreasing by "1" before reaching zero, the match counter circuit 30 controls the count value of the match counter MC30 to be reset to its preset value, and notifies the monitoring circuit 14 of the count state of the match counter MC30 through the state signal S16B. For the above two cases, after the monitoring circuit 14 learns the count state of the match counter MC30 according to the state signal S16B, the monitoring circuit 14 controls the counters DC22-DC26 to resume the down counting operation through the control signal S14C, controls the multiplexer 150 to select other sensing signals (i.e., scan other sensing channels) through the control signal S14A, and controls the demultiplexer 152 to output the sample value V151 as other sensing sample values ​​through the control signal S14B, thereby completing the polling of all sensing channels during a sampling period. In addition, the match counters MC31-MC34 also resume operation.

[0097] Figure 41 is a diagram showing a protection control circuit 17 according to an embodiment of the present invention. The protection control circuit 17 includes OR gates 40-44, AND gates 45-48, drivers 49-52, resistors 54, and transistors 53 and 55. OR gates 40 and 41, AND gate 45, and driver 49 form a protection circuit for conducting or cutting off the power output path of the system through the output terminal T40. A protection function start signal S40 is input to one end of the AND gate 45. OR gates 40 and 41 and AND gate 45 operate according to the protection start signal S16A_30-S16A_34 and the protection function start signal S40 to control the driver 49 to conduct or cut off the power output path. According to the above, when the protection function start signal S40 is enabled, when one of the protection start signals S16A_30~S16A_34 corresponding to the overvoltage protection operation, undervoltage protection operation, overcurrent protection operation, short circuit protection operation, and over / under temperature protection operation is enabled, the driver 49 cuts off the power output path.

[0098] The OR gate 42, the AND gate 46, and the driver 50 form another protection circuit for conducting or cutting off the power input path of the system through the output terminal T41. A protection function start signal S41 is input to one end of the AND gate 46. The OR gate 42 and the AND gate 46 operate according to the protection start signals S16A_30~S16A_32, S16A_34 and the protection function start signal S41 to control the driver 50 to conduct or cut off the power input path. According to the above, when the protection function start signal S41 is enabled, when one of the protection start signals S16A_30~S16A_32, S16A_34 corresponding to the overvoltage protection operation, the undervoltage protection operation, the overcurrent protection operation, and the over / under temperature protection operation is enabled, the driver 50 cuts off the power input path.

[0099] The OR gate 43, the AND gate 47, the driver 51, the transistor 53, and the resistor 54 constitute another protection circuit for providing or cutting off a discharge path between the input terminal T42 and the ground in the system. A protection function start signal S42 is input to one end of the AND gate 47. The OR gate 43 and the AND gate 47 operate according to the protection start signal S16A_30-S16A_32 and the protection function start signal S42 to control the driver 51 to turn on or off the transistor 53, thereby providing or cutting off a discharge path between the input terminal T42 and the ground. According to the above, when the protection function start signal S42 is enabled, when one of the protection start signals S16A_30-S16A_32 corresponding to the overvoltage protection operation, the undervoltage protection operation, and the overcurrent protection operation is enabled, the driver 51 turns on the transistor 53 to provide a discharge path between the input terminal T42 and the ground.

[0100] The OR gate 44, the AND gate 48, the driver 52, and the transistor 55 constitute another protection circuit for providing or cutting off a discharge path between the input terminal T43 and the ground in the system. A protection function start signal S43 is input to one end of the AND gate 48. The OR gate 44 and the AND gate 48 operate according to the protection start signal S16A_30-S16A_32 and the protection function start signal S43 to control the driver 52 to turn on or turn off the transistor 55, thereby providing or cutting off a discharge path between the input terminal T43 and the ground. According to the above, when the protection function start signal S43 is enabled, when one of the protection start signals S16A_30-S16A_32 corresponding to the overvoltage protection operation, the undervoltage protection operation, and the overcurrent protection operation is enabled, the driver 52 turns on the transistor 55 to provide a discharge path between the input terminal T43 and the ground. According to an embodiment of the present invention, the input terminals T42 and T43 are coupled to different nodes on a power path.

[0101] According to the above embodiment, the detection circuit 1 of the present invention can determine a sampling period by setting at least two initial count values, and detect whether a protection start event occurs in units of a sampling period. In addition, by setting the threshold values ​​TH30-TH34 and the preset values ​​of the matching counters MC30-MC34, the system can adapt to the conditions and requirements of different protection operations without using a large number of comparators, thereby avoiding increasing the size of the detection circuit 1.

[0102] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the definition of the preceding claims.

Claims

1. A detection circuit, characterized in that: include: A counter circuit performs a counting operation according to a first initial value and a second initial value to generate a first count value and a second count value respectively; A sensing circuit provides a first sensing channel and a second sensing channel; a monitoring circuit coupled to the counter circuit and generating at least one control signal according to the first count value and the second count value; a sampling circuit coupled to the sensing circuit and the monitoring circuit, and sampling a first sensing signal of the first sensing channel and a second sensing signal of the second sensing channel in a polling manner according to the at least one control signal to obtain a first sensing sampling value and a second sensing sampling value respectively; and A judgment circuit is coupled to the sampling circuit to receive the first sensing sampling value and the second sensing sampling value, and judges whether at least one protection activation event occurs according to the first sensing sampling value and the second sensing sampling value, so as to control at least one protection operation.

2. The detection circuit according to claim 1, characterized in that: The counter circuit includes: a first counter, which is loaded with the first initial value and performs a down-counting operation starting from the first initial value to generate the first count value; and A second counter is loaded with the initial value and starts to perform the down counting operation from the second initial value to generate the second count value.

3. The detection circuit according to claim 2, characterized in that: The circuit further comprises: a memory storing the first initial value and the second initial value; and a reload control circuit coupled to the first counter and the second counter to receive the first count value and the second count value respectively; When the first count value and the second count value corresponding to the first sampling period are both equal to zero, the reload control circuit controls the memory to reload the first initial value and the second initial value into the first counter and the second counter respectively.

4. The detection circuit according to claim 2, characterized in that: The monitoring circuit controls the sampling circuit to sample the first sensing signal according to the first count value and controls the sampling circuit to sample the second sensing signal according to the second count value through the at least one control signal.

5. The detection circuit according to claim 2, characterized in that: When the determination circuit determines that a first protection activation event of at least one protection activation event occurs according to the first sensing sample value, the monitoring circuit controls the first counter value to continue to perform the down-counting operation and controls the second counter value to suspend the down-counting operation.

6. The detection circuit according to claim 1, characterized in that: The first sensing channel corresponds to one of a voltage sensing circuit, a current sensing circuit, and a temperature sensor, and the second sensing channel corresponds to the other of the voltage sensing circuit, a current sensing circuit, and a temperature sensor.

7. The detection circuit according to claim 1, characterized in that: The at least one control signal includes a first control signal and a second control signal, and the sampling circuit includes; a multiplexer coupled to the first sensing channel and the second sensing channel and controlled by the first control signal to select one of the first sensing signal and the second sensing signal as an output signal; an analog-to-digital converter, coupled to the multiplexer, performing a digital-to-analog conversion operation on the output signal to generate a sample value; as well as a demultiplexer coupled to the analog-to-digital converter and comprising a plurality of output terminals; wherein the multiplexer is controlled by the second control signal to transmit the sampled value to one of the plurality of output terminals; When the multiplexer selects the first sensing signal as the output signal according to the first control signal, the sampling value is used as the first sensing sampling value; and When the multiplexer selects the second sensing signal as the output signal according to the first control signal, the sampling value is used as the second sensing sampling value.

8. The detection circuit according to claim 1, characterized in that: The judgment circuit comprises: a first buffer, coupled to the sampling circuit, receiving and storing the first sensing sample value; a first comparator coupled to the first buffer to receive the first sensing sample value, and compare the first sensing sample value with a first threshold value to generate a first comparison signal; and a first match counter coupled to the first comparator to receive the first comparison signal, wherein when the first comparison signal indicates a first specific relationship between the first sensing sample value and the first threshold value, the first match counter starts to perform a counting operation from a first preset value to generate a first count value; When the first count value reaches a count threshold, the judging circuit judges that a first protection activation event among the at least one protection activation event occurs, and enables a first flag signal associated with a first protection operation among the at least one protection operation.

9. The detection circuit according to claim 1, characterized in that: The control circuit includes: a second buffer, coupled to the sampling circuit, receiving and storing the second sensing sample value; a second comparator coupled to the second buffer to receive the second sensing sample value, and compare the second sensing sample value with a second threshold value to generate a second comparison signal; a second match counter coupled to the second comparator to receive the second comparison signal, wherein when the second comparison signal indicates a second specific relationship between the second sensing sample value and the second threshold value, the second match counter starts to perform the counting operation from a second preset value to generate a second count value; When the second count value reaches the count threshold, the judging circuit judges that a second protection activation event among the at least one protection activation event occurs, and enables a second flag signal associated with a second protection operation among the at least one protection operation.

10. The detection circuit according to claim 1, characterized in that: When the judgment circuit determines that a first protection activation event among at least one protection activation event occurs according to the first sensing sampling value, the monitoring circuit controls the counting operation of the counter circuit, and controls the sampling circuit through the at least one control signal to continuously sample the first sensing signal and suspend sampling the second sensing signal.

Images