A self-identifying switched DIP type package device test apparatus

Abstract

The application discloses a self-identification switching DIP type packaging device testing device, which comprises a clamping testing circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein the clamping testing circuit comprises an IC clamping seat J2, a gate connection end, a drain connection end and a source connection end; the IC clamping seat is used for placing a chip to be detected; and the gate connection end, the drain connection end and the source connection end are connected with a source table respectively. The self-identification switching DIP type packaging device testing device can recognize the G pole and automatically switch the testing circuit, solves the problem that the testing scheme needs manual identification, and is lower in risk and higher in efficiency in the whole testing process.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of DIP type packaged device testing, and particularly relates to a DIP type packaged device testing device capable of self-identification and switching. BACKGROUND

[0002] Electrical performance testing is a key step for detecting the performance of electronic components, and the performance of the components is detected by testing some specific parameter indexes, so as to evaluate the performance of electrical equipment and electronic products. Electrical performance testing is an important means to ensure the reliability and stability of electrical equipment and electronic products. For example, in order to ensure the normal operation of a MOSFET and meet the specification requirements, an effective method is to determine the characteristics of the MOSFET by tracking its I-V curve. By setting the source table Vstart initial voltage and Vstep step voltage for step voltage input, and connecting the gate G or drain D of the measured device, the drain current electrical parameter is measured, and the voltage resistance characteristics and the drain current of the device are verified, so as to judge the good or bad of the measured device.

[0003] At present, due to the test quantity requirement of the reliability test standard and the chip design verification for reducing cost, a Testkey (a structure for testing integrated circuits) is placed in a scribe line or a chip, and two or more same structures are connected for each Testkey, or two different Split structures of Testkey are connected to the Pad of each DIP package and the electrodes are led out through leads. In the IV electrical performance testing process, the electrical performance of each test structure in the DIP package needs to be tested, so as to compare the electrical performance under different Split and verify the reliability of the device. Since each Testkey in the DIP package has two same structures or two Testkeys are packaged, and the test quantity requirement needs to be tested and measured respectively, the test fixture plate needs to be replaced for corresponding I-V measurement of the front and rear test structures, and the DIP packaged device needs to be taken down and placed on another fixture plate, which greatly increases the test time, and the plugging of the line also causes the risk of personnel operation error, which leads to static breakdown of the device and connection error of the line. Figure 1 Figure 2 The main purpose of the application is to provide a DIP type packaged device testing device capable of self-identification and switching, which can identify the G pole and automatically switch the test circuit, so as to solve the problem that the test scheme needs to be manually identified, the risk of the whole test process is lower, and the efficiency is higher. SUMMARY

[0004] The main purpose of the application is to provide a DIP type packaged device testing device capable of self-identification and switching, which can identify the G pole and automatically switch the test circuit, so as to solve the problem that the test scheme needs to be manually identified, the risk of the whole test process is lower, and the efficiency is higher.

[0005] ​In order to achieve the above object, the application provides a DIP type package device test device capable of self-identification switching, comprising a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein:

[0006] The clamping test circuit comprises an IC clamping seat J2, a gate connection end (T7 / T10), a drain connection end (T8 / T11) and a source connection end (T9 / T12), the gate connection end, the drain connection end and the source connection end are source table test ports, the IC clamping seat is used for placing a chip to be detected, and the gate connection end, the drain connection end and the source connection end are connected with a source table respectively;

[0007] The channel selection circuit comprises relays K1, K2, K3, K4 and K5, the control circuit comprises a controller U2, the DAC output circuit comprises a relay K6, the ADC sampling circuit comprises a relay K7, one path of the drain connection end is electrically connected with a 2 pin of the relay K4 and another path is electrically connected with a 1 pin of the relay K7;

[0008] One path of the source connection end is electrically connected with a 1 pin of the relay K3, a 2 pin of the relay K3 is electrically connected with a 1 pin of the IC clamping seat J2, and a 3 pin of the relay K3 is electrically connected with a 5 pin of the IC clamping seat J2; another path of the source connection end is electrically connected with a 2 pin of the relay K5;

[0009] One path of the gate connection end is electrically connected with a 1 pin of the relay K1, a 2 pin of the relay K1 is electrically connected with a 28 pin of the IC clamping seat J2, and a 3 pin of the relay K1 is electrically connected with a 3 pin of the IC clamping seat J2; another path of the gate connection end is electrically connected with a 1 pin of the relay K6.

[0010] As a further preferred technical solution of the above technical solution, a 4 pin of the relay K1 is electrically connected with a collector of a triode Q1, a base of the triode Q1 is electrically connected with a 46 pin of the controller U2 through a resistor R1;

[0011] A 4 pin of the relay K2 is electrically connected with a collector of a triode Q2, a base of the triode Q2 is electrically connected with a 49 pin of the controller U2 through a resistor R4; a 1 pin of the relay K2 is electrically connected with a 26 pin of the IC clamping seat J2;

[0012] A 4 pin of the relay K3 is electrically connected with a collector of a triode Q3, a base of the triode Q3 is electrically connected with a 50 pin of the controller U2 through a resistor R7;

[0013] The 4-pin of the relay K4 is electrically connected with the collector of the transistor Q6, the base of the transistor Q6 is electrically connected with the 22-pin of the controller U2 through the resistor R15;

[0014] The 4-pin of the relay K5 is electrically connected with the collector of the transistor Q7, the base of the transistor Q7 is electrically connected with the 23-pin of the controller U2 through the resistor R18.

[0015] As a further preferred technical solution of the above technical solution, the 4-pin of the relay K6 is electrically connected with the collector of the transistor Q8, the base of the transistor Q8 is electrically connected with the 41-pin of the controller U2 through the resistor R21;

[0016] The 2-pin of the relay K6 is respectively connected with the emitter of the transistor Q4 and the collector of the transistor Q5 through the resistor R14, the base of the transistor Q4 and the base of the transistor Q5 are both connected with the output end of the operational amplifier U3 through the resistor R13, the positive input end of the operational amplifier U3 is electrically connected with the 20-pin of the controller U2.

[0017] As a further preferred technical solution of the above technical solution, the 2-pin of the relay K7 is grounded through the resistor R28 in one way and is electrically connected with the 14-pin of the controller U2 in another way;

[0018] The 4-pin of the relay K7 is electrically connected with the collector of the transistor Q9, the base of the transistor Q9 is electrically connected with the 42-pin of the controller U2 through the resistor R25.

[0019] As a further preferred technical solution of the above technical solution, the relays K1-K3 are single-pole double-throw switches, which are used for selecting the path of the source table connected to the chip;

[0020] The relays K4-K7 are single-pole single-throw switches, which are used for detecting the gate position.

[0021] As a further preferred technical solution of the above technical solution, when the chip is tested after being inserted into the IC clamping seat J2, the test is implemented by the following steps:

[0022] Step S1: detecting the gate position, making the relays K4-K7 all closed through the control circuit, and the relays K1-K3 are in the first position;

[0023] Step S2: the DAC output circuit works, after voltage following and amplification, through the relays K6 and K1, it is loaded to the Gate1 position (28-pin) of the IC clamping seat (DIP28);

[0024] Step S3: the ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct preset value (0.7V), it indicates that the initial position of the test chip inserted into the IC clamping seat is correct (i.e. the gate position of the test chip is inserted into the Gate1 position) and the gate detection of the test chip is qualified, and then step S7 is executed. If the voltage collected by the ADC is greater than the fault threshold value (2V+), it indicates that the position of the current test chip inserted into the IC clamping seat is incorrect (i.e. the gate position of the test chip is not in the Gate1 position but in the Gate2 position) or (when the gate position Gate1 is correct) the test chip is damaged, and then step S4 is executed.

[0025] Step S4: the DAC output circuit is closed by the control circuit, and the relays K1-K3 are switched to the second position.

[0026] Step S5: the DAC output circuit works, and after voltage following and amplification, it is loaded into the Gate2 position (3 pins) of the IC clamping seat (DIP28) through the relays K6 and K1.

[0027] Step S6: the ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct threshold value, it indicates that the gate position of the test chip is the Gate2 position and the gate detection of the test chip is qualified, and then step S7 is continued. If the voltage collected by the ADC is still greater than the fault threshold value, it indicates that the test chip is damaged.

[0028] Step S7: the DAC output circuit is closed, the relays K4-K7 are all disconnected, and the I-V test program in the source table is executed (i.e. the I-V test of the test chip is performed in the source table).

[0029] As a further preferred technical solution of the above technical solution, when the relays K1-K3 are in the first position, the 1 pin and the 2 pin of the relay K1 are connected, the 1 pin and the 2 pin of the relay K2 are connected, and the 1 pin and the 2 pin of the relay K3 are connected. The Source2 (5 pins) and the Gate2 (3 pins) of the IC clamping seat J2 (DIP28) are suspended, the Source1 (1 pin) and the B end (26 pins) are short-circuited and connected to the source connection end (T9, T12), the Drain (22 pins) is connected to the drain connection end, and the Gate1 (28 pins) is connected to the gate connection end.

[0030] When the relays K1-K3 are switched to the second position, the 1st and 3rd pins of the relay K1 are connected, the 1st and 3rd pins of the relay K2 are connected, the 1st and 3rd pins of the relay K3 are connected; the Source 1 and Gate 1 of the IC clamp J2 (DIP28) are left open, the Gate 2 and B are short-circuited and connected to the gate connection end, the Drain is connected to the drain connection end, and the Source 2 is connected to the source connection end.

[0031] As a further preferred technical solution of the above technical solution, when the gate of the test chip is aligned with the Gate 1 or Gate 2 of the IC clamp J2 (DIP28), that is, the gate of the test chip is loaded with an opening voltage, the test chip is turned on, the drain of the test chip (connected with the 22nd pin of J2) is pulled to a low level, and the voltage collected by the ADC collection circuit is the junction voltage of the test chip, which is less than the correct preset value. When the collected voltage is greater than the fault threshold (2.3V), it indicates that the test chip does not have a conduction phenomenon (damage). BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a device packaging schematic diagram of a Testkey.

[0033] Figure 2 is a device packaging schematic diagram of two Testkeys.

[0034] Figure 3 is a structural schematic diagram of the present application.

[0035] Figure 4 is a clamp test circuit diagram of the present application.

[0036] Figure 5 is a control circuit diagram of the present application.

[0037] Figure 6 is a DAC output circuit diagram of the present application.

[0038] Figure 7 is an ADC sampling circuit diagram of the present application.

[0039] Figure 8 is a channel selection circuit diagram of the present application. DETAILED DESCRIPTION

[0040] The following description is used to disclose the present application so that those skilled in the art can implement the present application. The preferred embodiments in the following description are only used as examples, and other obvious modifications can be thought of by those skilled in the art. The basic principles of the present application defined in the following description can be applied to other embodiments, modifications, improvements, equivalents and other technical solutions without departing from the spirit and scope of the present application.

[0041] The application discloses a DIP type packaged device test device capable of self-identification switching, and further describes the specific embodiments of the application in combination with preferred embodiments.

[0042] In the embodiments of the application, the skilled in the art should note that the chip and the source table and the like involved in the application can be regarded as prior art.

[0043] Preferred embodiments.

[0044] As Figures 1-8 shown, the application discloses a DIP type packaged device test device capable of self-identification switching, comprising a clamping test circuit, a control circuit, a DAC output circuit, an ADC sampling circuit and a channel selection circuit, wherein:

[0045] The clamping test circuit comprises an IC clamping seat J2, a gate connection end (T7 / T10), a drain connection end (T8 / T11) and a source connection end (T9 / T12), the IC clamping seat is used for placing a chip to be detected, and the gate connection end, the drain connection end and the source connection end are respectively connected with a source table (providing a test voltage and testing a leakage current of the chip);

[0046] The channel selection circuit comprises relays K1, K2, K3, K4 and K5, the control circuit comprises a controller U2 (MCU), the DAC output circuit comprises a relay K6, the ADC sampling circuit comprises a relay K7, one way of the drain connection end is electrically connected with a 2 pin of the relay K4, and another way is electrically connected with a 1 pin of the relay K7;

[0047] One way of the source connection end is electrically connected with a 1 pin of the relay K3, a 2 pin of the relay K3 is electrically connected with a 1 pin of the IC clamping seat J2, and a 3 pin of the relay K3 is electrically connected with a 5 pin of the IC clamping seat J2; another way of the source connection end is electrically connected with a 2 pin of the relay K5;

[0048] One way of the gate connection end is electrically connected with a 1 pin of the relay K1, a 2 pin of the relay K1 is electrically connected with a 28 pin of the IC clamping seat J2, and a 3 pin of the relay K1 is electrically connected with a 3 pin of the IC clamping seat J2; another way of the gate connection end is electrically connected with a 1 pin of the relay K6.

[0049] Specifically, a 4 pin of the relay K1 is electrically connected with a collector of a triode Q1, a base of the triode Q1 is electrically connected with a 46 pin of the controller U2 through a resistor R1;

[0050] The 4th pin of the relay K2 is electrically connected to the collector of the transistor Q2, and the base of the transistor Q2 is electrically connected to the 49th pin of the controller U2 through the resistor R4; the 1st pin of the relay K2 is electrically connected to the 26th pin of the IC clamping seat J2.

[0051] The 4th pin of the relay K3 is electrically connected to the collector of the transistor Q3, and the base of the transistor Q3 is electrically connected to the 50th pin of the controller U2 through the resistor R7.

[0052] The 4th pin of the relay K4 is electrically connected to the collector of the transistor Q6, and the base of the transistor Q6 is electrically connected to the 22nd pin of the controller U2 through the resistor R15.

[0053] The 4th pin of the relay K5 is electrically connected to the collector of the transistor Q7, and the base of the transistor Q7 is electrically connected to the 23rd pin of the controller U2 through the resistor R18.

[0054] More specifically, pin 4 of the relay K6 is electrically connected to the collector of the transistor Q8, and the base of the transistor Q8 is electrically connected to pin 41 of the controller U2 through resistor R21.

[0055] Pin 2 of relay K6 is connected to the emitter of transistor Q4 and the collector of transistor Q5 via resistor R14. The bases of transistors Q4 and Q5 are both connected to the output of operational amplifier U3 via resistor R13. The positive input of operational amplifier U3 is electrically connected to pin 20 of controller U2.

[0056] Furthermore, pin 2 of the relay K7 is grounded through resistor R28 and electrically connected to pin 14 of the controller U2 through another path.

[0057] The 4th pin of the relay K7 is electrically connected to the collector of the transistor Q9, and the base of the transistor Q9 is electrically connected to the 42nd pin of the controller U2 through the resistor R25.

[0058] Furthermore, relays K1-K3 are single-pole double-throw switches used to select the path from which the source meter is connected to the chip;

[0059] Relays K4-K7 are single-pole single-throw switches used for gate position detection.

[0060] Preferably, the test is performed after the test chip is inserted into the IC clamping socket J2, and the test is specifically implemented in the following steps:

[0061] Step S1: Perform gate position detection. The control circuit makes all relays K4-K7 close, and relays K1-K3 are in the first position.

[0062] Step S2: The DAC output circuit operates. After voltage follower and amplification, it is applied to the Gate1 position (pin 28) of the IC clamping socket (DIP28) through relays K6 and K1.

[0063] Step S3: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct preset value (0.7V), it means that the initial position of the test chip inserted into the IC clamp is correct (i.e., the gate position of the test chip is exactly inserted into the Gate1 position) and the gate detection of the test chip is qualified. Then proceed to step S7. If the voltage collected by the ADC is greater than the fault threshold (2V+), it means that the current position of the test chip inserted into the IC clamp is incorrect (i.e., the gate position of the test chip is not in the Gate1 position, but in the Gate2 position) or (when the gate position Gate1 is correct) the test chip is damaged. Then proceed to step S4.

[0064] Step S4: The DAC output circuit is turned off by the control circuit, and relays K1-K3 are switched to the second position;

[0065] Step S5: The DAC output circuit operates. After voltage follower and amplification, it is applied to the Gate2 position (pin 3) of the IC clamping socket (DIP28) through relays K6 and K1.

[0066] Step S6: The ADC sampling circuit samples the drain of the test chip. If the voltage collected by the ADC is less than the correct threshold, it means that the gate position of the test chip is Gate2 and the gate detection of the test chip is qualified. Continue to execute step S7. If the voltage collected by the ADC is still greater than the fault threshold, it indicates that the test chip is damaged.

[0067] Step S7: The DAC output circuit is turned off, all relays K4-K7 are disconnected, and the IV test program in the source meter is executed (i.e., the IV test of the test chip is performed in the source meter).

[0068] Preferably, when relays K1-K3 are in the first position, pins 1 and 2 of relay K1 are connected, pins 1 and 2 of relay K2 are connected, and pins 1 and 2 of relay K3 are connected; Source2 (pin 5) and Gate2 (pin 3) of IC clamping seat J2 (DIP28) are left floating, Source1 (pin 1) and B terminal (pin 26) are short-circuited and connected to the source connection terminal (T9, T12), Drain (pin 22) is connected to the drain connection terminal, and Gate1 (pin 28) is connected to the gate connection terminal;

[0069] When relays K1-K3 are switched to the second position, pins 1 and 3 of relay K1 are connected, pins 1 and 3 of relay K2 are connected, and pins 1 and 3 of relay K3 are connected; Source1 and Gate1 of IC clamping seat J2 (DIP28) are left floating, Gate2 and B terminal are short-circuited and connected to the gate connection terminal, Drain is connected to the drain connection terminal, and Source2 is connected to the source connection terminal.

[0070] Preferably, when the gate position of the test chip is aligned with Gate1 or Gate2 of IC clamping seat J2 (DIP28), that is, the gate of the test chip is loaded with an enable voltage, the test chip will be turned on, the drain of the test chip (connected to pin 22 of J2) will be pulled low, and the voltage collected by the ADC acquisition circuit is the junction voltage of the test chip. The value is less than the correct preset value. When the collected voltage is greater than the fault threshold (2.3V), it indicates that the test chip is not conducting (damaged).

[0071] For the present invention:

[0072] Before applying the test voltage to the source table, the fixture (T7-T12) of this invention first applies a conduction voltage to the pins where the gate (G) position may exist. When the gate voltage VGS is greater than VGS(th), the device under test (DUT) will be in a conducting state. By detecting the drain voltage using an ADC, the correct gate position of the IC can be determined, thereby identifying which Testkey structure the device belongs to. If the DUT does not detect conduction after the conduction voltage is applied, a channel selection circuit is provided to switch the connection route of the fixture until it is confirmed that the DUT can detect conduction when the gate voltage VGS is greater than VGS(th). At this point, the fixture issues an indication signal indicating that the currently selected connection route is compatible with the wiring required by the current DUT. Finally, the tester operates the source table to load the test program. The fixture, which uses a gate detection circuit and an automatic switching circuit, greatly reduces the tediousness of testing two structures within the same package and lowers the various risks associated with manually distinguishing chips. It can automatically identify and complete the IV electrical performance testing of two structures.

[0073] This invention tests two chips with different gate packages. Both chips share the same drain pin. Two wires are led out from the drain connection: one end is connected to a 5V high level via relay K4, and the other end is connected to the ADC sampling circuit via relay K7. The chip's source pin has two position options, designated Source1 and Source2 on the IC clamping socket (DIP28). Two wires are led out from the source connection: one connects to the two possible Source positions (Source1, Source2) in the DIP28 via relay K3, and the other end is connected to the MCU ground via relay K5. The chip's gate pin also has two position options, designated Gate1 and Gate2 on the IC clamping socket (DIP28). Two wires are led out from the gate connection: one connects to the two possible Gate positions (Source1, Source2) in the IC clamping socket (DIP28) via relay K1, and the last wire connects to the DAC output circuit via relay K6. Relays K1-K3 are single-pole double-throw switches used to select the path from which the source meter connects to the chip. Relays K4-K7 are single-pole single-throw switches used for gate position detection.

[0074] It is worth mentioning that the technical features such as chips and source meters involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0075] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A self-identifying, switched DIP-type package device test apparatus, characterized by, It comprises clamping test circuit, control circuit, DAC output circuit, ADC sampling circuit and channel selection circuit, wherein: The clamping test circuit comprises IC clamping seat J2, gate connection end, drain connection end and source connection end, the IC clamping seat is used for placing the chip to be detected, and the gate connection end, the drain connection end and the source connection end are connected with the source table respectively; The channel selection circuit comprises relays K1, K2, K3, K4 and K5, the control circuit comprises controller U2, the DAC output circuit comprises relay K6, the ADC sampling circuit comprises relay K7, one way of the drain connection end is electrically connected with the 2 pin of the relay K4 and the other way is electrically connected with the 1 pin of the relay K7; One way of the source connection end is electrically connected with the 1 pin of the relay K3, the 2 pin of the relay K3 is electrically connected with the 1 pin of the IC clamping seat J2 and the 3 pin of the relay K3 is electrically connected with the 5 pin of the IC clamping seat J2; the other way of the source connection end is electrically connected with the 2 pin of the relay K5; One way of the gate connection end is electrically connected with the 1 pin of the relay K1, the 2 pin of the relay K1 is electrically connected with the 28 pin of the IC clamping seat J2 and the 3 pin of the relay K1 is electrically connected with the 3 pin of the IC clamping seat J2; the other way of the gate connection end is electrically connected with the 1 pin of the relay K6.

2. A self-identifying switched DIP-type package device test apparatus as claimed in claim 1, wherein, The 4 pin of the relay K1 is electrically connected with the collector of the triode Q1, the base of the triode Q1 is electrically connected with the 46 pin of the controller U2 through the resistance R1; The 4 pin of the relay K2 is electrically connected with the collector of the triode Q2, the base of the triode Q2 is electrically connected with the 49 pin of the controller U2 through the resistance R4; the 1 pin of the relay K2 is electrically connected with the 26 pin of the IC clamping seat J2; The 4 pin of the relay K3 is electrically connected with the collector of the triode Q3, the base of the triode Q3 is electrically connected with the 50 pin of the controller U2 through the resistance R7; The 4 pin of the relay K4 is electrically connected with the collector of the triode Q6, the base of the triode Q6 is electrically connected with the 22 pin of the controller U2 through the resistance R15; The 4 pin of the relay K5 is electrically connected with the collector of the triode Q7, the base of the triode Q7 is electrically connected with the 23 pin of the controller U2 through the resistance R18.

3. A self-identifying, switched DIP-type package device test apparatus as defined in claim 2, wherein, The 4 pin of the relay K6 is electrically connected with the collector of the triode Q8, the base of the triode Q8 is electrically connected with the 41 pin of the controller U2 through the resistance R21; The 2 pin of the relay K6 is connected with the emitter of the triode Q4 and the collector of the triode Q5 respectively through the resistance R14, the base of the triode Q4 and the base of the triode Q5 are connected with the output end of the operational amplifier U3 through the resistance R13, the positive input end of the operational amplifier U3 is electrically connected with the 20 pin of the controller U2.

4. A DIP-type package self-identifying switching device test apparatus according to claim 3, wherein The 2-pin of the relay K7 is connected to ground through the resistor R28 and connected to the 14-pin of the controller U2; The 4-pin of the relay K7 is connected to the collector of the transistor Q9, and the base of the transistor Q9 is connected to the 42-pin of the controller U2 through the resistor R25.

5. A DIP-type package self-identifying switching device test apparatus according to claim 4, wherein The relays K1-K3 are single-pole double-throw switches, which are used to select the path of the source table connected to the chip. The relays K4-K7 are single-pole single-throw switches, which are used for the detection of the gate position.

6. A DIP-type package self-identifying switching device test apparatus according to claim 5, wherein, When the test chip is inserted into the IC clamping seat J2, the test is implemented as follows: Step S1: The gate position detection is performed, and the relays K4-K7 are all closed by the control circuit, and the relays K1-K3 are in the first position; Step S2: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate1 position of the IC clamping seat through the relays K6 and K1; Step S3: The ADC sampling circuit samples the drain of the test chip, and if the voltage collected by the ADC is less than the correct preset value, it indicates that the initial position of the test chip inserted into the IC clamping seat is correct and the gate detection of the test chip is qualified, and then step S7 is executed, and if the voltage collected by the ADC is greater than the fault threshold, it indicates that the position of the test chip inserted into the IC clamping seat is incorrect or the test chip is damaged, and then step S4 is executed; Step S4: The DAC output circuit is closed by the control circuit, and the relays K1-K3 are switched to the second position; Step S5: The DAC output circuit works, and after voltage following and amplification, it is loaded to the Gate2 position of the IC clamping seat through the relays K6 and K1; Step S6: The ADC sampling circuit samples the drain of the test chip, and if the voltage collected by the ADC is less than the correct threshold, it indicates that the gate position of the test chip is Gate2 position and the gate detection of the test chip is qualified, and then step S7 is continued to be executed, and if the voltage collected by the ADC is still greater than the fault threshold, it indicates that the test chip is damaged; Step S7: The DAC output circuit is closed, the relays K4-K7 are all disconnected, and the I-V test program of the source table is executed.

7. The self-identification switching DIP type package device test device according to claim 6, wherein when the relays K1-K3 are in the first position, the 1-pin and the 2-pin of the relay K1 are connected, the 1-pin and the 2-pin of the relay K2 are connected, and the 1-pin and the 2-pin of the relay K3 are connected; the Source2 and the Gate2 of the IC clamping seat J2 are left hanging, the Source1 and the B end are short-circuited and connected to the source connection end, the Drain is connected to the drain connection end, and the Gate1 is connected to the gate connection end. For the relay K1-K3 switch to the second position, the 1 pin and 3 pin of the relay K1 are connected, the 1 pin and 3 pin of the relay K2 are connected, the 1 pin and 3 pin of the relay K3 are connected; the Source1 and Gate1 of the IC clamp J2 are suspended, the Gate2 and B end are short-circuited and connected to the gate connection end, the Drain is connected to the drain connection end, and the Source2 is connected to the source connection end.

8. The self-identification switching DIP type package device test device according to claim 7, when the gate position of the test chip is aligned with the Gate1 or Gate2 of the IC clamp J2, that is, the gate of the test chip is loaded with an opening voltage, the test chip is turned on, the drain of the test chip is pulled to a low level, and the voltage collected by the ADC acquisition circuit is the junction voltage of the test chip, the value is less than the correct preset value, and when the collected voltage is greater than the fault threshold, it indicates that the test chip does not have the phenomenon of being turned on.

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