Optical proximity correction method and semiconductor manufacturing method using same

Abstract

The invention discloses an optical proximity correction method and a semiconductor manufacturing method using the same. The semiconductor manufacturing method comprises the following steps: performing optical proximity correction on a design pattern of a layout to generate a corrected layout; and forming a photoresist pattern on a substrate by using a photomask manufactured with the corrected layout. Performing the optical proximity correction includes: generating shape points on a contour of the design pattern; generating hash values of the shape points; selecting a first unique shape point representing the first shape point; determining a first correction bias for the first unique shape point; and creating a correction pattern by jointly applying the first correction bias to the first shape point. Generating the hash value includes: generating a query range around a target shape point; and generating the hash value based on a geometric analysis within the query range.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor manufacturing method, and more particularly, to an optical proximity correction (OPC) method and a semiconductor manufacturing method using the OPC method. Background Art

[0002] Semiconductor devices play an important role in the electronics industry due to their small size, multiple functions and / or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process operations on logic data, and hybrid semiconductor devices having both storage and logic elements. With the advanced development of the electronics industry, semiconductor devices have increasingly higher requirements for integration. For example, semiconductor devices have been increasingly required to have high reliability, high speed and / or multi-functions. In order to meet these required characteristics, semiconductor devices are gradually becoming more complex and more integrated. Summary of the invention

[0003] Some embodiments of the inventive concept provide an optical proximity correction (OPC) method capable of reducing time required for OPC.

[0004] Some embodiments of the inventive concept provide a method of fabricating a semiconductor device having increased integration and improved reliability.

[0005] According to some embodiments of the present inventive concept, a semiconductor manufacturing method may include: performing an optical proximity correction (OPC) step on a design pattern of a layout to generate a corrected layout; and forming a photoresist pattern on a substrate using a photomask manufactured using the corrected layout. The step of performing the OPC step may include: generating a plurality of shape points on the outline of the design pattern; generating a hash value for each of the plurality of shape points; selecting a first unique shape point from the plurality of shape points based on the hash value, wherein the first unique shape point represents a first shape point; calculating a first correction bias for the first unique shape point; and creating a correction pattern by applying the first correction bias to the first shape point together. The step of generating the hash value may include: generating a query range around a target shape point; and generating the hash value based on a geometric analysis within the query range.

[0006] According to some embodiments of the present invention, a semiconductor manufacturing method may include: dividing a layout into a plurality of patches; generating a plurality of shape points in the plurality of patches; selecting a unique shape point from the plurality of shape points; selecting a target patch from the plurality of patches, the target patch including the unique shape point; performing an optical proximity correction (OPC) step on the target patch to generate a corrected layout; and forming a photoresist pattern on a substrate using a photomask manufactured using the corrected layout.

[0007] According to some embodiments of the present inventive concept, an optical proximity correction method may include: performing a first optical proximity correction (OPC) step on a first layout; accumulating a first result of the first OPC step in an OPC library; selecting a unique block from blocks of a second layout, wherein the first result cannot be applied to the unique block; performing a second OPC step on the unique block; and accumulating a second result of the second OPC step in the OPC library. The first result may include a first correction offset for a first unique shape point in the first layout. The second result may include a second correction offset for a second unique shape point in the second layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example computer system for semiconductor design according to some embodiments of the inventive concept.

[0009] Figure 2 is a flowchart illustrating an example method of designing and fabricating a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 3 A conceptual diagram showing an example photolithography system using a manufactured photomask according to some embodiments of the inventive concept is illustrated.

[0011] Figure 4 is a simplified flow chart illustrating a detailed process of an example optical proximity correction method according to some embodiments of the inventive concept.

[0012] Figure 5 and Figure 6 is a top view showing an example design layout.

[0013] Figures 7 to 18 FIG. 1 is a diagram showing an optical proximity correction according to some embodiments of the present inventive concept. Figure 5 and Figure 6 An enlarged top view of region M of the example layout depicted in FIG.

[0014] Fig.19 is a top view illustrating a photomask according to some embodiments of the inventive concept.

[0015] Fig. 20 It is shown that by using Fig.19 A perspective view of a photomask forming an example photoresist pattern on a substrate.

[0016] Fig.21 is a simplified flow chart illustrating an example method of generating a library of OPC results according to some embodiments of the inventive concept.

[0017] Fig. 22 It shows that according to Fig.21 A block diagram of an example process.

[0018] Fig.23 and Fig.25 is a top view illustrating an example semiconductor fabrication method according to some embodiments of the inventive concept.

[0019] Fig.24A , Fig. 24B , Fig.24C and Fig.24D are respectively along Fig.23 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0020] Fig.26A , Fig.26B , Fig.26C and Fig.26D are respectively along Fig.25 Cross-sectional views taken along lines AA', BB', CC' and DD'. DETAILED DESCRIPTION

[0021] Illustrative embodiments of the inventive concepts will herein be described with reference to the accompanying drawings, wherein like reference numerals, when used, refer to corresponding elements throughout the several views.

[0022] Figure 1 FIG. 1 is a block diagram of an example computer system for semiconductor design according to some embodiments of the inventive concept. Figure 1 The computer system may include a central processing unit (CPU) 10, a working memory 30, an input / output (I / O) device 50, and an auxiliary storage device 70 (e.g., a non-transitory storage medium). The computer system may be provided as a dedicated device for designing layouts of the present invention. The computer system may be configured to drive various design and verification simulation programs.

[0023] The CPU 10 may be configured to enable the computer system to run software (e.g., application programs, operating systems, and device drivers). The CPU 10 may process (i.e., run) an operating system loaded in a working memory 30. The CPU 10 may run various application programs driven by an operating system (OS). For example, the CPU 10 may process a layout design tool 32 and / or an optical proximity correction (OPC) tool 34 loaded in the working memory 30.

[0024] An operating system (OS) or an application program may be loaded into the working memory 30. When the computer system is started, an operating system image (not shown) stored in the auxiliary storage device 70 may be loaded into the working memory 30 based on the boot sequence. The overall input / output operation of the computer system may be supported by the operating system (OS). The working memory 30 may be loaded with an application program selected by a user or provided for basic services. The layout design tool 32 and / or the OPC tool 34 may be loaded from the auxiliary storage device 70 into the working memory 30.

[0025] The layout design tool 32 may include a bias function configured to generate changed bias data, by which a specific layout pattern is changed in shape and / or position defined by a design rule. In addition, the layout design tool 32 may perform a design rule check (DRC) under the changed bias data condition. The OPC tool 34 may perform an optical proximity correction (OPC) on the layout data output from the layout design tool 32. The working memory 30 may be a volatile memory such as a static random access memory (SRAM) and a dynamic random access memory (DRAM), or a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), and a NOR flash memory.

[0026] The input / output device 50 can control the user input / output operation of the user interface. For example, the input / output device 50 can include a keyboard or a monitor so that the designer can enter relevant information. The user can use the input / output device 50 to receive information about the semiconductor area or data path that needs to adjust the operating characteristics. The input / output device 50 can display the progress status or process results of the OPC tool 34.

[0027] The auxiliary storage device 70 can be used as a non-temporary storage medium of the computer system. The auxiliary storage device 70 can store application programs, operating system images, and various data. The auxiliary storage device 70 can be provided in the form of, for example, a memory card (e.g., a multimedia card (MMC), an embedded multimedia card (eMMC), a secure digital (SD) card, and a micro SD card) and a hard disk drive (HDD). The auxiliary storage device 70 may include a NAND flash memory with a large storage capacity. Alternatively, the auxiliary storage device 70 may include a NOR flash memory or a next-generation volatile memory such as PRAM, MRAM, ReRAM, and FRAM.

[0028] The system interconnector 90 may be provided to be used as a system bus for providing a network in a computer system. The CPU 10, the working memory 30, the input / output device 50, and the auxiliary storage device 70 may be electrically connected through the system interconnector 90, and may exchange data with each other. The system interconnector 90 is not limited to the above description, and may also include an intermediate means for efficient management. The system interconnector 90 may be wired, wireless, or a hybrid combination of wired and wireless.

[0029] Figure 2 is a flowchart illustrating an example method of designing and manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 2 , you can use, for example, reference Figure 1 The computer system discussed is used to perform high-level design (S10) of a semiconductor integrated circuit. High-level design may mean that the integrated circuit corresponding to the design target is described in a high-level language of a hardware description language (HDL). For example, a high-level language such as C language may be used in the high-level design. Register transfer level (RTL) coding or simulation may be used to express the circuit designed by the high-level design in detail. In addition, the code created by the register transfer level coding may be converted into a netlist, which may be synthesized to describe the entire semiconductor device. The synthesized schematic circuit may be verified by a simulation tool, and an adjustment process may be performed based on the results of the verification.

[0030] Layout design can be performed to implement a logically completed semiconductor integrated circuit (S20) on a silicon substrate. For example, a layout design step can be performed based on a principle circuit synthesized in a high-level design step or a netlist corresponding to the principle circuit. The layout design step can include a wiring step for placing and connecting various standard cells provided from a cell library based on a prescribed design rule (e.g., a place-and-route process). The place-and-route process places each cell from the synthesized netlist into an available area on a target silicon substrate and uses the available wiring resources on the target silicon substrate to generate the interconnection of the cell.

[0031] The cell library for layout design can include information about the operation, speed and power consumption of standard cells. A cell library for representing the layout of a specific gate-level circuit as a layout can be defined in a layout design tool. The layout can be prepared to define the shape or size of the pattern of transistors and metal lines that will actually be formed on the silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, it may be necessary to properly place or describe the layout pattern such as PMOS, NMOS, N well, gate electrode and metal line thereon. To this end, a search can be first performed to select one of the predefined suitable inverters in the cell library.

[0032] Thereafter, a routing step may be performed to connect the selected and provided standard cells. Specifically, a routing step may be performed to connect the selected and placed standard cells to their overlying lines. The standard cells may be carefully designed to be connected to each other through the routing step. A series of these steps may be performed automatically or manually in a layout design tool. The steps of placing and routing the standard cells may be automatically performed by an additional placement and routing tool.

[0033] After the routing step, a verification step may be performed on the layout to check whether any part of the schematic circuit violates a given design rule of a specific manufacturing process. The verification step may include a design rule check (DRC) for verifying whether the layout satisfies a given design rule, an electrical rule check (ERC) for verifying whether there is an electrical disconnection or electrical short circuit problem in the layout, and a layout-to-principle relationship (LVS) for verifying whether the layout is consistent with the gate-level netlist.

[0034] A data preparation (DP) step may be performed to obtain mask data from a designed layout (S30). The data preparation step may include performing an optical proximity correction (OPC) step on the designed layout (S31) and performing a mask rule check (MRC) step on the OPC result (S32).

[0035] A photolithography process may be used to implement the layout pattern obtained by the layout design step on a silicon substrate. Optical proximity correction may be a technique for correcting unexpected optical effects that occur in a photolithography process or generally compensating for non-ideal behavior of light that may occur during a photolithography process. For example, optical proximity correction may correct for undesirable phenomena such as refraction, reflection, or process side effects caused by the characteristics of light in an exposure process using the layout pattern. When performing the optical proximity correction step, the designed layout pattern may be slightly changed (or offset) in shape and / or position.

[0036] MRC may be performed to verify whether the pattern modified by OPC satisfies a given design rule (S32). Patterns that do not satisfy the mask rule may be corrected to obtain a clean-up result such that each mask rule error is eliminated. The clean-up result may be obtained from the mask data that has undergone the data preparation step S30. Figures 4 to 11 , the data preparation step S30 according to the present inventive concept will be described in detail below.

[0037] The data preparation step S30 may be employed to generate a photomask (S40). The photomask may be generally manufactured by describing a layout pattern using a chrome layer coated on a glass substrate, but the embodiment is not limited thereto.

[0038] The generated photomask can be used to manufacture a semiconductor device (S50). Various exposure and etching processes can be repeatedly performed when using the photomask to manufacture a semiconductor device. Through these processes discussed above, the pattern defined in the layout design can be sequentially formed on the silicon substrate.

[0039] Figure 3 A conceptual diagram of a lithography system 1000 showing a photomask manufactured according to some embodiments of the inventive concept is illustrated. The lithography system 1000 may include a light source 1200, a photomask 1400, a reduction projection apparatus 1600, and a substrate stage 1800. The lithography system 1000 may also include Figure 3 For example, the lithography system 1000 may further include a sensor for measuring the height and the slope of the surface of the substrate SUB on the substrate stage 1800.

[0040] The light source 1200 may emit light. The light emitted from the light source 1200 may travel toward the photomask 1400. For example, a lens may be provided between the light source 1200 and the photomask 1400 to adjust the focus of the light. The light source 1200 may include an ultraviolet light source (e.g., a krypton fluoride (KrF) light source with a wavelength of 234 nanometers (nm), an argon fluoride (ArF) light source with a wavelength of 193nm) or an extreme ultraviolet (EUV) light source. The light source 1200 may include a single point light source P1, but the inventive concept is not limited thereto. In some embodiments, the light source 1200 may include a plurality of point light sources.

[0041] The photomask 1400 may include an image pattern for printing (realizing) a designed layout on the substrate SUB. The image pattern may be based on the data preparation steps discussed above ( Figure 2 The image pattern may be defined by transparent areas and opaque areas. The transparent areas may be formed by etching a metal layer (e.g., a chrome layer) on the photomask 1400. The transparent areas may be transparent to the light emitted from the light source 1200. In contrast, the opaque areas may block light without allowing light to pass through them.

[0042] The reduced projection device 1600 may receive light that passes through the transparent area of ​​the photomask 1400. The reduced projection device 1600 may match a layout pattern to be printed on the substrate SUB with the image pattern of the photomask 1400. The substrate SUB may be irradiated with the light that passes through the reduced projection device 1600. Therefore, a pattern corresponding to the image pattern of the photomask 1400 may be printed on the substrate SUB.

[0043] The substrate stage 1800 may support a substrate SUB. For example, the substrate SUB may include a silicon wafer. The reduced projection device 1600 may include an aperture. The aperture may be used to increase the depth of focus of ultraviolet light emitted from the light source 1200. For example, the aperture may include a dipole aperture or a quadruple aperture. The reduced projection device 1600 may also include a lens for adjusting the focus of light.

[0044] The increase in the integration of semiconductor devices can relatively reduce the distance between the image patterns of the photomask 1400. This "proximity" can induce interference and diffraction of light, and a distorted pattern can be printed on the substrate SUB. When a distorted pattern is printed on the substrate SUB, the designed circuit may work abnormally or not work at all.

[0045] Resolution enhancement techniques can be used to prevent pattern distortion. Optical proximity correction (see Figure 2S31) may be an example of a resolution enhancement technique. According to optical proximity correction, it may be possible to predict the degree of distortion such as interference and diffraction of light. Based on the predicted result, the designed layout may be changed (biased). Based on the changed layout, an image pattern may be formed on the photomask 1400, and then a desired pattern may be printed on the substrate SUB.

[0046] The layout of the semiconductor device may include multiple layers. For example, optical proximity correction may be performed to adjust the layout of a single layer. Specifically, optical proximity correction may be performed independently for each of the multiple layers. Multiple layers may be sequentially implemented on a substrate through a semiconductor process to form a semiconductor device. For example, a semiconductor device may include multiple stacked metal layers to implement a specific circuit.

[0047] Figure 4 is a simplified flowchart illustrating a detailed procedure of an example optical proximity correction process S31 according to some embodiments of the inventive concept. Figure 5 and Figure 6 is a top view showing an example design layout. Figures 7 to 18 FIG. 1 is a diagram showing an optical proximity correction according to some embodiments of the present inventive concept. Figure 5 and Figure 6 An enlarged top view of the region M depicted in FIG.

[0048] refer to Figure 4 , Figure 5 and Figure 7 , a layout LO generated by the layout design step S20 discussed above may be provided. The layout LO may be a single-layer layout. According to the neighboring environment and type of the unit device, the layout LO may be divided into a plurality of blocks (i.e., areas) PA. The blocks PA may be arranged two-dimensionally. For example, the blocks PA may have the same size relative to each other.

[0049] Multiple block PAs can be set accordingly in the OPC tool (see Figure 1 34) on multiple nodes. Figure 1 ) performs optical proximity correction (OPC) on multiple block PAs in parallel (ie, concurrently). Each block PA may be a basic unit on which optical proximity correction is performed.

[0050] A single block PA may include multiple design patterns LIP. For example, Figure 7 Depicted in Figure 5The region M of the design layout may include first to twelfth design patterns LIP1 to LIP12. According to the present embodiment, each of the first to twelfth design patterns LIP1 to LIP12 may be an island pattern. Each of the first to twelfth design patterns LIP1 to LIP12 may be in a quadrilateral shape. The first to twelfth design patterns LIP1 to LIP12 may be two-dimensionally arranged on the layout LO according to a first direction D1 and a second direction D2, which are parallel to the upper surface of the substrate SUB (i.e., horizontal) and intersect each other.

[0051] Figure 7 The shape of the designed layout LO shown may be an example to facilitate understanding of the inventive concept, but the inventive concept is not limited thereto. The layout LO may be provided as an initially designed layout. Figure 7 The illustrated first to twelfth design patterns LIP1 to LIP12 may express target patterns intended to be implemented (ie, formed) on the substrate SUB.

[0052] The data preparation step may be performed on the block PA including the first to twelfth design patterns LIP1 to LIP12 (see Figure 2 The data preparation step may include performing an optical proximity correction (OPC) step on the designed layout (see Figure 2 S31 of ) and performs a mask rule check (MRC) step on the OPC result (see Figure 2 S32).

[0053] refer to Figure 4 and Figure 8 , each of the first to twelfth design patterns LIP1 to LIP12 may be divided into a plurality of shape points SHP (S311). The shape points SHP may be generated on the outline of each of the first to twelfth design patterns LIP1 to LIP12. In an embodiment, the shape points SHP may be generated at regular intervals on each of the first to twelfth design patterns LIP1 to LIP12.

[0054] A hash value may be generated for each shape point SHP (S312). For example, a hash value may be generated for the first target point TSP1 or a shape point in the shape points SHP. A method of generating a hash value of a target point will be described below.

[0055] like Figure 8As shown, a first query range QR1 around the first target point TSP1 may be generated. For example, the first query range QR1 may be a peripheral area that can optically affect the first target point TSP1. The first query range QR1 may include not only the first target point TSP1 but also other shape points SHP around the first target point TSP1.

[0056] The hash value may be generated by geometric analysis within the first query range QR1. The geometric analysis may be performed based on information about the pattern image within the first query range QR1. For example, the information about the pattern image may include the number of shape points SHP around the first target point TSP1, the contour connecting the shape points SHP to each other, and the distance between the first target point TSP1 and the shape points SHP.

[0057] The hash value of the first target point TSP1 may be generated as a 64-bit unique value, but the implementation is not limited thereto. The hash value of the first target point TSP1 may be a hash ID of the first target point TSP1. For example, the hash value of the first target point TSP1 may be generated as a hash value 1.

[0058] refer to Figure 4 and Fig. 9 , a hash value of the second target point TSP2 can be generated (S312). A second query range QR2 around the second target point TSP2 can be created. The geometric analysis of the second query range QR2 can create a hash value of the second target point TSP2. According to the present embodiment, the second query range QR2 can have a pattern image that is the same as the pattern image of the first query range QR1. Therefore, the hash value of the second target point TSP2 can be generated as a hash value 1 that is the same as the hash value of the first target point TSP1.

[0059] refer to Figure 4 and Fig.10 , a hash value of the third target point TSP3 may be generated (S312). A third query range QR3 around the third target point TSP3 may be created. Geometric analysis of the third query range QR3 may create a hash value of the third target point TSP3. According to the present embodiment, the third query range QR3 may have a pattern image different from that of the first query range QR1. Therefore, the hash value of the third target point TSP3 may be generated as a hash value 2 different from the hash value of the first target point TSP1.

[0060] refer to Figure 4 and Fig.11 , a unique shape point USP may be selected based on the hash value of the shape point SHP (S313). A representative shape point in the shape point SHP having the same hash value may be selected as a unique shape point USP.

[0061] For example, Figure 8 The first target point TSP1 and Fig. 9 The second target point TSP2 may have the same value or hash value 1. Therefore, the first target point TSP1 representing one of the shape points SHP may be selected as the first unique shape point USP1. According to the present embodiment, seven unique shape points USP may be selected in the region M of the layout LO.

[0062] Fig.11 The unique shape points USP may include first to seventh unique shape points USP1 to USP7. The first to seventh unique shape points USP1 to USP7 may have their respective first to seventh hash values ​​#1 to #7 that are different from each other.

[0063] refer to Figure 4 and Figure 6 , a block including a unique shape point USP among the blocks PA can be selected as a target block TPA (S314). For example, seven blocks among twenty-five blocks PA can be selected as target blocks TPA. OPC can be performed only on the unique shape points USP in the seven target blocks TPA. The OPC conceived by the present invention may not be performed on all shape points SHP in all blocks PA. Since the OPC conceived by the present invention is selectively performed on the unique shape points in the target blocks, it is possible to maintain the consistency of the OPC and significantly reduce the time required to perform the OPC.

[0064] refer to Figure 4 and Fig.12 , OPC tools (see Figure 1 34) can be used to calculate a first bias BI1 (S315) to be applied to the first unique shape point USP1. The first bias BI1 may include information about the correction vector of the shape point. The first bias BI1 may include information about the moving direction (or angle) and moving distance (i.e., offset) of the shape point from the original position of the shape point.

[0065] When the OPC tool (see Figure 1 34) When performing OPC according to the present invention, the same correction bias may be applied to shape points SHP having the same hash value. The first bias BI1 may be commonly applied to first shape points SHP1 each having the same first hash value #1 as the hash value of the first unique shape point USP1. Therefore, the first shape point SHP1 may be biased (or changed) as much as the first bias BI1.

[0066] refer to Figure 4 and Fig.13 , OPC tools (see Figure 134) can be used to calculate a second bias BI2 to be applied to the second unique shape point USP2 (S315). The second bias BI2 can be commonly applied to the second shape points SHP2 each having the same second hash value #2 as the hash value of the second unique shape point USP2 (S316). Therefore, the second shape point SHP2 can be biased (or changed) as much as the second bias BI2. In an embodiment, the second bias BI2 can have the same Fig.12 The angle and distance of the first offset BI1 are different angles and distances.

[0067] refer to Figure 4 and Fig.14 , OPC tools (see Figure 1 34) can be used to calculate a third bias BI3 to be applied to the third unique shape point USP3 (S315). The third bias BI3 can be commonly applied to the third shape points SHP3 each having the same third hash value #3 as the hash value of the third unique shape point USP3 (S316). Therefore, the third shape point SHP3 can be biased (or changed) as much as the third bias BI3.

[0068] refer to Figure 4 and Fig.15 , OPC tools (see Figure 1 34) can be used to calculate a fourth bias BI4 to be applied to a fourth unique shape point USP4 (S315). The fourth bias BI4 can be commonly applied to fourth shape points SHP4 each having the same fourth hash value #4 as the hash value of the fourth unique shape point USP4 (S316). Therefore, the fourth shape point SHP4 can be biased (or changed) as much as the fourth bias BI4.

[0069] refer to Figure 4 and Fig.16 , OPC tools (see Figure 1 34) can be used to calculate the fifth bias BI5 to be applied to the fifth unique shape point USP5 (S315). The fifth bias BI5 can be commonly applied to the fifth shape points SHP5 each having the same fifth hash value #5 as the hash value of the fifth unique shape point USP5 (S316). Therefore, the fifth shape point SHP5 can be biased (or changed) as much as the fifth bias BI5.

[0070] refer to Figure 4 and Fig.17 , OPC tools (see Figure 134) can be used to calculate the sixth bias BI6 to be applied to the sixth unique shape point USP6 (S315). The sixth bias BI6 can be commonly applied to the sixth shape points SHP6 each having the same sixth hash value #6 as the hash value of the sixth unique shape point USP6 (S316). Therefore, the sixth shape point SHP6 can be biased (or changed) as much as the sixth bias BI6.

[0071] refer to Figure 4 and Fig.18 , OPC tools (see Figure 1 34) can be used to calculate the seventh bias BI7 to be applied to the seventh unique shape point USP7 (S315). The seventh bias BI7 can be commonly applied to the seventh shape points SHP7 each having the same seventh hash value #7 as the hash value of the seventh unique shape point USP7 (S316). Therefore, the seventh shape point SHP7 can be biased (or changed) as much as the seventh bias BI7.

[0072] Through the process discussed above, the correction bias can be applied to all shape points SHP. In the present invention, the correction bias may not be calculated and applied independently for each shape point SHP. When each shape point SHP is corrected independently, the time required to perform OPC may increase. According to some embodiments of the present invention, the correction bias of the unique shape point USP can be representatively calculated, and the correction bias can be commonly applied to the shape points SHP each having a hash value identical to the hash value of the unique shape point USP. Therefore, it may be possible to significantly reduce the time required to perform optical proximity correction.

[0073] The corrected shape points SHP may constitute a correction pattern COP. For example, the first to seventh design patterns LIP1 to LIP12 may be subjected to optical proximity correction to create first to twelfth correction patterns COP1 to COP12, respectively. Figure 6 However, the step of applying a correction bias to shape points each having the same hash value as the hash value of the unique shape point (S316) may be commonly applied to Figure 6 All blocks depicted in PA.

[0074] The OPC library may store correction biases BI1 to BI7 (S317) applied to the unique shape points USP1 to USP7 performed on the target block TPA. For example, the OPC results according to the unique hash values ​​of the unique shape points USP1 to USP7 may be stored in the OPC library in the form of a table. Thereafter, when the OPC step is performed on another layout, the results stored in the OPC library may be loaded into the other layout. Therefore, the efficiency of the OPC step may be improved.

[0075] When a correction pattern COP is generated for a design pattern LIP in a layout LO, a mask rule check (MRC) step may be performed on the created correction pattern COP (see Figure 2 The correction pattern COP may be additionally corrected by the MRC step, so that all mask rule violations may be resolved. Therefore, the data preparation step may be terminated, and the final result may be output as mask data.

[0076] Fig.19 is a top view showing an example photomask according to some embodiments of the inventive concept. Figure 2 and Fig.19 , a photomask 1400 (see FIG. 1400 ) may be manufactured based on the final correction pattern COP (eg, the first correction pattern COP1 to the twelfth correction pattern COP12 ). Figure 2 The photomask 1400 may include an image pattern IM. The image pattern IM may be formed based on the correction pattern COP in the layout LO discussed in this embodiment.

[0077] Fig. 20 is a conceptual illustration of the Fig.19 A three-dimensional image of a photomask forming a photoresist pattern on a substrate. Fig. 20 , Figure 3 The light source 1200 may emit light to the photomask 1400. The emitted light may pass through the transparent area of ​​the image pattern IM and then may proceed toward the photoresist layer PRL on the substrate SUB (exposure process). The area where the light is irradiated in the photoresist layer PRL may be converted into a photoresist pattern PRP. The photoresist pattern PRP may be formed to have the same Figure 7 The shape and size of the design pattern discussed in the LIP are similar in shape and size.

[0078] A development process may then be performed to leave the photoresist pattern PRP and remove the photoresist layer PRL. The remaining photoresist pattern PRP may be used as an etching mask to pattern the etching target layer TGL on the substrate SUB. Thus, a target pattern may be achieved on the substrate SUB. Thus, the aforementioned method may achieve a target pattern on each layer to manufacture a semiconductor device (see Figure 2 S50).

[0079] According to an embodiment of the present inventive concept, the patterning process for forming the photoresist pattern PRP may include an extreme ultraviolet (EUV) lithography process. The EUV lithography process may include an exposure and development process using extreme ultraviolet (EUV) radiation irradiated to the photoresist layer. For example, the photoresist layer may be an organic photoresist containing an organic polymer such as polyhydroxystyrene. The organic photoresist may also include a photosensitive compound that is sensitive to EUV. The organic photoresist may additionally include a material having a high EUV absorption coefficient, for example, an organic metal material, an iodine-containing material, or a fluorine-containing material. For another example, the photoresist layer may be an inorganic photoresist containing an inorganic material (such as tin oxide).

[0080] The photoresist layer may be formed relatively thin. The photoresist layer exposed to EUV may undergo a developing process to form a photoresist pattern. When viewed in a top view, the photoresist pattern may be in a line shape, an island shape, a zigzag shape, a honeycomb shape, or a circular shape extending in one direction, but the inventive concept is not limited to a specific example.

[0081] The photoresist pattern may be used as an etching mask to pattern one or more mask layers stacked under the photoresist pattern, thereby forming a mask pattern. The mask pattern may be used as an etching mask to pattern the etching target layer TGL to form a target pattern on the substrate SUB.

[0082] A value equal to or less than about 45 nm can be given as the minimum pitch between target patterns achieved by the EUV lithography process of the present embodiment. For example, an EUV lithography process in which only one photomask is sufficient to complete a complex and fine target pattern can be performed.

[0083] Fig.21 is a simplified flow chart illustrating an example method of generating a library of OPC results according to some embodiments of the inventive concept. Fig. 22 It shows that according to Fig.21 A conceptual block diagram of the example process.

[0084] refer to Fig.21 and Fig. 22 , through the above reference according to the present invention Figures 4 to 18 The first OPC process OPC1 discussed may store (or accumulate) a first OPC result PRT1 for the first unique shape point in the OPC library (S331). For example, the first OPC result PRT1 may include a table associated with a correction offset according to a unique hash value of the first unique shape point. Figure 5 All the blocks PA of the layout LO depicted in FIG. 1 perform a first OPC process OPC1.

[0085] A second OPC process OPC2 may be performed on the second layout. For example, the first OPC result PRT1 stored (or accumulated) in the OPC library may be loaded into the second layout. The second layout may include normal blocks having the first unique shape points included in the first OPC result PRT1 and unique blocks having new second unique shape points to which the first OPC result PRT1 cannot be applied. Because the second unique shape point has a different hash value from the first unique shape point, the first OPC result PRT1 cannot be applied to the unique block including the second unique shape point. Therefore, a process (S332) for searching and selecting a unique block therein may be first performed. In the present embodiment, the unique block may be similar to that described in reference above. Figure 4 and Figure 6 The target block TPA in step S314 is discussed.

[0086] A second OPC process OPC2 may be performed on the selected unique block. The second OPC process performed on the selected unique block may be the same as that described above with reference to Figures 4 to 18 The processes discussed are substantially the same.The second OPC process OPC2 may enable the OPC library to accumulate second OPC results PRT2 for second unique shape points (S333).

[0087] Thereafter, each time an additional OPC step is performed on an additional layout, steps S332 and S333 may be repeatedly performed. Thus, each time OPC is performed, OPC results may be continuously accumulated in the OPC library ( Fig. 22 PRT1 to PRT4).

[0088] In the OPC step according to some embodiments of the inventive concept, the design pattern may be divided into shape points, and the shape points may be corrected to create a free-form correction pattern. The accuracy of OPC may therefore be improved.

[0089] In the OPC step according to some embodiments of the inventive concept, unique shape points may be searched and selected, and OPC may be performed only on target blocks including unique shape points. Thus, it may be possible to maintain consistency of optical proximity correction and significantly reduce the time required to perform optical proximity correction.

[0090] In the OPC step according to some embodiments of the inventive concept, each time the OPC step is performed on multiple layouts, new OPC results can be accumulated in the OPC library. The generation of the OPC library can lead to improved efficiency of the OPC step and a gradual reduction in the time required to perform OPC.

[0091] Fig.23 and Fig.25A top view of a semiconductor manufacturing method according to some embodiments of the inventive concept is illustrated. Fig.24A , Fig. 24B , Fig.24C and Fig.24D are respectively along Fig.23 Cross-sectional views taken along lines AA', BB', CC' and DD'. Fig.26A , Fig.26B , Fig.26C and Fig.26D are respectively along Fig.25 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0092] refer to Fig.23 and FIG. 24A to FIG. 24D , a logic cell LC may be provided on the substrate SUB. The logic cell LC may include, for example, a logic transistor included in a logic circuit.

[0093] A first active pattern AP1 and a second active pattern AP2 may be formed on an upper portion of a substrate SUB. In an embodiment of the inventive concept, the first active pattern AP1 may be an NMOSFET region, and the second active pattern AP2 may be a PMOSFET region. The substrate SUB may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, or silicon germanium. For example, the substrate SUB may be a silicon substrate.

[0094] The formation of the first active pattern AP1 and the second active pattern AP2 may include forming a trench TR defining the first active pattern AP1 and the second active pattern AP2 on an upper portion of the substrate SUB. The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the first direction D1 across the trench TR. The first active pattern AP1 and the second active pattern AP2 may each be in the shape of a line extending in a second direction D2 intersecting the first direction D1. The device isolation layer ST may be formed to fill the trench TR. As may be used herein, the term "fill" (or "fill", "fill up" or similar terms) is intended to refer generally to completely filling a defined space (e.g., the trench TR) or partially filling a defined space; that is, the defined space does not have to be filled entirely, but may, for example, be partially filled or have gaps or other spaces everywhere. The device isolation layer ST may include a silicon oxide layer.

[0095] The formation of the first active pattern AP1 and the second active pattern AP2 may include forming a hard mask layer on the substrate SUB, forming a plurality of linear photoresist patterns on the hard mask layer, patterning the hard mask layer using the photoresist patterns as an etching mask, and etching the substrate SUB using the patterned hard mask layer as an etching mask. The photoresist patterns may be formed by using the above reference Fig.19 and Fig. 20 The photomask used to form the first active pattern AP1 and the second active pattern AP2 may be formed by the above-mentioned reference lithography process according to the inventive concept. Figures 4 to 18 The data preparation steps discussed (see Figure 2 S30).

[0096] A first channel pattern CH1 and a first source / drain pattern SD1 may be formed on the first active pattern AP1. Each of the first channel patterns CH1 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked in a third direction D3 perpendicular to the first direction D1 and the second direction D2, respectively. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0097] Each first source / drain pattern SD1 may include an impurity region having a first conductivity type (e.g., n-type). The first source / drain pattern SD1 may be an epitaxial pattern formed by a selective epitaxial growth process. For example, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as that of the substrate SUB.

[0098] A second channel pattern CH2 and a second source / drain pattern SD2 may be formed on the second active pattern AP2. Each second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 sequentially stacked along a third direction D3. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the third direction D3.

[0099] Each second source / drain pattern SD2 may include an impurity region having a second conductivity type (e.g., p-type). The second source / drain pattern SD2 may be an epitaxial pattern formed by a selective epitaxial growth process. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate SUB. Therefore, the second source / drain pattern SD2 may provide compressive stress to the second channel pattern CH2.

[0100] The gate electrode GE may be formed to extend in the first direction D1 while crossing the first and second active patterns AP1 and AP2. The gate electrode GE may be arranged at a regular pitch along the second direction D2. The gate electrode GE may vertically overlap the first and second channel patterns CH1 and CH2.

[0101] The gate electrode GE may be formed by the photolithography process discussed above according to the inventive concept. The photomask used to form the gate electrode GE may be formed by the photolithography process discussed above according to the inventive concept. Figures 4 to 18 The data preparation steps discussed (see Figure 2 S30).

[0102] The gate electrode GE may include a first internal electrode PO1 between the first semiconductor pattern SP1 and the active pattern AP1 or AP2, a second internal electrode PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3.

[0103] The gate electrode GE may surround the top surface TS, the bottom surface BS and the opposite sidewall SW of the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the third semiconductor pattern SP3. For example, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., an MBCFET or a GAAFET), in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2. The term "surrounding" (or "surrounding" or similar terms) as may be used herein is intended to refer generally to an element, structure or layer that extends, envelopes, surrounds or encapsulates another element, structure or layer around another element, structure or layer on all sides, but interruptions or gaps may also exist. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds.

[0104] A pair of gate spacers GS may be formed on opposite sidewalls of each gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. Relative to the upper surface of SUB, in a third direction D3, the top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer dielectric layer ILD1 to be discussed below. The gate spacer GS may include at least one selected from SiCN, SiCON, and SiN. Alternatively, the gate spacers GS may each include a plurality of layers formed of at least two materials selected from SiCN, SiCON, and SiN.

[0105] A gate capping pattern GP may be formed on each gate electrode GE. The gate capping pattern GP may extend in the first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to be discussed below. For example, the gate capping pattern GP may include at least one material selected from SiON, SiCN, SiCON, and SiN.

[0106] The gate dielectric layer GI may be formed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI may cover the top surface TS, the bottom surface BS, and the opposite sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 (see Fig.24D Unless specifically stated otherwise, the term "covering" (or "covered" or "covering" or similar terms) as may be used herein is intended to broadly refer to one material, layer or structure being on or over another material, layer or structure, but not requiring that the material, layer or structure entirely covers the other material, layer or structure.

[0107] In an embodiment of the present inventive concept, the gate dielectric layer GI may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0108] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI to form a first internal electrode PO1, a second internal electrode PO2, and a third internal electrode PO3. The first metal pattern may include a work function metal that controls a threshold voltage of the transistor. The thickness and composition of the first metal pattern may be adjusted to achieve a desired threshold voltage.

[0109] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0110] The outer electrode PO4 may include a first metal pattern and a second metal pattern. The second metal pattern may include a metal having a resistance less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0111] A first interlayer dielectric layer ILD1 may be formed on the substrate SUB. The first interlayer dielectric layer ILD1 may be formed to cover the gate spacer GS, the first source / drain pattern SD1, and the second source / drain pattern SD2. In the third direction D3, a top surface of the first interlayer dielectric layer ILD1 may be substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer ILD1 may be provided thereon with a second interlayer dielectric layer ILD2 formed to cover the gate capping pattern GP.

[0112] The pair of separation structures DB may be formed to face each other along the second direction D2 at opposite sides of the logic cell LC. The separation structure DB may extend in the first direction D1 in parallel with the gate electrode GE. The separation structure DB may penetrate the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2 (i.e., at least partially extend into the upper portion of each of the first active pattern AP1 and the second active pattern AP2). The separation structure DB may separate the active pattern of the logic cell LC from the active pattern of another logic cell adjacent to the logic cell LC.

[0113] The active contacts AC may be formed to penetrate the second dielectric layer ILD2 and the first interlayer dielectric layer ILD1 to be electrically connected with the first source / drain pattern SD1 and the second source / drain pattern SD2 . Each of the active contacts AC may be disposed between the pair of gate electrodes GE.

[0114] The active contact AC may be a self-aligned contact. For example, the gate capping pattern GP and the gate spacer GS may be used to form the active contact AC in a self-aligned manner. The active contact AC may cover, for example, at least a portion of the sidewall of the gate spacer GS. Although not explicitly shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

[0115] The formation of the active contact AC may include patterning the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 to form a contact hole, and filling the contact hole with a conductive material. For example, the active contact AC may be formed by using the photolithography process discussed above according to the inventive concept. The photomask used to form the active contact AC may be formed by using the photolithography process discussed above according to the inventive concept. Figures 4 to 18 The data preparation steps discussed (see Figure 2 S30).

[0116] A silicide pattern SC may be formed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide pattern SC. The silicide pattern SC may include a metal silicide, for example, at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0117] The gate contact GC may be formed to penetrate the second interlayer dielectric layer ILD2 and the gate capping pattern GP to be electrically connected to the gate electrode GE. Fig. 24B The active contact AC may have an upper portion adjacent to the gate contact GC, and an upper dielectric pattern UIP may be formed on the upper portion of the active contact AC. Therefore, a short circuit caused by contact between the gate contact GC and the adjacent active contact AC may be prevented from occurring.

[0118] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

[0119] refer to Fig.25 and FIG. 26A to FIG. 26D , a third interlayer dielectric layer ILD3 may be formed on the second interlayer dielectric layer ILD2. A first via VI1 may be formed in the third interlayer dielectric layer ILD3. A fourth interlayer dielectric layer ILD4 may be formed on the third interlayer dielectric layer ILD3. Wiring lines M1_R1, M1_R2, and M1_I may be formed in the fourth interlayer dielectric layer ILD4. The wiring lines M1_R1, M1_R2, and M1_I may include a first power line M1_R1, a second power line M1_R2, and a lower line M1_I.

[0120] Return to reference Fig.25, the first power line M1_R1 and the second power line M1_R2 may each extend in the second direction D2 while crossing the logic unit LC. A plurality of lower lines M1_I may be provided between the first power line M1_R1 and the second power line M1_R2. The plurality of lower lines M1_I may each be in a line shape or a strip shape extending in the second direction D2 and may be separated from each other in the first direction D1.

[0121] The first metal layer M1 may include wiring lines M1_R1, M1_R2, and M1_I and first vias VI1 thereunder. Each first via VI1 may be interposed between the wiring line and one of the active contact AC and the gate contact GC, and electrically connected to the wiring line and one of the active contact AC and the gate contact GC. Although not shown, metal layers M2, M3, M4, etc. may be additionally formed on the first metal layer M1.

[0122] The first via VI1 may be formed by using the photolithography process discussed above according to the present invention. For example, the photomask used to form the first via VI1 may be formed by using the photolithography process discussed above according to the present invention. Figures 4 to 18 The data preparation steps discussed (see Figure 2 S30).

[0123] The wiring lines M1_R1, M1_R2, and M1_I may be formed by using the photolithography process discussed above according to the inventive concept. For example, the photomask used to form the wiring lines M1_R1, M1_R2, and M1_I may be formed by using the photolithography process discussed above according to the inventive concept. Figures 4 to 18 The data preparation steps discussed (see Figure 2 S30).

[0124] In the OPC step according to the present invention, since the shape point is used to implement the free form correction pattern, the accuracy of the optical proximity correction (OPC) can be improved. In the OPC step according to the present invention, since the optical proximity correction (OPC) is selectively performed on the target block including the unique shape point, the consistency of the OPC can be maintained and the time required to perform the OPC can be significantly reduced. In the OPC step according to the present invention, the efficiency of the OPC can be improved by generating an OPC library.

[0125] Although some embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept. It should therefore be understood that the above embodiments are merely illustrative in all aspects and not restrictive.

Claims

1. A semiconductor manufacturing method, the semiconductor manufacturing method comprising: performing optical proximity correction on a design pattern of a semiconductor layout to generate a corrected layout; as well as forming a photoresist pattern on a substrate using a photomask manufactured using the corrected layout, Wherein, performing the optical proximity correction comprises: generating, by at least one processor, a plurality of shape points on an outline of the design pattern; generating a corresponding hash value for each of the plurality of shape points; selecting a first unique shape point from the plurality of shape points based on the corresponding hash values, wherein the first unique shape point represents a first shape point; determining a first correction offset for the first unique shape point; and creating a correction pattern by applying the first correction offsets collectively to the first shape points, Wherein, generating the corresponding hash value includes: generating a query range around a target shape point; and Based on the geometric analysis within the query range, the corresponding hash value is generated.

2. The semiconductor manufacturing method according to claim 1, wherein: The first shape point has a hash value that is the same as a hash value of the first unique shape point.

3. The semiconductor manufacturing method according to claim 1, wherein: The first correction offset includes a movement direction and a movement distance of the first shape point from a corresponding original position of the first shape point.

4. The semiconductor manufacturing method according to claim 1, wherein: Performing the optical proximity correction further comprises: selecting a second unique shape point from the plurality of shape points based on the corresponding hash values, wherein the second unique shape point represents a second shape point; calculating a second correction offset for the second unique shape point; and applying the second correction bias jointly to the second shape point, The second correction bias is different from the first correction bias.

5. The semiconductor manufacturing method according to claim 4, wherein: The first shape point has a first hash value, The second shape point has a second hash value, and The first hash value and the second hash value are different from each other.

6. The semiconductor manufacturing method according to claim 1, wherein: Performing the optical proximity correction further includes accumulating the first correction offset for the first unique shape point in an optical proximity correction library.

7. The semiconductor manufacturing method according to claim 1, wherein: The layout includes a plurality of blocks, and The optical proximity correction is selectively performed on a target block among the plurality of blocks, the target block including the first unique shape point.

8. The semiconductor manufacturing method according to claim 1, wherein: The design pattern has a polygonal shape formed by lines in a first direction and lines in a second direction, the first direction and the second direction are parallel to the upper surface of the substrate, the second direction intersects the first direction, and The calibration pattern is a free-form calibration pattern.

9. The semiconductor manufacturing method according to claim 1, further comprising: A mask rule checking step is performed on the corrected layout.

10. The semiconductor manufacturing method according to claim 1, further comprising: forming a transistor on the substrate; forming a contact electrically connected to the transistor; as well as forming a wiring line on the contact, The photoresist pattern defines a mask for forming the contact.

11. A semiconductor manufacturing method, the semiconductor manufacturing method comprising: The processor divides the layout into multiple blocks; generating, by the processor, a plurality of shape points in the plurality of blocks; selecting, by the processor, a unique shape point from the plurality of shape points; selecting, by the processor, a target block from the plurality of blocks, the target block including the unique shape point; performing, by the processor, optical proximity correction on the target block to generate a corrected layout; as well as A photoresist pattern is formed on a substrate using a photomask manufactured using the corrected layout.

12. The semiconductor manufacturing method according to claim 11, further comprising: determining a correction offset for the unique shape point using the optical proximity correction; as well as applying the correction bias to a first shape point among the plurality of shape points, Wherein, the first shape point has a hash value that is the same as a hash value of the unique shape point.

13. The semiconductor manufacturing method according to claim 12, wherein: The correction offset includes a movement direction and a movement distance of the first shape point from an original position of the first shape point.

14. The semiconductor manufacturing method according to claim 11, wherein: The plurality of shape points are generated on an outline of a design pattern in each of the plurality of blocks.

15. The semiconductor manufacturing method according to claim 11, wherein: Selecting the unique shape point includes: generating a query range around a target shape point; and Based on the geometric analysis within the query range, a hash value is generated.

16. An optical proximity correction method, the optical proximity correction method comprising: performing, by the processor, a first optical proximity correction on the first layout; accumulating first results of the first optical proximity correction in an optical proximity correction library; selecting, by the processor, a unique tile from a plurality of tiles of the second layout, wherein the first result cannot be applied to the unique tile; performing a second optical proximity correction on the unique block; and accumulating second results of the second optical proximity correction in the optical proximity correction library, wherein the first result comprises a first correction offset for a first unique shape point in the first layout, and The second result includes a second correction offset for a second unique shape point in the second layout.

17. The optical proximity correction method according to claim 16, wherein: The plurality of tiles of the second layout include the unique tile and a normal tile including the first unique shape point.

18. The optical proximity correction method according to claim 16, wherein: Performing the first optical proximity correction includes: generating a plurality of shape points on the outline of the design pattern in the first layout; selecting the first unique shape point among the plurality of shape points; and The first correction offset for the first unique shape point is determined.

19. The optical proximity correction method according to claim 18, wherein: Selecting the first unique shape point comprises: generating a query range around a target shape point; and Based on the geometric analysis within the query range, a hash value is generated.

20. The optical proximity correction method according to claim 16, wherein: The first correction offset includes a first movement direction and a first movement distance of the first unique shape point from an original position of the first unique shape point, and The second correction offset includes a second movement direction and a second movement distance of the second unique shape point from an original position of the second unique shape point.

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