System and method for performing dual precision high speed arithmetic operations

Abstract

A method for performing a dual precision high speed arithmetic operation includes: receiving first input data and second input data; generating first output data by performing a first logical operation on each of the first input data and the second input data; arranging a plurality of dot products in a row-by-row manner; generating second output data by performing a first arithmetic operation on the dot product; performing a transpose operation on the plurality of bit elements of the second output data by arranging the least significant bits and the most significant bits of the plurality of bit elements in consecutive rows; and generating final output data by performing a second arithmetic operation on the transposed bit elements.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of integrated circuits for video processing, and more particularly to systems and methods for performing double-precision high-speed arithmetic operations on integrated circuits. Background Art

[0002] As more media content is generated digitally, such as ultra-high definition (8K) video, there is a need to improve the techniques used to render these videos.

[0003] During video processing of ultra-high definition (8K) video with high frame rates (144Hz), multiplication operations are the most time-consuming and critical operations for high-performance application-specific integrated circuits (ASICs) used for video processing. In particular, meeting the timing requirements of 64-bit × 32-bit multiplication operations at 1400MHz is challenging. Furthermore, conventional components involved in performing multiplication operations cannot meet the timing requirements. In addition, when combined with other operations performed during video processing, conventional components involved in performing complex multiplication operations result in undefined errors. Summary of the invention

[0004] According to an embodiment of the present disclosure, a method for performing double-precision high-speed arithmetic operations on an integrated circuit includes: receiving first input data and second input data from one or more register circuits. The first input data includes a first plurality of bits, and the second input data includes a second plurality of bits. The method also includes generating first output data by performing a first logical operation on each of the received first input data and the second input data, wherein the first output data includes a plurality of dot products of the first plurality of bits and the second plurality of bits. The method also includes arranging the plurality of dot products in a row-by-row manner. In addition, the method includes generating second output data by performing a first arithmetic operation on the plurality of dot products arranged row by row. The second output data includes a plurality of bit elements. In addition, the method includes performing a transposition operation on a plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in consecutive rows in a predefined manner. The method also includes generating final output data by performing a second arithmetic operation on the transposed plurality of bit elements.

[0005] According to another embodiment of the present disclosure, a system for performing double-precision high-speed arithmetic operations on an integrated circuit includes: one or more register circuits that generate first input data and second input data. The first input data includes a first plurality of bits, and the second input data includes a second plurality of bits. The system also includes a first logic circuit that generates first output data by performing a first logic operation on each of the received first input data and the second input data. The first output data includes a plurality of dot products of the first plurality of bits and the second plurality of bits. The first logic circuit also arranges the plurality of dot products in a row-by-row manner. The system also includes a first calculation circuit that generates second output data by performing a first arithmetic operation on the plurality of dot products arranged row by row. The second output data includes a plurality of bit elements. The system also includes a transposition circuit that performs a transposition operation on a plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in a predefined manner in consecutive rows. In addition, the system includes a second calculation circuit that generates final output data by performing a second arithmetic operation on the transposed plurality of bit elements.

[0006] According to another embodiment of the present disclosure, there is provided a computer-readable non-transitory program storage device tangibly embodying a program of instructions executed by a computer to perform a method for performing double-precision high-speed arithmetic operations in an integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic block diagram of an environment for video enhancement and display processing according to an embodiment of the present disclosure.

[0008] Figure 2 is an exemplary block diagram of a system for performing double-precision high-speed arithmetic operations in an integrated circuit according to an embodiment of the present invention.

[0009] Figure 3 An exemplary process flow of multiplication processing for video enhancement according to an embodiment of the present disclosure is shown.

[0010] Figure 4 An exemplary process flow of multiplication processing for video enhancement according to another embodiment of the present disclosure is shown.

[0011] Figure 5 is a flow chart of a method for performing double-precision high-speed arithmetic operations on an integrated circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure provide an enhanced video processing method for performing complex multiplication operations within a desired time period. A video processing method includes performing double-precision high-speed arithmetic operations using an integrated circuit. For example, embodiments of the present disclosure provide an enhanced video processing method for performing multiplication operations on an integrated circuit that supports conversion of high-resolution video.

[0013] Figure 1 is a schematic block diagram of an environment 100 for video enhancement and display processing according to an embodiment of the present disclosure.

[0014] The system environment 100 includes a display processor 102 , a channel demodulator 104 , a central processing unit (CPU) 106 , a graphics processing unit (GPU) 108 , a neural processing unit (NPU) 110 , a double data rate (DDR) memory 112 , and a digital signal processor (DSP) 114 .

[0015] according to Figure 1 , the display processor 102 processes the received video signal and displays the processed video stream to the display device. Note that, in order to simplify the description, Figure 1 The display device and / or display panel are not shown.

[0016] The display processor 102 can reduce noise and / or artifacts in the received video signal. In an embodiment, the display processor 102 implements various techniques, such as but not limited to spatial filtering, temporal filtering, and wavelet-based denoising, to reduce unwanted noise and / or artifacts in the received video signal / image frame. For example, the display processor 102 can effectively recover a compressed video signal or a video signal received from a noisy channel.

[0017] The display processor 102 may also adjust and / or modify various characteristics of the video signal. These characteristics include, but are not limited to, resolution, aspect ratio, etc. In an embodiment, the display processor 102 implements various techniques, such as, but not limited to, interpolation, decimation, filtering, etc., to adjust and / or modify the characteristics of the video signal.

[0018] The display processor 102 may further process the received video signal to enhance the sharpness and clarity of the video signal and / or the image frames of the video signal. In an embodiment, the display processor 102 utilizes various image processing techniques (such as, but not limited to, contrast enhancement, edge enhancement, and noise reduction) to reduce noise in the video signal and add more clarity. In addition, the display processor 102 may implement various techniques, such as, but not limited to, noise reduction, motion smoothing, color correction, contrast enhancement, etc., to improve the quality of the received video signal. For example, the display processor 102 may enhance the resolution of the information in the received video signal to highlight details and increase the clarity of the information.

[0019] In some embodiments, display processor 102 may also adjust high dynamic range (HDR) values ​​of the video signal and / or image frames of the video signal in view of the display device.

[0020] The display processor 102 may also adjust the number of frames displayed per second. For example, the display processor 102 may synchronize the frame rate of information displayed on the display device with the refresh rate of the display device. Thus, the display processor 102 may eliminate various display problems such as, but not limited to, stuttering, jerky motion, tearing, etc.

[0021] In addition, the display processor 102 can expand the resolution and / or refresh rate of the video signal. In an embodiment, the display processor 102 converts a video signal of a lower resolution and / or refresh rate to a higher resolution and / or refresh rate. Thus, the display processor 102 improves the visual quality of the information in the video signal and eliminates resolution loss or distortion.

[0022] In an exemplary embodiment, in order to adjust and / or modify various characteristics / parameters of the video signal, the display processor 102 performs various arithmetic and / or logical operations. For example, the display processor 102 performs a multiplication operation. The multiplication operation adjusts the overall brightness or contrast of the video signal and / or the image frame of the video signal. In addition, in some embodiments, the multiplication operation is used to adjust the HDR value to a low dynamic range (LDR) value. For example, if the HDR value of the image frame is too bright for an LDR display device, the multiplication operation is used to reduce the brightness by a certain factor, such as 0.3. The multiplication by a factor of 0.3 reduces the brightness of the image frame while retaining the details of the image frame.

[0023] The multiplication operation is also used to adjust the contrast of the image frame. A high contrast image has a high brightness difference between the dark and light areas of the image frame, and a low contrast image has a lower brightness difference. Therefore, by adjusting the multiplication factor, the display processor 102 can adjust the contrast of the image frame.

[0024] In an exemplary embodiment, display processor 102 includes an integrated circuit that performs double-precision high-speed arithmetic operations to achieve the desired purpose. Figures 2 to 5 The operation of the integrated circuit of display processor 102 is described in detail.

[0025] The display processor 102 displays the processed video signal by using a display device.

[0026] Figure 1 Also shown is a channel demodulator 104, and various processing units such as a CPU 106, a GPU 108, an NPU 110, a DDR memory 112, and a DSP 114, which are general in nature and perform conventionally known functions. Therefore, for the sake of brevity, a detailed description of these components is omitted.

[0027] The embodiments are exemplary in nature, and integrated circuits that perform double-precision high-speed arithmetic operations may be implemented in any suitable technical field.

[0028] Figure 2 is an exemplary block diagram of a system 200 for performing double-precision high-speed arithmetic operations in an integrated circuit according to an embodiment of the present invention. In an embodiment, the system 200 corresponds to an IC and / or a device for double-precision high-speed arithmetic operations.

[0029] System 200 includes register circuits 202a and 202b, which are interchangeably referred to as "register circuits 202". Register circuit 202 generates first input data and second input data based on received information and / or signals. In an embodiment, the information and / or signals received by register circuit 202 correspond to the first input data and the second input data received by register circuit 202. Figure 1 The video signal and / or the image frame in the video signal received by the display processor 102 shown. In addition, the first input data and the second input data correspond to the pixel information of the video signal and the image frame in the video signal. In addition, the first input data includes a first plurality of bits, and the second input data includes a second plurality of bits.

[0030] In an exemplary embodiment, the arithmetic operation performed by system 200 corresponds to a multiplication operation, the first input data corresponds to the multiplicand, and the second input data corresponds to the multiplier.

[0031] The system 200 also includes a first logic circuit 204. The first logic circuit 204 receives the first input data and the second input data. The first logic circuit 204 generates the first output data by performing a first logic operation on each of the received first input data and the second input data. In an exemplary embodiment, the first logic operation is a bitwise AND operation, and the first logic circuit 204 performs a bitwise AND operation on each bit of the first input data and the second input data. In an embodiment, the first logic circuit 204 performs a bitwise AND operation on each bit of the first input data and the second input data to generate the first output data. In addition, the first output data includes a plurality of dot products corresponding to a first plurality of bits of the first input data and a second plurality of bits of the second input data. In an embodiment, the first output data may be referred to as a partial product (PP-0 to PP-(Y-1)). In addition, the first logic circuit 204 arranges the plurality of dot products in a row-wise manner. In an embodiment, the first logic circuit 204 corresponds to a gate circuit that implements a bitwise AND operation.

[0032] The system 200 also includes a first calculation circuit 206. The first calculation circuit 206 performs a first arithmetic operation on a plurality of dot products arranged row by row to generate second output data. In an exemplary embodiment, the first arithmetic operation corresponds to an addition operation, and the first calculation circuit 206 performs an addition operation on a plurality of dot products arranged row by row, and each of a plurality of bit elements is generated as an addition of a plurality of corresponding dot products. In addition, the second output data includes a plurality of bit elements, and each of a plurality of bit elements is generated as an addition of a plurality of corresponding dot products. In an embodiment, the first calculation circuit 206 may also be referred to as a column adder circuit implementing an addition operation. In addition, the second output data may be referred to as the sum of partial products (SOP-0 to SOP-(X+Y-2)).

[0033] The system 200 also includes a transpose circuit 208. The transpose circuit 208 performs a transpose operation on multiple bit elements of the second output data by arranging the least significant bits (LSBs) of the multiple bit elements and the most significant bits (MSBs) of the multiple bit elements in consecutive rows in a predefined manner. For example, the transpose circuit 208 rearranges the second output data and / or the sum of partial products. In an exemplary embodiment, the transpose circuit 208 generates a row of the sum of partial products by arranging the bit elements from LSB to MSB. In addition, for each consecutive row, the transpose circuit 208 left shifts multiple bit elements of the second output data. After performing the transpose operation, the transpose circuit 208 generates a transposed multiple bit elements. The transposed multiple bit elements can be referred to as a transposed sum of partial products (T[0] to T[log 2 BW]).

[0034] The system 200 also includes a second computing circuit 210. The second computing circuit 210 performs a second arithmetic operation on the transposed multiple bit elements to generate final output data. In an exemplary embodiment, the second arithmetic operation is an addition operation, and the second computing circuit 210 simultaneously performs the addition operation on the corresponding transposed multiple bit elements. In an embodiment, the final output data is the product of the first input data and the second input data. In addition, the system 200 includes one or more register circuits that receive the final result and / or the product.

[0035] In an exemplary embodiment, the first input data includes X number of bits, and the second input data includes Y number of bits, where X is not necessarily equal to Y. In addition, the number of bits (Y) of the second input data may also be referred to as a bit width (BW). The first logic circuit 204 performs a bitwise AND operation on the first input data and the second input data to generate Y partial products. In addition, each of the Y partial products includes X bit elements. For example, the number of partial products is equal to BW. In addition, the first logic circuit 204 arranges the Y partial products in a row-by-row manner and generates Y row partial products.

[0036] The first calculation circuit 206 adds each column of the Y partial products to generate a sum of (X+Y-1) partial products. The generated sum of partial products can be represented as PP_SUM. In addition, the transposition circuit 208 transposes the generated sum of partial products in a row-by-row manner so that each row includes (X+Y-1) bit elements. In an embodiment, the sum of partial products has a maximum value equal to BW. Therefore, the first calculation circuit 206 needs to log 2 (BW) + 1 bit represents the BW of the partial product sum. Therefore, after the transposition operation by the transposition circuit 208, the T0 to T[log 2 (BW)] value. The second calculation circuit 210 converts T[log 2 Each of the sums of the [(BW)]+1 transposed partial products is added in parallel to generate a multiplication result of the first input data and the second input data.

[0037] For example, if BW has 4 bits, the number of partial products will be 4. In addition, the sum of the partial products is less than or equal to 4. In addition, since 3 bits are required to store the number 4, 3 rows are generated to represent PP_SUM. In addition, the 3 rows correspond to T0 to T[log 2 (4)] value.

[0038] Figure 3 An exemplary process flow of multiplication processing for video enhancement according to an embodiment of the present disclosure is shown.

[0039] For example, Figure 3 304. The multiplication of first input data 302 and second input data 304 according to an embodiment of the present disclosure is shown. The first input data 302 may be referred to as a multiplicand, and the second input data 304 may be referred to as a multiplier. In addition, the first input data 302 includes 8 bits located at index positions 0-7, and the second input data 304 includes 4 bits located at index positions 0-3. In an exemplary embodiment, the first input data 302 is equal to a value of 127 in decimal format, and the second input data 304 is equal to a value of 7 in decimal format.

[0040] At step 1, the first logic circuit 204 generates partial products of the first input data 302 and the second input data 304. Since the second input data 304 includes 4 bits, the first logic circuit 204 generates 4 partial products, which are denoted as PP_0, PP_1, PP_2 and PP_3, and have been arranged row by row, as shown in FIG. Figure 3 In an exemplary embodiment, the first logic circuit 204 generates partial products PP_0 to PP_3 by performing a dot product operation on the first input data 302 and the second input data 304. In another embodiment, the first logic circuit 204 generates partial products PP_0 to PP_3 by performing a bitwise logical AND operation on the first input data 302 and the second input data 304.

[0041] At step 2, the first calculation circuit 206 generates a sum of partial products by performing column-wise addition of the partial products. The generated sum of partial products can be represented as PP_SUM. The first calculation circuit 206 also modifies the generated sum of partial products by separating the LSB and MSB of the sum of partial products in separate rows.

[0042] At step 3, the transposition circuit 208 rearranges the row-by-row data including the LSB and MSB of the sum of partial products in a predefined manner, which is called a transposition operation. For example, the transposition circuit 208 arranges the LSB and MSB in consecutive rows, and shifts each consecutive row leftward by 1 from the previous row. "0" is placed in an undefined position. The modified sum of partial products generated by the transposition circuit 208 can also be represented as "T_0" and "T_1".

[0043] At step 4, the second calculation circuit 210 adds the two terms ("T_0" and "T_1") of the modified sum of partial products to generate a product 306 of the first input data 302 and the second input data 304. The product 306 may also be represented by the character "Z", which includes 12 bits and is equal to the value 889 in decimal format.

[0044] Figure 4An exemplary process flow of multiplication processing for video enhancement according to another embodiment of the present disclosure is shown.

[0045] For example, Figure 4 404. The multiplication of first input data 402 and second input data 404 according to an embodiment of the present disclosure is shown. The first input data 402 may be referred to as a multiplicand, and the second input data 404 may be referred to as a multiplier. In addition, the first input data 402 includes 8 bits located at index positions 0-7, and the second input data 404 includes 4 bits located at index positions 0-3. Initially, the system 200 performs BOOTH encoding of the second input data to generate two bits corresponding to the second input data 404.

[0046] At step 1, the first logic circuit 204 generates partial products of the first input data 402 and the second input data 404. In an embodiment, the logic circuit 204 implements a BOOTH encoding technique to generate partial products. The partial products generated by the first logic circuit 204 are represented as PP_0 and PP_1 that have been arranged row by row. In an embodiment, the BOOTH encoding technique is used to generate partial products PP_0 and PP_1 for bits of the second input data (i.e., the multiplier) according to the BOOTH encoding radix-4 rule (BR_PP_0 and BR_PP_1).

[0047] In addition, steps 2-4 are similar to those in reference Figure 3 Steps 2-4 are described, and therefore, for the sake of brevity, descriptions of these steps are omitted. In addition, according to an embodiment of the present disclosure, a product 406 is obtained from the first input data 402 and the second input data 404 as a multiplication result.

[0048] Figure 5 is a flow chart of a method 500 for performing double-precision high-speed arithmetic operations in an integrated circuit according to an embodiment of the present disclosure.

[0049] refer to Figure 5 In an embodiment, at step 502, method 500 includes receiving first input data and second input data from one or more register circuits 202a, 202b. The first input data includes a first plurality of bits, and the second input data includes a second plurality of bits.

[0050] At step 504, method 500 includes generating first output data by performing a first logical operation on each of the received first input data and second input data. The first output data includes a plurality of dot products of the first plurality of bits and the second plurality of bits. The first logical operation is a bitwise AND operation, and the bitwise AND operation is performed on each bit of the first input data and the second input data.

[0051] At step 506, method 500 includes arranging a plurality of dot products in a row-by-row manner. At step 508, method 500 includes generating second output data by performing a first arithmetic operation on the plurality of dot products arranged row by row. The second output data includes a plurality of bit elements. In an embodiment, the first arithmetic operation is an addition operation performed on the plurality of dot products arranged row by row. In addition, each bit element in the plurality of bit elements is generated by adding the corresponding plurality of dot products.

[0052] At step 510, the method 500 includes performing a transposition operation on a plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in consecutive rows in a predefined manner. In addition, at step 512, the method 500 includes performing a second arithmetic operation on the transposed plurality of bit elements to generate the final output data. In an exemplary embodiment, the second arithmetic operation is an addition operation performed simultaneously on the corresponding transposed plurality of bit elements. In addition, the final output data is a multiplication product of the first input data and the second input data.

[0053] The embodiments described above are non-limiting and exemplary. Therefore, the method 500 may include additional steps or omit some of the above steps to perform the desired purpose of the embodiments of the present disclosure. In addition, the steps of the method 500 can be performed in any suitable order and / or by any suitable components of the system 300 to achieve the desired results.

[0054] Therefore, the embodiments of the present disclosure provide various technical effects, including but not limited to significantly reducing the number of steps required to perform the multiplication of the first input data and the second input data. By reducing the number of multiplication steps, the embodiments of the present disclosure can support high-resolution (8k) and high frame rate (144hz) video generation. In addition, by reducing the number of steps, the embodiments of the present disclosure reduce the latency of the system.

[0055] The accompanying drawings and the foregoing description give examples of embodiments. It will be appreciated by those skilled in the art that one or more of the elements described may be well combined into a single functional element. Alternatively, certain elements may be divided into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of the processes described herein may be changed and are not limited to the manner described herein.

Claims

1. A method for performing double-precision high-speed arithmetic operations in an integrated circuit, comprising: receiving first input data and second input data from one or more register circuits, wherein the first input data comprises a first plurality of bits and the second input data comprises a second plurality of bits; generating first output data by performing a first logical operation on each of the received first input data and second input data, wherein the first output data comprises a plurality of dot products of the first plurality of bits and the second plurality of bits; Arrange multiple dot products in a row-by-row manner; generating second output data by performing a first arithmetic operation on a plurality of dot products arranged row by row, wherein the second output data includes a plurality of bit elements; performing a transposition operation on the plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in consecutive rows in a predefined manner; and Final output data is generated by performing a second arithmetic operation on the transposed plurality of bit elements.

2. The method according to claim 1, in, The first logical operation is a bitwise AND operation, and Wherein, a bit-by-bit AND operation is performed on each bit of the first input data and the second input data.

3. The method according to claim 1, in, The first arithmetic operation is an addition operation performed on a plurality of dot products arranged row by row, and Each bit element of the plurality of bit elements is generated as a sum of a corresponding plurality of dot products.

4. The method according to claim 1, in, The second arithmetic operation corresponds to an addition operation, and The addition operation is performed simultaneously on the corresponding transposed multiple bit elements.

5. The method according to claim 1, wherein: The one or more register circuits generate first input data and second input data based on a video signal and / or an image frame in the video signal received by a display processor.

6. The method according to claim 1, wherein: Generating the first output data includes Booth encoding bits of the second input data.

7. A system for performing double-precision high-speed arithmetic operations on an integrated circuit, comprising: one or more register circuits that generate first input data and second input data, wherein the first input data comprises a first plurality of bits and the second input data comprises a second plurality of bits; First logic circuit: generating first output data by performing a first logical operation on each of the received first input data and second input data, wherein the first output data comprises a plurality of dot products of the first plurality of bits and the second plurality of bits; Arrange multiple dot products in a row-by-row manner; a first calculation circuit that generates second output data by performing a first arithmetic operation on a plurality of dot products arranged row by row, wherein the second output data includes a plurality of bit elements; a transposition circuit that performs a transposition operation on the plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in consecutive rows in a predefined manner; and A second calculation circuit generates final output data by performing a second arithmetic operation on the transposed plurality of bit elements.

8. The system according to claim 7, in, The first logical operation is a bitwise AND operation, and Wherein, a bit-by-bit AND operation is performed on each bit of the first input data and the second input data.

9. The system according to claim 7, in, The first arithmetic operation is addition, and The first arithmetic operation performs the addition operation on the plurality of dot products arranged row by row, and each of the plurality of bit elements is generated as the addition of the corresponding plurality of dot products.

10. The system according to claim 7, in, The second arithmetic operation is addition, and The addition operation is performed simultaneously on the corresponding transposed multiple bit elements.

11. The system according to claim 7, wherein: The final output data is a product of the first input data and the second input data, and the system further includes one or more register circuits that receive the final output data.

12. The system according to claim 7, wherein: The first input data includes X bits, the second input data includes Y bits, the first logic circuit generates Y partial products from the first input data and the second input data, each of the Y partial products includes X bit elements, and the first calculation circuit generates (X+Y-1) sums of the partial products by adding each column of the Y partial products.

13. The system according to claim 7, wherein: For each successive row, the transposition circuit generates a modified sum of the partial products by shifting a plurality of bit elements of the second output data from the previous row further left by 1 and placing “0” at undefined positions.

14. The system of claim 13, the second calculation circuit generates a product of the first input data and the second input data by adding two terms of the modified sum of the partial products.

15. A non-transitory computer-readable program storage device tangibly embodying a program of instructions executed by the computer to perform a method for performing double-precision high-speed arithmetic operations in an integrated circuit, the method comprising: receiving first input data and second input data, wherein the first input data comprises a first plurality of bits and the second input data comprises a second plurality of bits; generating first output data by performing a first logical operation on each of the received first input data and second input data, wherein the first output data comprises a plurality of dot products of the first plurality of bits and the second plurality of bits; Arrange multiple dot products in a row-by-row manner; generating second output data by performing a first arithmetic operation on a plurality of dot products arranged row by row, wherein the second output data includes a plurality of bit elements; performing a transposition operation on the plurality of bit elements of the second output data by arranging the least significant bits (LSBs) of the plurality of bit elements and the most significant bits (MSBs) of the plurality of bit elements in consecutive rows in a predefined manner; and Final output data is generated by performing a second arithmetic operation on the transposed plurality of bit elements.

16. The non-transitory computer readable program storage device according to claim 15, in, The first logical operation is a bitwise AND operation, and Wherein, a bit-by-bit AND operation is performed on each bit of the first input data and the second input data.

17. The non-transitory computer readable program storage device according to claim 15, in, The first arithmetic operation is an addition operation performed on a plurality of dot products arranged row by row, and Each bit element of the plurality of bit elements is generated as a sum of a corresponding plurality of dot products.

18. The non-transitory computer readable program storage device of claim 15, in, The second arithmetic operation corresponds to an addition operation, and The addition operation is performed simultaneously on the corresponding transposed multiple bit elements.

19. The non-transitory computer readable program storage device of claim 15, wherein: The method further includes generating first input data and second input data based on a video signal and / or an image frame in the video signal received by a display processor.

20. The non-transitory computer readable program storage device of claim 15, wherein: Generating the first output data includes Booth encoding bits of the second input data.

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