Processing device, processing method and computer readable storage medium

Abstract

The present disclosure relates to a processing device, a processing method and a computer-readable storage medium. A processing device includes: a decoding circuit for decoding a received semi-fixed vector permutation instruction, wherein the semi-fixed vector permutation instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permutation instruction includes: a function type identification field indicating the type of permutation function used to rearrange the data elements; a rearrangement circuit for rearranging the data elements based on the decoded semi-fixed vector permutation instruction; and a storage circuit for storing the rearranged data elements in a destination vector register.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of signal processing, and in particular, to a processing device, a processing method, and a computer-readable storage medium. Background Art

[0002] Permutation, the rearrangement of data elements within a vector based on a specified pattern, is a fundamental operation used in many signal processing applications. Permutations are widely used in a variety of signal processing algorithms, including fast Fourier transform (FFT) methods such as Cooley Tukey, Good-Thomas, and Winograd, as well as simple tasks such as computing complex multiplications using real vector multiplication instructions. In addition, permutations are used in network data switching and sorting algorithms. Summary of the invention

[0003] One aspect of the present disclosure provides a processing device, comprising: a decoding circuit, configured to decode a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction comprises: a function type identification field, which indicates a type of permute function used to rearrange the data elements; a permute circuit, configured to rearrange the data elements based on the decoded semi-fixed vector permute instruction; and a storage circuit, configured to store the rearranged data elements in a destination vector register.

[0004] An aspect of the present disclosure provides a processing method, comprising: decoding a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction includes: a function type identification field indicating a type of a permute function used to rearrange the data elements; rearranging the data elements based on the decoded semi-fixed vector permute instruction; and storing the rearranged data elements in a destination vector register.

[0005] One aspect of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein the computer-executable instructions, when executed by a processing circuit, cause the processing circuit to perform the processing method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals refer to similar elements.

[0007] Figure 1 An example of computing hardware that processes instructions is illustrated.

[0008] Figure 2A block diagram of an example processor and / or System on a Chip (SoC) is illustrated, which may have one or more cores and have an integrated memory controller.

[0009] Figure 3 An example of a general permutation operation is illustrated.

[0010] Figure 4 An example of the percentage of data reflow in an application is illustrated.

[0011] Figure 5 The operation of an example vector register gather instruction is illustrated.

[0012] Figure 6 The operation of example vector indexed load and store instructions is illustrated.

[0013] Figure 7 The operation of a vector data shuffle instruction according to an embodiment of the present disclosure is illustrated.

[0014] Figure 8 A rearrangement function of a 24-point Good-Thomas FFT according to an embodiment of the present disclosure is illustrated.

[0015] Fig. 9 Depicted is a typical format of a RISC-V vector data shuffle instruction according to an embodiment of the present disclosure.

[0016] Fig.10 Illustrated are instruction encodings and associated control and status registers (CSRs) for an example semi-fixed vector permute function according to an embodiment of the present disclosure.

[0017] Fig.11 The diagram illustrates a calculation process of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0018] Fig.12 The diagram illustrates the layout of input data during calculation of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0019] Fig.13 The diagram illustrates a rearrangement operation of the real part of a result of complex number multiplication during calculation of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0020] Fig.14 The diagram illustrates an operation of rearranging the imaginary part of a result of complex number multiplication during calculation of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0021] Fig.15 The diagram illustrates a rearrangement operation of packing complex multiplication results during calculation of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0022] Fig.16 The figure illustrates the second stage of pre-rearrangement in the calculation process of the 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0023] Fig.17 The diagram illustrates the pre-rearrangement in the third stage of the calculation process of the 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0024] Fig.18 FIG. 4 illustrates the pre-rearrangement in the fourth stage of the calculation process of the 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0025] Fig.19 The diagram illustrates a rearrangement operation in a post-processing stage during calculation of a 16-point Radix-2 Cooley-Tukey FFT according to an embodiment of the present disclosure.

[0026] Fig. 20 A flowchart of a processing method according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0027] The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments may be implemented using the parts of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are provided to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments may be implemented without these specific details. In other examples, known features may be omitted or simplified in order to avoid blurring the illustrative embodiments.

[0028] In addition, various operations are described as multiple discrete operations in sequence in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be interpreted as implying that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0029] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. These phrases generally do not refer to the same embodiment; however, they may refer to the same embodiment. Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0030] Figure 1 An example of computing hardware for processing instructions is illustrated. According to some embodiments of the present disclosure, the instructions may include, but are not limited to, arithmetic instructions (e.g., addition (ADD) instructions, subtraction (SUB) instructions, etc.), and memory access instructions, such as memory access for register overflow (e.g., memory load (LOAD) or storage (STORE)) instructions. As shown in the figure, the storage device 103 stores instructions 101 to be executed.

[0031] Instruction 101 is received by decoder circuit 105. For example, decoder circuit 105 receives the instruction from a fetch circuit (not shown). The instruction may take any suitable format. In one example, the instruction includes fields for an opcode, (one or more) source identifiers, and a destination identifier. In some examples, the source and destination are registers, while in other examples, one or more of them are memory locations. In some examples, one or more of the sources may be immediate operands. In some examples, the opcode details one or more operations to be performed.

[0032] A more detailed example of at least one instruction format for the instruction will be described in detail later. Decoder circuit 105 decodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be executed by execution circuitry (e.g., execution circuitry 109). Decoder circuit 105 also decodes instruction prefixes.

[0033] In some examples, register renaming, register allocation and / or scheduling circuitry 107 provides functionality for one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some examples); 2) assigning status bits and flags to decoded instructions; and 3) scheduling decoded instructions from an instruction pool for execution by execution circuitry (e.g., using a reservation station in some examples).

[0034] Registers (register files) and / or memory 108 store data as operands of instructions, which are operated on by execution circuitry 109. Example register types include packed data registers, general purpose registers (GPRs), and floating point registers.

[0035] The execution circuit 109 executes the decoded instruction. Executing the decoded instruction causes the execution circuit to perform the corresponding operation. In some examples, the retirement / writeback circuit 111 architecturally commits the destination register to a register or memory 108 and retires the instruction.

[0036] An example of the format of an instruction is OPCODE DST, SRC1, SRC2. In some examples, OPCODE is the opcode mnemonic for the instruction, such as ADD, SUB, STORE, LOAD, etc. DST is a field for the destination operand, such as a packed data register or memory. SRC1 and SRC2 are fields for the source operand, such as a packed data register and / or memory.

[0037] Figure 2 A block diagram of an example processor and / or SoC 200 is illustrated, which may have one or more cores and have an integrated memory controller. The processor 200 illustrated by the solid line box has a single core 202(A), a system agent unit circuit 210, and a set of one or more interface controller unit circuits 216, while the optionally added dashed line box illustrates an alternative processor 200 as having multiple cores 202(A)-(N), a set of one or more integrated memory control unit circuits 214 in the system agent unit circuit 210, dedicated logic 208, and a set of one or more interface controller unit circuits 216. Note that the processor 200 may be one of a processor or a coprocessor.

[0038] Thus, different implementations of processor 200 may include: 1) a CPU, where dedicated logic 208 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 202 (A)-(N) are one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 202 (A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 202 (A)-(N) are a large number of general purpose in-order cores. Thus, processor 200 may be a general purpose processor, a coprocessor, or a special purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 200 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0039] The memory hierarchy includes one or more levels of cache unit circuits 204(A)-(N) within the cores 202(A)-(N), a set of one or more shared cache unit circuits 206, and external memory (not shown) coupled to the set of integrated memory controller unit circuits 214. The set of one or more shared cache unit circuits 206 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples an interface network circuit 212 (e.g., a ring interconnect) provides an interface to the dedicated logic 208 (e.g., integrated graphics logic), the set of shared cache unit circuits 206, and the system agent unit circuit 210, alternative examples use any number of well-known techniques to provide interfaces to these units. In some examples, coherency is maintained between one or more circuits in the shared cache unit circuits 206 and the cores 202(A)-(N). In some examples, interface controller unit circuitry 216 couples the cores 202 to one or more other devices 218 , such as one or more I / O devices, storage, one or more communication devices (eg, wireless network, wired network, etc.), and the like.

[0040] In some examples, one or more of the cores 202(A)-(N) have multi-threading capabilities. The system agent unit circuit 210 includes those components that coordinate and operate the cores 202(A)-(N). The system agent unit circuit 210 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to regulate the power state of the cores 202(A)-(N) and / or the dedicated logic 208 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0041] The cores 202(A)-(N) may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 202(A)-(N) may be heterogeneous with respect to ISA; that is, a subset of the cores 202(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of the ISA or may be capable of executing another ISA.

[0042] As mentioned earlier, permutation is a basic operation widely used in many signal processing applications, which rearranges the data elements within a vector based on a specified pattern. Permutation is widely used in various signal processing algorithms, including FFT methods such as Cooley Tukey, Good-Thomas, and Winograd, as well as simple tasks such as calculating complex multiplication using real vector multiplication instructions. In addition, permutation is also used in network data switching and sorting algorithms.

[0043] Figure 3 An example of a general permutation operation is shown in the figure. Figure 3 The original vector has index i Each element of (0≤i≤7) is relocated to the i' The new position of the index.

[0044] Vector permutation instructions play an important role in the calculation of signal processing algorithms and have a crucial impact on the performance of signal processing algorithms. For example, in the N-point Radix-2 Cooley-Tukey FFT, the algorithm consists of N· log N / 2 complex multiplications and N· log N The rearrangement of the elements also adds up to N· log N times, which closely reflects the overall computational complexity of the algorithm. Similarly, when performing element-wise complex multiplication between two vectors using the real vector multiplication instruction, there are 4N real multiplications, N real additions, and 4N element rearrangements. Figure 4 The percentage of data rearrangements involved is shown graphically.

[0045] Currently, there are generally two types of vector permutation instructions, namely general vector permutation instructions and fixed vector permutation instructions. General permutation is the most flexible way to perform any type of horizontal movement of data within a vector register. In contrast, fixed permutation is limited to rearranging data according to a predefined pattern. The X86 AVX extension and the ARM SVE extension support both general and fixed permutations, while the fifth-generation Reduced Instruction Set Computer-V (RISC-V) vector extension only supports general permutations. The following introduces general vector permutation instructions and fixed vector permutation instructions respectively.

[0046] Generic vector permute instruction

[0047] For ease of description only, the present disclosure illustrates general permutations in conjunction with the RISC-V vector extension.

[0048] The current RISC-V vector extension features data shuffling with two main types of instructions: vector register gather instructions, and vector index load and store instructions. Both types of instructions involve preparing a mapping list for each index before the data shuffling instruction and storing it in a vector register, however, this can lead to inefficiencies and performance degradation. The following describes these two types of instructions separately.

[0049] Type 1: Vector register gather instructions

[0050] For vector register gather instructions, an example of this type of instruction is vrgather.vv vd, vs2, vs1,vm. In this instruction, each element vd[i] of the destination vector register corresponds to the value vs2[vs1[i]] in the source vector register vs2, where vs1[i] specifies the index of the element to be read. The operation of this instruction is as follows Figure 5 shown.

[0051] Vector register gather instructions have the following disadvantages:

[0052] Increased latency due to read-after-write (RAW) data dependencies: Using vrgather.vv introduces RAW data dependencies, which increases latency and pipeline stalls. Before executing vrgather.vv to rearrange the elements, the index value for the target location must be calculated and stored in vs1. Instructions cannot be issued to the functional units until all index calculations are completed.

[0053] Resource inefficiency: Explicitly storing index values ​​in vector registers (vs1) for regular shuffle mode is unnecessary and inefficient. This occupies vector registers that could be used for different instructions, wastes resources and increases energy consumption due to microarchitectural operations such as register renaming and writeback.

[0054] Type 2: vector-indexed load and store instructions

[0055] Vector-indexed load and store instructions move data elements between memory locations that are offset from a base address. For example, consider the vector-indexed load instruction vluxei8.v vd, (rs1), vs2: where integer register rs1 holds the base address, and vs2 contains an 8-bit offset value. Each element in vs2 specifies an offset from the base address. The data is fetched from the memory location that is the i-th offset from the base address and stored in the i-th element of the destination vector register vd. This operation is as follows: Figure 6 shown.

[0056] Vector-indexed load and store instructions have the following disadvantages:

[0057] In addition to having the disadvantages of vector register gather instructions, vector indexed load and store instructions also have the problem of not retrieving data in units of cache lines.

[0058] In many signal processing algorithms, data is contiguous in memory, which makes it efficient to load an entire cache line at a time. However, in implementations, vector indexed loads and stores are often broken up into separate scalar loads and stores. Even if some offsets correspond to data in the same cache line, these data are accessed separately, which requires extra effort to handle these loads. It is more efficient to use unit-stride vector load instructions to load contiguous data into vector registers cache line by cache line and rearrange the data accordingly.

[0059] Fixed vector permute instructions

[0060] Fixed permutations encode the reordering mode in the instruction. The reordering modes supported by AVX and SVE extensions include broadcast, copy, pack, and unpack.

[0061] Fixed vector permute instructions have the following disadvantages:

[0062] Due to the limited instruction encoding space, only a limited number of permutation patterns can be supported. Often, the more complex patterns required by signal processing algorithms cannot be directly supported. This requires using a fairly large number of fixed permutations where possible, or eventually moving to general permutations.

[0063] For example, many data rearrangement operations in FFT cannot be performed using existing fixed permutation instructions.

[0064] In view of the shortcomings and problems of existing vector permutation instructions, the present disclosure proposes to optimize data rearrangement by using regular patterns that can be expressed mathematically. These regular patterns are similar to the patterns in the fast algorithm for discrete Fourier transform, rather than the irregular data dependency patterns used in the sorting algorithm. The present disclosure proposes a novel vector permutation instruction that can outperform the existing vector permutation instruction in the vector extension of RISC-V.

[0065] Specifically, the present disclosure proposes semi-fixed vector permute instructions, in which data rearrangement patterns are represented as mathematical functions with parameters. These functions are encoded as fixed parts in the instructions, while their parameters are provided in control and status registers (CSRs) or as variable parts.

[0066] The semi-fixed vector permutation instruction proposed in the present disclosure combines the advantages of both the fixed vector permutation instruction and the general vector permutation instruction.

[0067] On the one hand, similar to fixed permutations, semi-fixed permutations have several benefits over general-purpose permutations such as RISC-V vector data reordering instructions:

[0068] - Higher performance: No need to wait for all index mappings to be ready before starting shuffle. This avoids RAW vector register data dependencies and hides latency by computing shuffle index mappings and reading from source registers simultaneously.

[0069] - Higher efficiency: Since no instructions are needed to compute and store a separate index map, instruction count is reduced and vector registers are saved.

[0070] On the other hand, unlike fixed permutations, semi-fixed permutations provide great flexibility for various applications. The shuffle behavior can be configured by adjusting parameters. A single instruction supports various shuffle patterns that share a common math format. This allows support for a wider range of more complex shuffle patterns.

[0071] The following first describes the format of the semi-fixed vector permutation instructions according to an embodiment of the present disclosure, then uses these instructions to illustrate the implementation of a 16-point Cooley-Tukey FFT, and finally performs a performance analysis to show the advantages of the semi-fixed permutation according to an embodiment of the present disclosure compared with general permutation and fixed permutation.

[0072] Format of semi-fixed vector permute instruction

[0073] In signal processing algorithms, when a transform algorithm is performed on a vector of length N, the data often needs to be rearranged in a vector of length multiple of N. For example, in a 2N-point Radix-2 FFT, each stage involves rearranging 2N elements, while operations such as complex addition and complex subtraction are performed on N elements. The granularity of the data rearrangement may also be different from the original data. An example is performing complex multiplication with a real multiplier. For a 32-bit complex number, it needs to be rearranged on a 16-bit element basis.

[0074] In one embodiment, the semi-fixed vector permute instruction can be designed as a widening / narrowing instruction, in which the effective vector register group multiplier (emul) and the effective element width (eew) are different from the corresponding vector length multiplier (lmul) and the original set element width (sew) in the existing setting. This method eliminates the need for reconfiguration through vset(i)vl(i) before and after the semi-fixed vector permute instruction proposed in the present disclosure. For details, please refer to the vsetvli instruction in subroutines 1 / 2 / 3 in the appendix below.

[0075] Therefore, the operation of the instruction proposed in the present disclosure involves obtaining emul source vector registers and applying a reordering function to reorder the data, and the corresponding results are written into emul destination vector registers. In an embodiment, let vl represent the number of elements in the vector. The reordering function can be defined as i' = f ( i ), where 0≤ i ≤ vl -1 and 0≤ i' ≤ vl -1. This means that the ith element in the source vector should be mapped to the ith element in the destination vector. i' elements. Figure 7 This operation is illustrated, emphasizing that rearrangement patterns can be used with mathematical functions f ( i ) is expressed concisely.

[0076] The shuffle function can vary for different applications. In the Fast Fourier Transform algorithm, a one-dimensional vector is often represented as a two-dimensional matrix after shuffling. In RISC-V, each row can be stored in a vector register. For clarity, the shuffle function f Expressed as ( i',i'' )= f ( i ). This function converts the first i The elements are assigned to the first i' The vector i'' elements (rows i' ,List i'' ). Figure 8 The figure shows a 24-point Good-Thomas FFT decomposed into a 3 x 8 array, where the rearrangement function is ( i',i'' )=( i% 3 ,i%8). Note that Figure 8 In the example shown, three vector registers are grouped together, ie, emul is equal to 3. For vector permute instructions, emul is not necessarily a power of 2.

[0077] In an example implementation, the reordering mode may include:

[0078] A 3-bit field for emul (effective vector register group multiplier) which specifies the number of vector registers in the group, ranging from 1 to 8.

[0079] · A 2-bit field for the effective element width scale factor, which indicates the ratio of the element width to the original set element width. As an example, let s be a two's complement value, then eew / sew = 2 s .

[0080] An ID indicating the function type, encoded as ⌈log N f ⌉ bits, where N f is the number of supported function types. Examples of function types include f 0:( i',i'' )=( i%n',i%n'' ), f 1:( i',i'' )=( i / n,i%n )wait.

[0081] If the function type has P parameters, then the number of parameters m i (in i =0,…, P -1) Total required For example, f 0:( i',i'' )=( i%n',i%n'' ) has parameters n' and n'' , each parameter is represented by 3 bits, for f 0 requires 6 bits in total.

[0082] Fig. 9 Depicted is the typical format of a RISC-V vector data shuffle instruction. The bits highlighted in grey have a defined use and serve a fixed purpose, while the remaining bits can be flexibly used to encode other information.

[0083] Because no vector index register is needed in the instructions proposed in the present disclosure, the bit 19-15 field is reserved for encoding the reorder function information. For custom extensions, the fields funct3 and funct6 can also be used for this purpose.

[0084] Typically, instructions encode relatively fixed information, while CSRs store variable details. Therefore, in embodiments of the present disclosure, a function type ID may be encoded in the instruction, and the parameters of the function type may be encoded in the specified CSR. emul and effective element width scaling factors may be placed in either position.

[0085] The following is a specific example of a semi-fixed vector permutation function according to an embodiment of the present disclosure: vshfl.f3(4).l2.s0 vd, vs2. The name vshfl indicates that it is a vector data reordering instruction. The f3 suffix specifies the function type. f :( i', i'' )=(( i / n)%2, ( i%n)+n· ( i / 2n )), where the parameter n is 4. l2 indicates that emul is equal to 2, and s0 indicates that the element width is scaled by a factor of 1 (2 0 ).

[0086] The parameters are stored in a permutation-specific CSR called vshflpar, while other information is encoded directly in the instruction. Fig.10 This design is shown.

[0087] Implementation of 16-point Radix-2 Cooley-Tukey FFT

[0088] Fig.11 The figure shows the calculation process of the frequency-decimated (DIF) 16-point Radix-2 Cooley-Tukey Fast Fourier Transform (FFT). The calculation process consists of four stages, each of which includes a "butterfly" operation followed by a multiplication of the twiddle factors.

[0089] Phase 1

[0090] The vector length (VLEN) of the input data is 256, and the 16 complex input elements are distributed over 2 vectors, specifically, v2 and v3. The data layout is as follows Fig.12 shown.

[0091] No data reordering is required at this stage. The "butterfly" operation can be performed directly on the original vector via the following instructions:

[0092] vadd.vv v4, v2, v3 # v4 = v2 + v3

[0093] vsub.vv v5, v2, v3 # v5 = v2 - v3

[0094] Next, multiply v5 by the twiddle factor, assuming the twiddle factor is stored in v1.

[0095] The following is an overview of how to compute a complex multiplication between two vectors using the real vector multiply instruction.

[0096] First, use the rearrange function f 0(2 , 8) Rearrange v1 and v5 to obtain the intermediate result of the real part stored in v10, such as Fig.13 The corresponding instructions are as follows:

[0097] vshfl.f0 (2, 8).l1.s0 v8, v1

[0098] vshfl.f0 (2, 8).l1.s0 v9, v5

[0099] vmul.vv v10, v8, v9

[0100] li t0, 0xFF00

[0101] vmv.sx v0, t0

[0102] li t1, -1

[0103] vmul.vx v10, v10, t1, v0.t

[0104] Second, use the rearrange function f 1(2 , 8) Rearrange v1 to obtain v8, which is used to calculate the intermediate result of the imaginary part, such as Fig.14 shown.

[0105] The result is stored in v11. The corresponding instructions are as follows:

[0106] vshfl.f1 (2, 8).l1.s0 v8, v1

[0107] vmul.vv v11, v8, v9

[0108] Finally, the previously scattered real (v10) and imaginary (v11) parts are assembled into the final result (v8, v9). This is done by using f 2(16,2,8) are rearranged, and then v8 and v9 are added. Fig.15 Note that the two vector registers are shuffled together and emul is set to 2.

[0109] The corresponding instructions are as follows:

[0110] vshfl.f2 (16, 2, 8).l2.s0 v8, v10

[0111] vadd.vv v5, v8, v9

[0112] After obtaining the result of v5 through multiplication of the rotation factors, the first stage ends. The completed results of the first stage are in v4 and v5.

[0113] Phase 2

[0114] Unlike the first stage, the data must be rearranged before the "butterfly" step. The rearrangement function used for this purpose is f 3(4). Note that the two vector registers are reordered together, with emul set to 2. Fig.16 An intuitive description of this process is provided.

[0115] After this, the "butterfly" operation is performed using the vector addition instruction as shown below.

[0116] vshfl.f3 (4).l2.s1 v2, v4

[0117] vadd.vv v4, v2, v3 # v4 = v2 + v3

[0118] vsub.vv v5, v2, v3 # v5 = v2 - v3

[0119] Then, multiply v5 by the rotation factor.

[0120] Phase 3

[0121] It follows the same process as phase 2, except that the rearrangement function is f 3(2). Fig.17 The process is illustrated.

[0122] Phase 4

[0123] It follows the same process as phase 2, except that the rearrangement function is f 3(1). Fig.18 The process is illustrated.

[0124] Post-processing

[0125] After stage 4, the data needs to be rearranged in a bit-reversed fashion to ensure that the FFT output is in the correct order. This rearrangement is done using f 4(4) is achieved. f 4(4) performs a bit-reversal function with the index width as its parameter. Here, the two vector registers are shuffled together and emul is set to 2. Fig.19The process is illustrated.

[0126] Performance Analysis

[0127] Comparing the code with and without the vector permute instruction proposed in this disclosure, it is possible to find the improvement in performance and efficiency:

[0128] 1. Using existing RISC-V instructions to implement the functionality of any vector permute instruction proposed in this disclosure requires a large number of instructions. This is evident when comparing the code snippets of vshfl.f0(2,8).l1.s0, vshfl.f1(2,8).l1.s0, and vshfl.f2(16,2,8).l2.s0 in subroutine 1, vshfl.f3(n).l2.s1 in subroutine 2, and vshfl.f4(n).l2.s1 in subroutine 3 as detailed in the appendix.

[0129] Without the instructions proposed by the present disclosure, the instruction count is 2315. In contrast, using the instructions proposed by the present disclosure reduces the count to 66, achieving a 35-fold reduction.

[0130] 2. The instructions proposed in this disclosure also improve performance by reducing latency. This improvement comes from eliminating the need to prepare a vector index vector before executing the permute instruction, and optimizations such as bypassing configuration changes through vsetvli. Latency improvements in the pipeline without bubbles are now calculated.

[0131] Assume that the latency of the relevant vector instructions in the existing RISC-V is as shown in the following Table 1:

[0132] Table 1

[0133]

[0134] The delay of the instructions proposed in this disclosure is shown in Table 2 below:

[0135] Table 2

[0136]

[0137] For scalar instructions, the latency is shown in Table 3 below:

[0138] Table 3

[0139]

[0140] Therefore, in an implementation without the instructions proposed in the present disclosure, the execution time totals 2565 cycles. With the instructions proposed in the present disclosure, the execution time drops to 154 cycles, a 16-fold reduction.

[0141] 3. The instructions proposed in the present disclosure also save the number of required registers. This can be explained by the reduction in the number of rewritten vector registers marked in the comments of subroutines 1 / 2 / 3 in the traditional implementation, not to mention the reduction in the number of widely used integer registers.

[0142] Fig. 20 2000 according to some embodiments of the present disclosure. In some embodiments, the method 2000 may be performed at a processing device. The method 2000 may include steps 2010, 2020, and 2030.

[0143] At step 2010, the received semi-fixed vector permute instruction is decoded, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction may include: a function type identification field indicating the type of permute function used to rearrange the data elements.

[0144] At step 2020, data elements are rearranged based on the decoded semi-fixed vector permute instruction.

[0145] At step 2030, the rearranged data elements are stored in the destination vector register.

[0146] In some embodiments of the present disclosure, the rearrangement function has one or more parameters, which are stored in the control and status register. In some embodiments of the present disclosure, the control and status register may also store the following items: an effective vector register group multiplier field, which is used to indicate the number of source vector registers or destination vector registers; and an effective element width scale factor field, which is used to indicate the ratio of the width of the data element to the original set element width.

[0147] In some embodiments of the present disclosure, the semi-fixed vector permute instruction may further include: an effective vector register group multiplier field, used to indicate the number of source vector registers or destination vector registers; and an effective element width scale factor field, used to indicate the ratio of the width of the data element to the original set element width.

[0148] In some embodiments of the present disclosure, the function type identification field is encoded as ⌈log N f ⌉ bits, where N f Indicates the number of function types supported by the semi-fixed vector permute instructions.

[0149] It is understood that the specific details of the method 2000 can be referred to in conjunction with the above Figures 1 to 17The specific contents and related contents are not repeated here. In addition, it is understood that the method 2000 may include more, less or different steps in some other embodiments, which is not limited here.

[0150] The following paragraphs describe examples of various embodiments.

[0151] Example 1 includes a processing device, comprising: decoding circuitry for decoding a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction includes: a function type identification field indicating a type of permute function used to rearrange the data elements; a permute circuitry for rearranging the data elements based on the decoded semi-fixed vector permute instruction; and a storage circuitry for storing the rearranged data elements in a destination vector register.

[0152] Example 2 includes the apparatus of Example 1, wherein the rearrangement function has one or more parameters, the parameters being stored in control and status registers.

[0153] Example 3 includes the apparatus described in Example 2, wherein the control and status register further stores the following items: an effective vector register group multiplier field for indicating the number of the source vector registers or the destination vector registers; and an effective element width scale factor field for indicating the ratio of the width of the data element to the original set element width.

[0154] Example 4 includes the apparatus described in Example 2, wherein the semi-fixed vector permute instruction further includes: an effective vector register group multiplier field for indicating the number of the source vector registers or the destination vector registers; and an effective element width scale factor field for indicating the ratio of the width of the data element to the original set element width.

[0155] Example 5 includes the apparatus of Example 1, wherein the function type identification field is encoded as ⌈log N f ⌉ bits, where N f Indicates the number of function types supported by the semi-fixed vector permute instruction.

[0156] Example 6 includes a processing method, comprising: decoding a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction includes: a function type identification field, which indicates a type of permute function used to rearrange the data elements; rearranging the data elements based on the decoded semi-fixed vector permute instruction; and storing the rearranged data elements in a destination vector register.

[0157] Example 7 includes the method of Example 6, wherein the rearrangement function has one or more parameters, the parameters being stored in control and status registers.

[0158] Example 8 includes the method described in Example 7, wherein the control and status register further stores the following items: an effective vector register group multiplier field, used to indicate the number of the source vector registers or the destination vector registers; and an effective element width scale factor field, used to indicate the ratio of the width of the data element to the original set element width.

[0159] Example 9 includes the method described in Example 7, wherein the semi-fixed vector permute instruction further includes: an effective vector register group multiplier field, used to indicate the number of the source vector registers or the destination vector registers; and an effective element width scale factor field, used to indicate the ratio of the width of the data element to the original set element width.

[0160] Example 10 includes the method of Example 6, wherein the function type identification field is encoded as ⌈log N f ⌉ bits, where N f Indicates the number of function types supported by the semi-fixed vector permute instruction.

[0161] Example 11 includes a computer-readable storage medium having computer-executable instructions stored thereon, wherein the computer-executable instructions, when executed by a processing circuit, cause the processing circuit to perform the method of any of Examples 6-10.

[0162] Although certain embodiments are illustrated and described herein for descriptive purposes, various alternative and / or equivalent embodiments or implementations planned to achieve the same purpose may replace the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, it is readily understood that the embodiments described herein are limited only by the appended claims and their equivalents.

[0163] Appendix: Implementation code of 16-point Radix-2 Cooley-Tukey FFT

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[0165]

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[0167]

Claims

1. A processing device, comprising: A decoding circuit, configured to decode a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction comprises: a function type identification field, which indicates a type of permute function used to rearrange the data elements, wherein the permute function has one or more variable parameters n1, n2, ..., n m , m is a positive integer greater than or equal to 1, and the rearrangement function is i'=f(i, n1,n2, …, n m ) or (i',i'')=f(i, n1, n2, …, n m ), i represents the index of the data element in the source vector register, i' and i'' represent the index of the data element in the destination vector register; Rearrangement circuitry for rearranging the data elements based on the decoded semi-fixed vector permute instruction; and A storage circuit stores the rearranged data elements in the destination vector register.

2. The device according to claim 1, wherein: The parameters are stored in control and status registers.

3. The device as claimed in claim 2, wherein: The control and status register also stores the following items: an effective vector register set multiplier field, for indicating the number of the source vector register or the destination vector register; and The effective element width scaling factor field is used to indicate the ratio of the width of the data element to the original set element width.

4. The device as claimed in claim 2, wherein: The semi-fixed vector permutation instruction also includes: an effective vector register set multiplier field, for indicating the number of the source vector register or the destination vector register; and The effective element width scaling factor field is used to indicate the ratio of the width of the data element to the original set element width.

5. The device according to claim 1, wherein: The function type identification field is encoded as bits, of which N f Indicates the number of function types supported by the semi-fixed vector permute instruction.

6. A processing method comprising: decoding a received semi-fixed vector permute instruction, wherein the semi-fixed vector permute instruction is used to rearrange data elements in a source vector register, and the semi-fixed vector permute instruction comprises: a function type identification field indicating a type of permute function used to rearrange the data elements, wherein the permute function has one or more variable parameters n1, n2, ..., n m , m is a positive integer greater than or equal to 1, and the rearrangement function is i'=f(i, n1, n2, …, n m ) or (i',i'')=f(i, n1, n2, …, n m ), i represents the index of the data element in the source vector register, i' and i'' represent the index of the data element in the destination vector register; rearranging the data elements based on the decoded semi-fixed vector permute instruction; and The rearranged data elements are stored in the destination vector register.

7. The method of claim 6, wherein: The parameters are stored in control and status registers.

8. The method of claim 7, wherein: The control and status register also stores the following items: an effective vector register set multiplier field, for indicating the number of the source vector register or the destination vector register; and The effective element width scaling factor field is used to indicate the ratio of the width of the data element to the original set element width.

9. The method of claim 7, wherein: The semi-fixed vector permutation instruction also includes: an effective vector register set multiplier field, for indicating the number of the source vector register or the destination vector register; and The effective element width scaling factor field is used to indicate the ratio of the width of the data element to the original set element width.

10. The method of claim 6, wherein: The function type identification field is encoded as bits, of which N f Indicates the number of function types supported by the semi-fixed vector permute instruction.

11. A computer-readable storage medium having computer-executable instructions stored thereon, wherein the computer-executable instructions, when executed by a processing circuit, cause the processing circuit to perform the method of any one of claims 6-10.

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