Hardware acceleration system for data processing

Abstract

The invention belongs to the technical field of hardware acceleration data processing, and particularly relates to a hardware acceleration system for data processing, which comprises a processing unit for realizing acceleration of different data processing tasks by adopting a mode of combining a programmable logic device (FPGA) and an application specific integrated circuit (ASIC); a programmable logic device (FPGA) uses the FPGA to realize a programmable computing core to adapt to different algorithm requirements, and meanwhile, an application specific integrated circuit (ASIC) processes specific tasks through an ASIC module to improve the performance; through reasonable cooperative processing of a processing unit, a storage unit, an interface unit and an intelligent learning and optimization processing unit, the problems that an existing hardware accelerator usually optimizes specific tasks, is difficult to adapt to various data processing requirements and is high in power consumption, and in a high-load state, the energy consumption of an existing system is remarkably increased, so that the operation cost is increased, and the energy consumption is low are solved. And the problems that the complexity of the system is increased and the maintenance is difficult due to the fact that a plurality of different hardware units are often needed in the existing solution are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of hardware accelerated data processing, and in particular relates to a hardware accelerated system for data processing. Background Art

[0002] With the rapid development of information technology, the amount of data is growing exponentially. Traditional data processing systems face performance bottlenecks when processing massive amounts of data and cannot meet the needs of real-time processing and efficient computing. Although existing hardware accelerators such as GPUs and FPGAs can improve processing performance, they still have the following shortcomings: 1. Lack of flexibility: Existing hardware accelerators are usually optimized for specific tasks and are difficult to adapt to various data processing needs.

[0003] 2. High power consumption: Under high load conditions, the energy consumption of existing systems increases significantly, leading to increased operating costs.

[0004] 3. Low integration: Existing solutions often require multiple different hardware units, which increases system complexity and makes maintenance difficult.

[0005] In view of this, we propose a hardware acceleration system for data processing. Summary of the invention

[0006] The object of the present invention is to provide a hardware acceleration system for data processing to solve the problems raised in the above background technology.

[0007] In view of this, the present invention provides a hardware acceleration system for data processing, comprising: The processing unit uses a combination of field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) to accelerate different data processing tasks. FPGAs use FPGAs to implement programmable computing cores to adapt to different algorithm requirements, while application-specific integrated circuits (ASICs) process specific tasks through ASIC modules to improve performance. The storage unit specifically includes cache optimization, hardware optimization and task result cache. The hardware optimization is used to classify and process different data. The task result cache is used to cache the processed task results to avoid repeated calculations. Interface unit, which provides multiple data transmission interfaces, such as PCIe, Ethernet, etc., and supports high-speed data exchange with external devices; The scheduling management unit specifically includes an optimization algorithm unit and load balancing, and is used to dynamically allocate resources according to task types and optimize system performance; Data preprocessing, which is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management module to reduce the complexity and time of subsequent processing; The intelligent learning and optimization processing unit is used to use machine learning algorithms to intelligently schedule data processing, optimize resource utilization, and predict data processing needs in advance by analyzing historical data to optimize resource allocation.

[0008] In the above technical solution, further, a field-programmable gate array (FPGA) can be configured to accelerate matrix operations in machine learning, while an application-specific integrated circuit (ASIC) is used for video encoding.

[0009] In the above technical solution, further, cache optimization utilizes RAM for caching to reduce the read and write operations on the hard disk, and sets an appropriate cache size to adjust the cache settings of the application to improve data processing efficiency.

[0010] In the above technical solution, further, the hardware optimization includes: A hard disk (HDD), wherein the hard disk (HDD) is used to process conventional simple data or data with a small memory; Solid-state drive (SSD), which is used to process important data or data that takes up a large amount of memory. Using the solid-state drive (SSD) to replace the traditional hard disk (HDD) has a faster read and write speed, which can greatly improve the data access speed, improve the data read and write speed, and reduce I / O bottlenecks; The NVMe protocol, which is used for SSDs, provides higher bandwidth and lower latency compared to traditional SATA SSDs.

[0011] In the above technical solution, further, the interface unit is used to support standard data transmission protocols to ensure compatibility with various external devices; at the same time, a high-bandwidth transmission interface, such as PCIe4.0, is adopted to ensure that the data transmission rate meets the needs of large-scale data processing.

[0012] In the above technical solution, further, data preprocessing includes: Data transmission adopts RESTful API design, designs concise and efficient APIs, uses appropriate HTTP methods, avoids unnecessary data transmission, and uses protocol optimization: consider using lighter protocols (such as gRPC, Thrift) to replace traditional RESTful APIs.

[0013] In the above technical solution, further, the optimization algorithm unit includes: An efficient scheduling algorithm unit, which is used in shortest job first (SJF), priority scheduling or round robin scheduling, can reduce the waiting time of tasks and improve the overall performance of the system; Dynamic scheduling, which is used to dynamically adjust the scheduling strategy according to real-time load and task characteristics to cope with different operating environments; Parallel processing includes distributed computing and task parallelization. Distributed computing is used to distribute data processing tasks to multiple nodes using distributed computing frameworks (such as Apache Hadoop and Apache Spark) to improve processing speed. Task parallelization is used to split data processing tasks into multiple subtasks and use multi-threading or multi-process parallel processing to fully utilize the performance of multi-core CPUs.

[0014] In the above technical solution, further, load balancing includes: Dynamic load balancing, which is used to monitor the load of each processing node and dynamically allocate tasks to avoid overloading of certain unit nodes, which would cause a decrease in the overall processing speed; Resource management, which is used to reasonably allocate CPU, memory, and I / O resources to ensure that each task can run efficiently.

[0015] In the above technical solution, further, data preprocessing includes: Data cleaning and conversion: The data cleaning and conversion is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management unit, reducing the complexity and time of subsequent processing; Incremental update: The incremental update is used for dynamic data sources, using an incremental update method to avoid full data processing.

[0016] The beneficial effects of the present invention are: The hardware acceleration system for data processing solves the problems of existing hardware accelerators being usually optimized for specific tasks and difficult to adapt to various data processing needs through reasonable coordination of processing units, storage units, interface units, intelligent learning and optimization processing units; high power consumption: under high load conditions, the energy consumption of existing systems increases significantly, resulting in increased operating costs; and low integration: existing solutions often require multiple different hardware units, resulting in increased system complexity and difficult maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An overview of a hardware acceleration system for data processing is shown; Figure 2 A schematic diagram of the structure of a processing unit processing hardware accelerated data processing is shown; Figure 3 A schematic diagram of the structure of hardened optimized hardware accelerated data processing is shown; Figure 4 A schematic diagram of the data preprocessing hardware acceleration data processing structure is shown; Figure 5 A schematic diagram of the data transmission processing hardware acceleration data processing structure is shown; Figure 6 A schematic diagram of the structure of the scheduling management unit processing hardware accelerated data processing is shown. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the terms used herein are only for describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. For ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be regarded as part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0021] It should be noted that, in the description of the present application, the orientation or positional relationship indicated by terms such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise stated, these orientation words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present application; the orientation words "inside and outside" refer to the inside and outside relative to the contour of each component itself.

[0022] It should be noted that, in the present application, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0023] Embodiment 1: See also Figure 1-6 As shown in the figure, this embodiment provides a hardware acceleration system for data processing, including: The processing unit uses a combination of field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) to accelerate different data processing tasks. FPGAs use FPGAs to implement programmable computing cores to adapt to different algorithm requirements, while application-specific integrated circuits (ASICs) process specific tasks through ASIC modules to improve performance. The storage unit specifically includes cache optimization, hardware optimization and task result cache. The hardware optimization is used to classify and process different data. The task result cache is used to cache the processed task results to avoid repeated calculations. Interface unit, which provides multiple data transmission interfaces, such as PCIe, Ethernet, etc., and supports high-speed data exchange with external devices; The scheduling management unit specifically includes an optimization algorithm unit and load balancing, and is used to dynamically allocate resources according to task types and optimize system performance; Data preprocessing, which is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management module to reduce the complexity and time of subsequent processing; The intelligent learning and optimization processing unit is used to use machine learning algorithms to intelligently schedule data processing, optimize resource utilization, and predict data processing needs in advance by analyzing historical data, optimize resource allocation, and analyze system load conditions using machine learning algorithms. It optimizes resource allocation according to real-time task requirements and improves the system's processing power and energy efficiency. It solves the problems that existing hardware accelerators are usually optimized for specific tasks and are difficult to adapt to a variety of data processing requirements. The unit has high power consumption: under high load conditions, the energy consumption of existing systems increases significantly, resulting in increased operating costs; and low integration: existing solutions often require multiple different hardware units, resulting in increased system complexity and difficult maintenance.

[0024] Embodiment 2: This embodiment provides a hardware acceleration system for data processing. In addition to the technical solutions of the above embodiments, it also has the following technical features: the programmable logic device (FPGA) can be configured to accelerate matrix operations in machine learning, while the application-specific integrated circuit (ASIC) is used for video encoding, which can concentrate on optimizing specific tasks and adapt to various data processing needs.

[0025] This embodiment provides a hardware acceleration system for data processing. In addition to the technical solutions of the above embodiments, it also has the following technical features: the cache optimization utilizes RAM for caching to reduce the read and write operations on the hard disk, sets an appropriate cache size to adjust the cache settings of the application to improve data processing efficiency, reduce operation under high load conditions, significantly reduce the system's energy consumption, and avoid rising operating costs.

[0026] Embodiment 4: This embodiment provides a hardware acceleration system for data processing, which, in addition to the technical solutions of the above embodiments, also has the following technical features, wherein the hardware optimization includes: A hard disk (HDD), wherein the hard disk (HDD) is used to process conventional simple data or data with a small memory; Solid-state drive (SSD), which is used to process important data or data that takes up a large amount of memory. Using the solid-state drive (SSD) to replace the traditional hard disk (HDD) has a faster read and write speed, which can greatly improve the data access speed, improve the data read and write speed, and reduce I / O bottlenecks; The NVMe protocol, which is used for SSDs, provides higher bandwidth and lower latency compared to traditional SATA SSDs.

[0027] Embodiment 5: This embodiment provides a hardware acceleration system for data processing. In addition to the technical solutions of the above embodiments, it also has the following technical features: the interface unit is used to support standard data transmission protocols to ensure compatibility with various external devices; at the same time, a high-bandwidth transmission interface, such as PCIe4.0, is used to ensure that the data transmission rate meets the needs of large-scale data processing.

[0028] Embodiment 6: This embodiment provides a hardware acceleration system for data processing, which, in addition to the technical solutions of the above embodiments, also has the following technical features. The data preprocessing includes: Data transmission adopts RESTful API design, designs concise and efficient APIs, uses appropriate HTTP methods, avoids unnecessary data transmission, and uses protocol optimization: consider using lighter protocols (such as gRPC, Thrift) to replace traditional RESTful APIs.

[0029] Embodiment 7: This embodiment provides a hardware acceleration system for data processing, which, in addition to the technical solutions of the above embodiments, also has the following technical features, wherein the optimization algorithm unit includes: An efficient scheduling algorithm unit, which is used in shortest job first (SJF), priority scheduling or round robin scheduling, can reduce the waiting time of tasks and improve the overall performance of the system; Dynamic scheduling, which is used to dynamically adjust the scheduling strategy according to real-time load and task characteristics to cope with different operating environments; Parallel processing includes distributed computing and task parallelization. Distributed computing is used to distribute data processing tasks to multiple nodes using distributed computing frameworks (such as Apache Hadoop and Apache Spark) to improve processing speed. Task parallelization is used to split data processing tasks into multiple subtasks and use multi-threaded or multi-process parallel processing to fully utilize the performance of multi-core CPUs, solving the problem of requiring multiple different hardware units, resulting in increased system complexity and difficult maintenance.

[0030] Embodiment 8: This embodiment provides a hardware acceleration system for data processing, which, in addition to the technical solutions of the above embodiments, also has the following technical features, wherein the load balancing includes: Dynamic load balancing, which is used to monitor the load of each processing node and dynamically allocate tasks to avoid overloading of certain unit nodes, which would cause a decrease in the overall processing speed; Resource management, which is used to reasonably allocate CPU, memory, and I / O resources to ensure that each task can run efficiently.

[0031] Embodiment 9: This embodiment provides a hardware acceleration system for data processing, which, in addition to the technical solutions of the above embodiments, also has the following technical features. The data preprocessing includes: Data cleaning and conversion: The data cleaning and conversion is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management unit, reducing the complexity and time of subsequent processing; Incremental update: The incremental update is used for dynamic data sources. It adopts the incremental update method to avoid full data processing, avoid running under high load conditions, and prevent the system's energy consumption from increasing significantly, leading to increased operating costs.

[0032] The embodiments of the present application are described above in conjunction with the accompanying drawings. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A hardware acceleration system for data processing, characterized in that: include: The processing unit uses a combination of field-programmable logic devices (FPGAs) and application-specific integrated circuits (ASICs) to accelerate different data processing tasks; Programmable FPGA (FPGA) uses FPGA to implement programmable computing cores to adapt to different algorithm requirements. At the same time, application-specific integrated circuits (ASIC) process specific tasks through ASIC modules to improve performance; The storage unit specifically includes cache optimization, hardware optimization and task result cache. The hardware optimization is used to classify and process different data. The task result cache is used to cache the processed task results to avoid repeated calculations. Interface unit, which provides multiple data transmission interfaces, such as PCIe, Ethernet, etc., and supports high-speed data exchange with external devices; The scheduling management unit specifically includes an optimization algorithm unit and load balancing, and is used to dynamically allocate resources according to task types and optimize system performance; Data preprocessing, which is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management module to reduce the complexity and time of subsequent processing; The intelligent learning and optimization processing unit is used to use machine learning algorithms to intelligently schedule data processing, optimize resource utilization, and predict data processing needs in advance by analyzing historical data to optimize resource allocation.

2. The hardware acceleration system for data processing according to claim 1, characterized in that: The field-programmable gate array (FPGA) can be configured to accelerate matrix operations in machine learning, while the application-specific integrated circuit (ASIC) is used for video encoding.

3. The hardware acceleration system for data processing according to claim 1, characterized in that: The cache optimization utilizes RAM for caching to reduce the read and write operations to the hard disk, and sets an appropriate cache size to adjust the cache settings of the application to improve data processing efficiency.

4. The hardware acceleration system for data processing according to claim 1, characterized in that: The hardware optimization includes: A hard disk (HDD), wherein the hard disk (HDD) is used to process conventional simple data or data with a small memory; Solid-state drive (SSD), which is used to process important data or data that takes up a large amount of memory. Using the solid-state drive (SSD) to replace the traditional hard disk (HDD) has a faster read and write speed, which can greatly improve the data access speed, improve the data read and write speed, and reduce I / O bottlenecks; The NVMe protocol, which is used for SSDs, provides higher bandwidth and lower latency compared to traditional SATA SSDs.

5. The hardware acceleration system for data processing according to claim 1, characterized in that: The interface unit is used to support standard data transmission protocols to ensure compatibility with various external devices; at the same time, a high-bandwidth transmission interface, such as PCIe4.0, is adopted to ensure that the data transmission rate meets the needs of large-scale data processing.

6. The hardware acceleration system for data processing according to claim 1, characterized in that: The data preprocessing includes: Data transmission adopts RESTful API design, designs concise and efficient APIs, uses appropriate HTTP methods, avoids unnecessary data transmission, and uses protocol optimization: consider using lighter protocols (such as gRPC, Thrift) to replace traditional RESTful APIs.

7. The hardware acceleration system for data processing according to claim 1, characterized in that: The optimization algorithm unit comprises: An efficient scheduling algorithm unit, which is used in shortest job first (SJF), priority scheduling or round robin scheduling, can reduce the waiting time of tasks and improve the overall performance of the system; Dynamic scheduling, which is used to dynamically adjust the scheduling strategy according to real-time load and task characteristics to cope with different operating environments; Parallel processing includes distributed computing and task parallelization. Distributed computing is used to distribute data processing tasks to multiple nodes using distributed computing frameworks (such as Apache Hadoop and Apache Spark) to improve processing speed. Task parallelization is used to split data processing tasks into multiple subtasks and use multi-threading or multi-process parallel processing to fully utilize the performance of multi-core CPUs.

8. The hardware acceleration system for data processing according to claim 1, characterized in that: The load balancing includes: Dynamic load balancing, which is used to monitor the load of each processing node and dynamically allocate tasks to avoid overloading of certain unit nodes, which would cause a decrease in the overall processing speed; Resource management, which is used to reasonably allocate CPU, memory, and I / O resources to ensure that each task can run efficiently.

9. The hardware acceleration system for data processing according to claim 1, characterized in that: The data preprocessing includes: Data cleaning and conversion: The data cleaning and conversion is used to perform necessary data cleaning and preprocessing before the data enters the scheduling management unit, reducing the complexity and time of subsequent processing; Incremental update: The incremental update is used for dynamic data sources, using an incremental update method to avoid full data processing.

Images