Computing system, information management method, equipment, medium and program product

Abstract

The invention discloses a computing system, an information management method, equipment, a medium and a program product in the technical field of computers. The invention provides a complex computing system comprising a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device, and a pooling management controller in the system can construct a device allocation table corresponding to each host in the host resource pool. And enabling each host to store the equipment information which is identified by the own basic input / output system and is not recorded in the received equipment distribution table into the first file, and storing the equipment information in the received equipment distribution table into the second file, so that the equipment information displayed on the host side is consistent with the equipment actually controlled by the host.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a computing system, information management method, device, medium and program product. Background Art

[0002] In complex computing systems, the computing devices and storage devices that a host can control will be flexibly adjusted according to actual conditions. However, it is difficult for the host to identify the adjusted devices after it is turned on, resulting in inconsistency between the device information displayed on the host side and the device information actually controlled by the host.

[0003] Therefore, how to achieve consistency between the device information displayed on the host side and the devices actually controlled by the host is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a computing system, information management method, device, medium and program product to achieve consistency between the device information displayed on the host side and the devices actually managed by the host. The specific scheme is as follows:

[0005] In a first aspect, the present invention provides a computing system, comprising: a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device; the host resource pool comprises: a plurality of hosts; the management resource pool comprises: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool comprises: a plurality of computing devices; the storage resource pool comprises: a plurality of storage devices;

[0006] The network switching device is connected to each host, the pooling management controller, each computing device and each storage device; the switching manager is connected to each host, each computing device and each storage device;

[0007] The pooling management controller is used to: construct a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device; and send the device allocation table corresponding to each host to the corresponding host;

[0008] Each host is used to: store the device information recognized by its own basic input and output system but not recorded in the received device allocation table into the first file, and store the device information in the received device allocation table into the second file.

[0009] Optionally, the exchange manager and each host, the exchange manager and each computing device, and the exchange manager and each storage device are connected via the same type of connector.

[0010] Optionally, the switching manager includes: a first switching chip and a plurality of second switching chips; a plurality of buses are provided between the first switching chip and the plurality of second switching chips;

[0011] Correspondingly, the pooling management controller is connected to the plurality of second switching chips through the first switching chip and the plurality of buses; the upstream port of each second switching chip is connected to the corresponding host, and the downstream port is connected to the corresponding computing device and storage device; the second switching chips are interconnected in pairs;

[0012] Correspondingly, the pooled management controller is used to: receive, through the first switching chip and the multiple second switching chips, the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device.

[0013] Optionally, each port of each second switching chip is connected to a corresponding connector port; one connector port is correspondingly connected to one host or one computing device or one storage device.

[0014] Optionally, each computing device is used to: after startup, use the second baseboard management controller in itself to identify and establish a mapping relationship between identification information of its own connector port and identification information of the connector port of the second switching chip connected to the corresponding connector port.

[0015] Optionally, the pooling management controller is used to manage the temperature, traffic, port type and routing information of the plurality of second switching chips through the first switching chip.

[0016] Optionally, the pooling management controller is used to: configure routing registers in the plurality of second switching chips through the first switching chip to update allocation relationships between hosts connected to corresponding second switching chips and computing devices and storage devices.

[0017] Optionally, the pooling management controller is used to: read routing registers in the plurality of second switching chips through the first switching chip to obtain allocation relationships between hosts connected to corresponding second switching chips and computing devices and storage devices.

[0018] Optionally, the pooling management controller is used to: compare the device allocation table corresponding to each host with the allocation relationship obtained by reading the routing registers in the multiple second switching chips; if the two are consistent, send the device allocation table corresponding to each host to the corresponding host; if they are inconsistent, update the device allocation table corresponding to each host according to the allocation relationship obtained by reading the routing registers in the multiple second switching chips, and then send the device allocation table corresponding to each host to the corresponding host.

[0019] Optionally, the pooled management controller is used to receive and manage the IP address broadcast by the first baseboard management controller in each host, the IP address broadcast by the second baseboard management controller in each computing device, and the IP address broadcast by the third baseboard management controller in each storage device.

[0020] Optionally, each host is used to, after startup, use its own basic input and output system to enumerate and obtain a device information table corresponding to the current host.

[0021] Optionally, the second baseboard management controller in each computing device is used to monitor and record the first device information of the corresponding computing device in an out-of-band manner.

[0022] Optionally, the third baseboard management controller in each storage device is used to monitor and record the second device information of the corresponding storage device in an out-of-band manner.

[0023] Optionally, the first baseboard management controller in each host is used to display the first file and the second file.

[0024] Optionally, the pooling management controller is used to: display a device allocation table corresponding to each host.

[0025] Optionally, each host is used to: send the execution task to the device in the corresponding device allocation table according to its corresponding device allocation table.

[0026] In a second aspect, the present invention provides an information management method, which is applied to a computing system, wherein the computing system comprises: a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device; the host resource pool comprises: a plurality of hosts; the management resource pool comprises: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool comprises: a plurality of computing devices; the storage resource pool comprises: a plurality of storage devices;

[0027] The network switching device is connected to each host, the pooling management controller, each computing device and each storage device; the switching manager is connected to each host, each computing device and each storage device;

[0028] Accordingly, the information management method includes:

[0029] The pooling management controller constructs a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device; and sends the device allocation table corresponding to each host to the corresponding host;

[0030] Each host stores the device information recognized by its own basic input and output system but not recorded in the received device allocation table in the first file, and stores the device information in the received device allocation table in the second file.

[0031] In a third aspect, the present invention provides an electronic device, comprising:

[0032] Memory for storing computer programs;

[0033] The processor is used to execute the computer program to implement the aforementioned disclosed information management method.

[0034] In a fourth aspect, the present invention provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed information management method when executed by a processor.

[0035] In a fifth aspect, the present invention provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed information management method when executed by a processor.

[0036] In a sixth aspect, the present invention provides an information management method, which is applied to a pooled management controller, wherein the pooled management controller is provided in a computing system, wherein the computing system comprises: a host resource pool, a management resource pool, and a network switching device; the host resource pool comprises: a plurality of hosts; the management resource pool comprises: a pooled management controller and a switching manager connected to the pooled management controller;

[0037] Wherein, the network switching device connects each host and the pooling management controller; the switching manager connects each host;

[0038] The method includes:

[0039] According to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device connected to the pooling management controller, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device connected to the pooling management controller, construct a device allocation table corresponding to each host respectively;

[0040] The device allocation table corresponding to each host is sent to the corresponding host, so that each host stores the device information recognized by its basic input and output system but not recorded in the received device allocation table in the first file, and stores the device information in the received device allocation table in the second file.

[0041] It can be seen from the above scheme that the present invention provides a computing system, including: a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device; the host resource pool includes: a plurality of hosts; the management resource pool includes: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool includes: a plurality of computing devices; the storage resource pool includes: a plurality of storage devices; wherein the network switching device is connected to each host, the pooled management controller, each computing device and each storage device; the switching manager is connected to each host, each computing device and each storage device; the pooled management controller is used to: construct a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device; send the device allocation table corresponding to each host to the corresponding host; each host is used to: store the device information recognized by its own basic input and output system that is not recorded in the received device allocation table to the first file, and store the device information in the received device allocation table to the second file.

[0042] It can be seen that the beneficial effects of the present invention are: for a complex computing system including a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device, the pooled management controller in the system can construct a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device, so that each host stores the device information recognized by its own basic input and output system that is not recorded in the received device allocation table to the first file, and stores the device information in the received device allocation table to the second file, so that the device information displayed on the host side and the equipment actually controlled by the host can be kept consistent.

[0043] Correspondingly, an information management method, device, medium and program product provided by the present invention also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a computing system disclosed in the present invention;

[0046] Figure 2 A flow chart of an information management method disclosed in the present invention;

[0047] Figure 3 A schematic diagram of another computing system disclosed in the present invention;

[0048] Figure 4 This is a flow chart of another information management method disclosed in the present invention;

[0049] Figure 5 A flow chart of another information management method disclosed in the present invention;

[0050] Figure 6 A server structure diagram provided by the present invention;

[0051] Figure 7 A terminal structure diagram provided by the present invention;

[0052] Figure 8A schematic diagram of the connection between a pooling management controller, an I2C Switch chip, and a PCIe switch chip disclosed in the present invention;

[0053] Fig. 9 The present invention discloses a schematic diagram of interconnecting two different PCIe switch chips. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] At present, in complex computing systems, the computing devices and storage devices that a host can control will be flexibly adjusted according to actual conditions, but it is difficult for the host to identify the adjusted devices after it is turned on, resulting in inconsistency between the device information displayed on the host side and the device information actually controlled by the host. To this end, the present invention provides an information management solution that can achieve consistency between the device information displayed on the host side and the devices actually controlled by the host.

[0056] See also Figure 1 As shown, an embodiment of the present invention discloses a computing system, including: a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device; the host resource pool includes: a plurality of hosts; the management resource pool includes: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool includes: a plurality of computing devices; the storage resource pool includes: a plurality of storage devices.

[0057] The network switching device connects various hosts, the pooled management controller, various computing devices, and various storage devices; the switching manager connects various hosts, various computing devices, and various storage devices.

[0058] In a computing system, a pooled management controller is used to: construct a device allocation table corresponding to each host according to a device information table corresponding to the corresponding host sent by a first baseboard management controller in each host, first device information of the corresponding computing device sent by a second baseboard management controller in each computing device, and second device information of the corresponding storage device sent by a third baseboard management controller in each storage device; and send the device allocation table corresponding to each host to the corresponding host.

[0059] In the computing system, each host is used to: store the device information recognized by its basic input and output system but not recorded in the received device allocation table into the first file, and store the device information in the received device allocation table into the second file.

[0060] In this embodiment, a computing device includes multiple computing cores, such as GPU, FPGA, etc.

[0061] In one embodiment, the switch manager and each host, the switch manager and each computing device, and the switch manager and each storage device are connected through the same type of connector (such as CDFP). The switch manager includes: a first switch chip and multiple second switch chips; accordingly, the pooling management controller is connected to multiple second switch chips through the first switch chip; and multiple second switch chips are connected to each computing device and each storage device.

[0062] In one implementation, each second switching chip is provided with a plurality of connector ports; one connector port is correspondingly connected to one computing device or one storage device; that is to say, the computing device or the storage device is also provided with a corresponding connector port.

[0063] Specifically, the switching manager includes: a first switching chip and a plurality of second switching chips; a plurality of buses are provided between the first switching chip and the plurality of second switching chips; accordingly, the pooling management controller connects the plurality of second switching chips through the first switching chip and the plurality of buses; the upstream port of each second switching chip is connected to the corresponding host, and the downstream port is connected to the corresponding computing device and storage device; each second switching chip is interconnected in pairs; accordingly, the pooling management controller is used to: receive the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device through the first switching chip and the plurality of second switching chips. Each port of each second switching chip is connected to a corresponding connector port; one connector port is correspondingly connected to one host, one computing device, or one storage device.

[0064] In one embodiment, each computing device is used to: after startup, use the second baseboard management controller in itself to identify and establish a mapping relationship between the identification information of its own connector port and the identification information of the connector port of the second switching chip connected to the corresponding connector port.

[0065] In one implementation, the pooling management controller is used to manage the temperature, traffic, port type, and routing information of a plurality of second switching chips through the first switching chip.

[0066] In one embodiment, the pooling management controller is used to: configure routing registers in multiple second switching chips through the first switching chip to update the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device.

[0067] In one implementation, the pooling management controller is used to: read routing registers in multiple second switching chips through the first switching chip to obtain allocation relationships between hosts connected to corresponding second switching chips and computing devices and storage devices.

[0068] In one embodiment, the pooling management controller is used to: compare the device allocation table corresponding to each host with the allocation relationship obtained by reading the routing registers in multiple second switching chips; if the two are consistent, the device allocation table corresponding to each host is sent to the corresponding host; if they are inconsistent, the device allocation table corresponding to each host is updated according to the allocation relationship obtained by reading the routing registers in multiple second switching chips, and then the device allocation table corresponding to each host is sent to the corresponding host.

[0069] In one embodiment, the pooled management controller is used to receive and manage the IP address broadcast by the first baseboard management controller in each host, the IP address broadcast by the second baseboard management controller in each computing device, and the IP address broadcast by the third baseboard management controller in each storage device.

[0070] In one implementation, each host is used to, after being powered on, use its own basic input / output system to enumerate and obtain a device information table corresponding to the current host.

[0071] In one implementation, the second baseboard management controller in each computing device is used to monitor and record the first device information of the corresponding computing device in an out-of-band manner.

[0072] In one implementation, the third baseboard management controller in each storage device is used to monitor and record the second device information of the corresponding storage device in an out-of-band manner.

[0073] In one embodiment, the first baseboard management controller in each host is used to display the first file and the second file. Correspondingly, the pooling management controller is used to display the device allocation table corresponding to each host.

[0074] In one implementation, each host is used to send execution tasks to devices in the corresponding device allocation table according to its corresponding device allocation table.

[0075] It can be seen that in this embodiment, for a complex computing system including a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device, the pooled management controller in the system can construct a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device, so that each host stores the device information recognized by its own basic input and output system that is not recorded in the received device allocation table in the first file, and stores the device information in the received device allocation table in the second file, so that the device information displayed on the host side and the devices actually controlled by the host can be kept consistent.

[0076] An information management method provided by an embodiment of the present invention is introduced below. The information management method described below can be referenced to other embodiments described in this document.

[0077] The embodiment of the present invention discloses an information management method, which is applied to a computing system, wherein the computing system includes: a host resource pool, a management resource pool, a computing resource pool, a storage resource pool and a network switching device; the host resource pool includes: a plurality of hosts; the management resource pool includes: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool includes: a plurality of computing devices; the storage resource pool includes: a plurality of storage devices. The network switching device connects each host, the pooled management controller, each computing device and each storage device; the switching manager connects each host, each computing device and each storage device.

[0078] Correspondingly, an embodiment of the present invention also discloses an information management method, which is applied to a pooled management controller. The pooled management controller is arranged in a computing system, and the computing system includes: a host resource pool, a management resource pool and a network switching device; the host resource pool includes: multiple hosts; the management resource pool includes: a pooled management controller and a switching manager connected to the pooled management controller; wherein the network switching device connects each host and the pooled management controller; and the switching manager connects each host.

[0079] Specifically, the method applied to the pooled management controller includes: constructing a device allocation table corresponding to each host according to a device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, first device information of the corresponding computing device sent by the second baseboard management controller in each computing device connected to the pooled management controller, and second device information of the corresponding storage device sent by the third baseboard management controller in each storage device connected to the pooled management controller; sending the device allocation table corresponding to each host to the corresponding host, so that each host stores the device information recognized by its own basic input and output system but not recorded in the received device allocation table in the first file, and stores the device information in the received device allocation table in the second file.

[0080] In this embodiment, the switch manager and each host, the switch manager and each computing device, and the switch manager and each storage device are connected through the same type of connector (such as CDFP). The switch manager includes: a first switch chip and multiple second switch chips; accordingly, the pooled management controller is connected to multiple second switch chips through the first switch chip; multiple second switch chips are connected to each computing device and each storage device. Correspondingly, each second switch chip is provided with multiple connector ports; one connector port corresponds to one computing device or one storage device; that is to say: the computing device or storage device is also provided with a corresponding connector port.

[0081] In one embodiment, after being powered on, each computing device uses its own second baseboard management controller to identify and establish a mapping relationship between identification information of its own connector port and identification information of the connector port of the second switching chip connected to the corresponding connector port.

[0082] See also Figure 2 , the information management method disclosed in the embodiment of the present invention includes:

[0083] S201, the pooling management controller builds a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device; and sends the device allocation table corresponding to each host to the corresponding host.

[0084] S202. Each host stores the device information recognized by its own basic input and output system but not recorded in the received device allocation table in a first file, and stores the device information in the received device allocation table in a second file.

[0085] In one embodiment, the pooling management controller further performs the following steps: managing the temperature, flow, port type and routing information of multiple second switching chips through the first switching chip. The routing registers in multiple second switching chips are configured through the first switching chip to update the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device. The routing registers in multiple second switching chips are read through the first switching chip to obtain the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device. The device allocation table corresponding to each host is compared with the allocation relationship obtained by reading the routing registers in multiple second switching chips; if the two are consistent, the device allocation table corresponding to each host is sent to the corresponding host; if they are inconsistent, the device allocation table corresponding to each host is updated according to the allocation relationship obtained by reading the routing registers in multiple second switching chips, and then the device allocation table corresponding to each host is sent to the corresponding host. Receive and manage the IP address broadcasted by the first baseboard management controller in each host, the IP address broadcasted by the second baseboard management controller in each computing device, and the IP address broadcasted by the third baseboard management controller in each storage device.

[0086] In one implementation, after each host is powered on, it uses its own basic input / output system to enumerate and obtain a device information table corresponding to the current host.

[0087] In one implementation, the second baseboard management controller in each computing device monitors and records the first device information of the corresponding computing device in an out-of-band manner.

[0088] In one implementation, the third baseboard management controller in each storage device monitors and records the second device information of the corresponding storage device in an out-of-band manner.

[0089] In one embodiment, the first baseboard management controller in each host also displays the first file and the second file. Correspondingly, the pooling management controller also displays the device allocation table corresponding to each host.

[0090] It can be seen that the information management method provided in this embodiment enables the host to obtain the device table obtained by BIOS enumeration and the downstream computing devices and storage devices actually controlled by the host collected by the pooled management controller, thereby solving the problem of inconsistency between the device information displayed on the host side and the devices actually controlled by the host.

[0091] See also Figure 3, another computing system under the fusion architecture includes: 1 IO Box (i.e. 1 IO resource pool), 2 GPU Boxes (i.e. 2 computing devices), 2 NVME Boxes (i.e. 2 storage devices) and 8 Host Boxes (i.e. 8 hosts). Each Box is designed with a BMC (Baseboard Management Controller) module to manage the corresponding Box. The BMC firmware adopts the OpenBMC architecture. All BMCs are connected to the same network switch to form an internal LAN. The BMC in the IO Box is the Pooled System Management Controller PSMC (Pooled System Management Controller). The PSMC can communicate with the BMCs in each Box through the network to realize the management and control functions of the entire system.

[0092] The IO Box contains 4 layers of PCIe Switch boards, each of which has two PCIe Switch chips (i.e., the second switch chip) to expand, network, and distribute the PCIe resources of multiple CPUs in the Host Box. The PCIe Switch chip can expand a set of PCIe signals into multiple sets of PCIe signals for expanding CPU IO resources. Each PCIe Switch chip leads to 5 CDFP connector ports (high-speed signal ports), and the entire IO Box can ultimately provide 8×5=40 CDFP ports to the outside. Each device Box is also equipped with a corresponding CDFP port, and the device Box is connected to the IO Box via a CDFP cable.

[0093] PSMC is connected to the aforementioned 8 PCIe Switch chips through an I2C link (the I2C link is provided with a first switching chip I2C Switch). The PCIe Switch firmware provides basic functions for reading and writing registers. PSMC sends I2C commands to the 8 PCIe Switch firmwares to read and write the internal registers of the 8 managed chips, thereby achieving unified management and configuration of all PCIe Switch chips. For example, it can monitor the PCIe Switch chip temperature, port traffic information, modify port type, device routing information, etc. in real time.

[0094] It should be noted that the converged architecture can decouple the entire system into different independent pooled modules. In the converged architecture cabinet, these independent pooled modules exist in the form of separate Boxes. In the converged architecture cabinet, all IO resources are concentrated in one IO Box, and the device Boxes are mounted under the IO Box. There are multiple high-speed signal ports on the IO Box and the device Box. The high-speed signal port on the device Box is connected to the IO Box through a connector to achieve high-speed signal transmission. The GPU and NVME resources of the entire system can be dynamically allocated and managed through the pooled management controller PSMC in the IO Box to meet the configuration requirements of different hosts.

[0095] The hardware devices included in a Host Box, such as CPU, memory, GPU, NVME, etc., are all in one chassis. When the host in the chassis is turned on, the Host BIOS will send the identified device asset information to the Host BMC. The Host BMC parses the device asset information sent by the Host BIOS and displays it. The dynamic allocation of GPU and NVME resources of the entire system is such as: allocating unallocated GPUs and NVME devices in the device resource pool (such as the computing resource pool or the storage resource pool) to a certain host; or removing some GPUs and NVME devices allocated under Host0 and allocating them to other hosts. After dynamic allocation, since each Host will not restart, the Host BIOS cannot recognize the new GPU and NVME devices. For this reason, this embodiment uses PSMC to collect device information.

[0096] In this embodiment, the PSMC and the device Box BMC support the LLDP function to discover downstream devices using the Link Layer Discovery Protocol (LLDP). After the device Box is powered on, the Box BMC broadcasts its own management IP information so that it can be discovered by the PSMC. The PSMC manages the IP and Box number information of all the device Box BMCs in the cabinet so that the PSMC can communicate with each device Box BMC through the network.

[0097] In this embodiment, the eight PCIe Switch chips are fully interconnected. The upstream is connected to the Host Box via a CDFP cable, and the downstream is connected to the GPU Box or NVMe Box via a CDFP cable. PSMC sends I2C commands to the eight PCIe Switch firmware to read and write registers inside the chip, and can configure the PCIe Switch chip port type, upstream and downstream Fabric interconnection, etc.

[0098] In order to maintain the allocation relationship between the IO resource devices and the Host of the entire system, the above hardware is software numbered according to the following example:

[0099] Host_ID: Host ID, which is set according to the U positions of the eight hosts in the cabinet, namely Host0 to Host7.

[0100] DeviceBox_ID: GPU Box and NVMEBox ID. According to the U position setting of the device Box in the cabinet, the two GPUBoxes are GPUBox0 and GPUBox1, and the two NVMe Boxes are NVMeBox0 and NVMeBox1.

[0101] Switch_CDFP_ID: 40 CDFP port numbers on the IO Box. Each CDFP port has an identification chip to store the port number. Each port number is unique and is defined as follows:

[0102] The port numbers of the four ports included in the PCIe Switch chip 1 of the first layer are: 00, 01, 02, 03, 04; the port numbers of the four ports included in the PCIe Switch chip 2 of the first layer are: 10, 11, 12, 13, 14.

[0103] The port numbers of the four ports included in the second-layer PCIe Switch chip 2 are: 20, 21, 22, 23, 24; the port numbers of the four ports included in the second-layer PCIe Switch chip 2 are: 30, 31, 32, 33, 34.

[0104] The port numbers of the four ports included in the third-layer PCIe Switch chip 2 are: 40, 41, 42, 43, 44; the port numbers of the four ports included in the third-layer PCIe Switch chip 2 are: 50, 51, 52, 53, 54.

[0105] The port numbers of the four ports included in the PCIe Switch chip 2 of the fourth layer are: 60, 61, 62, 63, 64; the port numbers of the four ports included in the PCIe Switch chip 2 of the fourth layer are: 70, 71, 72, 73, 74.

[0106] Switch_ID: The number of the switch chip defined in the PCIe Switch BOX, ranging from 0 to 7.

[0107] Switch_PortID: The port number of a single PCIe Switch chip defined in the PCIe Switch firmware, such as 0x200060, which corresponds to a set of registers inside the Switch chip.

[0108] Box_CDFP_ID: The 16 CDFP port numbers on the GPU Box are CDFP0-CDFP15; the 12 CDFP port numbers on the NVME Box are CDFP0-CDFP11.

[0109] After the software number is defined, the fixed mapping relationship between the hardware is configured in the PSMC configuration file based on the hardware design. The fixed mapping relationship between the hardware is as follows: (1) The mapping relationship between the CDFP port number (Switch_CDFP_ID) and the Switch chip port number (Switch_ PortID) on the IO Box; (2) The mapping relationship between the CDFP port number (Box_CDFP_ID) and the GPU slot silk screen (Location) in the GPU Box; (3) The mapping relationship between the CDFP port number (Box_CDFP_ID) and the NVMe slot silk screen (Location) in the NVMe Box.

[0110] There are three uncertain mapping relationships: (1) The internal Fabric interconnection relationship between the Switch chip port numbers (Switch_Port) maintained by the PCIe Switch firmware. (2) The mapping relationship between the Switch chip port numbers (Switch_Port) maintained by the PCIe Switch firmware and the GPU or NVMe device BDF information. (3) The mapping relationship between the CDFP port number (Switch_CDFP_ID) on the IO Box and the Host number (Host_ID) is fixed, but the mapping relationship with the CDFP port (Box_CDFP_ID) on the GPU Box and NVMe Box is uncertain. Among the uncertain mapping relationships, (1) and (2) are maintained by the PCIe Switch firmware and are affected by the allocation relationship between the GPU, NVMe device and Host. The PSMC obtains it from the PCIe Switch firmware through I2C commands. (3) It is affected by the connection between the CDFP ports, that is, the connection between the CDFP port on the IO Box and the CDFP port on the Host is fixed, but the connection between the CDFP port on the GPU Box and the NVMe Box is uncertain. The number of connections between the CDFP port on the IO Box and the CDFP port on the GPU Box and NVMe Box can be adjusted as needed. The BMC in the GPU Box and NVMe Box needs to identify the CDFP port identification chip on the IO Box through I2C, read the port number (Switch_CDFP_ID) stored in it, and report the mapping relationship between Switch_CDFP_ID and Box_CDFP_ID to the PSMC.

[0111] PSMC summarizes and processes the above mapping relationships to establish a distribution relationship table of GPU, NVMe devices and Host. The distribution relationship table is shown in the following Json format data structure example, which can clearly show which GPU devices in which GPU Boxes and which NVME devices in which NVME Boxes are allocated under a Host.

[0112] The allocation relationship table of the Json format data structure example:

[0113] {

[0114] "Host_ID": "Host0",

[0115] "IP": "100.2.74.43",

[0116] "Switch_CDFP_ID": "CDFP0-0",

[0117] "Switch_Port": "0x000040",

[0118] "Devices": [

[0119] {

[0120] "DeviceBox_ID": "GPUBox0",

[0121] "Switch_CDFP_ID": "CDFP0-1",

[0122] "Switch_Port": "0x000050",

[0123] "Box_CDFP_ID": "CDFP0",

[0124] "Location": "GPU3",

[0125] "BusNumber": XX,

[0126] "DeviceNumber": XX,

[0127] "FunctionNumber": XX

[0128] },

[0129] {

[0130] "DeviceBox_ID": "NVMEBox0",

[0131] "Switch_CDFP_ID": "CDFP3-2",

[0132] "Switch_Port": "0x400060",

[0133] "Box_CDFP_ID": "CDFP0",

[0134] "BusNumber": XX,

[0135] "DeviceNumber": XX,

[0136] "FunctionNumber": XX,

[0137] "Location": "NVMe0, NVMe1"

[0138] } ]

[0140] }

[0141] In one example, PSMC also provides a display interface and Redfish interface for implementing the allocation and adjustment of GPU and NVMe resources. For example, when GPU0 is removed from Host0 and allocated to Host1, it is necessary to call I2C commands through the Redfish interface to interact with the PCIe Switch firmware and set the corresponding PCIe Switch related registers to configure the routing relationship; after the setting is successful, PSMC updates the allocation relationship table of GPU, NVMe devices and Host to ensure the accuracy of the allocation relationship.

[0142] In the converged architecture system, each Box is powered on collaboratively by sending instructions to the PSMC. The PSMC first sends a power-on instruction to the GPU Box and NVMe Box. After the GPU Box and NVMe Box are successfully powered on, the PSMC sends a power-on instruction to the Host.

[0143] For GPU Box and NVME Box, after each Box is powered on, the Box BMC scans the I2C channel where each CDFP port is located in turn, identifies the CDFP port identification chip on the IO Box side, reads the CDFP port identifier (Switch_CDFP_ID), and establishes a mapping relationship between Switch_CDFP_ID and Box_CDFP_ID.

[0144] For GPU Box and NVME Box, after each Box is powered on, the BMC in the Box obtains the asset information of GPU or NVME through the I2C link. Taking GPU Box as an example, add the gpu-manager module in the BMC firmware to monitor the 16 GPU devices in the Box out-of-band, and configure the correspondence between the I2C virtual bus number of each GPU device, the GPU silk screen, and the CDFP port number on the Box in the file.

[0145] The information monitored by the gpu-manager module can be found in the following code:

[0146] {

[0147] "conf":[

[0148] {

[0149] "I2CBus": 90,

[0150] "Location" : "GPU3",

[0151] "Box_CDFP_ID" : "CDFP0"

[0152] },

[0153] {

[0154] "I2CBus": 91,

[0155] "Location" : "GPU5",

[0156] "Box_CDFP_ID" : "CDFP1"

[0157] } ...... ]

[0160] }

[0161] The gpu-manager module loads the configuration file, obtains the asset information of each GPU device, such as Product Name, Part Number, Serial Number, Vendor ID, Device ID, etc., and puts this information on Dbus. The bmcweb module provides a redfish interface for PSMC to call and query GPU asset information. The data structure is as follows:

[0162] {

[0163] "GPUAsset":[

[0164] {

[0165] "Location" : "GPU3",

[0166] "ProductName" : "XXXXXX",

[0167] "PartNumber" : "XXXXXX",

[0168] "SerialNumber" : "XXXXXX",

[0169] "VendorID" : "XXXXXX",

[0170] "DeviceID" : "XXXXXX"

[0171] },

[0172] {

[0173] "Location" : "GPU5",

[0174] "ProductName" : "XXXXXX",

[0175] "PartNumber" : "XXXXXX",

[0176] "SerialNumber" : "XXXXXX",

[0177] "VendorID" : "XXXXXX",

[0178] "DeviceID" : "XXXXXX"

[0179] } ...... ]

[0182] }

[0183] Similarly, NVMe Box BMC establishes a mapping relationship between NVMe Location and asset information, and provides a redfish interface in the bmcweb module for PSMC to call and query NVMe asset information.

[0184] See also Figure 4 After the Host is powered on, the Host BIOS identifies the hardware devices in the Box and the GPU and NVMe devices assigned to the Host, and sends the device asset information to the Host BMC. The PSMC interacts with each Host BMC to obtain the device asset information sent by the Host BIOS and stored in the Host BMC; the PSMC interacts with the BMC in the GPU Box and NVMe Box to obtain the device asset information and topology information in each Box. The PSMC interacts with the 8 PCIe Switch firmware to obtain the mapping relationship between the current GPU, NVMe and the Switch_Port of the Host, and then summarizes various mapping relationships to finally establish the allocation relationship table of the GPU, NVMe devices and the Host. The PSMC can display the GPU, NVMe devices and their asset information assigned to each Host. The GPU, NVMe devices and their asset information assigned to the current Host displayed by the Host BMC are also correct. PSMC sends the device allocation table to Host BMC according to the Host number. Host BMC parses the device asset information sent by Host BIOS. According to the BDF in the device allocation table sent by PSMC, the GPU and NVMe device asset information recorded in the allocation table assigned to the Host is saved to file a.json, and other device asset information is saved to file b.json. Other device asset information is: devices controlled by the host that are recognized by BIOS and not recorded in the allocation table, which may be some devices connected to the host Box.

[0185] Among them, the data structure of the allocation relationship table is as follows:

[0186] {

[0187] "Host_ID": "Host0",

[0188] "IP": "100.2.74.43",

[0189] "Switch_CDFP_ID": "CDFP0-0",

[0190] "Switch_Port": "0x000040",

[0191] "Devices": [

[0192] {

[0193] "DeviceBox_ID": "GPUBox0",

[0194] "Switch_CDFP_ID": "CDFP0-1",

[0195] "Switch_Port": "0x000050",

[0196] "Box_CDFP_ID": "CDFP0",

[0197] "Location": "GPU3",

[0198] "BusNumber": XX,

[0199] "DeviceNumber": XX,

[0200] "FunctionNumber": XX,

[0201] "Asset": {

[0202] "ProductName": "XXXXXX",

[0203] "PartNumber": "XXXXXX",

[0204] "SerialNumber": "XXXXXX",

[0205] "VendorID": "XXXXXX",

[0206] "DeviceID": "XXXXXX"

[0207] }

[0208] },

[0209] {

[0210] "DeviceBox_ID": "NVMEBox0",

[0211] "Switch_CDFP_ID": "CDFP3-2",

[0212] "Switch_Port": "0x400060",

[0213] "Box_CDFP_ID": "CDFP0",

[0214] "BusNumber": XX,

[0215] "DeviceNumber": XX,

[0216] "FunctionNumber": XX,

[0217] "Location": "NVMe0, NVMe1",

[0218] "Asset": [

[0219] {

[0220] "Location": "NVMe0",

[0221] "ProductName": "XXXXXX",

[0222] "PartNumber": "XXXXXX",

[0223] "SerialNumber": "XXXXXX",

[0224] "VendorID": "XXXXXX",

[0225] "DeviceID": "XXXXXX"

[0226] },

[0227] {

[0228] "Location": "NVMe1",

[0229] "ProductName": "XXXXXX",

[0230] "PartNumber": "XXXXXX",

[0231] "SerialNumber": "XXXXXX",

[0232] "VendorID": "XXXXXX",

[0233] "DeviceID": "XXXXXX"

[0234] } ]

[0236] } ]

[0238] }

[0239] See also Figure 5 During the BIOS startup process, the device information assigned to its own host is scanned. After the PSMC sends the allocation relationship table to the host, based on the load situation in the entire system, the user sends instructions to the PSMC through the human-computer interaction interface to dynamically allocate GPU and NVMe devices. Specifically, the PSMC interacts with the PCIe Switch firmware to perform hot removal of devices; the PSMC sends instructions to the BMC in the specified GPU or NVMe Box to reset the specified GPU or NVMe device; the PSMC interacts with the PCIeSwitch firmware to perform hot addition of devices; after the dynamic allocation operation is completed, the PSMC updates the allocation relationship table of the GPU, NVMe device and the Host to ensure the accuracy of the allocation relationship; the PSMC sends the updated device allocation relationship to the Host BMC according to the Host number; the Host BMC updates the a.json file according to the device asset information in the latest allocation relationship. Furthermore, the PSMC displays the GPU, NVMe devices and their asset information allocated to each Host, and the Host BMC displays the GPU, NVMe devices and their asset information allocated to the current Host after dynamic allocation. This solves the problem that in a converged architecture system, after the GPU and NVMe devices in the resource pool are dynamically allocated, the Host BMC displays incorrect asset information of the GPU, NVME and other devices allocated to the corresponding Host.

[0240] See also Figure 8The pooled management controller is connected to the I2C Switch chip through the I2C bus, and the I2C Switch chip is connected to 8 PCIe switch chips through 8 independent I2C buses; and the upstream port host port (HP) of a single PCIe switch chip is connected to the CDFP port through the PCIe bus, and then to the Host; the downstream port device port (DP) of the PCIe switch chip is connected to the CDFP port through the PCIe bus, and then to the GPU; the downstream port fabric port (FP) of the PCIe switch chip is used for the internal interconnection of the 8 PCIe switch chips. The internal interconnection of the 8 PCIe switch chips can be referred to Fig. 9 . Fig. 9 The H / D in the figure indicates HP port or DP port.

[0241] In this embodiment, the pooled management controller PSMC in the IO Box is responsible for the management of the entire system. After the entire cabinet is powered on and powered on, an allocation relationship table of GPU, NVME devices and Host is established based on the connection topology of the entire system. Through this allocation relationship table, it can be clearly displayed which GPU devices in which GPU Box, which NVME devices in which NVMEBox and the asset information of these devices are allocated under a Host. According to the load situation in the system, after dynamically adjusting the GPU and NVME devices, PSMC interacts with the PCIe Switch firmware to re-establish the allocation relationship table of GPU, NVME devices and Host. Based on the latest allocation relationship table, PSMC sends the latest device asset information to Host BMC, and Host BMC updates the asset information storage file based on the received device asset information, thereby solving the problem of incorrect display of asset information, which is conducive to the flexible reconfiguration and rapid upgrade of key devices such as CPU, GPU, NVMe, etc., and can greatly improve the utilization of server hardware resources.

[0242] An electronic device provided by an embodiment of the present invention is introduced below, and the electronic device described below can be referenced to other embodiments described herein. The electronic device in this embodiment can be the host, the first baseboard management controller, the second baseboard management controller, the third baseboard management controller, the network switching device, and the pooling management controller in the aforementioned embodiments.

[0243] An embodiment of the present invention discloses an electronic device, including:

[0244] Memory, used to store computer programs;

[0245] A processor is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0246] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device, a device allocation table corresponding to each host is constructed; and the device allocation table corresponding to each host is sent to the corresponding host.

[0247] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: device information recognized by its own basic input and output system but not recorded in the received device allocation table is stored in a first file, and device information in the received device allocation table is stored in a second file.

[0248] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: after startup, the second baseboard management controller in itself is used to identify and establish a mapping relationship between the identification information of its own connector port and the identification information of the connector port of the second switching chip connected to the corresponding connector port.

[0249] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: managing the temperature, flow, port type and routing information of multiple second switching chips through the first switching chip.

[0250] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: configuring the routing registers in multiple second switching chips through the first switching chip to update the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device.

[0251] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: reading the routing registers in multiple second switching chips through the first switching chip to obtain the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device.

[0252] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: comparing the device allocation table corresponding to each host with the allocation relationship obtained by reading the routing registers in multiple second switching chips; if the two are consistent, sending the device allocation table corresponding to each host to the corresponding host; if they are inconsistent, updating the device allocation table corresponding to each host according to the allocation relationship obtained by reading the routing registers in multiple second switching chips, and then sending the device allocation table corresponding to each host to the corresponding host.

[0253] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: receiving and managing the IP address broadcasted by the first baseboard management controller in each host, the IP address broadcasted by the second baseboard management controller in each computing device, and the IP address broadcasted by the third baseboard management controller in each storage device.

[0254] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after startup, the processor uses its own basic input and output system to enumerate and obtain a device information table corresponding to the current host.

[0255] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: monitoring and recording the first device information of the corresponding computing device in an out-of-band manner.

[0256] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: monitoring and recording the second device information of the corresponding storage device in an out-of-band manner.

[0257] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: displaying the first file and the second file. Accordingly, the pooling management controller is used to display the device allocation table corresponding to each host.

[0258] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sending the execution task to the device in the corresponding device allocation table according to the device allocation table corresponding to the processor.

[0259] Furthermore, an embodiment of the present invention also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7 Terminal shown. Figure 6 and Figure 7All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of application of the present invention.

[0260] Figure 6 A schematic diagram of the structure of a server provided in an embodiment of the present invention. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the information management disclosed in any of the aforementioned embodiments.

[0261] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present invention, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0262] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0263] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the information management method disclosed in any of the above embodiments, the computer program can also further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, the data can also include data such as application developer information.

[0264] Figure 7 A schematic diagram of the structure of a terminal provided in an embodiment of the present invention, wherein the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0265] Generally, the terminal in this embodiment includes: a processor and a memory.

[0266] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0267] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the information management method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

[0268] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0269] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0270] A nonvolatile storage medium provided in an embodiment of the present invention is introduced below. The nonvolatile storage medium described below and other embodiments described herein may be cross-referenced.

[0271] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the information management method disclosed in the above-mentioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method may be temporary storage or permanent storage.

[0272] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device, a device allocation table corresponding to each host is constructed; and the device allocation table corresponding to each host is sent to the corresponding host.

[0273] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: the device information recognized by its own basic input and output system and not recorded in the received device allocation table is stored in a first file, and the device information in the received device allocation table is stored in a second file.

[0274] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: after startup, the second baseboard management controller in itself is used to identify and establish a mapping relationship between the identification information of its own connector port and the identification information of the connector port of the second switching chip connected to the corresponding connector port.

[0275] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: managing the temperature, flow, port type and routing information of multiple second switching chips through the first switching chip.

[0276] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: configuring the routing registers in multiple second switching chips through the first switching chip to update the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device.

[0277] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: reading the routing registers in multiple second switching chips through the first switching chip to obtain the allocation relationship between the host connected to the corresponding second switching chip and the computing device and storage device.

[0278] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: comparing the device allocation table corresponding to each host with the allocation relationship obtained by reading the routing registers in multiple second switching chips; if the two are consistent, sending the device allocation table corresponding to each host to the corresponding host; if they are inconsistent, updating the device allocation table corresponding to each host according to the allocation relationship obtained by reading the routing registers in multiple second switching chips, and then sending the device allocation table corresponding to each host to the corresponding host.

[0279] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: receiving and managing the IP address broadcast by the first baseboard management controller in each host, the IP address broadcast by the second baseboard management controller in each computing device, and the IP address broadcast by the third baseboard management controller in each storage device.

[0280] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after startup, the processor uses its own basic input and output system to enumerate and obtain a device information table corresponding to the current host.

[0281] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: monitoring and recording the first device information of the corresponding computing device in an out-of-band manner.

[0282] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: monitoring and recording the second device information of the corresponding storage device in an out-of-band manner.

[0283] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: displaying the first file and the second file. Accordingly, the pooling management controller is used to display the device allocation table corresponding to each host.

[0284] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: sending the execution task to the device in the corresponding device allocation table according to the device allocation table corresponding to the processor.

[0285] A computer program product provided by an embodiment of the present invention is introduced below. The computer program product described below can be referenced to other embodiments described in this document.

[0286] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned disclosed information management method when executed by a processor.

[0287] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0288] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0289] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A computing system, characterized in that: include: Host resource pool, management resource pool, computing resource pool, storage resource pool and network switching equipment; The host resource pool includes: a plurality of hosts; the management resource pool includes: a pooled management controller and a switching manager connected to the pooled management controller; the computing resource pool includes: a plurality of computing devices; the storage resource pool includes: a plurality of storage devices; The network switching device is connected to each host, the pooled management controller, each computing device and each storage device; the switching manager is connected to each host, each computing device and each storage device; The pooling management controller is used to: construct a device allocation table corresponding to each host according to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device; and send the device allocation table corresponding to each host to the corresponding host; Each host is used to: store the device information recognized by its basic input and output system but not recorded in the received device allocation table into the first file, and store the device information in the received device allocation table into the second file.

2. The system according to claim 1, characterized in that The exchange manager and each host, the exchange manager and each computing device, and the exchange manager and each storage device are connected through the same type of connector.

3. The system according to claim 1, characterized in that The switching manager comprises: a first switching chip and a plurality of second switching chips; a plurality of buses are arranged between the first switching chip and the plurality of second switching chips; Correspondingly, the pooling management controller is connected to the plurality of second switching chips through the first switching chip and the plurality of buses; the upstream port of each second switching chip is connected to the corresponding host, and the downstream port is connected to the corresponding computing device and storage device; the second switching chips are interconnected in pairs; Correspondingly, the pooled management controller is used to: receive, through the first switching chip and the multiple second switching chips, the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device.

4. The system according to claim 3, characterized in that Each port of each second switching chip is connected to a corresponding connector port; one connector port is correspondingly connected to one host or one computing device or one storage device.

5. The system according to claim 4, characterized in that Each computing device is used to: after startup, use the second baseboard management controller in itself to identify and establish a mapping relationship between the identification information of its own connector port and the identification information of the connector port of the second switching chip connected to the corresponding connector port.

6. The system according to claim 3, characterized in that The pooling management controller is used to manage the temperature, flow, port type and routing information of the plurality of second switching chips through the first switching chip.

7. The system according to claim 3, characterized in that The pooling management controller is used to configure the routing registers in the plurality of second switching chips through the first switching chip to update the allocation relationship between the host connected to the corresponding second switching chip and the computing device and the storage device.

8. The system according to claim 7, characterized in that The pooling management controller is used to read the routing registers in the plurality of second switching chips through the first switching chip to obtain the allocation relationship between the host connected to the corresponding second switching chip and the computing device and the storage device.

9. The system according to claim 8, characterized in that The pooling management controller is used to compare the device allocation table corresponding to each host with the allocation relationship obtained by reading the routing registers in the plurality of second switching chips; If the two are consistent, the device allocation table corresponding to each host is sent to the corresponding host; if they are inconsistent, the device allocation table corresponding to each host is updated according to the allocation relationship obtained by reading the routing registers in the multiple second switching chips, and then the device allocation table corresponding to each host is sent to the corresponding host.

10. The system according to claim 1, characterized in that The pooled management controller is used to receive and manage the IP address broadcasted by the first baseboard management controller in each host, the IP address broadcasted by the second baseboard management controller in each computing device, and the IP address broadcasted by the third baseboard management controller in each storage device.

11. The system according to claim 1, characterized in that Each host is used to, after startup, use its own basic input and output system to enumerate and obtain the device information table corresponding to the current host.

12. The system according to claim 1, characterized in that The second baseboard management controller in each computing device is used to monitor and record the first device information of the corresponding computing device in an out-of-band manner.

13. The system according to claim 1, characterized in that The third baseboard management controller in each storage device is used to monitor and record the second device information of the corresponding storage device in an out-of-band manner.

14. The system according to any one of claims 1 to 13, characterized in that: The first baseboard management controller in each host is used to display the first file and the second file.

15. The system according to any one of claims 1 to 13, characterized in that: The pooling management controller is used to display the device allocation table corresponding to each host.

16. The system according to any one of claims 1 to 13, characterized in that Each host is used to send execution tasks to the devices in the corresponding device allocation table according to its corresponding device allocation table.

17. An information management method, characterized in that: Applied to a pooled management controller, the pooled management controller is arranged in a computing system, the computing system comprises: a host resource pool, a management resource pool and a network switching device; the host resource pool comprises: a plurality of hosts; the management resource pool comprises: a pooled management controller and a switching manager connected to the pooled management controller; Wherein, the network switching device connects each host and the pooling management controller; the switching manager connects each host; The method includes: According to the device information table corresponding to the corresponding host sent by the first baseboard management controller in each host, the first device information of the corresponding computing device sent by the second baseboard management controller in each computing device connected to the pooling management controller, and the second device information of the corresponding storage device sent by the third baseboard management controller in each storage device connected to the pooling management controller, construct a device allocation table corresponding to each host respectively; The device allocation table corresponding to each host is sent to the corresponding host, so that each host stores the device information recognized by its basic input and output system but not recorded in the received device allocation table in the first file, and stores the device information in the received device allocation table in the second file.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein the computer program implements the method according to claim 17 when executed by a processor.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to claim 17 is implemented.

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