Processor and data access monitoring method

Abstract

The present invention proposes a processor and data access monitoring method. It belongs to the technical field of operation and memory access of multi-core processors; the processor includes an input / output block, and the input / output block is used to connect each of the cores and the system memory, wherein the input / output block includes a historical access record table, and the historical access record table is used to temporarily store the address of at least a part of the data accessed by the cache of each core. Since the information of the cache accessed before is recorded in the historical access record table, once the information of the desired target data is found in the historical record table, the core with the data can be accurately required to release the data, thereby significantly reducing the frequency of broadcast snooping.

Description

Technical Field

[0001] The invention proposes a processor and a data access monitoring method, belonging to the technical field of multi-core processor operation and memory access. Background Art

[0002] Generally, a system with a processor uses a memory controller to control and access system memory resources. When the memory controller effectively receives a memory access request, the memory controller buffers the memory access request and processes the buffered memory access request according to certain specified priorities.

[0003] Each core of the current processor is equipped with a cache. In this way, a physical block of system memory may be accessed by more than one core at the same time, so it is necessary to avoid the situation where data is not synchronized between multiple caches. Cache race conditions between multiple processors mainly occur when there is a write action. At this time, it is necessary to use the snoop cache coherency protocol to snoop the cache and bus, and the snooping will know the behavior of the cache, and then decide which action to take.

[0004] A common consistency protocol is the MOESI (Modified Owned Exclusive Shared Invalid) protocol. According to this protocol, each cache line includes a status bit to indicate the MOESI status of the cache line. These statuses include indicating that the cache line is modified (Modified; M), the cache line is exclusive (Exclusive; E) or shared (Shared; S), or the cache line is invalid (Invalid; I). The Owned (Owned; O) status indicates that the cache line in the cache has been modified, the cache can share copies with other caches, and the data in the memory is stale.

[0005] However, according to the above technical means, the processor operation process needs to constantly change the state of the cache line, which will obviously reduce the performance of the processor. Therefore, reducing the access demand to the system memory and thereby reducing the number of times data moves between the system memory and the cache can improve system performance. Summary of the invention

[0006] The present invention provides a processor and data access monitoring method to solve the problem that the performance of the processor is reduced due to the behavior of the cache being constantly changed by snooping.

[0007] The present invention proposes a processor, which includes multiple cores and all the cores are connected to the system memory. The processor includes an input / output block, and the input / output block is used to connect each of the cores and the system memory, wherein the input / output block includes a historical access record table, and the historical access record table is used to temporarily store the address of at least a portion of the data accessed by the cache of each of the cores.

[0008] Furthermore, the historical access record table of the input / output block is connected to a consistency circuit unit and a memory controller, wherein the consistency circuit unit is connected to the core, and the memory controller is connected to the system memory.

[0009] Furthermore, the consistency circuit unit includes any one of MOSEI and MESI protocols.

[0010] Furthermore, when a cache line switches between different states, a delay is generated. For example, in the MESI protocol, a cache line may switch from the exclusive (E) state to the shared (S) state, or from the modified (M) state to the invalid (I) state; each state switch involves the sending and receiving of messages, as well as the response processing of these messages; the state switch delay can be calculated by the following formula:

[0011]

[0012] Where n represents the total number of state switching steps; represents the initialization time of the i-th step; represents the propagation time of the i-th step; represents the propagation distance of the i-th step; y represents the influencing factor of the propagation distance; Indicates the confirmation time of step i;

[0013] In the cache coherence protocol, when a core needs to update the cache status of other cores, it needs to be implemented through message passing. The message passing delay includes the propagation time of the message on the bus and the processing time at the target core. It is calculated by the following formula:

[0014]

[0015] Where m represents the total number of message passing steps; represents the sending time of step j; represents the transmission time of step j; represents the number of transmission nodes in step j; represents the processing time of step j;

[0016] In some operations, such as write operations, a core may need to wait for responses from other cores to complete the update of cache status. Waiting for response latency is the time it takes from sending a request to receiving all necessary responses. It is calculated by the following formula:

[0017]

[0018] in, Indicates the time when the request is sent; p indicates the total number of corresponding steps, represents the response time of the kth step.

[0019] Adding the above three delays together, we get the total delay in the cache coherence protocol:

[0020]

[0021] The performance of the cache consistency protocol is evaluated by calculating the total delay. If the total delay is lower than a preset threshold, the performance of the cache consistency protocol is considered acceptable; if it is higher than the threshold, the protocol or hardware design needs to be optimized to reduce the delay. Further, the input step of the input / output block includes:

[0022] When any core of the processor performs a read or write operation on its cache, the relevant information of the operation (such as the system memory address of the data) is captured and entered into the historical access record table of the input / output block;

[0023] The historical access record table in the input / output block interacts with the consistency circuit unit, and the consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol;

[0024] When the core cache state changes (such as data being modified, replaced or invalidated), the change information is input into the historical access record table through the consistency circuit unit to update the record;

[0025] When a core needs to load data from system memory into a cache, or write data from a cache back to system memory, information about the operation is exchanged with the memory controller through the input / output block.

[0026] Furthermore, the output step of the input / output block includes:

[0027] When the core needs to access specific data, it issues a query request to the historical access record table in the input / output block;

[0028] If the historical access record shows that the specific data has been accessed (i.e., exists in the cache of a certain core), the core that is ready to access the data will wait for the core that has accessed the data to release the data (possibly coordinated by a consistency circuit unit);

[0029] If the data is released, the core that is ready to use it obtains the data from system memory or another core's cache;

[0030] If the historical access records show that a particular data has not been accessed (i.e., it is not present in any core’s cache), the I / O block broadcasts a snoop message to all cores;

[0031] During the data acquisition process, the input / output block works with the memory controller to ensure the correct transfer of data from the system memory to the cache;

[0032] At the same time, the input / output block updates the historical access record table in real time.

[0033] Furthermore, the access steps of the historical access record table include:

[0034] When any core of the processor performs a read or write operation on the cache, the system captures relevant information of the operation; the information includes the system memory address of the data, the operation type (read / write), and the core number that performs the operation;

[0035] The captured operation information is input into a historical access record table in the input / output block; the historical access record table stores at least a portion of the information, the at least a portion including a system memory address of the data;

[0036] The historical access record table interacts with the consistency circuit unit, and the consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol;

[0037] When the core cache state changes (such as data being modified, replaced or invalidated), the consistency circuit unit transmits the change information to the historical access record table;

[0038] When the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the information of the operation interacts with the memory controller through the input / output block;

[0039] The memory controller is responsible for the actual data transfer, while the input / output block records the relevant information of the operation (especially the system memory address of the data) in the historical access record table;

[0040] When the core needs to access specific data, a query request is issued to the historical access record table in the input / output block, wherein the query request includes the system memory address of the data to be accessed;

[0041] After receiving the query request, the historical access record table checks the stored records to determine whether the data has been accessed by the cache of other cores;

[0042] If the data has been accessed, the core that is ready to access the data will wait for the core that has accessed the data to release the data;

[0043] Once the data is released, the core that is ready to access it can fetch said data from system memory or another core's cache;

[0044] If the data is not being accessed, the I / O block broadcasts a snoop message to all cores to ensure that no core is using the data;

[0045] Then, the core that is ready to access the data obtains the data from the system memory;

[0046] During the data acquisition process, the input / output block will update the historical access record table in real time and display the new data access situation, which includes the latest access status, access time and other information of the recorded data.

[0047] A data access monitoring method proposed by the present invention includes a processor having multiple cores, and the monitoring method includes:

[0048] In the historical access record table, relevant information of the data that has been accessed by the cache is recorded; the relevant information includes the address of the data in the system memory;

[0049] When the core processor needs to access specific data, it queries the historical access record table;

[0050] If the historical access record shows that the specific data has been accessed, the core that has accessed the specific data releases the specific data, and the core that is ready to access the specific data goes to the system memory to access the specific data;

[0051] If the historical access record shows that the specific data has not been accessed, a snoop is broadcast to each core to release the specific data, and the core that is ready to access the specific data goes to the system memory to access the specific data.

[0052] Furthermore, the step of releasing the specific data from the core that has accessed the specific data and preparing to access the specific data from the core in the system memory includes:

[0053] When the requesting core needs to access specific data, the historical access record table is queried to determine whether the data has been accessed by the cache of the holding core;

[0054] The historical access record table returns a query result indicating whether the data has been accessed; if the query result shows that the data has been accessed (i.e., exists in the cache of a core), the next step is entered;

[0055] The requesting core notifies the holding core through a bus or communication mechanism inside the processor that it wants to access the data; after receiving the notification, the holding core prepares to release the data, including marking the data as "invalid" or "dirty" from the cache (if the data has been modified) and preparing to write it back to the system memory (if the data is "dirty");

[0056] The consistency circuit unit monitors this process, and if the data is "dirty", the consistency circuit unit coordinates writing the data from the cache holding the core back to the system memory;

[0057] Once the data is freed (or if the data has never been cached, directly accesses system memory), the requesting core fetches said data by accessing system memory; and loads the data from system memory into its cache;

[0058] Finally, the historical access record table is updated to complete data access.

[0059] Furthermore, the step of broadcasting snooping to each core so that the specific data is released and preparing the core to access the specific data to the system memory to access the specific data includes:

[0060] When the requesting core needs to access specific data, the historical access record table is queried to determine whether the data has been accessed by the cache of other cores;

[0061] If the historical access record table shows that the specific data has not been accessed (i.e., not in the cache of any core), proceed to the next step;

[0062] The requesting core triggers a snooping mechanism of the processor, and the snooping mechanism sends a snooping request to all other cores through an internal bus or a communication network; the snooping request includes address information of the data to be accessed in the system memory;

[0063] After receiving the snoop request, each core checks whether its cache contains the requested data;

[0064] If the hit core finds that its cache contains the requested data, it will prepare to release the data; the hit core marks the relevant data in the cache as "invalid" or "dirty" (if the data has been modified); if the data is "dirty", the hit core writes the data back to the system memory;

[0065] The hitting core broadcasts a data release notification to all cores through the processor's internal mechanism, indicating that it is ready to release the data or has written the data back to system memory;

[0066] After receiving the data release notification, the requesting core obtains information that the data is now in the system memory or is about to be released back to the system memory;

[0067] The requesting core reads the data from the system memory, loads it into the cache, and updates the historical access record table to record the result of this data access and the latest access status of the data.

[0068] Furthermore, the steps after each core receives the snoop request further include:

[0069] After each core receives the snoop request and checks its cache, the time from receiving the snoop request to determining whether it hits (i.e., whether the cache contains the requested data) is recorded, and the time is called "snoop response time";

[0070] For each hit core, record the total time from determining the hit to preparing to release the data (including marking the data as "invalid" or "dirty", and writing the data back to the system memory if necessary); this time is called "data preparation time";

[0071] After collecting a certain number of snoop event data (for example, every thousand snoops or every minute), calculate the average snoop delay; where the average snoop time is calculated using the following formula:

[0072]

[0073] Where N is the number of snooping events, Indicates the number of snoop events that hit; represents the set of response times of all snooping events; Represents the set of data preparation times for all snooping events that hit; and represents the weight coefficient, which is used to adjust the importance of response time and data preparation time in the average delay; β represents the base of the logarithm, which is used to perform logarithmic conversion on the response time; Represents the coefficient of the exponential function, which is used to adjust the exponential growth of data preparation time.

[0074] Among them, if a snoop request does not hit the cache of any core, the data preparation time is 0;

[0075] Judging the efficiency of the snooping mechanism based on a preset threshold;

[0076] If the average snooping delay is lower than the set threshold, the snooping mechanism is judged to be efficient;

[0077] If the average snooping delay is higher than the set threshold, the snooping mechanism is judged to be inefficient;

[0078] If the snooping mechanism is judged to be inefficient, the reasons for the high snooping delay are analyzed, which may be internal bus congestion, communication network delay, inefficient processor snooping logic, etc.

[0079] According to the analysis results, corresponding disposal measures are taken, which include upgrading hardware components such as internal buses, communication networks or processors, and improving algorithms or strategies of snooping mechanisms, such as reducing unnecessary snooping requests, optimizing data access patterns, etc.

[0080] Feedback the measures taken and their effects to the relevant teams or personnel, make iterative adjustments based on the actual results, and continuously monitor the performance of the mechanism.

[0081] The beneficial effects of the present invention are as follows: by recording the information that the cache has accessed in the historical access record table, once the information of the target data is found in the historical record table, the core with the data can be accurately required to release the data, so the frequency of broadcast snooping can be significantly reduced. By combining the historical access record table with the consistency circuit unit, the data consistency between the cores can be effectively maintained, data conflicts and errors can be reduced, and the reliability of the system can be improved; in the data request process, by querying the historical records, it can be quickly determined whether the data has been accessed by other cores, thereby reducing unnecessary data transmission and delay, and improving the overall efficiency of data access; by real-time monitoring and recording the access of data, the frequent access to the system memory can be reduced, the occupation of memory bandwidth can be reduced, and the system performance can be improved; by recording the historical access information, when an error or failure occurs, the problem can be quickly located, and the fault recovery capability of the system can be improved; by monitoring the delay and efficiency of the snooping mechanism, data support can be provided for system performance optimization, helping the development team to identify bottlenecks and make improvements; the real-time updated historical access record table and the snooping mechanism provide support for dynamic management of data access, so that the processor can flexibly respond to different load conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 A schematic diagram showing a processor architecture according to an embodiment of the present invention;

[0083] Figure 2 A data access monitoring flow chart according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0084] See also Figure 1 The embodiment in the figure discloses that the processor 100 includes a plurality of cores 101, 102, 103, 104 such as C0, C1, C2...Cn, and each core 101~104 is respectively equipped with a cache (indicated by the "$" symbol in the figure). The processor 100 has an input / output block (I / O block) 120, and the I / O block 120 is connected to each of the cores 101~104. Secondly, the processor 100 is connected to the system memory 130 via the I / O block 120.

[0085] Specifically, the input / output block 120 includes a history access record table 121 connected to a first multiplexer 122, a second multiplexer 123, and a consistency circuit unit 124, wherein the first multiplexer 122 is connected to the second multiplexer 123. A memory controller 125 is connected to the second multiplexer 123. The consistency circuit 124 is connected to the core 101.

[0086] Furthermore, the first multiplexer 122 is connected to each of the cores 101-104, so that the request command of each of the cores 101-104 can be transmitted to the historical access record table 121 or to the second multiplexer 123 through the first multiplexer 122. The output result of the historical access record table 121 can be transmitted to the second multiplexer 123 or the consistency circuit unit 124. The output result of the second multiplexer 123 can be transmitted to the memory controller 125 to access the data of the system memory 130. The output result of the consistency circuit unit 124 can be transmitted to each of the cores 101-104.

[0087] The above-mentioned historical access record table 121 is a memory queue similar to a cache, and its storage content includes: address, validity and data source, so as to correspond to the address of data accessed by at least a part of the cache. The consistency circuit unit 124 can adopt the known MOESI protocol or MESI protocol.

[0088] See also Figure 2 An embodiment of the present invention discloses a data access monitoring method, taking the correspondence between core A and core B and applying the MESI protocol as an example:

[0089] Block 201 reveals that core A wants to access a data S;

[0090] Block 202 discloses that core A first goes to the historical access record table to check the records in the historical access record table. Whether data S is recorded in the historical access record table depends on whether data S has been accessed. Once data S has been accessed, it is recorded in the historical access record table. It is understandable that if the recorded time is too long or the historical access record table needs to clear space, data S may also be cleared.

[0091] Block 203 discloses a determination step for determining whether the data S is recorded in the historical access record table;

[0092] Block 204 discloses that if data S is in the historical access record table and is shown to be accessed by core B, the status of data S is determined again. If the status of data S is declared to be invalid for sharing, core A can access data S from system memory according to block 205.

[0093] In the determination step disclosed in block 204 , if the data S is not shared (S) or invalid (I), the state of the data S is either modified (M) or exclusive (E), and thus the process disclosed in block 206 can be executed.

[0094] Block 206 discloses that, under the condition that the state of data S is modified (M) or exclusive (E), core A requires core B to abandon / release data S and declare the state of data S in core B as invalid (I); thus, core A can access data S from system memory according to block 205.

[0095] If it is found in the determination step of block 203 that data S is not recorded in the historical access record table, then according to block 207, core A broadcasts snooping to each core;

[0096] Then, as disclosed in block 208 , each core is required to clear / release the state of the data S and declare the state of the data S according to the cache coherence protocol.

[0097] After each core completes the clearing and data S is re-declared, core A can access data S from the system memory, as shown in block 205 .

[0098] Since the historical access record table records the information that the cache has accessed, once the information of the target data is found in the historical record table, the core with the data can be accurately requested to release the data, thereby significantly reducing the frequency of broadcast snooping. It is understandable that the larger the memory capacity of the historical access record table, the smaller the frequency of broadcast snooping.

[0099] In the MESI protocol, cache lines have four states: modified (M), exclusive (E), shared (S), and invalid (I). When the data state of a cache line changes, such as switching from the exclusive (E) state to the shared (S) state, or from the modified (M) state to the invalid (I) state, a state switching operation is required. The state switching delay is obtained by the following formula:

[0100]

[0101] Where n represents the total number of state switching steps; represents the initialization time of the i-th step; represents the propagation time of the i-th step; represents the propagation distance of the i-th step; y represents the influencing factor of the propagation distance; Indicates the confirmation time of step i;

[0102] When a core modifies the data in a cache line, the state of the cache line changes from exclusive (E) or shared (S) to modified (M). When other cores need to access the data, they request access to the data through message passing. Depending on the type of request and the current state of the cache line, the cache controller decides whether to send the data to the requester (shared state) or invalidate the requester's cache line (invalid state). Each state switch involves the sending and receiving of messages, as well as the response processing of these messages. Message passing latency includes the propagation time of the message on the bus and the processing time at the target core. The response processing time depends on how quickly the target core processes the received message. Message passing latency is obtained by the following formula:

[0103]

[0104] Where m represents the total number of message passing steps; represents the sending time of step j; represents the transmission time of step j; represents the number of transmission nodes in step j; represents the processing time of step j;

[0105] In some operations, such as write operations, a core may need to wait for responses from other cores to complete the update of the cache state. When a core needs to modify the data in a cache line, it first checks the state of the cache line. If the cache line is in the exclusive (E) state, the core can modify the data directly and update the state to modified (M). If the cache line is in the shared (S) state, the core needs to send a message to other cores that own the cache line, requesting them to invalidate their respective cache lines. After sending the request, the core needs to wait for responses from all relevant cores. Waiting for response delay refers to the time it takes from sending a request to receiving all necessary responses. If a core fails to respond in time, it may cause the write operation to be blocked, thereby increasing the overall delay. Among them, the waiting for response delay is obtained by the following formula:

[0106]

[0107] Where m represents the total number of message passing steps; represents the sending time of step j; represents the transmission time of step j; represents the number of transmission nodes in step j; represents the processing time of step j;

[0108] By adding the above three delays, we can get the total delay in the cache consistency protocol.

[0109] Total delay = state switching delay + message delivery delay + waiting response delay.

[0110] By calculating the total delay, the performance of the cache consistency protocol can be evaluated; if the total delay is lower than the preset threshold, the performance of the cache consistency protocol is considered acceptable; if the total delay is higher than the threshold, the protocol or hardware design needs to be optimized to reduce the delay; by subdividing the delay into state switching delay (STA), message delivery delay (MPD) and waiting response delay (RED), the main sources of delay in the cache consistency protocol can be more accurately identified; it helps developers to optimize specific sources of delay and improve optimization efficiency. Through the specific calculation formula, the quantification of delay becomes possible; the calculated total delay (TD) can be used to intuitively evaluate the performance of the cache consistency protocol. The preset threshold is set as the standard for performance evaluation. By comparing the total delay with the threshold, it can be determined whether the performance of the cache consistency protocol is acceptable. When the total delay is higher than the threshold, it provides a direction for optimizing the protocol or hardware design. Developers can analyze which links have room for optimization based on the parameters in the delay calculation formula, so as to make targeted optimizations. By optimizing the sources of delay in the cache consistency protocol, the total delay can be reduced, which helps to improve the response speed and overall performance of the system. Reducing latency is crucial to improving user experience; in application scenarios with high real-time requirements, such as games and real-time communications, reducing latency can significantly improve user experience. Cache consistency protocol performance optimization helps reduce system instability caused by excessive latency, improves system reliability and stability, and reduces the risk of system crashes or freezes. Through in-depth research on cache consistency protocol latency, we can promote protocol innovation and development, and developers can explore more efficient and concise protocol designs to adapt to the ever-changing computing environment.

[0111] When any core of the processor performs a read or write operation on its cache, the relevant information of the operation (such as the system memory address of the data, the type of operation, etc.) will be captured, and the captured information will then be entered into the historical access record table of the input / output block. This step ensures that each core access to the cache is recorded, providing basic data for subsequent data access monitoring. The historical access record table in the input / output block interacts with the consistency circuit unit. Through the consistency circuit unit, based on the cache consistency protocol such as MOESI or MESI, the consistency of data between cores is maintained. When the cache state of the core changes (such as data is modified, replaced or invalidated), these change information will be entered into the historical access record table through the consistency circuit unit, and the record will be updated in real time. When the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the information of these operations will interact with the memory controller through the input / output block. The memory controller performs corresponding memory read and write operations based on the received information to ensure the correct loading and writing of data.

[0112] By capturing the read and write operation information of the processor core on the cache and inputting it into the historical access record table, the technical solution realizes real-time access monitoring of data, which helps system administrators or developers to understand the flow of data in real time and ensure the correctness and security of data; the historical access record table in the input / output block interacts with the consistency circuit unit, and the consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol, ensuring that there will be no data conflicts or inconsistencies when the multi-core processor processes data, thereby improving the stability and reliability of the system; when the core's cache state changes (such as data is modified, replaced or invalidated), the change information is input into the historical access record table through the consistency circuit unit, and the record is updated, ensuring that the information in the historical access record table is always consistent with the core cache The actual state of the processor is kept consistent, providing an accurate basis for subsequent data access and processing; when the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the operation information interacts with the memory controller through the input / output block, which helps the system to manage memory resources more effectively, reduce unnecessary memory access and transmission, and improve the overall performance and efficiency of the system; through the input steps of the input / output block, the system can more flexibly handle data access and consistency maintenance issues in multi-core processors, which facilitates future expansion and upgrades of the system and enables the system to adapt more easily to new hardware and software environments; by real-time monitoring of data access and maintaining data consistency, the system can promptly discover and handle potential problems, which helps to reduce system maintenance costs and reduce system crashes and repair work caused by data errors or inconsistencies.

[0113] When a core needs to access specific data, it sends a query request to the historical access record table in the input / output block; after receiving the request, the input / output block queries the historical access record table to determine the location of the required data; if the historical access record shows that the specific data has been accessed (that is, it exists in the cache of a core), the core that is ready to access the data will enter a waiting state, waiting for the core that has accessed the data to release the data; if the historical access record shows that the specific data has not been accessed (that is, it does not exist in the cache of any core), the input / output block will broadcast a snoop message to all cores to find out whether the data is in the cache of other cores. The data is not recorded in the cache (although this situation is rare, it may be caused by recording delays or errors). Once the core that has accessed the data releases the data (which may be coordinated by the consistency circuit unit), the core that is ready to access it can obtain the data from the system memory or the cache of another core. During the data acquisition process, the input / output block works closely with the memory controller to ensure the correct transmission of data from the system memory to the cache. Regardless of whether the data is obtained from the system memory or from the cache of other cores, the input / output block will update the historical access record table in real time to reflect the latest data access status.

[0114] By querying the historical access record table, the core that is ready to access the data can quickly understand whether the data is occupied by other cores, thereby avoiding unnecessary waiting. Once the data is released, the core that is ready to access can immediately obtain the data from the system memory or the cache of another core, thereby improving the speed and efficiency of data access. Through the coordination of the consistency circuit unit, multiple cores can maintain data consistency when accessing and modifying data, thereby avoiding data conflicts and errors. During the data acquisition process, the collaborative work of the input / output block and the memory controller ensures the correct transmission of data from the system memory to the cache, and maintains the integrity of the data. Through efficient data access management and optimization, the number of system accesses to the memory is reduced, thereby reducing the system's overhead and energy consumption. The input / output block can update the historical access record table in real time, provide the system with accurate data access status information, and help the system allocate and utilize resources more reasonably. Through flexible data access strategies and optimization, the technical solution can adapt to different application scenarios and requirements, and improve the flexibility and adaptability of the system. Through real-time updating of the historical access record table and collaborative work, the input / output block can timely discover and handle potential data access problems, thereby reducing the risk of system crashes.

[0115] When any core of the processor performs a read or write operation on the cache, the system captures detailed information related to the operation, including the system memory address of the data, the type of operation (read or write), and the core number that performs the operation; the captured operation information is then entered into the historical access record table in the input / output block. The record table stores at least the system memory address of the data, which is the key basis for data access query; the historical access record table maintains close interaction with the consistency circuit unit. The consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol. These protocols ensure that when data is shared or modified between multiple cores, the copies of the data can be synchronized and consistent; when the cache state of the core changes (for example, the data is modified, replaced, or invalidated), the consistency circuit unit will pass these change information to the historical access record table. This ensures that the information in the record table is always consistent with the actual state of the core cache; when the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the information of these operations will interact with the memory controller through the input / output block. The memory controller is responsible for the actual data transfer task; at the same time, the input / output block will record the relevant information of these operations (especially the system memory address of the data) in the historical access record table. This ensures that the record table can reflect the access status of the data in real time; when the core needs to access specific data, it will issue a query request to the historical access record table in the input / output block. The request contains the system memory address of the data to be accessed; after receiving the query request, the historical access record table will check the stored records to determine whether the data has been accessed by the cache of other cores. If the data has been accessed, the core that is ready to access the data will wait for the core that has accessed the data to release the data (this process is coordinated by the consistency circuit unit); once the data is released, the core that is ready to access can obtain the data from the system memory or the cache of another core. If the data is not accessed, the input / output block will broadcast a snoop message to all cores to ensure that no core is using the data, and obtain the data from the system memory; during the data acquisition process, the input / output block will update the historical access record table in real time to display the new data access situation, including the latest access status, access time and other information of the recorded data.

[0116] The historical access record table allows the core to quickly query the access status of specific data, thereby avoiding unnecessary memory access and data transmission delays; through real-time updating and querying, the system can timely discover and handle data access conflicts and reduce waiting time between cores; the core can more effectively use cache resources because the historical access record table provides accurate information on whether data is cached; by reducing unnecessary memory access, the scheme optimizes the use of memory bandwidth and improves overall system performance; the interaction between the historical access record table and the consistency circuit unit ensures the consistency of data between cores and avoids data conflicts and errors; the real-time update of data access status ensures that the system can always obtain the latest data status information; through real-time updating and querying, the system can timely discover potential data access problems and reduce the risk of system crash and data loss; during data transmission and access, the historical access record table ensures the integrity and accuracy of the data; through flexible data access strategies and optimizations, the scheme can adapt to different application scenarios and requirements, improving the flexibility and adaptability of the system; by centrally managing data access status, the design and implementation of the system are simplified. The rapid location and resolution of data access problems reduces the debugging and maintenance costs of the system.

[0117] When a processor core (called the "requesting core") needs to access specific data, it first queries the historical access record table. The record table stores all previous accesses to the data by all cores, including whether the data is held by the cache of a core. The purpose of the query is to determine whether the data has been cached by another core (called the "holding core"). The historical access record table returns a query result, telling the requesting core whether the data has been accessed. If the data has been accessed (that is, it exists in the cache of a core), the requesting core needs to wait for the holding core to release the data. The requesting core notifies the holding core through the bus or communication mechanism inside the processor that it wants to access the data. After receiving the notification, the holding core prepares to release the data. The holding core marks the data from the cache as "invalid" or "dirty"; if the data is "dirty" (that is, it has been modified), the holding core needs to prepare to write the data back to the system memory. The consistency circuit unit monitors the data release process. If the data is "dirty", the consistency circuit unit coordinates writing the data from the holding core's cache back to the system memory; once the data is released (or if the data has never been cached, the system memory is accessed directly), the requesting core can access the system memory to obtain the data; the requesting core loads the data from the system memory into its cache for subsequent fast access; finally, the historical access record table is updated to reflect the latest access to the data.

[0118] By querying the historical access record table, the requesting core can quickly determine the location of the data, avoiding unnecessary memory access, thereby improving the efficiency of data access; when the data is released or directly accessed from the system memory, the requesting core can quickly obtain the required data, reducing the waiting time; the introduction of the consistency circuit unit ensures the consistency of data among multiple cores. In particular, when the data is modified (i.e. becomes "dirty" data), the consistency circuit unit will coordinate to write the data back to the system memory, thereby ensuring the accuracy of the data in the system memory; by marking the data from the cache as "invalid" or "dirty" and writing it back to the system memory in a timely manner, the scheme effectively avoids data conflicts and errors; the scheme makes full use of cache resources and reduces the consumption of memory bandwidth by reducing unnecessary memory access; at the same time, by updating the historical access record table in real time, the system can more effectively manage the data access status and improve the overall resource utilization; through strict data access control and consistency maintenance, the scheme reduces the risk of system crash and data loss. During the data access process, any potential problems can be discovered and handled in a timely manner, thereby enhancing the stability and reliability of the system, being able to adapt well to the environment of multi-core processors, and supporting data sharing and consistent access between multiple cores. By optimizing data access strategies, it provides strong support for the efficient operation of multi-core processors. By centrally managing data access status, it simplifies the design and implementation of the system. At the same time, by providing a clear data access process and consistency maintenance mechanism, it reduces the development and maintenance costs of the system.

[0119] When a requesting core needs to access specific data, it first queries the historical access record table to determine whether the data has been accessed by the cache of other cores; if the historical access record table shows that the data has not been accessed (that is, it is not in the cache of any core), the requesting core knows that it needs to obtain the data from the system memory; the requesting core triggers the processor's snooping mechanism, which is achieved by sending a snooping request to all other cores through an internal bus or communication network; the snooping request contains the address information of the data that needs to be accessed in the system memory, so that other cores can check whether their own caches contain this data; after receiving the snooping request, each core will check whether its cache contains the requested data; if a core (called a hit core) finds that its cache contains the requested data, it will prepare to release the data. The hit core marks the data from its cache as "invalid" or "dirty" (if the data has been modified); if the data is "dirty" (i.e., it has been modified), the hit core will write it back to the system memory to ensure the accuracy of the data in the system memory; the hit core broadcasts a data release notification to all cores through the processor's internal mechanism; this notification indicates that the hit core is ready to release the data (if the data has not been modified) or has written the data back to the system memory (if the data is "dirty"); after receiving the data release notification, the requesting core knows that the data is now in the system memory or is about to be released back to the system memory. Therefore, the requesting core can read the data from the system memory and load it into its own cache for subsequent fast access. Finally, the requesting core updates the historical access record table to record the results of this data access and the latest access status of the data.

[0120] The snooping mechanism ensures that when a core needs to access specific data, if the data has been cached by other cores, it will be released or written back to the system memory in time, thereby ensuring data consistency. By broadcasting data release notifications, all cores can know the latest status of the data in real time, avoiding data conflicts and errors; when the data is not in the cache of the requesting core, the snooping mechanism can quickly locate the actual location of the data (i.e., the system memory or the cache of other cores), reducing unnecessary memory access, improving the efficiency of data access, and reducing system latency; snooping requests and data release notifications are sent through the internal bus or communication network. These communications are local and targeted, and will not cause excessive consumption of bus bandwidth. Compared with the traditional bus monitoring method, the snooping mechanism is more efficient and energy-saving. Through strict data access control and consistency maintenance, the risk of system crash and data loss is reduced. During the data access process, any potential problems can be discovered and handled in time, thereby enhancing the stability and reliability of the system. As the number of processor cores increases, the snooping mechanism can ensure consistency and efficient access of data among multiple cores. By centrally managing data access status and historical access record tables, the scheme simplifies the management process of data access. Developers can focus more on the logical implementation of the application without having to pay too much attention to the underlying data access details.

[0121] When a core in the system needs to access a data item that may exist in the cache of other cores, a snoop request is initiated; each core that receives the snoop request checks its cache to determine whether it contains the requested data (i.e., whether it is a hit); for each snoop request, the time from receiving the request to determining whether it is a hit is recorded, which is called the "snoop response time"; for the hit core, the total time from determining the hit to preparing to release the data (including marking the data as "invalid" or "dirty", and possibly writing the data back to the system memory) is further recorded, which is called the "data preparation time"; after collecting a certain number of snoop event data (for example, every thousand snoops or every minute), the average snoop delay is calculated. The average snoop time is calculated using the following formula:

[0122]

[0123] Where N is the number of snooping events, Indicates the number of snoop events that hit; represents the set of response times of all snooping events; Represents the set of data preparation times for all snooping events that hit; and represents the weight coefficient, which is used to adjust the importance of response time and data preparation time in the average delay; β represents the base of the logarithm, which is used to perform logarithmic conversion on the response time; Represents the coefficient of the exponential function, which is used to adjust the exponential growth of data preparation time. The efficiency of the snooping mechanism is judged based on the preset threshold. If the average snooping delay is lower than the set threshold, the snooping mechanism is considered to be efficient; otherwise, it is considered to be inefficient; if the snooping mechanism is judged to be inefficient, the reasons for the high snooping delay are analyzed, and possible reasons include internal bus congestion, communication network delay, and inefficient processor snooping logic; according to the analysis results, take corresponding disposal measures, such as upgrading hardware components (internal bus, communication network, processor, etc.) or improving the algorithm or strategy of the snooping mechanism (such as reducing unnecessary snooping requests, optimizing data access mode, etc.); feedback the disposal measures taken and their effects to the relevant teams or personnel. Iterate and adjust according to the actual results, and continuously monitor the performance of the snooping mechanism to ensure its continued efficient operation.

[0124] By recording the response time and data preparation time of each snooping request, the scheme can accurately measure the performance of the snooping mechanism; the calculation formula of the average snooping delay not only considers the response time of the snooping request, but also incorporates the data preparation time, and adjusts the relative importance of the two in the average delay through the weight coefficients α and γ. The logarithmic base β and the exponential function coefficient λ in the formula allow adjustment according to specific application scenarios to adapt to different performance requirements and hardware environments. By recording the response time and data preparation time of each snooping request and combining them with the formula for calculation, an accurate average snooping delay can be obtained, providing accurate performance data for system administrators or developers, helping them to better understand the operation status of the snooping mechanism. When the average snooping delay is higher than the set threshold, the formula can trigger the performance optimization process. By deeply analyzing the reasons for high delay and taking corresponding disposal measures (such as upgrading hardware components, improving algorithms or strategies, etc.), the snooping delay can be significantly reduced and the system performance can be improved. The average snooping delay formula is not only used for current performance evaluation, but also provides strong support for the continuous improvement of the system by continuously monitoring the performance of the snooping mechanism. Feedback and iterative adjustment mechanisms enable the system to continuously optimize according to actual results to adapt to changing workloads and hardware environments. An efficient snooping mechanism can reduce data access latency and improve system response speed. By optimizing the snooping mechanism, data access conflicts and errors can be reduced, the risk of system crashes or data loss can be reduced, the reliability and stability of the system can be enhanced, and the system can be ensured to operate stably in the long term. Based on precise performance evaluation, the solution can accurately determine the efficiency of the snooping mechanism; when the average snooping delay is higher than the set threshold, the system can automatically trigger the performance optimization process, including cause analysis, formulation and implementation of disposal measures, etc. The solution provides tools for in-depth analysis of the causes of high snooping delays, helping to identify problems such as internal bus congestion, communication network delays, and inefficient processor snooping logic. This flexibility allows system administrators or developers to develop effective solutions for specific problems. The solution not only focuses on current performance, but also ensures that the system can maintain efficient operation in the long term by continuously monitoring the performance of the snooping mechanism. The feedback and iterative adjustment mechanism enables the system to be continuously optimized according to actual results to adapt to the ever-changing workload and hardware environment; by optimizing the snooping mechanism, the solution can reduce data access latency and improve the overall system performance; an efficient snooping mechanism helps reduce data access conflicts and errors and enhances the reliability and stability of the system.

[0125] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A processor, comprising a plurality of cores and all the cores are connected to a system memory, characterized in that: The processor includes an input / output block, and the input / output block is used to connect each of the cores and the system memory, wherein each of the input / output blocks includes a historical access record table, and the historical access record table is used to temporarily store the address of the data accessed by the cache of each of the cores; The input step of the input / output block includes: When any core of the processor performs a read or write operation on its cache, relevant information of the read or write operation is captured and input into a historical access record table of the input / output block; The historical access record table in the input / output block interacts with the consistency circuit unit, and the consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol; When the core cache state changes, the change information is input into the historical access record table through the consistency circuit unit to update the record; When the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the information of the read and write operations interacts with the memory controller through the input / output block; The core is used to receive a snoop request. The steps after the core receives the snoop request include: After each core receives the snoop request and checks its cache, the time from receiving the snoop request to determining whether it hits is recorded, and the time is the snoop response time; For each hit core, the total time from determining the hit to preparing to release the data is recorded, wherein the time from determining the hit to preparing to release the data includes marking the data as "invalid" or "dirty" and writing the data back to the system memory; the total time is the data preparation time; After collecting snooping event data, the average snooping delay is calculated; the average snooping time is calculated using the following formula: Where N is the number of snooping events, Indicates the number of snoop events that hit; represents the set of all snoop response times; Represents the set of data preparation times for all snooping events that hit; and represents the weight coefficient, which is used to adjust the importance of response time and data preparation time in the average delay; β represents the base of the logarithm, which is used to perform logarithmic conversion on the response time; represents the coefficient of the exponential function, which is used to adjust the exponential growth of data preparation time; Judging the efficiency of the snooping mechanism based on a preset threshold; If the average snooping delay is lower than the set threshold, the snooping mechanism is judged to be efficient; If the average snooping delay is higher than the set threshold, the snooping mechanism is judged to be inefficient; If the snooping mechanism is judged to be inefficient, the cause of the high snooping delay is analyzed; and corresponding disposal measures are taken according to the analysis results; The measures taken and their effects will be fed back to the relevant teams or personnel, iterative adjustments will be made based on the actual results, and the performance of the snooping mechanism will be continuously monitored.

2. A processor according to claim 1, characterized in that: The historical access record table of the input / output block is connected to a consistency circuit unit and a memory controller, wherein the consistency circuit unit is connected to the core, and the memory controller is connected to the system memory.

3. A processor according to claim 2, characterized in that: The consistency circuit unit includes protocols in MOSEI and MESI protocols.

4. A processor according to claim 1, characterized in that: The output step of the input / output block includes: When the core needs to access specific data, it issues a query request to the historical access record table in the input / output block; If the historical access record shows that the specific data has been accessed, the core that is ready to access the specific data will wait for the core that has accessed the cached data to release the specific data; If the data is released, the core that is ready to use it obtains the specific data from the system memory or the cache of another core; If the historical access records show that specific data has not been accessed, the input / output block broadcasts a snoop message to all cores; During the data acquisition process, the input / output block works with the memory controller to ensure the correct transfer of data from the system memory to the cache; At the same time, the input / output block updates the historical access record table in real time.

5. A processor according to claim 1, characterized in that: The steps of accessing the historical access record table include: When any core of the processor performs a read or write operation on the cache, the system captures relevant information of the operation; The captured operation information is input into a historical access record table in the input / output block; the historical access record table stores at least a portion of the operation information, the at least a portion including a system memory address of the data; The historical access record table interacts with the consistency circuit unit, and the consistency circuit unit maintains the consistency of data between cores based on the MOESI or MESI protocol; When the core cache state changes, the consistency circuit unit transmits the change information to the historical access record table; When the core needs to load data from the system memory to the cache, or write data back from the cache to the system memory, the information of the operation interacts with the memory controller through the input / output block; The memory controller is responsible for the actual data transfer, while the input / output block records the relevant information of the operation into the historical access record table; When the core needs to access specific data, a query request is issued to the historical access record table in the input / output block, wherein the query request includes the system memory address of the data to be accessed; After receiving the query request, the historical access record table checks the stored records to determine whether the data has been accessed by the cache of other cores; If the data has been accessed, the core that is ready to access the data will wait for the core that has accessed the data to release the data; Once the data is released, the core that is ready to access it can fetch said data from system memory or another core's cache; If the data is not being accessed, the I / O block broadcasts a snoop message to all cores to ensure that no core is using the data; Then, the core that is ready to access the data obtains the data from the system memory; During the data acquisition process, the input / output block will update the historical access record table in real time and display the new data access status.

6. A data access monitoring method, implemented by using a processor as claimed in any one of claims 1 to 5; characterized in that: The monitoring method comprises: In the historical access record table, relevant information of the data that has been accessed by the cache is recorded; the relevant information includes the address of the data in the system memory; When the core processor needs to access specific data, it queries the historical access record table; If the historical access record table shows that the specific data has been accessed, the core that has accessed the specific data releases the specific data and is ready to use the core of the specific data to access the specific data in the system memory; If the historical access record table shows that the specific data has not been accessed, a snoop is broadcast to each core to release the specific data, and the core that is ready to access the specific data goes to the system memory to access the specific data.

7. A data access monitoring method according to claim 6, characterized in that: The step of releasing the specific data from the core that has accessed the specific data and preparing to access the specific data from the core in the system memory to access the specific data includes: When the requesting core needs to access specific data, the historical access record table is queried to determine whether the specific data has been accessed by the cache of the holding core; The historical access record table will return a query result indicating whether the specific data has been accessed; if the query result shows that the data has been accessed, proceed to the next step; The requesting core notifies the holding core through a bus or communication mechanism inside the processor, indicating that the specific data is to be accessed; after receiving the notification, the holding core prepares to release the specific data, including marking the specific data as "invalid" or "dirty" from the cache and preparing to write it back to the system memory; The consistency circuit unit monitors this process, and if specific data is "dirty", the consistency circuit unit coordinates writing the specific data from the cache holding the core back to the system memory; Once the specific data is released, the requesting core obtains the specific data by accessing the system memory; and loads the specific data from the system memory into its cache; Finally, the historical access record table is updated to complete data access.

8. A data access monitoring method according to claim 6, characterized in that: The step of broadcasting snooping to each core to release the specific data and preparing to access the core of the specific data to the system memory to access the specific data includes: When the requesting core needs to access specific data, the historical access record table is queried to determine whether the specific data has been accessed by the cache of other cores; If the historical access record table shows that the specific data has not been accessed, proceed to the next step; The requesting core triggers a snoop mechanism of the processor, which sends a snoop request to all other cores via an internal bus or communication network; After receiving the snoop request, each core checks whether its cache contains the specific data requested; If the hit core finds that its cache contains the requested specific data, it will prepare to release the specific data; the hit core marks the relevant data in the cache as "invalid" or "dirty"; if the data is "dirty", the hit core writes the data back to the system memory; The hit core broadcasts data release notification to all cores through the processor's internal mechanism; After receiving the data release notification, the requesting core obtains information that the data is now in the system memory or is about to be released back to the system memory; The requesting core reads the data from the system memory, loads it into the cache, and updates the historical access record table to record the result of this data access and the latest access status of the data.

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