Power failure protection method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a power failure protection method and device, electronic equipment and a storage medium, and relates to the technical field of storage. Comprising the step of storing data in a cache of the storage equipment in a first storage area in nonvolatile storage areas of the storage equipment under the condition that the abnormal power-down protection circuit is detected to be abnormal and the storage equipment is subjected to abnormal power-down. Because the performance of storing the data in the first storage area is better than the performance of storing the data in the second storage area, the time for storing the data in the first storage area is greatly shortened, and the first capacitor used for supplementing power supply can adopt a capacitor with lower cost, the reliability of the storage equipment is improved, and meanwhile, the reliability of the storage equipment is improved. The cost of the storage equipment is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a power-off protection method, device, electronic equipment and storage medium. Background Art

[0002] The ability of a storage device to protect users from loss of data when an abnormal power outage occurs is an important indicator of storage device reliability.

[0003] Taking SSD (Solid-State Disk) as an example, enterprise-level SSD products usually use DRAM (Dynamic Random Access Memory) as a cache for user data. When the user data in the cache meets the data volume of a Logic Stripe, the user data is written to NAND Flash (NAND flash memory). Since the physical characteristics of DRAM determine that the data stored in it will be lost when the power is off, the power-off protection mechanism will be considered when designing the system of enterprise-level SSD. When an abnormal power failure occurs, it switches to the PLP (Power Loss Protect) circuit backup power supply, thereby saving the user data in DRAM to NAND Flash.

[0004] However, the PLP circuit itself may also fail. For example, a capacitor in the PLP circuit may fail. In the event of a PLP circuit failure and an abnormal power outage in the system, user data may still be lost, affecting system reliability.

[0005] In order to further improve reliability, a large amount of capacitor margin is often set on the PLP circuit in the related technology (for example, the actual number of capacitors on the SSD is more than 1.5 times the theoretical required number of capacitors) to ensure that it can still work normally when facing capacitor failure. The need to install a large number of expensive tantalum capacitors increases the cost of the SSD, and it cannot absolutely guarantee that user data will not be lost when an abnormal power failure occurs after the PLP circuit fails. Summary of the invention

[0006] The purpose of the embodiments of the present disclosure is to provide a power-off protection method, device, electronic device and storage medium.

[0007] To solve the above technical problems, the embodiments of the present disclosure are implemented through the following aspects.

[0008] According to a first aspect of an embodiment of the present disclosure, there is provided a power-off protection method, which is applied to a storage device, wherein the storage device includes an abnormal power-off protection circuit, and the method includes: when an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs, saving data in a cache of the storage device in a first storage area of ​​a non-volatile storage area of ​​the storage device; wherein the performance of storing the data in the first storage area is better than the performance of storing the data in a second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area.

[0009] According to a second aspect of an embodiment of the present disclosure, there is provided a power-off protection device, which is applied to a storage device, wherein the storage device includes an abnormal power-off protection circuit, and the device includes: a power-off protection module, which is used to save data in a cache of the storage device in a first storage area of ​​a non-volatile storage area of ​​the storage device when an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs; wherein the performance of storing the data in the first storage area is better than the performance of storing the data in a second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area.

[0010] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is used to execute the steps of the power-off protection method described in the first aspect above.

[0011] One of the above technical solutions has the following advantages or beneficial effects: since the performance of storing the data in the first storage area is better than the performance of storing the data in the second storage area, the time for storing in the first storage area is greatly shortened, and the first capacitor used for supplementary power supply can adopt a lower-cost capacitor, thereby improving the reliability of the storage device and reducing the cost of the storage device.

[0012] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

[0013] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0015] Figure 1 A schematic diagram showing a flow chart of a power-off protection method provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of power supply for storing data in a first storage area provided by an embodiment of the present disclosure is shown; Figure 3 Another schematic diagram of a power-off protection method provided by an embodiment of the present disclosure is shown; Figure 4 A schematic diagram of power supply for storing data in a second storage area provided by an embodiment of the present disclosure is shown; Figure 5 Another schematic diagram of a power-off protection method provided by an embodiment of the present disclosure is shown; Figure 6 Another schematic diagram of a power-off protection method provided by an embodiment of the present disclosure is shown; Figure 7 Another schematic diagram of a power-off protection method provided by an embodiment of the present disclosure is shown; Figure 8 A block diagram of a power-off protection device provided in an embodiment of the present application is shown; Fig. 9 A block diagram of another power-off protection device provided in an embodiment of the present application is shown; Fig.10 A schematic diagram of the hardware structure of an electronic device for executing the power-off protection method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present disclosure.

[0017] It should be noted that although the present disclosure uses an SSD as an example to describe the embodiments of the corresponding technical solution, those skilled in the art can, based on the records of the disclosed embodiments, apply other embodiments to other storage devices without any creative work, and these embodiments should also fall within the scope of protection of the present disclosure.

[0018] First, technical terms involved in the present disclosure are introduced.

[0019] FTL, Flash Translation Layer, Flash conversion layer, mainly implements the core part of the Flash control algorithm.

[0020] L2P table, Logic address to Physical address Table, a mapping table that converts the host logical address (LBA) to the Flash physical address.

[0021] AU, the data unit corresponding to the logical address in the L2P table.

[0022] Logic Stripe, logical stripe, the smallest unit of wear leveling and garbage collection in the FTL algorithm.

[0023] SLC Block: The storage area of ​​NAND uses SLC flash memory particles. Its storage area space is small, but the storage performance is better.

[0024] TLC Block, a storage area in NAND that uses TLC flash memory particles. TLC Block can be configured in SLC mode and used as SLC Block, that is, to obtain better storage performance at the expense of part of the storage capacity.

[0025] The execution subject of the power-off protection method provided in the embodiment of the present disclosure may be a control unit of a storage device. The control unit of the storage device may be integrated in the storage device or may be an external control unit electrically connected to the storage device. The present disclosure does not impose any limitation on this.

[0026] Figure 1 A schematic diagram of a power-off protection method provided by an embodiment of the present disclosure is shown, which is applied to a storage device, wherein the storage device includes an abnormal power-off protection circuit, such as Figure 1 As shown, the method may include the following steps: In step S101, when it is detected that an abnormality exists in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs, data in the cache of the storage device is saved in a first storage area in the non-volatile storage area of ​​the storage device.

[0027] wherein the performance of storing the data in the first storage area is better than the performance of storing the data in the second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area; The storage device includes a first number of first capacitors and a second number of second capacitors, the first capacitors are used to provide supplementary power when data is stored in a first storage area, and the second capacitors are used to provide power when data is stored in a second storage area.

[0028] In some embodiments, the storage device may be an SSD solid state storage disk, the non-volatile storage area may be a NAND Flash in the SSD solid state storage disk, the first storage area may be an SLC Block in the NAND Flash, the second storage area may be a TLC Block in the NAND Flash, the first capacitor may be a ceramic capacitor, and the second capacitor may be a tantalum capacitor.

[0029] When an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off occurs in the storage device, the amount of data in the cache of the storage device may be sufficient for one Logic Stripe or may not be sufficient for one Logic Stripe. Since the performance of storing data in the first storage area is better than the performance of storing data in the second storage area, the time required to save the data in the cache of the storage device in the first storage area is significantly less than the time required to save the data in the cache of the storage device in the second storage area. For example, if the first storage area is SLC Block and the second storage area is TLC Block, the time required to save the data in SLC Block is about 150us, and the time required to save the data in TLC Block is about 2ms.

[0030] In hardware design, the second capacitor is used to provide power for the abnormal power-off protection circuit when there is no abnormality in the abnormal power-off protection circuit and the storage device is abnormally powered off, so that the storage device can save data in the second storage area through the abnormal power-off protection circuit. By setting a first number of first capacitors on the storage device, and providing supplementary power supply for storing data in the first storage area through the first capacitor, the second number of second capacitors does not need to provide redundancy or provide excessive redundancy for the failure of the abnormal power-off protection circuit, thereby reducing the second number of second capacitors. For example, in the related art, it is usually necessary to provide 50% redundancy of the second capacitor (tantalum capacitor), while in the embodiment of the present disclosure, no second capacitor redundancy may be provided, or only a small amount of tantalum capacitor redundancy (for example, 5%) may be provided, and the number of first capacitors added is small, and low-cost ceramic capacitors may be used, thereby saving costs.

[0031] Figure 2A schematic diagram of power supply for storing data in a first storage area provided by an embodiment of the present disclosure is shown. Figure 2 As shown in the figure, when the external input voltage of the SSD is detected to be reduced from the normal 5V to 4.5V (i.e. Figure 2 After a->b in the figure, the storage device can generate a power-off interrupt and trigger the abnormal power-off protection. At this time, if the abnormal power-off protection circuit is abnormal, it triggers the data in the cache of the storage device to be saved in the first storage area (SLCBlock) in the non-volatile storage area of ​​the storage device, and the power can be supplied by the residual power of the mainboard (such as Figure 2 In the b->c section, for example, there may still be some normal second capacitors in the abnormal power-off protection circuit. When the voltage further drops to 4V, the first capacitor can be used for supplementary power supply (such as Figure 2 In the c->d section in the middle), the data can be stored in the first storage area within the time of replenishing the power supply. When the voltage drops further below 2.3V, the data cannot be stored until the capacitor is exhausted (such as Figure 2 (d->e in the middle).

[0032] By adopting the above technical solution, since the performance of storing data in the first storage area is better than the performance of storing data in the second storage area, the time for storing data in the first storage area is greatly shortened, and the first capacitor used for supplementary power supply can adopt a low-cost capacitor, thereby improving the reliability of the storage device and reducing the cost of the storage device.

[0033] Figure 3 Another flow chart of the power-off protection method provided by the embodiment of the present disclosure is shown as follows: Figure 3 As shown, the method may further include the following steps.

[0034] In step S102, when it is detected that there is no abnormality in the abnormal power-off protection circuit and abnormal power-off of the storage device occurs, the data in the cache of the storage device is stored in the second storage area.

[0035] Still taking the storage device as an SSD as an example, when there is no abnormality in the abnormal power-off protection circuit of the SSD and an abnormal power-off of the storage device occurs, the second capacitor in the abnormal power-off protection can be used to provide power and the data in the cache of the storage device can be saved in the TLC Block.

[0036] Figure 4 A schematic diagram of power supply for saving data to a second storage area provided by an embodiment of the present disclosure is shown. Figure 4 As shown in the figure, when the external input voltage of the SSD is detected to be reduced from the normal 5V to 4.5V (i.e. Figure 4After a->b in the figure, the storage device can generate a power-off interrupt, triggering abnormal power-off protection, and provide backup power for the storage device through the abnormal power-off protection circuit. When the voltage further drops to 4.2V, the second capacitor can be used for supplementary power supply (such as Figure 4 In the c->d section in the middle), the data is stored in the second storage area. When the voltage drops further to below 4.2V, the data cannot be stored until the capacitor is exhausted (such as Figure 4 (d->e in the middle).

[0037] By adopting the above technical solution, different power-off protection strategies can be determined based on the state of the abnormal power-off protection circuit, and the reliability of the power-off protection can be further improved by constructing a multi-level power-off protection technical solution.

[0038] Figure 5 Another flow chart of the power-off protection method provided by the embodiment of the present disclosure is shown as follows: Figure 5 As shown, the method may also include the following steps: In step S103, when the ratio of the input voltage to the rated voltage of the storage device is less than or equal to a preset first ratio threshold, it is determined that an abnormal power failure of the storage device occurs.

[0039] Still taking the storage device as an SSD with a rated voltage of 5V as an example, in some possible implementations, the first ratio threshold may be, for example, 90%. When it is detected that the ratio of the input voltage of the storage device to the rated voltage is less than or equal to 90% (that is, the input voltage of the storage device is less than or equal to 4.5V), it is determined that an abnormal power failure of the storage device has occurred.

[0040] Figure 6 Another flow chart of the power-off protection method provided by the embodiment of the present disclosure is shown as follows: Figure 6 As shown, the method may also include the following steps: In step S104, a charge and discharge test is performed on the second capacitor. When the ratio of the total capacitance of the second capacitor to the rated total capacitance is less than or equal to a preset second ratio threshold, it is determined that there is an abnormality in the abnormal power-off protection circuit; or, when the ratio of the total capacitance to the rated total capacitance is greater than the second ratio threshold, it is determined that there is no abnormality in the abnormal power-off protection circuit.

[0041] In some embodiments, a corresponding second ratio threshold may be set based on the redundancy of the second capacitor. For example, the theoretical total capacitance required to store data in the second storage area is The total redundant capacity is , you can refer to The second ratio threshold is set. That is, when the total capacitance of the second capacitor that has not failed in the abnormal power-off protection circuit cannot meet the theoretical total capacitance required for storing data in the second storage area, it is determined that the abnormal power-off protection circuit is abnormal; otherwise, it is determined that the abnormal power-off protection circuit is not abnormal.

[0042] In other embodiments, in order to avoid the contingency of a single charge and discharge test, a charge and discharge test can also be performed according to a preset cycle. For example, a periodic charge and discharge test can be performed when the storage device is idle, and the result of each charge and discharge test is recorded. When the number of consecutive charge and discharge tests reaches a preset number threshold, and the ratio of the total capacitance of the second capacitor in each test to the rated total capacitance is less than or equal to a preset second ratio threshold, it is determined that an abnormality exists in the abnormal power-off protection circuit.

[0043] By adopting the above-mentioned technical solution, it is possible to accurately determine whether there is an abnormality in the abnormal power-off protection circuit and whether an abnormal power-off of the storage device occurs, so that when an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs, the data in the cache of the storage device is saved in the first storage area in the non-volatile storage area of ​​the storage device, thereby improving the reliability of the storage device and reducing the cost of the storage device.

[0044] Figure 7 Another flow chart of the power-off protection method provided by the embodiment of the present disclosure is shown as follows: Figure 7 As shown, the first quantity of the first capacitor can be determined by the following method.

[0045] In step S201, the required total capacitance of the first capacitor is determined according to the average operating current of the storage device, the rated time for storing data in the first storage area, and the specification of the first capacitor.

[0046] In some embodiments, the rated time for saving data to the first storage area may be determined based on the required time for saving data to the first storage area. For example, in order to further improve reliability, the rated time for saving data to the first storage area may be a preset multiple (e.g., 2 times) of the required time for saving data to the first storage area. For example, when the required time for saving data to the first storage area is 150us, the rated time for saving data to the first storage area may be 300us.

[0047] In some possible implementations, the required total capacitance of the first capacitor may be determined by the following formula 1.

[0048] (Formula 1) in, is the required total capacitance of the first capacitor, is the stop working voltage of the first capacitor. Taking the first capacitor as a ceramic capacitor as an example, the default voltage is 2.3V. is the initial voltage of the first capacitor. Taking the first capacitor as a ceramic capacitor as an example, the default voltage is 4V. is the rated time for data to be stored in the first storage area. When the storage device is an SSD, the rated time may be 300us. is the average operating current of the storage device, and the value may be determined by the specifications of the storage device.

[0049] It is understandable that those skilled in the art may also make appropriate adjustments to the values ​​of the variables in the above formulas based on design requirements.

[0050] In step S202, a first quantity is determined according to a required total capacitance of the first capacitor.

[0051] For example, the first quantity may be determined by the required total capacitance and the capacitance of each first capacitor.

[0052] By adopting the above-mentioned technical solution, the first quantity of the first capacitor can be accurately determined, which is convenient for corresponding hardware design, so that based on the supplementary power supply of the first capacitor, the data in the cache of the storage device can be stored in the first storage area in the non-volatile storage area of ​​the storage device, thereby improving the reliability of the storage device and reducing the cost of the storage device.

[0053] In some embodiments, when an abnormality is detected in the abnormal power-off protection circuit, the operating mode of the storage device is determined to be the first operating mode; or, when no abnormality is detected in the abnormal power-off protection circuit, the operating mode of the storage device is determined to be the second operating mode.

[0054] For example, the first working mode may be a PLD (Power Loss Detect) working mode. When the working mode of the storage device is the PLD working mode and abnormal power failure of the storage device is detected, the first working mode may be a PLD (Power Loss Detect) working mode. Figure 2 The power supply mode shown stores data in the cache of the storage device in the first storage area.

[0055] The second working mode may be a PLP working mode. When the working mode of the storage device is the PLP working mode and abnormal power failure of the storage device is detected, the Figure 4 The power supply mode shown stores data in the cache of the storage device in the second storage area.

[0056] By adopting the above technical solution, the working mode of the storage device can be saved, and power-off protection can be performed based on the working mode and the abnormal power-off situation of the storage device, without the need to frequently perform charge and discharge tests on the abnormal protection working circuit, thereby further improving the reliability of the storage device.

[0057] Figure 8 A block diagram of a power-off protection device provided in an embodiment of the present application is shown, which is applied to a storage device, wherein the storage device includes an abnormal power-off protection circuit, such as Figure 8 As shown, the power-off protection device 100 comprises: The power-off protection module 110 is used to save the data in the cache of the storage device in the first storage area of ​​the non-volatile storage area of ​​the storage device when an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs; wherein the performance of storing the data in the first storage area is better than the performance of storing the data in the second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area; The storage device includes a first number of first capacitors and a second number of second capacitors, the first capacitors are used to provide supplementary power when data is stored in a first storage area, and the second capacitors are used to provide power when data is stored in a second storage area.

[0058] Optionally, the power-off protection module 110 is further configured to: When it is detected that there is no abnormality in the abnormal power-off protection circuit and abnormal power-off of the storage device occurs, the data in the cache of the storage device is stored in the second storage area.

[0059] The device 100 provided in the embodiment of the present application can execute each method in the foregoing method embodiment and realize the functions and beneficial effects of each method in the foregoing method embodiment, which will not be repeated here.

[0060] Fig. 9 A block diagram of another power-off protection device provided in an embodiment of the present application is shown. Fig. 9 As shown, the power-off protection device 100 further includes a detection module 120, which is used to: When the ratio of the input voltage to the rated voltage of the storage device is less than or equal to a preset first ratio threshold, it is determined that an abnormal power failure of the storage device occurs.

[0061] Optionally, the detection module 120 is further configured to: Performing a charge and discharge test on the second capacitor, and determining that the abnormal power-off protection circuit has an abnormality when the ratio of the total capacitance of the second capacitor to the rated total capacitance is less than or equal to a preset second ratio threshold; or When the ratio of the total capacitance to the rated total capacitance is greater than the second ratio threshold, it is determined that there is no abnormality in the abnormal power-off protection circuit.

[0062] Optionally, the detection module 120 is further configured to: When the number of continuous charge and discharge tests reaches a preset number threshold, and the ratio of the total capacitance of the second capacitor to the rated total capacitance in each test is less than or equal to a preset second ratio threshold, it is determined that an abnormality exists in the abnormal power-off protection circuit.

[0063] Optionally, the power-off protection module 110 is further configured to: When an abnormality is detected in the abnormal power-off protection circuit, the operation mode of the storage device is determined to be the first operation mode; or, when no abnormality is detected in the abnormal power-off protection circuit, the operation mode of the storage device is determined to be the second operation mode.

[0064] Fig.10 A schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure is shown. Fig.10 As shown, at the hardware level, the electronic device includes at least one processor, and optionally includes an internal bus, a network interface, and a memory. The memory may include a memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage, etc. Of course, the electronic device may also include hardware required for other services.

[0065] The processor, network interface and memory can be interconnected through an internal bus, which can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one bidirectional arrow is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0066] The memory stores the program. Specifically, the program may include a program code, and the program code includes at least one computer operation instruction. The memory may include a memory and a non-volatile memory, and provides instructions and data to the processor.

[0067] At least one processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a device for locating the target user at the logical level. At least one processor executes the program stored in the memory and specifically performs: the method disclosed in the embodiment shown in the first aspect and realizes the functions and beneficial effects of each method described in the method embodiment above, which will not be repeated here.

[0068] The method disclosed in the embodiment shown in the first aspect of the present disclosure can be applied to at least one processor or implemented by at least one processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware or software instructions in at least one processor. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present disclosure can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present disclosure can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0069] The electronic device can also execute the methods described in the foregoing method embodiments, and realize the functions and beneficial effects of the methods described in the foregoing method embodiments, which will not be repeated here.

[0070] Of course, in addition to software implementation, the electronic device disclosed in the present invention does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0071] In short, the above is only a preferred embodiment of the present disclosure and does not limit the protection scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0072] The systems, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0073] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0074] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

Claims

1. A power-off protection method, characterized in that: Applied to a storage device, the storage device includes an abnormal power-off protection circuit, and the method includes: When it is detected that the abnormal power-off protection circuit is abnormal and the storage device is abnormally powered off, the data in the cache of the storage device is stored in a first storage area in the non-volatile storage area of ​​the storage device; wherein the performance of storing the data in the first storage area is better than the performance of storing the data in a second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area; The storage device includes a first number of first capacitors and a second number of second capacitors, the first capacitors are used to provide supplementary power when the data is stored in the first storage area, and the second capacitors are used to provide power when the data is stored in the second storage area.

2. The method according to claim 1, characterized in that The method further comprises: When it is detected that there is no abnormality in the abnormal power-off protection circuit and abnormal power-off occurs in the storage device, the data in the cache of the storage device is stored in the second storage area.

3. The method according to claim 1, characterized in that: The method further comprises: When the ratio of the input voltage to the rated voltage of the storage device is less than or equal to a preset first ratio threshold, it is determined that an abnormal power failure of the storage device occurs.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Performing a charge and discharge test on the second capacitor, and determining that the abnormal power-off protection circuit has an abnormality when the ratio of the total capacitance of the second capacitor to the rated total capacitance is less than or equal to a preset second ratio threshold; or When the ratio of the total capacitance to the rated total capacitance is greater than the second ratio threshold, it is determined that there is no abnormality in the abnormal power-off protection circuit.

5. The method according to claim 4, characterized in that When the ratio of the total capacitance of the second capacitor to the rated total capacitance is less than or equal to a preset first ratio threshold, determining that the abnormal power-off protection circuit is abnormal includes: When the number of continuous charge and discharge tests reaches a preset number threshold, and the ratio of the total capacitance of the second capacitor to the rated total capacitance in each test is less than or equal to a preset second ratio threshold, it is determined that the abnormal power-off protection circuit has an abnormality.

6. The method according to claim 4, characterized in that The first quantity is determined by the following method: determining a required total capacitance of the first capacitor according to an average operating current of the storage device, a rated time for storing the data in the first storage area, and a specification of the first capacitor; The first quantity is determined according to a required total capacitance of the first capacitor.

7. The method according to claim 4, characterized in that The method further comprises: In the case where an abnormality is detected in the abnormal power-off protection circuit, determining that the operation mode of the storage device is the first operation mode; or, When it is detected that there is no abnormality in the abnormal power-off protection circuit, the operation mode of the storage device is determined to be the second operation mode.

8. The method according to claim 1, characterized in that: The storage device is an SSD, the non-volatile storage area is a NAND Flash, the first storage area is an SLC Block, the second storage area is a TLC Block, the first capacitor is a ceramic capacitor, and the second capacitor is a tantalum capacitor.

9. A power-off protection device, characterized in that: Applied to a storage device, the storage device includes an abnormal power-off protection circuit, and the device includes: A power-off protection module, configured to save data in the cache of the storage device in a first storage area in the non-volatile storage area of ​​the storage device when an abnormality is detected in the abnormal power-off protection circuit and an abnormal power-off of the storage device occurs; The performance of storing the data in the first storage area is better than the performance of storing the data in the second storage area, and the second storage area is a storage area other than the first storage area in the non-volatile storage area.

10. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the power-off protection method according to any one of claims 1 to 7.

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