Self-sensing method for unit failure in data flow reconfigurable architecture

Abstract

The invention provides a self-sensing method for unit failure in a data flow reconfigurable architecture, the data flow reconfigurable architecture is a CGRA architecture capable of organizing and managing processing units according to data flow of a task, and the data flow reconfigurable architecture comprises a self-sensing controller and a plurality of processing units. Each processing unit comprises a computing component, a routing component and a storage component, the routing component comprises a control route and a data route, each component is provided with a sensing module, and the method comprises the following steps: the self-sensing controller sends a detection request to the processing units; each sensing module in the processing unit detects whether the calculation component, the storage component, the control route and the data route are normal or not according to the detection request to obtain a detection result; and the self-sensing control module collects detection results fed back by each processing unit.

Description

Technical Field

[0001] The present invention relates to the field of computers, in particular to the field of computer architecture, and more particularly to a method for self-sensing unit failure in a data flow reconfigurable architecture. Background Art

[0002] Reconfigurable architectures have wide applications in fields such as artificial intelligence, digital signal processing, and scientific computing.

[0003] FPGA (Field Programmable Gate Array) is a relatively mature reconfigurable chip. However, due to its fine-grained structure and static reconstruction method, it has disadvantages such as low area efficiency, high power consumption, large amount of configuration data, and long reconstruction time.

[0004] Reconfigurable architectures represented by CGRA (Coarse-Grained Reconfigurable Array) are reconfigured through a combination of software and hardware, which can change the way the algorithm is mapped on the array; it has high performance and high main frequency while being programmable and flexible. Compared with general-purpose processors, it has the advantage of high energy efficiency. CGRA uses a computing granularity and structure that matches the application. Compared with FPGA, it has great advantages in terms of area efficiency, energy efficiency, and reconstruction time.

[0005] However, the current reconfigurable processor arrays are large in scale, with 4×4, 8×8 and even 64×64 computing arrays. During operation, a large number of units may fail or be damaged. If one or a part of several units in an array fails, it may cause computing, storage or network errors, or even the entire reconfigurable processor cannot be used. Existing module-wide self-test (Build in Selftest, referred to as BIST) is mainly used in storage.

[0006] When the inventors were conducting research on reconfigurable arrays, they found that the existing technologies focused on how to map algorithms to computing arrays to obtain higher acceleration performance, how to accelerate the reconfigurable mapping process, etc. However, less attention was paid to whether a unit in the array failed and how to dynamically adjust the mapping after failure.

[0007] Most existing self-sensing methods involve redundant multiple backups, which play an extremely important role in fields that urgently need reliability, such as aerospace. However, the CGRA architecture used for accelerators is an area- and resource-sensitive application scenario. Redundant backup will occupy too much valuable on-chip resources and is not very applicable.

[0008] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0009] Therefore, the purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a method for self-sensing unit failure in a data stream reconfigurable architecture.

[0010] The objective of the present invention is achieved through the following technical solutions:

[0011] According to a first aspect of the present invention, there is provided a method for self-perception of unit failure in a data flow reconfigurable architecture, wherein the data flow reconfigurable architecture refers to a CGRA architecture that can organize and manage processing units according to the data flow of a task, and the data flow reconfigurable architecture comprises a self-perception controller and a plurality of processing units, each processing unit comprises a computing component, a routing component and a storage component, the routing component comprises a control route and a data route, and each component is provided with a perception module, and the method comprises: the self-perception controller sends a detection request to the processing unit; each perception module in the processing unit respectively detects whether the computing component, the storage component, the control route and the data route are normal according to the detection request to obtain a detection result; and the self-perception control module collects the detection results fed back by each processing unit.

[0012] According to a second aspect of the present invention, there is provided a remapping method for a data flow reconfigurable architecture, comprising: obtaining detection results of a plurality of processing units obtained according to the method of the first aspect; constructing a bitmap according to the detection result of each processing unit, in which the state of each processing unit is set; determining new processing array information according to the bitmap, which includes processing units that can work normally and updates the routing path for establishing an on-chip network; obtaining tasks of related nodes in a data flow graph, remapping the tasks to processing units in a normal state according to the new processing array information, and transmitting task-related data according to the updated routing path.

[0013] Compared with the prior art, the advantages of the present invention are:

[0014] The method of the present invention is provided with a sensing module in the computing component, routing component and storage component of each processing unit, which is used to detect whether the computing component, storage component, control routing and data routing are normal, and collect the detection results fed back by all processing units. Thus, the status of all processing units in terms of computing components, storage components, control routing and data routing can be known, so as to better organize the related processing units to complete the task processing efficiently and accurately in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of a data flow reconfigurable architecture according to an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of a self-sensing structure of a computing component according to an embodiment of the present invention;

[0018] Figure 3 A schematic diagram of a self-sensing process of a computing component according to an embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a self-sensing structure of a routing component according to an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of a data packet sending process of a routing component during self-sensing according to an embodiment of the present invention;

[0021] Figure 6 Schematic diagram of data transmission under different shielding modes according to an embodiment of the present invention;

[0022] Figure 7 A schematic diagram of a bitmap of multi-unit failure according to an embodiment of the present invention;

[0023] Figure 8 The figure is a schematic diagram of converting a bitmap into a graph with side length information according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] As mentioned in the background technology section, the CGRA architecture used for accelerators is itself an area- and resource-sensitive application scenario. Redundant backup will occupy too much valuable on-chip resources and is not very applicable. Therefore, the present invention proposes a self-perception method for unit failure in a data flow reconfigurable architecture. In this method, a perception module is provided in the computing component, routing component and storage component of each processing unit to detect whether the computing component, storage component, control routing and data routing are normal, and to collect the detection results fed back by all processing units. In this way, the status of all processing units in terms of computing components, storage components, control routing and data routing can be known, so as to better organize the relevant processing units to complete task processing efficiently and accurately in the future.

[0026] The technical solution of the present invention is described below through some embodiments.

[0027] For ease of understanding, the reconfigurable architecture used in this implementation is first introduced here.

[0028] According to an embodiment of the present invention, a schematic structure of a data flow reconfigurable architecture is provided, and the data flow reconfigurable architecture refers to a CGRA architecture that can organize and manage processing units according to the data flow of tasks. Figure 1 , the data flow reconfigurable architecture includes: a computing array, a data cache, a self-sensing controller and / or a reconstruction unit. Among them:

[0029] The computing array includes multiple processing elements PE (Processing Element, referred to as PE, also known as execution unit), which are equipped with computing components, routing components and storage components. It should be noted that due to the limited image size, Figure 1 The three components are abbreviated as computing, routing and storage. The processing units PE are connected through an on-chip network (such as a Mesh network).

[0030] The computing unit is used to complete relevant calculations based on the input data. The computing unit includes an arithmetic logic unit ALU, a tensor computing unit Tensor and / or other units responsible for calculations (such as multipliers, etc.). Some exemplary computing devices can be referred to Figure 2 .

[0031] The routing component is the interface that connects the processing unit to the entire on-chip network. The on-chip network consists of a data network that can transmit data in the array and a control network for control. The data network and the control network are abstractions at the logical level. In actual hardware implementation, there may be two independent networks or a set of common networks. Correspondingly, the routing component is also divided into data routing and control routing. The on-chip network of the array and the routing component of the processing unit are inseparable. If either side fails, the network will be unavailable.

[0032] The entire array needs to be configured differently for different program requirements. When executing program A, it will first be compiled externally to generate a mapping file for how to map program A to the entire array. Then, based on the mapping file, it will generate control information such as instruction information and dependencies that each PE in the array needs to execute. These control information are parsed through control routing and control the operation of each module in the PE. Then the data required for the execution of each PE is transmitted to each PE through accessing memory and other means. These data packets are parsed using data routing and provided to the internal data cache. Not only that, when data interaction occurs between PEs, the data routing is also responsible for providing and receiving data.

[0033] In short, the control routing is responsible for the control information of the entire array, and the data routing is responsible for the operation data of the entire array. However, it should be noted that there may be some designs in which data and control information are uniformly controlled by one routing, but they are separated in the present invention.

[0034] When the data routing fails, it means that the current PE cannot receive data, and the data cannot be transmitted to other PEs through this PE. Because if cross-PE transmission is required, the intermediate PE is required for transfer. When the data routing of the intermediate PE fails, it cannot receive data and cannot assume the function of transfer. Since the current PE cannot receive data, it naturally cannot perform any calculations and can only be blocked.

[0035] When the control routing fails, it means that the current PE cannot receive and parse control information (including instructions, dependencies, etc.). The current PE cannot be mapped to any tasks that need to be executed because it cannot receive any control information from the host. Then the current PE cannot perform any calculations, but the data routing is intact and can assume the function of transfer and transmit data to other PEs.

[0036] The storage component, as the data storage structure inside the processing unit, includes cache, registers and / or SPM, etc.

[0037] Data cache (Memory Buffer) is used to store data, including data sent from hosts outside the array and / or data generated by the computing array (such as intermediate results, final results, etc.).

[0038] In addition, the above computing components, routing components and storage components are respectively provided with perception modules. Due to the limited image size, Figure 1 In the figure, the perception module is abbreviated as perception. It can be seen that in each computing component, an independent perception module is provided for the above three components. The perception module in the computing component is used to detect whether the computing component is normal and obtain the detection result of the computing component. The perception module in the routing component is used to detect whether the control routing and data routing are normal and obtain the detection results of the control routing and data routing. The perception module in the storage component is used to detect whether the storage component is normal and obtain the detection result of the storage component. Only a brief introduction is given here, and some schematic structures of the perception module will be further given later.

[0039] The self-sensing controller is used to send detection requests to the processing units and collect the detection results fed back by each processing unit. The self-sensing controller and the independent perception modules in each processing unit are combined into a self-sensing detection system on the CGRA architecture.

[0040] The reconstruction unit is used to organize the mapping relationship and data flow relationship of each processing unit in the computing array to complete the calculation of each node in the data flow graph in order to obtain the calculation result. If some processing units fail, remapping is required to adjust the mapping relationship and data flow relationship.

[0041] According to an embodiment of the present invention, a method for self-sensing unit failure in a data stream reconfigurable architecture is provided, the method comprising:

[0042] S1, the self-sensing controller sends a detection request to the processing unit;

[0043] S2, each perception module in the processing unit detects whether the computing component, storage component, control routing and data routing are normal according to the detection request, and obtains the detection result; and / or

[0044] S3. The self-sensing control module collects the detection results fed back by each processing unit.

[0045] In order to better understand the present invention, each step is described in detail below in conjunction with specific embodiments.

[0046] Step S1: The self-sensing controller sends a detection request to the processing unit.

[0047] According to one embodiment of the present invention, the self-sensing controller can be configured to periodically send a detection request to the processing unit, for example, every N minutes, hours or days according to user needs. Of course, the self-sensing controller can also be configured to trigger detection in other ways, such as being triggered by user means to send a detection request.

[0048] Step S2: Each perception module in the processing unit detects whether the computing component, storage component, control routing and data routing are normal according to the detection request, and obtains the detection result.

[0049] According to an embodiment of the present invention, if the processing unit receives a detection request, it notifies / controls each sensing module to detect whether the corresponding component is normal. Preferably, receiving the detection request and feeding back the detection result can be implemented by control routing; however, it should be understood that data routing can also be implemented.

[0050] In addition to detecting the status of each component, another design goal of the present invention is to not occupy too many on-chip resources during the self-sensing process. Therefore, in order to reduce the area overhead of the perception module, the embodiment of the present invention is cleverly configured in multiple aspects in combination with the needs of the test to achieve the purpose of detection with less overhead. The configuration of the perception module is described below.

[0051] According to one embodiment of the present invention, the perception module of the computing component performs the following operations: obtaining test data for various operation tests in the test computing component generated according to preset generation rules, the test data including test input data and reference results, wherein the preset generation rules require that at least one of the two calculation elements contained in the generated test input data has a specified property, so that the reference result can be directly obtained according to the numerical value and / or single calculation element set in the rule; transmitting the test input data to the element that performs the corresponding calculation function in the computing component to obtain the calculation result, and determining whether the computing component is normal based on the reference result and the calculation result. It should be noted that in order not to introduce additional addition, subtraction, multiplication and division logic, the generated test data needs to be able to intuitively obtain the result, and there is no need to introduce additional ALU or other calculation gate circuits in the computing component. In this way, the purpose of saving area and power consumption can be achieved, and there will be no large overhead due to the introduction of the self-perception system. The technical solution of this embodiment can at least achieve the following beneficial technical effects: when the embodiment of the present invention generates relevant use cases for operation tests, it is considered that if the calculation elements in the test input data are generated completely randomly, it is necessary to actually perform a calculation based on the calculation elements to obtain accurate reference results, which is time-consuming and costly; therefore, the embodiment of the present invention sets preset generation rules so that the reference results can be obtained directly according to the numerical values ​​and / or single calculation elements set in the rules, without the need for additional calculations to obtain the reference results, which can greatly simplify the cost of obtaining relevant use cases for the test.

[0052] The data flow reconfigurable architecture may include one or more computing devices for addition, multiplication, matrix multiplication and convolution. The embodiment of the present invention is directed to the computing components in the processing unit, in which a perception module is added, such as Figure 2As shown, it includes a test data generator and a calculation detector. The test data generator generates targeted test data O2 for different computing devices, including test input data and reference results. These test input data can obtain correct reference results without additional calculations: the test data generator transmits the test input data to the selector SL, and outputs a selection signal to the selector SL, so that the test input data is transmitted to the computing device, and the cache is held by sending a blocking information h, and new data is loaded for calculation after the test is completed. At the same time, the test data generator transmits the reference result of the test data to the calculation detection module, and the calculation detection module collects the output of the computing component and compares it with the correct reference result to obtain the result of whether the computing component is normal (if the output of any computing device is inconsistent with the reference result, the overall computing component is marked as wrong, which is abnormal), and transmits it to the self-sensing controller. In addition, these two parts can act as the internal perception module (BIST) of the current processing unit, or they can act as the external perception module of the surrounding processing units. For example, when performing auxiliary detection on the surrounding processing units, they may receive the calculation result I1 obtained from other processing units based on the test input data, and compare the calculation result I1 with the reference result to determine whether the calculation components of other processing units are normal.

[0053] Some relevant preferred embodiments for testing these devices are schematically given below. It should be understood that those skilled in the art may adopt some alternative implementations inspired by the embodiments of the present invention.

[0054] According to one embodiment of the present invention, the multiple operation tests include one or more of the following addition tests: a first addition test, wherein the two calculation elements in the test input data are the first operand and the second operand, wherein the second operand is 0, and the reference result is equal to the first operand; a second addition test, wherein the two calculation elements in the test input data are the non-zero third operand and the non-zero fourth operand, wherein the fourth operand is equal to the value obtained by negating the third operand, and the reference result is set to 0; a fourth addition test, wherein the two calculation elements in the test input data are the fifth operand and the sixth operand, wherein the lowest bit to the N-1th bit of the fifth operand are all 1, the lowest bit of the sixth operand is 1, and the reference result is set to the Nth bit being 1 and the lowest bit to the N-1th bit being all 0, and N is the bit width of the adder. In this way, the calculation result (i.e., the reference result) corresponding to the generated test input data can be directly obtained, reducing the on-chip resources used for the test. If this method is not adopted and two operands a and b are randomly generated, then in order to verify whether the generated data is calculated correctly in the ALU, additional addition logic needs to be introduced in the data generation module to calculate the result c of a+b, and compare the result generated by the ALU with the correct result c to determine whether the ALU is invalid. The introduction of additional calculation logic in the data generation module not only increases the chip area, but also may introduce more error factors due to errors in the calculation logic in the data generation module, resulting in incorrect judgments.

[0055] According to one embodiment of the present invention, the multiple operation tests include one or more of the following multiplication tests: a first multiplication test, in which the two calculation elements in the test input data are the seventh operand and the eighth operand, respectively, wherein the seventh operand is 0 and the reference result is set to 0; and / or a second multiplication test, in which the two calculation elements in the test input data are the ninth operand and the tenth operand, respectively, wherein the ninth operand is 1 and the reference result is equal to the tenth operand. For example, for the multiplication operation, random data a and 1 are generated, then the correct reference result is a; random data a and 0 are generated, then the reference result is 0. By generating 0 and 1 and calculating twice, the problem of detection failure can be greatly reduced. Because in integrated circuits, common errors include flip errors and component damage. In a flip error, a certain data, such as 1000101, may be programmed as 1010001, which can be detected. In the case of component damage, one or several levels of logic gates in the adder or multiplier responsible for addition may be damaged, resulting in no output or incorrect output of results. This can also be detected because there is a problem with the calculation result, perhaps missing bits or mismatching results.

[0056] According to one embodiment of the present invention, the multiple operation tests include one or more of the following matrix multiplication tests: a first matrix multiplication test, in which the two calculation elements in the test input data are the first matrix and the second matrix, wherein the second matrix is ​​an all-0 matrix, and the reference result is an all-0 matrix; a second matrix multiplication test, in which the two calculation elements in the test input data are the third matrix and the fourth matrix, wherein the third matrix is ​​a unit matrix, and the reference result is equal to the fourth matrix. For example, a random matrix a and a 0 matrix are generated, then the reference result is 0; a random matrix a and a unit matrix are generated, then the correct result is a.

[0057] According to one embodiment of the present invention, the multiple operation tests include one or more of the following convolution tests: a first convolution test, in which the two computing elements in the test input data are a first tensor representing features and a second tensor representing a convolution kernel, and the step size of the convolution kernel is set to 1, wherein only one element in the second tensor is 1 and the rest are all 0, and the reference result is a related sub-region directly intercepted from the first matrix based on the rules of the convolution operation; a second convolution test, in which the two computing elements in the test input data are a third tensor representing features and a fourth tensor representing the convolution kernel, wherein all elements in the fourth tensor are all 0, and the reference result is an all-0 tensor. For example, the first tensor can be a randomly generated feature of dimension M×N, the second tensor can be a convolution kernel of dimension A×B, the element in the upper left corner of the second tensor is 1 and the rest of the elements are all 0, then the reference result is a sub-region of dimension C×D cut out from the M×N feature by the convolution kernel of A×B; the specific values ​​of C and D and the part of the region of the M×N feature cut out can be directly defined based on the setting of the convolution method. In addition, for the second convolution test, it is directly defined that the M×N feature can be randomly generated as the third tensor, a convolution kernel of dimension A×B with all elements of 0 is generated as the fourth tensor, and the reference result is a C×D tensor of all 0s.

[0058] According to one embodiment of the present invention, the perception module of each computing component performs the following operations: receiving the scheduling of the self-perception controller, and detecting whether the computing component of the neighbor processing unit is normal when the neighbor processing unit does not feedback the detection result. In order to prevent the self-perception module of the computing component from failing, the perception module of each computing component can not only be used for testing the processing unit where it is located, but also can be used to assist in testing the computing components of other processing units. When a processing unit does not transmit the perception result of the computing component back to the self-perception controller, the self-perception controller will start the perception module of the computing component in the processing unit around this processing unit to test this processing unit to verify whether the perception module fails or the computing component fails. It can be seen that the detection of the computing component of the present invention includes module-internal detection BIST and module-external detection. In general, only BIST is used for detection. When BIST itself fails, module-external detection is started, and the dual backup detection method increases the reliability of the detection module itself.

[0059] According to an example of the present invention, the self-sensing process of the entire computing component is as follows: Figure 3 As shown, the schematic implementation steps are as follows:

[0060] Step S101, after a set interval, the controller controls the self-sensing to start; that is, after a period of time, the controller controls the start of the self-sensing process (equivalent to issuing a detection request), and the time interval of the self-sensing can be customized;

[0061] Step S102, generating test data; Figure 2 The test data generator in generates test data for each computing module (for example, ALU addition, ALU multiplication, or Tensor convolution, etc.) for testing;

[0062] Step S103, the current processing unit executes a self-sensing process internally, including performing three operations simultaneously: Operation 1, outputting a selection signal to the selector, selecting the data output by the test data generator as the input data for calculation; Operation 2, transmitting a signal to the input data cache, keeping it, and performing subsequent calculations after the test is completed; Operation 3, transmitting the correct result to the Figure 2The calculation detection module in the calculation detection module is used as the basis for the correctness of the calculation; because the input data is first cached and then input into the calculation component. Holding means switching the state of the cache to a blocking state, and notifying the outside by sending a blocking signal (or holding signal) that the cache is now suspended from transmitting data to it, so that the input data cache no longer provides data to the calculation component, and the outside no longer continues to input data into the data cache, which can prevent the data transmitted from the outside from overwriting the useful data in the cache. The reason for holding the data is that normal calculations cannot be performed during testing. During testing, the data cache is stopped from providing data to the computing device, and data is provided after the test is completed.

[0063] Step S104, acting as an external test module for other PEs, which happens when a problem occurs in the self-sensing module in another PE itself; Figure 2 The output signal O2 of the test data generator in the controller can transmit data to the PE located above / below / left / right of the controller. Two operations are performed at the same time: Operation 1, transmitting the generated test data to the PE located above / below / left / right of the controller; Operation 2, transmitting the correct result to the calculation detection module of the current PE.

[0064] Step S105, self-sensing is performed in the current PE, and after the calculation is completed, the calculation detection module obtains the calculation result;

[0065] Step S106, acting as an external test module for other PEs, after the external calculation is completed, the calculation detection module obtains the calculation results of the PE located above / below / left / right, and transmits them to the calculation detection module through the signal I1;

[0066] Step S107, calculate whether the detection module has received data, if all calculation results are received, go to step S109; otherwise, go to step S108;

[0067] Step S108, represents that the calculation detection module did not receive one, some or all of the calculation results that should have been received. There may be two reasons for this: first, one or several calculation modules (such as ALU, Tensor or others) of the calculation component are damaged and cannot output data; second, the self-sensing module of the current PE is damaged. In order to confirm which of the two reasons is, it is necessary to apply to the self-sensing controller and perform tests outside the module to prove it (this is why step S104 appears).

[0068] Step S109, determine whether the calculated result is correct, if correct, proceed to step S110; otherwise, proceed to step S111.

[0069] Step S110, indicating that the computing component is currently operating normally;

[0070] Step S111 represents an error in the calculation component.

[0071] Step S112, output the results obtained in step S110 and step S111 to the controller, and the output signal is O1.

[0072] Secondly, the present invention divides the failure of routing components into failure of control routing and failure of data transmission. It should be noted that in some simple CGRAs, the on-chip network design is very simple, and the routing components may not be divided into data and control, or even the network shares the same set. Then, when one of them fails, it means that all data and control fail. In this example, a more complex network routing design is adopted, and the control network and data network are separated and independent. The self-sensing design of the routing module is as follows: Figure 4 As shown, it includes a control test module and a data test module.

[0073] According to one embodiment of the present invention, the perception module of the routing component is configured to: perform control routing related test operations, including: a first operation: generate a first data packet with sender information and a first tag (special tag), and send the first data packet to a one-hop neighbor processing unit on the on-chip network through a control routing mechanism, wherein the first tag is used to indicate that the first data packet is a data packet used to test the control routing; a second operation: when the processing unit receives the first data packet sent by other neighbor processing units, it feeds back a second data packet with receiver information and a second tag, wherein the second tag is used to indicate that the second data packet is a data packet fed back by the receiver after correctly receiving the first data packet; a third operation: if the second data packet fed back by all one-hop neighbor processing units is received, it is confirmed that the control routing of this processing unit is normal, otherwise it is abnormal.

[0074] According to one embodiment of the present invention, the perception module of the routing component is also configured to: perform data routing related test operations, including: a fourth operation: generate a random number, construct a third data packet containing the random number and sender information, and send the third data packet to a one-hop neighbor processing unit on the on-chip network through a data routing mechanism; a fifth operation: when the processing unit receives the third data packet sent by other neighbor processing units, it feeds back a fourth data packet containing the received random number and receiver information; a sixth operation: if the fourth data packets fed back by all one-hop neighbor processing units are received and the random numbers carried in each of the fourth data packets are consistent with the generated random number, then it is confirmed that the data routing of this processing unit is normal, otherwise it is abnormal.

[0075] See also Figure 3, the present invention is aimed at the routing components in the processing unit, and subdivides them into data routing and control routing. For data routing and control routing, a self-sensing module is added therein, which is composed of a control test module and a data test module. The control test module has two functions: Function 1: Generate a data packet with a tag (special tag, i.e. a string of unique identifiers), and the data packet contains the information of the sender. When the receiver parses the tag, it will find that this is a self-sensing test packet, and will pass the parsed data to the control test module; Function 2: Transmit the test results of this processing unit to the self-sensing controller. The data test module has two functions: Function 1: Generate a random data packet, and temporarily store it, and transmit it to the receiver through the data routing; Function 2: After the receiver retransmits the data back, compare it with the temporarily stored data packet to determine whether there are problems with the data routing and the network, and transmit the comparison results to the control test module.

[0076] According to an example of the present invention, a schematic process of testing a routing component is as follows: Figure 5 As shown (taking the test between PE0 and PE1 as an example):

[0077] Step 1: PE0 sends a control test data packet to PE1; that is, sends the first data packet

[0078] Step 2: If PE1 receives the data packet sent by PE0, it replies to PE0, that is, replies with the second data packet.

[0079] Step 3, regardless of whether PE0 receives a reply data packet from PE1 or not, PE0 transmits the data packet generated by the data test module to PE1 and temporarily stores the generated random number; that is, generates a third data packet of the random number to be sent to PE1;

[0080] Step 4: If PE1 receives the data sent by PE0, it resends it to PE0; that is, the random number is repackaged and sent to PE1 via the fourth data packet.

[0081] Among them, PE0 compares the received data with the data temporarily stored in the data test module. If they are consistent, the normal data signal is transmitted to the control test module, otherwise the transmission is incorrect. The control test module integrates the information received in step 2 with the information returned by the data test module to obtain the overall routing information and transmit it to the self-sensing controller. It should be noted that in the CGRA architecture, the routing component test needs to be performed on the PEs located above, below, to the left, and to the right at the same time.

[0082] Secondly, the setting of the perception module for the storage component can adopt the existing technology. At present, there are many public algorithms and architectures for the module self-test BIST of the storage component, which will not be repeated in the present invention. Any test method can be used, and then the test results are transmitted back to the self-sensing controller.

[0083] Finally, the present invention adjusts the remapping on the CGRA according to different failure situations.

[0084] The data flow reconfigurable architecture described in the present invention refers to the data transmission between different units (PE) and the mapping of application programs on the array in the CGRA array. The idea of ​​data flow is adopted. When the data is ready, the calculation can be performed, and the program is converted into the form of a data flow graph. The nodes in the data flow graph are mapped to the PE in the array for execution. Therefore, the present invention includes a description of the remapping method after the unit fails, and the routing includes data routing and control routing. Among them, the control routing controls the PE to parse the control signal sent by the host, including the instructions to be executed and the node dependencies of the data flow graph. The data routing is responsible for reading the data in the memory and the data interaction between PEs.

[0085] The method of the present invention proposes different adjustment methods for different possible failure modes. The failure modes of processing units in the CGRA architecture are divided into independent unit failure and adjacent multi-unit failure. Independent unit failure is defined as a failure of a part of a processing unit, but the 8 processing units around the processing unit are operating normally. There are 15 possible independent unit failures, and each corresponding mode of occurrence is described in detail in the aforementioned implementation. The processing methods are divided into two parts: for the current mapping and for subsequent mapping. There are two processing methods for the current mapping: transferring the task of the processing unit to other processing units; refreshing the calculation array of CGRA, re-mapping and calculation. For subsequent mapping, there are two processing methods: ignore and mask. Ignore means that the transmission operation can be performed through the processing unit; mask means that no operation (including calculation, storage, and transmission operations) can be performed through the execution unit, and the on-chip network is disconnected here. Adjacent multi-unit failure is defined as a failure of a part of a processing unit, and there are also failed units in the 8 processing units around it. In the case of adjacent multi-unit failure, the self-sensing controller will summarize the information of the processing units in the entire array, represent the normal processing units with 1, represent the ignored processing units with 0, and represent the shielded processing units with -1, and generate a bitmap representing the entire array. Then the bitmap is converted into a graph with edge length information, and the BFS or DFS algorithm is used for each node in the graph to obtain the shortest path information between the nodes, and these shortest path information are used as the new data transmission path in the mapping. Some illustrative embodiments of remapping are given below.

[0086] According to one embodiment of the present invention, a remapping method for a data flow reconfigurable architecture is provided, comprising: obtaining the detection results of multiple processing units obtained according to the self-sensing method of unit failure in the data flow reconfigurable architecture of the aforementioned embodiment; constructing a bitmap according to the detection results of each processing unit, wherein the state of each processing unit is set; determining new processing array information according to the bitmap, which includes processing units that can work normally and updating the routing path for establishing an on-chip network; obtaining the tasks of the relevant nodes in the data flow graph, remapping the tasks to the processing units in the normal state according to the new processing array information, and transmitting the task-related data according to the updated routing path. Preferably, the state is divided into a normal state, a shielded state and an ignored state, wherein if the computing components, storage components, control routing and data routing of a processing unit are all normal, it is a normal state, as long as the data routing of a processing unit is not normal, it is a shielded state, as long as the data routing of a processing unit is normal, it is an ignored state, when updating the routing path of the on-chip network, the processing units in the normal state and the processing units in the ignored state can both be used as routing nodes, and the processing units in the shielded state cannot be used as routing nodes.

[0087] Indicatively, since the present invention divides PE into three major parts (computing, routing and storage) and four minor parts (routing is divided into data and control), there may be a total of 15 possible abnormal situations (also called failure situations), and each error situation has two problems to be solved (how to process the current operation and how to adjust the mapping scheme later). Most of the errors are independent PE failures, that is, the 8 PEs around the PE are normal PEs, so adjustments can be made directly according to the following 15 possibilities:

[0088] 1. The computing component fails. In the current operation, the instructions and data in the PE are sent to one of the four adjacent PEs, determined by the self-sensing controller, to complete the current operation, avoiding the overhead of reinitializing the CGRA array, mapping the algorithm, and recalculating. In subsequent operations, it is ignored and the algorithm is mapped. The data transmission is as follows Figure 6 The left half of the diagram is shown.

[0089] 2. Data routing failure. This means that the PE cannot transmit or receive data, so the PE can only be blocked and cannot perform any operations. Therefore, the current calculation needs to be remapped and re-executed. In subsequent calculations, it is blocked and its data transmission is Figure 6 The right half of .

[0090] 3. Control routing failure. This means that the PE cannot receive any instructions and control information. The current calculation needs to be remapped and re-executed. In subsequent operations, it is ignored and the algorithm is mapped. Its data transmission is as follows: Figure 6 The left half of the diagram is shown.

[0091] 4. Storage failure. This means that the PE cannot store any data, so the PE cannot perform calculations. The current calculation needs to be remapped and re-executed. In the subsequent operation mapping, it is ignored and the algorithm mapping is performed. Its data transmission is as follows Figure 6 The left half of the diagram is shown.

[0092] 5. The computing components and data routing are both invalid. The PE can only be blocked and cannot perform any operations. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows: Figure 6 The right half of .

[0093] 6. Both the computing component and the control routing are invalid. The data routing of this PE is normal and it can only be used as a relay point for data transmission. Therefore, the current calculation needs to be remapped and re-executed. In the mapping of subsequent calculations, it is ignored and its data transmission is as follows: Figure 6 The left half of the diagram is shown.

[0094] 7. Both the computing component and the storage component fail. The data routing of this PE is normal, and it can only be used as a relay point for data transmission. Therefore, the current calculation needs to be remapped and re-executed. In the mapping of subsequent calculations, it is ignored, and its data transmission is as follows Figure 6 The left half of the diagram is shown.

[0095] 8. Both data routing and control routing are invalid. The PE can only be blocked and cannot perform any operation. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows: Figure 6 The right half of .

[0096] 9. Data routing and storage components are both invalid. The PE can only be blocked and cannot perform any operations. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows: Figure 6 The right half of .

[0097] 10. Both the control routing and storage components fail. The data routing of this PE is normal and it can only be used as a relay point for data transmission. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is ignored and its data transmission is as follows Figure 6 The left half of the diagram is shown.

[0098] 11. The computing component, data routing and control routing are all invalid. The PE can only be blocked and cannot perform any operation. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows Figure 6The right half of .

[0099] 12. Data routing, control routing and storage components are all invalid. The PE can only be blocked and cannot perform any operation. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows Figure 6 The right half of .

[0100] 13. The computing components, data routing and storage components are all invalid. The PE can only be blocked and cannot perform any operations. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows: Figure 6 The right half of .

[0101] 14. The computing component, control routing and storage components are all failed. The data routing of this PE is normal and it can only be used as a relay point for data transmission. Therefore, the current calculation needs to be remapped and re-executed. In the mapping of subsequent calculations, it is ignored and its data transmission is as follows: Figure 6 The left half of the diagram is shown.

[0102] 15. All parts are invalid. The PE can only be blocked and cannot perform any operation. Therefore, the current calculation needs to be remapped and re-executed. In the subsequent calculation mapping, it is blocked and its data transmission is as follows Figure 6 The right half of .

[0103] If multiple units fail, the failures are summarized into a bitmap and reported to the self-sensing controller. It should be noted that the intact PE is marked as 1 in the bitmap; the PE that is ignored and can still perform data transmission, such as Figure 6 As shown on the left, the flag is 0; the shielded one cannot transmit data and must be bypassed, and the flag is -1. Figure 7 If there are multiple PEs on the array and adjacent PEs fail, such as Figure 7 As shown, a self-sensing controller is required to readjust the data transmission network in the array.

[0104] Will Figure 7 The bitmap in is converted into a graph containing the path length, and then the breadth-first algorithm (BFS) or depth-first algorithm (DFS) can be used to obtain the shortest path to obtain the connection method between each node.

[0105] According to an example of the present invention, taking the depth-first algorithm (DFS) as an example, the schematic steps of converting a bitmap into a graph are as follows: Figure 8 As shown:

[0106] Step S201, starting from the first cell as the root node; that is, starting from the vertex of the array, if the vertex of the array is a -1 or 0 cell, then starting from the first cell in the first row with a value of 1, and taking it as the root node;

[0107] Step S202, edge-length=1; that is, the edge length value edge-length of the graph is initialized to 1;

[0108] Step S203, determine whether the previous cell is 1; that is, whether the previous cell of the current vertex is 1; it should be noted that if there are vertices above, below, left, and right around the current vertex, it is necessary to search all around; if it is 1, jump to step S204; otherwise jump to step S205;

[0109] Step S204, when the previous cell is 1, it is recorded as a node in the graph, and an edge between two nodes is created, and the length of the edge is edge-length;

[0110] Step S205, determine whether the previous cell is 0, if it is 0, then jump to step S206; otherwise jump to step S207;

[0111] Step S206, skip and continue searching the next cell; that is, when the current cell is 0, ignore this cell;

[0112] Step S207, changing the search direction; that is, if the previous cell is -1, it means that the path is blocked and the search direction needs to be changed, and the process jumps to step S203;

[0113] Step S208, edge-length=1, indicating that after the nodes and edges are constructed, the edge length value edge-length is initialized to 1;

[0114] Step S209, edge-length=edge-length+1, indicating that a cell with a value of 0 is skipped, and the edge length value edge-length is increased by 1;

[0115] Step S210, determine whether all cells have been traversed; if there are no subsequent cells, end; otherwise jump to step S203 to continue execution.

[0116] It should be noted that there are many excellent open source algorithms and acceleration methods for BFS and DFS, which will not be described in detail in the embodiments of the present invention.

[0117] In general, the self-sensing method proposed in the present invention can enhance the reliability of the reconfigurable processor and can continue to maintain the computing power of the CGRA array when some units fail. Before the method proposed in the present invention, any failure in the CGRA array could not be judged, and the entire CGRA array could not continue to perform subsequent operations. Therefore, the method of the present invention can complete the reconfigurable processor detection with a small area overhead, and remap based on the detection results, so that the remaining normal processing units can be reorganized to complete subsequent calculations.

[0118] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0119] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0120] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0121] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for self-sensing unit failure in a data flow reconfigurable architecture, wherein the data flow reconfigurable architecture refers to a CGRA architecture that can organize and manage processing units according to the data flow of tasks, and the data flow reconfigurable architecture includes a self-sensing controller and multiple processing units, each processing unit includes a computing component, a routing component and a storage component, the routing component includes a control route and a data route, and each component is provided with a sensing module, The method comprises: The self-sensing controller sends a detection request to the processing unit; Each perception module in the processing unit detects whether the computing component, storage component, control routing and data routing are normal according to the detection request, and obtains the detection result; The self-sensing control module collects the detection results fed back by each processing unit.

2. The method according to claim 1, characterized in that: The perception module of the computing component performs the following operations: Acquire test input data and reference results of multiple operation tests in the test calculation component generated according to a preset generation rule, wherein the preset generation rule requires that at least one of the two calculation elements contained in the generated test input data has a specified property so that the reference result can be directly obtained according to the value and / or single calculation element set in the rule; The test input data is transmitted to the components in the computing unit that perform the corresponding computing functions to obtain the computing results, and whether the computing unit is normal is determined based on the reference results and the computing results.

3. The method according to claim 2, characterized in that The various arithmetic tests include one or more of the following addition tests: A first addition test, wherein two calculation elements in the test input data are respectively a first operand and a second operand, wherein the second operand is 0, and the reference result is equal to the first operand; A second addition test, wherein two calculation elements in the test input data are respectively a non-zero third operand and a non-zero fourth operand, wherein the fourth operand is equal to a value obtained by negating the third operand, and the reference result is set to 0; The fourth addition test, in which the two calculation elements in the test input data are the fifth operand and the sixth operand, respectively, wherein the lowest bit to the N-1th bit of the fifth operand are all 1, and the lowest bit of the sixth operand is 1, and the reference result is set to the Nth bit as 1 and the lowest bit to the N-1th bit as all 0, and N is the bit width of the adder.

4. The method according to claim 2, characterized in that: The multiple arithmetic tests include one or more of the following multiplication tests: A first multiplication test, wherein two computational elements in the test input data are the seventh operand and the eighth operand, respectively, wherein the seventh operand is 0 and the reference result is set to 0; and / or The second multiplication test tests two calculation elements in the input data are the ninth operand and the tenth operand, respectively, wherein the ninth operand is 1 and the reference result is equal to the tenth operand.

5. The method according to claim 2, characterized in that: The various operations tests include one or more of the following matrix multiplication tests: A first matrix multiplication test, in which two calculation elements in the test input data are a first matrix and a second matrix, wherein the second matrix is ​​an all-0 matrix, and the reference result is an all-0 matrix; The second matrix multiplication test, in which two calculation elements in the test input data are the third matrix and the fourth matrix, wherein the third matrix is ​​the unit matrix, and the reference result is equal to the fourth matrix.

6. The method according to claim 2, characterized in that The various operation tests include one or more of the following convolution tests: The first convolution test, in which the two computational elements in the test input data are the first tensor representing the feature and the second tensor representing the convolution kernel, and the step size of the convolution kernel is set to 1, where only one element in the second tensor is 1 and the rest are all 0, and the reference result is the relevant sub-region directly intercepted from the first matrix based on the rule of the convolution operation; The second convolution test tests that the two computational elements in the input data are the third tensor representing the features and the fourth tensor representing the convolution kernel. All elements in the fourth tensor are 0, and the reference result is a tensor of all 0s.

7. The method according to claim 2, characterized in that: The perception module of the routing component is configured as follows: Perform control routing related test operations, including: The first operation is to generate a first data packet with sender information and a first tag, and send the first data packet to a one-hop neighbor processing unit on the network on chip through a control routing mechanism, wherein the first tag is used to indicate that the first data packet is a data packet for testing the control routing; The second operation: after receiving the first data packet sent by other neighboring processing units, the processing unit feeds back a second data packet with receiver information and a second tag, where the second tag is used to indicate that the second data packet is a data packet fed back by the receiver after correctly receiving the first data packet; The third operation: if the second data packet fed back by all one-hop neighbor processing units is received, it is confirmed that the control routing of the processing unit is normal, otherwise it is abnormal.

8. The method according to claim 7, characterized in that The perception module of the routing component is also configured to: Perform data routing related test operations, including: Fourth operation: generating a random number, constructing a third data packet with the random number and sender information, and sending the third data packet to a one-hop neighbor processing unit on the on-chip network through a data routing mechanism; The fifth operation: after receiving the third data packet sent by other neighboring processing units, the processing unit feeds back a fourth data packet carrying the received random number and the receiver information; Operation 6: If the fourth data packets fed back by all one-hop neighbor processing units are received and the random number carried in each of the fourth data packets is consistent with the generated random number, it is confirmed that the data routing of the processing unit is normal; otherwise, it is abnormal.

9. The method according to any one of claims 1 to 8, characterized in that: The perception module of each computing component performs the following operations: Receive the scheduling of the self-sensing controller, and detect whether the computing component of the neighbor processing unit is normal when the neighbor processing unit does not feed back the detection result.

10. A remapping method for a data flow reconfigurable architecture, comprising: Obtaining detection results of multiple processing units obtained according to the method of any one of claims 1-9; According to the detection result of each processing unit, a bitmap is constructed, in which the state of each processing unit is set; Determining new processing array information according to the bitmap, which includes processing units that can work normally and updating a routing path for establishing an on-chip network; The tasks of the related nodes in the data flow graph are obtained, the tasks are remapped to the processing units in the normal state according to the new processing array information, and the data related to the tasks are transmitted according to the updated routing path.

11. The method according to claim 10, characterized in that The states are divided into normal state, shielded state and ignored state, wherein if the computing components, storage components, control routing and data routing of a processing unit are all normal, it is in normal state; as long as the data routing of a processing unit is not normal, it is in shielded state; as long as the data routing of a processing unit is normal, it is in ignored state. When updating the routing path of the on-chip network, the processing units in the normal state and the processing units in the ignored state can both serve as routing nodes, and the processing units in the shielded state cannot serve as routing nodes.

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