Universal FPGA (Field Programmable Gate Array) logic structure and design method thereof

Abstract

The embodiment of the invention provides a universal FPGA (Field Programmable Gate Array) logic structure and a design method, and the universal FPGA logic structure comprises a function module, a data exchange module and a signal conversion module, the function modules comprise a solidification function module and a user-defined function module, whether each function module is instantiated or not, a base address and an address space size are set through a macro definition file, and data flow directions among the function modules are configured; the data exchange module is used for realizing data transmission among the functional modules according to the configured data flow directions among the functional modules; the input and the output of the data exchange module adopt self-defined standard time sequence interfaces; and the signal conversion module is used for connecting each functional module with the data exchange module to realize signal conversion between the custom standard time sequence interface and the common interface of each functional module. According to the invention, the application range of the module is expanded, and continuously changing design requirements can be effectively met.

Description

Technical Field

[0001] This document relates to the field of electronic design technology, and in particular to a generalized FPGA logic structure and its design method. Background Art

[0002] FPGAs, with their fine-grained parallelism at the lookup table and logic gate levels, are widely used in various electronic systems that have stringent requirements on real-time, deterministic, and bandwidth-critical computing units. They are widely used in digital signal processing, communications, video and audio signal processing, industrial control, military applications, instrumentation, and high-performance computing. The biggest advantage of FPGA is its extremely fine-grained parallelism, but its extremely fine-grained parallel architecture also brings many problems to engineering design, which are mainly reflected in the following aspects: High design threshold: The highly parallel operation mode of FPGA is quite different from the serial thinking mode of the human brain, making it have a higher design threshold than most programming languages ​​​​such as C, C++, Python, and C#; Weak module versatility: FPGA's module-level reuse is not only closely related to signal names and signal functions, but the timing relationship between signals will also affect module functions, which greatly reduces the versatility between FPGA modules; Long synthesis implementation time: The synthesis implementation of FPGA design code needs to correspond to the trigger mechanism of each basic unit, which makes the synthesis implementation time of medium-scale designs relatively long. For example, the synthesis implementation time of Xilinx's 7k325t is about 30 minutes or more.

[0003] Therefore, in response to the problems existing in FPGA engineering applications, with the main goal of improving development efficiency, it is of great engineering significance to conduct research on structured, universal and standardized architectures. Drawing on modern SOC design ideas, a reconfigurable and universal FPGA logic structure is proposed to improve the efficiency of FPGA customized development. Based on the proposed reconfigurable and universal FPGA logic structure, the logic design, verification and related application deployment of the prototype system are completed in response to the relevant needs of the industrial control field. Summary of the Invention

[0004] One or more embodiments of this specification provide a generalized FPGA logic structure, including: a functional module, a data exchange module, and a signal conversion module; The functional modules include fixed functional modules and custom functional modules. The macro definition file is used to set whether each functional module is instantiated, the base address and the address space size, and the data flow between the functional modules is configured; The data exchange module is used to realize data transmission between each functional module according to the data flow between the configured functional modules; the input and output of the data exchange module both adopt a custom standard timing interface; The signal conversion module is used to connect each functional module with the data exchange module to achieve signal conversion between the custom standard timing interface and the common interface of each functional module.

[0005] Furthermore, the address space of each functional module is determined by a base address and an offset address.

[0006] Furthermore, the memory corresponding to the address space of each functional module includes a register file and a RAM, the register file is located in the starting area of ​​the address space, and the RAM is located in the address space outside the area where the register file is located.

[0007] Furthermore, the data exchange module divides the output signals into four groups: enable, addr, data, and ready according to the output signal characteristics. Each group is provided with a multiplexer equal to the number of output signals included. The signal interconnection of different functional modules is completed by configuring the selection signal of the multiplexer; wherein, the selection signal of the multiplexer is automatically generated by the host computer after being configured according to the needs.

[0008] Furthermore, the data exchange module includes a data input exchange module and a data output exchange module, and there is a deterministic exchange delay between the data input exchange module and the output exchange module.

[0009] Furthermore, the signal conversion module realizes the conversion of the following six common interfaces of functional modules to custom standard timing interfaces, specifically including: Register input conversion: used to write calculation result data into the register file of the address space; Register output conversion: used to read data from the register file in the address space for its own calculation function; Data sending conversion: used to send certain data in its own address space to the target module; Function module write conversion: used to write data to its own address space or a certain address in the target module address space; Function module read conversion: used to read data from its own address space for its own calculation function; Target address feedback conversion: used to receive data sent by the target functional module for its own calculation.

[0010] Furthermore, the input data of the customized standard timing interface includes data obtained by the data sending conversion, the function module writing conversion and the function module reading conversion.

[0011] Furthermore, a priority is set for the conversion operation of the commonly used interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the missed conversion operation is cached until the conversion operation is executed when it has the highest priority.

[0012] One or more embodiments of this specification provide a generalized FPGA logic structure design method, including: The macro definition file is used to set whether each functional module is instantiated, the base address and the address space size, and configure the data flow between each functional module; the functional modules include fixed functional modules and custom functional modules; The data exchange module realizes data transmission between each functional module according to the data flow between the configured functional modules; the input and output of the data exchange module both adopt a custom standard timing interface; Each functional module is connected to the data exchange module through a signal conversion module to achieve signal conversion between the custom standard timing interface and the common interface of each functional module.

[0013] Furthermore, when the signals of the custom standard timing interface and the commonly used interfaces of each functional module are converted, a priority is set for the conversion operation from the commonly used interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the missed conversion operation is cached until the conversion operation is executed when it has the highest priority.

[0014] By adopting the embodiment of the present invention, the functional modules are solidified and customized, so that users can flexibly select and adjust functions according to specific application requirements and support a variety of application scenarios; the module instantiation, base address and address space size are set through the macro definition file, which reduces the complexity of the design process and improves the development efficiency; the data exchange module is responsible for configuring and managing the data flow between the functional modules, ensuring efficient and accurate data transmission and reducing the delay of data processing; the data between different modules are interacted through the customized standard timing interface, and the signal conversion module is introduced to allow seamless connection between different functional modules and the data exchange module, support compatibility between different interfaces, expand the scope of application of the module, and is suitable for a variety of complex applications, which can effectively respond to changing design requirements.

[0015] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of a generalized FPGA logic structure provided for one or more embodiments of this specification; Figure 2 A schematic diagram of a data exchange module design for a generalized FPGA logic structure provided in one or more embodiments of this specification; Figure 3 A schematic diagram of a signal conversion module design for a generalized FPGA logic structure provided in one or more embodiments of this specification; Figure 4 A schematic diagram of a generalized prototype system software design for a generalized FPGA logic structure provided in one or more embodiments of this specification; Figure 5 A flowchart of a generalized FPGA logic structure design method provided in one or more embodiments of this specification. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this document. Example 1

[0019] According to an embodiment of the present invention, a generalized FPGA logic structure is provided. Figure 1 A schematic diagram of a generalized FPGA logic structure provided in one or more embodiments of this specification, such as Figure 1 As shown, the generalized FPGA logic structure according to an embodiment of the present invention specifically includes a functional module, a data exchange module and a signal conversion module. Each functional module, such as pulse width modulation PWM, analog-to-digital converter ADC and universal asynchronous receiver transmitter UART, is processed by the signal conversion module and then realizes data transmission between each other through the data exchange module.

[0020] Functional modules are mainly used to implement a relatively independent category or function, including verified solidified functional modules and customized functional modules for special user needs. Each functional module is allocated an address space. The macro definition file can be used to set whether each functional module is instantiated, the base address and address space size, and configure the data flow between functional modules.

[0021] The address space of each functional module is determined by a base address and an offset address. The base address is the starting address of the functional module in the memory or peripheral address space. This address is a fixed address assigned to the module and is usually set during system initialization. The offset address is a value relative to the base address and is used to identify a specific register or memory location. Within the same functional module, the offset address is usually variable and is used to access different registers or data. The memory corresponding to each functional module's address space includes a register stack and RAM. The register stack is located in the starting area of ​​the address space, and the RAM is located in the address space outside the register stack area.

[0022] The data exchange module is used to realize data transmission between functional modules according to the configured data flow between the functional modules. Its input and output both adopt customized standard timing interface and have strong scalability.

[0023] Figure 2 This is a schematic diagram of the design structure of the data exchange module, such as Figure 2 As shown, the data exchange module divides output signals into four groups based on their characteristics: enable, addr, data, and ready. Each group is equipped with multiplexers equal to the number of output signals it contains. Signals from different functional modules are interconnected by configuring the multiplexer's selection signals. The multiplexer's selection signals are automatically generated by the host computer after configuration based on requirements. When interconnecting a specific output signal of one functional module with a specific input signal of another functional module, the first step is to determine which group of output signals (such as the enable group or addr group) is involved. The multiplexer corresponding to the output signal in that group is then found. Next, the multiplexer's selection signal is configured based on the desired signal source and the requirements of the target module, so that the multiplexer outputs the correct input signal, thereby completing the interconnection between the two functional modules for that specific output signal. For example, if the data output signal of one functional module is to be interconnected with the input port of another functional module, the multiplexer corresponding to the data output signal in the data group must be found and its selection signal configured to achieve the correct signal connection.

[0024] The data exchange module includes a data input exchange module and a data output exchange module. The exchange delay between the data input exchange module and the output exchange module is deterministic. For example, when the system clock is set to 100MHz, the delay from the input to the output of the data exchange module is 10ns.

[0025] In order to access the data exchange module, each functional module needs to complete the conversion of the original data interface of the module to the custom standard timing interface. The signal conversion module is used to connect each functional module with the data exchange module to realize the signal conversion between the custom standard timing interface and the common interface of each functional module. Common interfaces include register interface, RAM interface, etc. During the conversion process, issues such as timing constraints, address hits, priority judgment during data conflicts, and data caching need to be considered.

[0026] Signal conversion module design scheme as follows Figure 3 As shown in the figure, the signal conversion module converts the commonly used interfaces of each functional module to a custom standard timing interface, completes the cleaning of the functional module input and output data, and implements data conflict priority judgment and data caching mechanism. Specifically, the signal conversion module can convert the following six commonly used interfaces to a custom standard timing interface, including: Register input conversion: used to write calculation result data into the register file of the address space; Register output conversion: used to read data from the register file in the address space for its own calculation function; Data sending conversion: used to send certain data in its own address space to the target module; Function module write conversion: used to write data to its own address space or a certain address in the target module address space; Function module read conversion: used to read data from its own address space for its own calculation function; Target address feedback conversion: used to receive data sent by the target functional module for its own calculation.

[0027] Priority is set for the conversion operation from the commonly used interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the conversion operation that is not hit is cached until the conversion operation is executed at the highest priority. Specifically, the address space of each functional module is composed of a register stack and a RAM. During the operation of the register stack and the RAM, write conflicts should be avoided. In addition, if a single-port RAM is used, simultaneous read operations should also be avoided. Therefore, in this embodiment, during the design process, the signal conversion module virtualizes operations such as data sending, functional module writing, and functional module reading as input data of the custom standard timing interface. All operations of the custom timing interface are hit according to the priority, and the address and data information that are not hit is cached until the operation is executed at the highest priority.

[0028] Based on the aforementioned design ideas for a reconfigurable, general-purpose FPGA structure, we established a prototype system to meet certain design requirements in the industrial control field (focusing on analyzing digital power supply and motor drive control requirements) and verify the feasibility of the reconfigurable, general-purpose FPGA structure. The core processor of the hardware board consists of two parts: FPGA and DSP. Among them, FPGA is mainly used to implement external AD sampling, PWM output, PWM input signal acquisition, Ethernet, SRIO and other interface drivers, as well as high real-time and high determinism algorithm implementation. DSP is mainly used to complete user control algorithms and communicate with the upper system.

[0029] In response to the needs of industrial control in terms of sampling, drive control and communication, the proposed reconfigurable general FPGA logic structure is used to carry out prototype system design work, such as Figure 4 As shown in the figure, the general prototype system software mainly consists of three parts: FPGA, DSP and host computer. The FPGA is designed with a reconfigurable general structure. The DSP part is a driver library designed for FPGA, which is convenient for application programs to call. The host computer generates FPGA configuration parameters and corresponding DSP library functions according to the requirements of each project.

[0030] The functional modules included in the general prototype system software are shown in Table 1: Table 1

[0031] Currently, the software system has been deployed and applied to DSP+FPGA controllers and is used in digital power supply projects. Example 2

[0032] According to an embodiment of the present invention, a generalized FPGA logic structure design method is provided. Figure 5 This is a flowchart of a generalized FPGA logic structure design method provided in one or more embodiments of this specification. The generalized FPGA logic structure design method according to an embodiment of the present invention specifically includes: S1 through the macro definition file for each functional module is instantiated, the base address and address space size are set, and configure the data flow between the functional modules; the functional modules include curing functional modules and custom functional modules; S2. Data exchange module according to the configuration of the data flow between the functional modules to achieve data transmission between the functional modules; the input and output of the data exchange module are custom standard timing interface; S3. Connect each functional module to the data exchange module through a signal conversion module to achieve signal conversion between the custom standard timing interface and the common interface of each functional module.

[0033] Furthermore, when the signals of the custom standard timing interface and the commonly used interfaces of each functional module are converted, a priority is set for the conversion operation from the commonly used interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the missed conversion operation is cached until the conversion operation is executed when it has the highest priority.

[0034] This embodiment of the present invention corresponds to the above-mentioned embodiment 1. The specific operations can be understood by referring to the description of embodiment 1 and will not be repeated here.

[0035] The beneficial effects of the present invention are as follows: By adopting the embodiment of the present invention, the functional modules are solidified and customized, so that users can flexibly select and adjust functions according to specific application requirements and support a variety of application scenarios; the module instantiation, base address and address space size are set through the macro definition file, which reduces the complexity of the design process and improves the development efficiency; the data exchange module is responsible for configuring and managing the data flow between the functional modules, ensuring efficient and accurate data transmission and reducing the delay of data processing; the data between different modules are interacted through the customized standard timing interface, and the signal conversion module is introduced to allow seamless connection between different functional modules and the data exchange module, support compatibility between different interfaces, expand the scope of application of the module, and is suitable for a variety of complex applications, which can effectively respond to changing design requirements.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A generalized FPGA logic structure, characterized in that: include: Functional module, data exchange module and signal conversion module; The functional modules include fixed functional modules and custom functional modules. The macro definition file is used to set whether each functional module is instantiated, the base address and the address space size, and the data flow between the functional modules is configured; The data exchange module is used to realize data transmission between each functional module according to the data flow direction between the configured functional modules; the input and output of the data exchange module both adopt a custom standard timing interface; The signal conversion module is used to connect each functional module with the data exchange module to achieve signal conversion between the custom standard timing interface and the common interface of each functional module.

2. The structure according to claim 1, characterized in that: The address space of each functional module is determined by a base address and an offset address.

3. The structure according to claim 2, characterized in that: The memory corresponding to the address space of each functional module includes a register stack and a RAM. The register stack is located in the starting area of ​​the address space, and the RAM is located in the address space outside the area where the register stack is located.

4. The structure according to claim 1, characterized in that The data exchange module divides the output signals into four groups of enable, addr, data and ready according to the output signal characteristics. Each group is provided with a multiplexer equal to the number of output signals included. The signal interconnection of different functional modules is completed by configuring the selection signal of the multiplexer; wherein the selection signal of the multiplexer is automatically generated by the host computer after being configured according to the requirements.

5. The structure according to claim 1, characterized in that: The data exchange module includes a data input exchange module and a data output exchange module, and there is a deterministic exchange delay between the data input exchange module and the output exchange module.

6. The structure according to claim 1, characterized in that The signal conversion module realizes the conversion of the common interfaces of the following six functional modules to the custom standard timing interfaces, specifically including: Register input conversion: used to write the calculation result data into the register file of the address space; Register output conversion: used to read data from the register file of the address space for its own calculation function; Data sending conversion: used to send certain data in its own address space to the target module; Function module write conversion: used to write data to a certain address in its own address space or the target module address space; Function module read conversion: used to read data from its own address space for its own calculation function; Target address feedback conversion: used to receive data sent by the target functional module for its own calculation.

7. The structure according to claim 6, characterized in that The input data of the custom standard timing interface includes data obtained by the data sending conversion, the function module writing conversion and the function module reading conversion.

8. The structure according to claim 7, characterized in that Priority is set for the conversion operation from the common interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the missed conversion operation is cached until the conversion operation is executed when it has the highest priority.

9. A generalized FPGA logic structure design method, characterized in that: include: Whether each functional module is instantiated, the base address and the address space size are set through the macro definition file, and the data flow between each functional module is configured; the functional module includes a fixed functional module and a custom functional module; The data exchange module realizes data transmission between the functional modules according to the data flow direction between the configured functional modules; the input and output of the data exchange module both adopt a custom standard timing interface; Each functional module is connected to the data exchange module through a signal conversion module to achieve signal conversion between the custom standard timing interface and the common interface of each functional module.

10. The method according to claim 9, characterized in that When the signals of the custom standard timing interface and the common interfaces of each functional module are converted, a priority is set for the conversion operation from the common interface of the functional module to the custom standard timing interface, the conversion operation of the custom standard timing interface is hit according to the priority, and the address and data information in the input data of the missed conversion operation is cached until the conversion operation is executed when it has the highest priority.

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