Address counter using asynchronous input and method for operating address counter

Abstract

The invention relates to an address counter using asynchronous input and an operation method of the address counter. The address counter includes a flip-flop that, in response to a first logic signal provided to a flip-flop SET terminal and a second logic signal provided to a flip-flop RESET terminal, performs a loading operation of loading a start column address signal, and performs a counting operation of sequentially increasing a data value of the start column address signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0083422 filed in the Korean Intellectual Property Office on June 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to an electronic device, and more particularly, to an address counter and an operating method of the address counter. Background Art

[0004] The storage device stores data under the control of the host device. The storage device may include a memory device that stores data and a storage controller that controls the memory device. The memory device may be classified as a volatile memory device or a non-volatile memory device.

[0005] The nonvolatile memory device may decode addresses through a row decoder and a column decoder and transmit the decoded addresses to a memory cell array. Summary of the invention

[0006] An embodiment provides an address counter using asynchronous input. According to one aspect of the present disclosure, there is provided an address counter including a flip-flop, the flip-flop being configured to perform a load operation of loading a start column address signal in response to a first logic signal received at a set input of the flip-flop and a second logic signal received at a reset input of the flip-flop, and to perform a count operation of sequentially increasing a data value of the start column address signal.

[0007] According to another aspect of the present disclosure, a method of operating an address counter including a trigger is provided, the method including: generating a first logic signal and a second logic signal; applying the first logic signal to a set terminal of the trigger; applying the second logic signal to a reset terminal of the trigger; and loading a start column address signal when at least one of the first logic signal and the second logic signal has a first logic level. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will now be described more fully with reference to the accompanying drawings; however, example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0009] In the accompanying drawings, dimensions may be exaggerated for ease of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 The embodiment according to the present disclosure is shown in detail. Figure 1 A block diagram of a non-volatile memory device is shown in FIG.

[0012] Figure 3 The embodiment according to the present disclosure is shown in detail. Figure 2 The circuit diagram of the address counter is shown in .

[0013] Figure 4 The invention is a detailed description of the use of the embodiment according to the present disclosure. Figure 2 Circuit diagram of a four-bit address counter implementing the counter shown in FIG.

[0014] Figure 5 is a timing diagram illustrating a loading operation according to an embodiment of the present disclosure.

[0015] Figure 6 is a timing diagram illustrating a counting operation according to an embodiment of the present disclosure.

[0016] Figure 7 is a flowchart illustrating an operation method of an address counter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are only used to illustrate embodiments of the concepts according to the present disclosure. Embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0018] Figure 1 2 is a block diagram showing a memory device according to an embodiment of the present disclosure. The memory device 50 may include a nonvolatile memory device 100 and a memory controller 200 .

[0019] The nonvolatile memory device 100 may store data under the control of the memory controller 200. The nonvolatile memory device 100 may include an address counter 160. The address counter 160 may generate a column address according to a command received from the memory controller 200. The column address is necessary for the memory controller 200 to store data in the nonvolatile memory device 100 or read data stored in the nonvolatile memory device 100. The address counter 160 may use an asynchronous input. This will be described below with reference to FIG. Figure 2 This is described in detail.

[0020] In some embodiments, the nonvolatile memory device 100 may be a NAND flash memory, but the scope of the present disclosure is not limited thereto. The nonvolatile memory device 100 may be one of a variety of memory devices capable of retaining stored data even when power is interrupted, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), and a ferroelectric random access memory (FRAM).

[0021] The memory controller 200 may control the operation of the nonvolatile memory device 100 based on a command received from the host. The memory controller 200 may store data in the nonvolatile memory device 100 or read data stored in the nonvolatile memory device 100 according to the command of the host.

[0022] Figure 2 The embodiment according to the present disclosure is shown in detail. Figure 1 A block diagram of a non-volatile memory device is shown in FIG.

[0023] Reference Figure 2 The nonvolatile memory device 100 may include a memory cell array 110 , a row decoder 120 , a voltage generating circuit 130 , a page buffer circuit 140 , a column decoder 150 , an address counter 160 , and a control logic circuit 170 .

[0024] The memory cell array 110 may include a plurality of memory blocks. Each memory block may include a plurality of cell strings. Each cell string may be connected to the row decoder 120 through a word line WL, and connected to the page buffer circuit 140 through a bit line BL.

[0025] Each cell string may include a plurality of memory cells. Each of the plurality of memory cells may have a cell transistor connected in series between a bit line BL and a selection line. The plurality of cell transistors may be connected to a drain selection line, a word line, and a source selection line.

[0026] In some embodiments, the row decoder 120, the voltage generating circuit 130, the page buffer circuit 140, the column decoder 150, and the address counter 160 may be collectively designated as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic circuit 170. The peripheral circuit may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0027] The row decoder 120 may be connected to the memory cell array through the word lines WL. The row decoder 120 may receive a row address signal RA, thereby activating a word line corresponding to the row address signal RA.

[0028] The voltage generating circuit 130 may generate various operating voltages for the operation of the nonvolatile memory device 100. For example, the voltage generating circuit 130 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of verification voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, and a plurality of erase verification voltages based on the power supply voltage VCC.

[0029] The page buffer circuit 140 may be connected to the memory cell array 110 through the bit line BL. The page buffer circuit 140 may sense a voltage change of the bit line BL to read data stored in the memory cell array 110 and temporarily store the read data. The page buffer circuit 140 may receive data from the column decoder 150 and control the bit line BL based on the received data to store the data in the memory cell array 110.

[0030] The column decoder 150 may transfer data DATA received from an external device to the page buffer circuit 140 through a data line corresponding to a column address signal CA.

[0031] The address counter 160 may generate a column address signal CA by sequentially increasing a data value of a start column address signal CA_ST. The address counter 160 may transmit the column address signal CA to the column decoder 150.

[0032] In some embodiments, the address counter 160 may be connected to the column decoder 150 through a plurality of address lines. When the column address signal CA includes four bits, the least significant bit of the column address signal CA may be output to the column decoder 150 through a first address line, the first bit of the column address signal CA may be output to the column decoder 150 through a second address line, the second bit of the column address signal CA may be output to the column decoder 150 through a third address line, and the most significant bit of the column address signal CA may be output to the column decoder 150 through a fourth address line.

[0033] The start column address signal CA_ST may refer to a column address signal at a point where data starts to be input. The address counter 160 may generate a column address signal CA assigned to consecutive input data by sequentially increasing the received start column address signal CA_ST.

[0034] The address counter 160 may perform a loading operation and a counting operation. The loading operation may be an operation of loading the received start column address signal CA_ST to the address counter 160. The counting operation may be an operation of sequentially increasing the value starting from the data value of the loaded start column address signal CA_ST until a column address signal CA having a desired data value is generated. That is, the start column address signal CA_ST loaded to the address counter 160 and the column address signal CA at the start of the counting operation may have the same value.

[0035] The address counter 160 can perform a load operation using an asynchronous input and a count operation using a synchronous input. Figure 3 This is described in detail.

[0036] The control logic circuit 170 may control the operation of the nonvolatile memory device 100. For example, the control logic circuit 170 may control the row decoder 120, the voltage generating circuit 130, the page buffer circuit 140, the column decoder 150, and the address counter 160 in response to a command CMD received from an external device such as the memory controller 200.

[0037] Figure 3 The embodiment according to the present disclosure is shown in detail. Figure 2 The circuit diagram of the address counter is shown in .

[0038] Reference Figure 3 The address counter 160 includes a first AND gate AG1, an inverter INV, a second AND gate AG2, an XOR gate XR, and a flip-flop DF. The address counter 160 can perform a load operation and a count operation on one bit. Figure 3 The address counter 160 shown in FIG. 1 may include a one-bit counter. The one-bit counter may perform a load operation and a count operation on one bit.

[0039] Hereinafter, for convenience of description, the nth bit of the start column address signal CA_ST may be designated as a first bit signal CA_ST[n], and the nth bit of the column address signal CA may be designated as a second bit signal CA[n].

[0040] The first AND gate AG1 can generate a first logic signal S output to the SET input terminal S of the D flip-flop DF by performing an AND operation on the first bit signal CA_ST[n] and the enable signal EN. Therefore, the enable signal EN can be a signal for performing a load operation. For example, when the enable signal EN is logic 1, the address counter 160 can perform a load operation by forcing the Q output of the flip-flop DF to logic 1. Therefore, the enable signal EN can be considered as a load enable signal.

[0041] The inverter INV can output the inverted logic level of the first bit signal CA_ST[n]. Therefore, the second AND gate AG2 can generate a second logic signal RS output to the RESET input terminal RS of the flip-flop DF by performing an AND operation on the inverted signal CA_ST[n] and the enable signal EN. The enable signal EN can be Figure 2 The control logic circuit 170 shown in FIG. 1 receives the signal.

[0042] Since the second AND gate AG2 generates the second logic signal RS by performing an AND operation on the inverted signal CA_ST[n] and the enable signal EN, when the enable signal EN1 is logic 1, at least one of the first logic signal S and the second logic signal RS may be logic 1. When the enable signal EN has a second logic level, i.e., logic zero, the first logic signal S and the second logic signal RS may have a second logic level, i.e., logic zero.

[0043] The XOR gate XR may output a third bit signal CA_CNT[n] by performing an XOR operation on the second bit signal CA[n] and the carry signal CR. The third bit information CA_CNT[n] may be the nth bit of the count column address signal CA_CNT.

[0044] When the carry signal CR has a first logic level, that is, logic 1, the XOR gate XR can output a third bit signal CA_CNT[n] obtained by inverting the logic level of the second bit signal CA[n]. For example, when the carry signal CR is logic 1 and the previous data value of the second bit signal CA[n] is logic 1, the XOR gate XR can output the third bit signal CA_CNT[n] whose previous data value is logic zero. When the carry signal CR has a logic high level, that is, logic 1, and the previous data value of the second bit signal CA[n] is logic zero, the XOR gate XR can output the third bit signal CA_CNT[n] whose previous data value is logic 1. That is, when the carry signal CR has a logic high level, the XOR gate XR can output a counting column address signal CA_CNT in which the binary data of the column address signal CA is increased by "1".

[0045] When the carry signal CR has the second logic level or logic zero, the XOR gate XR may output the third bit signal CA_CNT[n] having the same logic level as the second bit signal CA[n].

[0046] The flip-flop DF may include a D terminal (also referred to as a D "input terminal") receiving a third bit signal CA_CNT[n], a clock input terminal (also referred to as a clock "input terminal") receiving a clock signal CLK, an S (SET) terminal (also referred to as a SET "input terminal") receiving a first logic signal or logic 1, an RS (Reset) terminal (also referred to as an RS "input terminal") receiving a second logic signal or logic zero, a Q output terminal (also referred to as a Q "output terminal") connected to an XOR gate XR, and a QB terminal (also referred to as a QB or Q' "output terminal") in a floating state. The clock signal CLK may be received from Figure 2 The control logic circuit 170 shown in FIG. 1 receives the signal.

[0047] In a preferred embodiment, the flip-flop DF may be a D-type flip-flop. In an alternative embodiment, the flip-flop may be a JK-type flip-flop with the "K" input fixed at logic zero.

[0048] Hereinafter, the operation of the address counter 160 according to the first logic signal and the second logic signal will be described.

[0049] The address counter 160 may perform one of a load operation and a count operation based on the first logic signal and the second logic signal. When at least one of the first logic signal S and the second logic signal RS has a first logic level, i.e., logic 1, the address counter 160 may perform a load operation. When the first logic signal and the second logic signal have a second logic level, i.e., logic 0, the address counter 160 may perform a count operation.

[0050] When at least one of the first logic signal S and the second logic signal RS has a first logic level, i.e., logic 1, the flip-flop DF may output the first logic signal to the S terminal. The first logic signal S output at the Q terminal may be fed back to the XOR gate XR. In some embodiments, when the enable signal EN has a first logic level, i.e., logic 1, the first logic signal S may have the same data value as the first bit signal CA_ST[n]. When the enable signal EN has a first logic level, i.e., logic 1, the address counter 160 may load the first bit signal CA_ST[n] as the second bit signal CA[n].

[0051] When the first logic signal S and the second logic signal RS have the second logic level, i.e., logic 0, the flip-flop DF can output the third bit signal CA_CNT[n] input to the D terminal for each rising edge time of the clock signal CLK. The third bit signal CA_CNT[n] output at the Q terminal can be fed back to the XOR gate XR.

[0052] In some embodiments, when the carry signal CR has a first logic level, ie, logic 1, and the first and second logic signals S and RS have a second logic level, ie, logic zero, the address counter 160 may increase the data value of the second bit signal CA[n] by '1'.

[0053] In some embodiments, when the enable signal EN has a first logic level, i.e., logic 1, at least one of the first logic signal S and the second logic signal RS may have a first logic level, i.e., logic 1. When the enable signal EN has a second logic level, i.e., logic zero, the first logic signal S and the second logic signal RS may have a second logic level, i.e., logic zero. That is, when the enable signal EN has a first logic level, i.e., logic 1, the address counter 160 may perform a load operation. When the enable signal EN has a second logic level, i.e., logic zero, the address counter 160 may perform a count operation. The first logic level may be logic 1 or a high level. The second logic level may be logic zero or a low level.

[0054] As described above, the address counter 160 may load the first bit signal CA_ST[n] through a load operation, and generate a signal whose data value sequentially increases from the first bit signal CA_ST[n] through a count operation.

[0055] In the case of a general address counter, the address counter outputs a signal for performing one of a load operation and a count operation to the flip-flop DF through the multiplexer. Therefore, when the address counter performs the count operation, a time delay may occur in the multiplexer, the XOR gate XR, and the flip-flop DF.

[0056] However, referring to Figure 3 , the address counter 10 can separate the loading operation and the counting operation from each other through the asynchronous input and the synchronous input. When at least one of the signals received from the S terminal and the RS terminal of the flip-flop DF has a first logic level, the address counter 160 can perform a loading operation. When the received signals from the S terminal and the RS terminal have a second logic level, the address counter 160 can perform a counting operation. Therefore, when the address counter 160 performs a counting operation, a time delay may occur in the XOR gate XR and the flip-flop DF. Unlike an ordinary address counter, the multiplexer does not have any time delay, so the operating speed of the address counter 160 of the present disclosure can be improved.

[0057] Figure 4 The invention is a detailed description of the use of the embodiment according to the present disclosure. Figure 2 The address counter 160 shown in FIG. 1 is a circuit diagram of a four-bit address counter implemented by the address counter 160 .

[0058] Reference Figure 4 , shows an address counter 160, including: a zeroth bit counter to a third bit counter CNT0 to CNT3, a third AND gate AG3, a fourth AND gate AG4, and a fifth AND gate AG5. The address counter 160 can perform a load operation and a count operation on four bits. Since the zeroth bit counter CNT0 to the third bit counter CNT3 have Figure 3 The address counter 160 shown in FIG. 1 has the same topology structure, so each of the zeroth bit counter CNT0 to the third bit counter CNT3 may correspond to Figure 3 Each of the zeroth to third bit counters CNT0 to CNT3 may include a first AND gate AG1, an inverter INV, a second AND gate AG2, an XOR gate XR, and a flip-flop DF.

[0059] Hereinafter, for convenience of description, it is illustrated that each of the start column address signal CA_ST[3:0] and the column address signal CA[3:0] is a signal having four bits.

[0060] The zeroth bit counter CNT0 may perform a load operation on the least significant bit CA_ST[0] of the start column address signal and perform a count operation on the least significant bit number CA[0] of the column address signal.

[0061] The zeroth bit counter CNT0 may generate its own first logic signal S and its own second logic signal RS based on the least significant bit CA_ST[0] of the start column address signal and the enable signal EN. When at least one of the first logic signal S and the second logic signal RS has a first logic level or logic 1, the zeroth bit counter CNT0 may output the least significant bit CA_ST[0] of the start column address signal as the least significant bit CA[0] of the column address signal.

[0062] Thereafter, when the first logic signal S and the second logic signal RS have the second logic level or logic zero, the zeroth bit counter CNT0 may generate the least significant bit of the counted column address signal by performing an XOR operation on the least significant bit CA[0] of the column address signal and the carry signal CR0. In some embodiments, the carry signal CR0 received by the zeroth bit counter CNT0 may always have the first logic level. In response to the rising edge of the clock signal CLK, the zeroth bit counter CNT0 may output the least significant bit of the counted column address signal as the least significant bit CA[0] of the column address signal.

[0063] The third AND gate AG3 may generate a carry signal CR1 output to the first bit counter CNT1 by performing an AND operation on the least significant bit CA[0] of the column address signal and the carry signal CR0.

[0064] The first bit counter CNT1 may perform a load operation on the first bit CA_ST[ 1 ] of the start column address signal and perform a count operation on the first bit CA[ 1 ] of the column address signal.

[0065] Like the zeroth bit counter CNT0, the first bit counter CNT1 can generate its own first logic signal S and its own second logic signal RS based on the first bit CA_ST[1] of the start column address signal and the enable signal EN. When at least one of the first logic signal S and the second logic signal RS of the first bit counter CNT1 has a first logic level, the first bit counter NT1 can output the first bit CA_ST[1] of the start column address signal as the first bit CA[1] of the column address signal.

[0066] Thereafter, when the first logic signal S and the second logic signal RS have the second logic level, the first bit counter CNT1 may generate the first bit of the counted column address signal by performing an XOR operation on the least significant bit CA[1] of the column address signal and the carry signal CR1. In response to a rising edge of the clock signal CLK, the first bit counter CNT1 may output the first bit of the counted column address signal as the first bit CA[1] of the column address signal.

[0067] The fourth AND gate AG4 may generate a carry signal CR2 output to the second bit counter CNT2 by performing an AND operation on the first bit CA[1] of the column address signal and the carry signal CR1.

[0068] The second bit counter CNT2 has the same topology as the zeroth bit counter CNT0 and the first bit counter CNT1. Therefore, the second bit counter CNT2 can perform a load operation on the second bit CA_ST[2] of the start column address signal and a count operation on the second bit CA[2] of the column address signal.

[0069] The second bit counter CNT2 may generate a first logic signal S and a second logic signal RS based on the second bit CA_ST[2] of the start column address signal and the enable signal EN. When at least one of the first logic signal S and the second logic signal RS has a first logic level, the second bit counter CNT2 may output the second bit CA_ST[2] of the start column address signal as the second bit CA[2] of the column address signal.

[0070] Thereafter, when the first logic signal S and the second logic signal RS have a second logic level, the second bit counter CNT2 may generate a second bit of the counted column address signal by performing an XOR operation on the second bit CA[2] of the column address signal and the carry signal CR2. In response to a rising edge of the clock signal CLK, the second bit counter CNT2 may output the second bit of the counted column address signal as the second bit CA[2] of the column address signal.

[0071] The fifth AND gate AG5 may generate a carry signal CR3 output to the third bit counter CNT3 by performing an AND operation on the second bit CA[2] of the column address signal and the carry signal CR2.

[0072] The third bit counter CNT3 also has the same topology as other bit counters, and can perform a load operation on the most significant bit CA_ST[3] of the start column address signal, and perform a counting operation on the most significant bit CA[3] of the column address signal.

[0073] The third bit counter CNT3 may generate a first logic signal and a second logic signal based on the most significant bit CA_ST[3] of the start column address signal and the enable signal EN. When at least one of the first logic signal and the second logic signal has a first logic level, the third bit counter CNT3 may output the most significant bit CA_ST[3] of the start column address signal as the most significant bit CA[3] of the column address signal.

[0074] Thereafter, when the first logic signal and the second logic signal have the second logic level, the third bit counter CNT3 may generate the most significant bit of the counted column address signal by performing an XOR operation on the most significant bit CA[3] of the column address signal and the carry signal CR3. In response to a rising edge of the clock signal CLK, the third bit counter CNT3 may output the most significant bit of the counted column address signal as the most significant bit CA[3] of the column address signal.

[0075] Figure 5 is a timing diagram illustrating a loading operation according to an embodiment of the present disclosure.

[0076] Reference Figure 4 and Figure 5, describes the loading operation of the address counter 160, in which the start column address signal CA_ST[3:0] is loaded as the column address signal CA[3:0]. Hereinafter, for convenience of description, it is shown that each of the start column address signal CA_ST[3:0] and the column address signal CA[3:0] is a signal having four bits.

[0077] Between time Ta and time Tb, the enable signal EN may have a logic low level. The start column address signal CA_ST[3:0] may have a binary data value of "1100". The column address signal CA[3:0] may have data in an unknown state. For example, the column address signal CA[3:0] may be any one of the data values ​​that can be represented by four bits.

[0078] At time Tb, the logic level of the enable signal EN may be changed from a logic low level to a logic high level. Based on the enable signal EN having a logic high level, the address counter 160 may load the start column address signal CA_ST[3:0] as the column address signal CA[3:0]. Therefore, from time Tb to time Tc, the column address signal CA[3:0] may have a binary data value of "1100".

[0079] In some embodiments, the output column address signal CA[3:0] may be fed back to the address counter 160. Thereafter, the address counter 160 may perform a counting operation on the received column address signal CA[3:0] according to the logic level of the enable signal EN.

[0080] Figure 6 is a timing diagram illustrating a counting operation according to an embodiment of the present disclosure.

[0081] Reference Figure 4 and Figure 6 , describes the counting operation of the address counter 160 on the column address signal CA[3:0]. Hereinafter, for the convenience of description, it is shown that each of the start column address signal CA_ST[3:0] and the column address signal CA[3:0] is a signal having four bits, and it is shown that the carry signal CR0 received by the zeroth bit counter CNT0 always has a logic high level.

[0082] Between time Td and time To, the enable signal EN may have a logic low level. Between time Td and time To, the address counter 160 may perform a counting operation.

[0083] At time Te, based on the rising edge of the clock signal CLK, the address counter 160 may output the count column address signal CA_CNT[3:0] as the column address signal CA[3:0]. Due to the time delay of the flip-flop, from time Tf onwards, the column address signal CA[3:0] may have the same binary data value (e.g., 0001) as the count column address signal CA_CNT[3:0].

[0084] Between time Tf and time Ti, the address counter 160 may output the count column address signal CA_CNT[3:0] having a binary data value (e.g., 0010) obtained by increasing the binary data value (e.g., 0001) of the column address signal CA_CNT[3:0] by '1'. However, due to the time delay of the XOR gate, between time Tg and time Tj, the count column address signal CA_CNT[3:0] may have binary data '0001'.

[0085] At time Th, based on the rising edge of the clock signal CLK, the address counter 160 may output the counted column address signal CA_CNT[3:0] as the column address signal CA[3:0]. Due to the time delay of the flip-flop, from time Ti onwards, the column address signal CA[3:0] may have the same binary data value (e.g., 0010) as the counted column address signal CA_CNT[3:0].

[0086] Between time Ti and time Tl, the address counter 160 may output a count column address signal CA_CNT[3:0] having a binary data value (e.g., 0011) obtained by increasing the binary data value (e.g., 0010) of the column address signal CA[3:0] by '1'. However, due to the time delay of the XOR gate, between time Tj and time Tm, the count column address signal CA_CNT[3:0] may have binary data '0011'.

[0087] At time Tk, based on the rising edge of the clock signal CLK, the address counter 160 may output the count column address signal CA_CNT[3:0] as the column address signal CA[3:0]. Due to the time delay of the flip-flop, from time T1, the column address signal CA[3:0] may have the same binary data value (e.g., 0011) as the count column address signal CA_CNT[3:0].

[0088] Between time T1 and time To, the address counter 160 may output a count column address signal CA_CNT[3:0] having a binary data value (e.g., 0100) obtained by increasing the binary data value (e.g., 0011) of the column address signal CA[3:0] by '1'. However, due to the time delay of the XOR gate, from time Tm onwards, the count column address signal CA_CNT[3:0] may have binary data '0100'.

[0089] At time Tn, based on the rising edge of the clock signal CLK, the address counter 160 may output the count column address signal CA_CNT[3:0] as the column address signal CA[3:0]. Due to the time delay of the trigger, from time To, the column address signal CA[3:0] may have the same binary data value (e.g., 0100) as the count column address signal CA_CNT[3:0].

[0090] As described above, when the address counter 160 performs a counting operation, the XOR gate XR and the flip-flop DF may have a time delay. Unlike a common address counter, the multiplexer does not have any time delay, so the operation speed of the address counter 160 of the present disclosure can be improved.

[0091] For convenience of description, the enable signal EN, the clock signal CLK, the count column address signal CA_CNT[3:0], and the column address signal CA[3:0] are disclosed between time Td and time To. However, the present disclosure is not limited thereto, and the address counter 160 may perform a counting operation on the column address signal CA[3:0].

[0092] Figure 7 is a flowchart illustrating steps of an operation method of an address counter according to an embodiment of the present disclosure.

[0093] Reference Figure 7 ,describe Figure 3 The operation method of the address counter 160 is shown in FIG. The address counter 160 may of course include a D-type flip-flop DF.

[0094] In step S110, the address counter 160 may generate a first logic signal and a second logic signal. In some embodiments, the address counter 160 may generate the first logic signal by performing a first logic operation on the start column address signal and the enable signal. The address counter 160 may generate an inverted signal obtained by inverting the logic level of the start column address signal. The address counter 160 may generate the second logic signal by performing a first logic operation on the inverted signal and the enable signal. The first logic operation may be an AND operation.

[0095] In step S120 , the address counter 160 may apply a first logic signal to the S terminal of the flip-flop DF.

[0096] In step S130, the address counter 160 may apply the second logic signal to the RS terminal of the flip-flop DF. It is illustrated that step 130 is performed after step S120. However, the present disclosure is not limited thereto, and step S120 may be performed after step S130, or steps S120 and S130 may be performed simultaneously.

[0097] In step S140, the address counter 160 may check whether at least one of the first logic signal and the second logic signal has a first logic level. When at least one of the first logic signal and the second logic signal has the first logic level, the address counter 160 may perform step S150. When at least one of the first logic signal and the second logic signal does not have the first logic level, the address counter 160 may perform step S160.

[0098] In step S150 , the address counter 160 may load a start column address signal.

[0099] In step S160, the address counter 160 may sequentially increase the data value of the start column address signal. The start column address signal may be a signal that the address counter 160 loads according to whether the enable signal has a first logic level in the previous operation of the address counter 160. In some embodiments, the address counter 160 may generate a third logic signal by performing a second logic operation on the column address signal and the carry signal. The third logic signal may be a signal having a data value obtained by increasing the data value of the column address signal by "1". The address counter 160 may feed back the third logic signal as a column address signal in response to a rising edge of the clock signal. The second logic operation may be an XOR operation.

[0100] According to the present disclosure, an address counter using asynchronous input can be provided. Using asynchronous input reduces the number of logic gates, thereby reducing time delay and increasing the operating speed of a memory device.

[0101] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but is determined not only by the appended claims but also by the equivalents of the claims.

[0102] In the above embodiment, Figure 7The steps of the method shown are not necessarily performed in the exact order shown, but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely intended to facilitate understanding of the examples of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

Claims

1. An address counter, comprising a trigger, wherein the trigger performs a loading operation of loading a start column address signal in response to a first logic signal received at a set input terminal of the trigger and a second logic signal received at a reset input terminal of the trigger, and performs a counting operation of sequentially increasing a data value of the start column address signal.

2. The address counter according to claim 1, wherein: The trigger: performing the loading operation when at least one of the first logic signal and the second logic signal has a first logic level; and The counting operation is performed when the first logic signal and the second logic signal have a second logic level.

3. The address counter according to claim 2, further comprising a first logic gate, the first logic gate generating the first logic signal by performing a first logic operation on the start column address signal and an enable signal, in, When the enable signal has the first logic level, at least one of the first logic signal and the second logic signal has the first logic level, and When the enable signal has the second logic level, both the first logic signal and the second logic signal have the second logic level.

4. The address counter according to claim 3, further comprising: An inverter, inverting the logic level of the start column address signal; as well as a second logic gate, generating the second logic signal by performing the first logic operation on the inverted start column address signal and the enable signal; Wherein, the first logical operation is an AND operation.

5. The address counter according to claim 2, further comprising a third logic gate, the third logic gate generating a count column address signal by performing a second logic operation on the column address signal and the carry signal, in, The flip-flop receives the counting column address signal through a D input terminal of the flip-flop.

6. The address counter according to claim 5, wherein: When at least one of the first logic signal and the second logic signal has the first logic level, the flip-flop outputs the first logic signal to the third logic gate.

7. The address counter according to claim 5, wherein: When both the first logic signal and the second logic signal have the second logic level, the flip-flop outputs the count column address signal to the third logic gate in response to a rising edge of a clock signal.

8. The address counter according to claim 5, wherein: The first logic level is a logic high level, the second logic level is a logic low level, and the second logic operation is an XOR operation.

9. The address counter according to claim 1, wherein: The loading operation is performed through an asynchronous input of the flip-flop, and the counting operation is performed through a synchronous input of the flip-flop.

10. A method of operating an address counter, the address counter comprising a trigger, the method comprising: generating a first logic signal and a second logic signal; applying the first logic signal to a set terminal of the flip-flop; applying the second logic signal to a reset terminal of the flip-flop; as well as When at least one of the first logic signal and the second logic signal has a first logic level, a start column address signal is loaded.

11. The method according to claim 10, further comprising: generating the first logic signal by performing a first logic operation on the start column address signal and an enable signal; generating an inversion signal by inverting a logic level of the start column address signal; as well as generating the second logic signal by performing the first logic operation on the inverted signal and the enable signal, Wherein, the first logical operation is an AND operation.

12. The method according to claim 10, further comprising: When the first logic signal and the second logic signal have a second logic level, a data value of the start column address signal is sequentially increased.

13. The method according to claim 12, wherein: Sequentially increasing the data value of the start column address signal further comprises: generating a third logic signal by performing a second logic operation on the column address signal and the carry signal; and In response to a rising edge of a clock signal, the third logic signal is fed back as the column address signal.

14. The method according to claim 13, wherein: The first logic level is a logic high level, the second logic level is a logic low level, and the second logic operation is an XOR operation.

Images