System and method to avoid overprogramming when infrequent smart verification acquisition for high performance 3D NAND

Abstract

A method of programming a memory device is disclosed herein. The method comprises the following steps: performing an intelligent verification operation to obtain an initial programming voltage; starting to execute a programming operation on the selected word line by using the initial programming voltage; performing a bit scan operation on the highest state being verified; and adjusting the initial program voltage for programming a subsequent word line based on a result of the bit scan operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 522,267, filed on June 21, 2023. The entire disclosures of the above-referenced applications are incorporated herein by reference. Background Art 1. Technical Field

[0003] The present disclosure relates generally to memory devices, and more particularly, to techniques for verifying the threshold voltage of a memory cell during a programming operation.

[0004] 2. Related technologies

[0005] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0006] The NAND memory device includes a chip having a plurality of memory blocks, each of which includes an array of memory cells arranged in a plurality of word lines. Programming the memory cells of the word lines to hold data typically occurs in a plurality of program loops, each of which includes applying a programming pulse to a control gate of the word line, and optionally includes a verification operation for sensing the threshold voltage of the memory cell being programmed. In many programming techniques, the programming pulse has an initial programming voltage in the first program loop, and then the voltage of the programming pulse is incrementally increased between program loops until programming is completed. The optimal value for the initial programming voltage varies across a plurality of memory blocks in the chip, and may also vary between word lines of a single memory block. If the initial programming voltage is set too high, over-programming of some memory cells may occur, but if the initial programming voltage is set too low, programming performance may be impaired.

[0007] One way to improve programming performance instead of just setting the initial programming voltage at a high level so that over-programming may occur is to perform a smart verification operation at the beginning of a programming operation in a memory block. The smart verification operation includes multiple smart verification programming loops, each of which includes a programming pulse and at least one verification operation. During the verification operation of each smart verification programming loop, the number of memory cells having a threshold voltage greater than a predetermined verification voltage is determined and compared to a target. If the number of memory cells is higher than the target, the verification operation "fails" and the voltage of the last programming pulse is stored in the chip's NAND register and, after adding an optionally configurable offset value, is used as the initial programming voltage for subsequent programming operations in the memory block. Summary of the invention

[0008] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0009] An object of the present disclosure is to provide a memory device and a method of operating the memory device that addresses and overcomes the disadvantages described herein.

[0010] Therefore, one aspect of the present disclosure is to provide a method for programming a memory device. The method includes the following steps: performing a smart verification operation to obtain an initial programming voltage; starting a programming operation on a selected word line with the initial programming voltage; performing a bit scan operation on the highest state being verified; and adjusting the initial programming voltage for programming subsequent word lines based on the result of the bit scan operation.

[0011] Therefore, one aspect of the present disclosure is to provide a memory device. The memory device includes: at least one memory block, the at least one memory block including a plurality of memory cells arranged in a plurality of word lines; a control circuit, the control circuit being configured to program the memory cells of the at least one memory block in a plurality of program cycles, the control circuit being configured to: perform a smart verification operation to obtain an initial programming voltage; start a programming operation on a selected word line with the initial programming voltage; perform a bit scan operation on the highest state being verified; and adjust the initial programming voltage for programming subsequent word lines based on the result of the bit scan operation.

[0012] Therefore, one aspect of the present disclosure is to provide a device. The device includes: at least one storage block, the at least one storage block including a plurality of memory cells arranged in a plurality of word lines; and a programming component, the programming component is used to program user data into the plurality of memory cells, and is configured to program the memory cells of the at least one storage block in a plurality of program cycles. The programming component is configured to: perform a smart verification operation to obtain an initial programming voltage; start a programming operation on a selected word line with the initial programming voltage; perform a bit scan operation on the highest state being verified; and adjust the initial programming voltage for programming subsequent word lines based on the result of the bit scan operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A more detailed description is set forth below with reference to the exemplary embodiments depicted in the accompanying drawings. It is understood that these drawings depict only exemplary embodiments of the present disclosure and, therefore, should not be considered to limit the scope thereof. The present disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0014] Figure 1A is a block diagram of an exemplary memory device;

[0015] Figure 1B is a block diagram of an exemplary control circuit;

[0016] Figure 2 Depicted Figure 1A a block of memory cells in an exemplary two-dimensional configuration of a memory array;

[0017] Figure 3A and Figure 3B depicts a cross-sectional view of an exemplary floating gate memory cell in a NAND string;

[0018] Figure 4A and Figure 4B depicts a cross-sectional view of an exemplary charge trapping memory cell in a NAND string;

[0019] Figure 5 depicts an exemplary block diagram of the sensing block SB1 of FIG. 1 ;

[0020] Fig. 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 ;

[0021] Figure 6B Depicted Fig. 6A An exemplary cross-sectional view of a portion of one of the blocks;

[0022] Figure 6C Depicted Figure 6B A graph of memory hole diameters in a stack of;

[0023] Fig.6D Depicted Figure 6B A close up view of region 622 of the stack;

[0024] Fig. 7A Depicted Figure 6B A top view of an exemplary word line layer WLL0 of the stack;

[0025] Figure 7B Depicted Figure 6B A top view of an exemplary top dielectric layer DL116 of the stack;

[0026] Figure 8 depicts a threshold voltage distribution for a page of memory cells programmed to one bit per memory cell (SLC);

[0027] Fig. 9 depicts a threshold voltage distribution for a page of memory cells programmed to three bits per memory cell (TLC);

[0028] Fig.10 depicts a threshold voltage distribution for a page of memory cells programmed to four bits per memory cell (QLC);

[0029] Fig.11 a voltage waveform depicting the voltage applied to the control gate of a selected word line during a programming operation;

[0030] Fig.12 depicts voltage waveforms of voltages applied to a control gate of a selected word line during and immediately after a smart verify operation;

[0031] Fig.13 depicting threshold voltage distributions of a plurality of memory cells before and after a plurality of program cycles of a smart verify operation;

[0032] Fig.14 Depicts the steps of a regular program flow with smart validation;

[0033] Fig.15 Depicts the steps of a program flow with smart verification over-programming protection according to an exemplary embodiment of the present disclosure;

[0034] Fig.16 Depicts the steps of a program flow with smart verification over-programming protection according to another exemplary embodiment of the present disclosure;

[0035] Fig.17 Depicted are steps of a program flow with smart verification over-programming protection according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] When programming starts with a programming voltage (e.g., VPGM) that is too high, the memory cells start out being strongly programmed, and since some memory cells do not need to be exposed to the high programming voltage, these memory cells often end up being overprogrammed. In contrast, if the starting VPGM is too low, programming performance is reduced. If an unnecessary low programming pulse is applied initially, programming requires extra time.

[0037] To solve this problem, a smart verification algorithm is performed. The smart verification algorithm involves first acquiring the VPGM to start programming. Once the information is acquired, it is applied to other strings or other word lines during programming. Once the information is acquired, as long as the physical properties of the word line or string do not change greatly, the information should remain accurate.

[0038] However, there are natural process variations across word lines, and if the acquired information is used for too long at a certain point, the information is no longer valid for the word line. For example, because the width of the memory hole is different, when the word line where the information is acquired is far away, the information becomes obsolete for the current word line being programmed. When the information is reacquired, the information is refreshed based on the current physical properties of the word line. Therefore, accurate information is obtained each time the information is acquired. The Vth distribution is tightened, which improves reliability and reduces error rates. However, if the information is acquired too frequently, there is a performance loss. The embodiments described herein attempt to strike a balance between having accurate information and acquisition frequency. If the information is acquired more frequently, the information will be more accurate, but it will be at a cost in terms of performance.

[0039] To explore the foregoing in more detail, we will now describe Figure 1A . Figure 1A 1 is a block diagram of an exemplary memory device 100 configured to operate according to the programming techniques of the present disclosure. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ..., SBp (sense circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between a host 140 and the controller 122 via a data bus 120, and between the controller and one or more memory dies 108 via a line 118.

[0040] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include an array of one or more memory cells, the array of one or more memory cells comprising a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, without intervening substrates. The memory structure 126 may include any type of non-volatile memory integrally formed in an array of memory cells having one or more physical levels of active regions disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0041] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations.

[0042] The storage area 113 may, for example, be provided for programming parameters. The programming parameters may include a programming voltage, a programming voltage bias, a location parameter indicating the location of a memory cell, a contact wire connector thickness parameter, a verification voltage, etc. The location parameter may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. The contact wire connector thickness parameter may indicate the thickness of the contact wire connector, the substrate or material constituting the contact wire connector, etc.

[0043] The on-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module may include drivers for the word lines, SGS transistors, and SGD transistors and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0044] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit that is configured to perform the actions described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoder 114 / 132, the power control module 116, the sense blocks SBb, SB2, ... SBp, the read / write circuit 128, the controller 122, etc., or a combination thereof.

[0045] The control circuit may include a programming circuit configured to perform programming and verification operations on a group of memory cells, wherein the group of memory cells includes memory cells assigned to represent one data state of multiple data states, and memory cells assigned to represent another data state of multiple data states; the programming and verification operations include multiple programming and verification iterations; and in each programming and verification iteration, the programming circuit performs programming for a selected word line, after which the programming circuit applies a verification signal to the selected word line. The control circuit may also include a counting circuit configured to obtain a count of memory cells that pass a verification test for one data state. The control circuit may also include a determination circuit configured to determine whether the programming operation is completed based on an amount by which the count exceeds a threshold.

[0046] For example, Figure 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151 , a counting circuit 152 , and a determination circuit 153 .

[0047] The off-chip controller 122 may include a processor 122c, a storage device (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, there may be uncorrectable errors. The technology provided herein reduces the possibility of uncorrectable errors.

[0048] The storage devices 122a, 122b include code, such as an instruction set, and the processor 122c is operable to execute the instruction set to provide the functions described herein. Alternatively or in addition, the processor 122c can access code from the storage device 126a of the memory structure 126, such as a reserved area of ​​a memory cell in one or more word lines. For example, the controller 122 can use the code to access the memory structure 126, such as for programming operations, read operations, and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 and enables the controller 122 to access the memory structure 126 during the boot or startup process. The controller 122 can use the code to control one or more memory structures 126. At power-on, the processor 122c takes out the boot code from the ROM 122a or the storage device 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM 122b, it is executed by the processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0049] In general, the control code may include instructions to perform the functions described herein, including the steps of the flow charts discussed further below, and provide voltage waveforms, including those discussed further below.

[0050] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable storage devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0051] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0052] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0053] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0054] Multiple memory elements may be configured so that they are connected in series or so that each element may be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0055] A NAND memory array can be configured so that the array consists of multiple memory strings, where the string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0056] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of the memory elements are formed, or it may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0057] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0058] The three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0059] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), each column having a plurality of memory cells. The columns may be arranged in a two-dimensional configuration, such as in an xy plane, resulting in a three-dimensional arrangement of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0060] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0061] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between the memory device levels.

[0062] The two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0063] Figure 2 Blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array 126 may include many such memory blocks 200, 210. Each exemplary block 200, 210 includes a plurality of NAND strings and corresponding bit lines, such as BL0, BL1, ... shared between blocks. Each NAND string is connected to a drain side select gate (SGD) at one end, and the control gate of the drain select gate is connected via a common SGD line. The NAND string is connected to a source side select gate (SGS) at its other end, which is in turn connected to a common source line 220. One hundred and twelve word lines (e.g., WL0-WL111) extend between SGS and SGD. In some embodiments, a memory block may include more or less than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines that do not contain user data may also be used in a memory array adjacent to a select gate transistor. Such dummy word lines can shield edge data word lines from certain edge effects.

[0064] One type of nonvolatile memory that may be provided in a memory array is a floating gate memory, such as Figure 3A and Figure 3B However, other types of non-volatile memory may also be used. As discussed in further detail below, Figure 4A and Figure 4BIn another example shown, a charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0065] In another approach, an NROM cell is used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0066] Figure 3A A cross-sectional view of an exemplary floating gate memory cell 300, 310, 320 in a NAND string is shown. In this figure, the bit line or NAND string direction is into the page, and the word line direction is from left to right. For example, word line 324 extends across the NAND string, which includes corresponding channel regions 306, 316 and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305 and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315 and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325 and channel region 326. Each of memory cells 300, 310 and 320 is in a different corresponding NAND string. An inter-polysilicon dielectric (IPD) layer 328 is also shown. The control gates 302, 312, 322 are part of a word line. Figure 3B A cross-sectional view along the contact line connector 329 is provided in FIG.

[0067] The control gate 302, 312, 322 is wrapped around the floating gate 304, 314, 321, thereby increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacitance, which results in a higher coupling ratio, which makes programming and erasing easier. However, when the NAND memory device is scaled down, the spacing between adjacent cells 300, 310, 320 becomes smaller, so there is almost no space for the control gate 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 302, 312, 322.

[0068] As an alternative, Figure 4A and Figure 4B As shown, a flat or planar memory cell 400, 410, 420 has been developed in which the control gate 402, 412, 422 is flat or planar; that is, the control gate is not wrapped around the floating gate, and the only contact of the control gate with the charge storage layer 428 is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0069] Figure 4A A cross-sectional view of an exemplary charge trapping memory cell 400, 410, 420 in a NAND string is shown. The view is in the word line direction of the memory cell 400, 410, 420 including a planar control gate and a charge trapping region as a two-dimensional example of the memory cell 400, 410, 420 in the memory cell array 126 of FIG. 1 . Charge trapping memory can be used in NOR and NAND flash memory devices. Compared to floating gate MOSFET technology that uses conductors such as doped polysilicon to store electrons, this technology uses insulators such as SiN films to store electrons. For example, a word line 424 extends across a NAND string that includes corresponding channel regions 406, 416, 426. Portions of the word line provide control gates 402, 412, 422. An IPD layer 428, a charge trapping layer 404, 414, 421, a polysilicon layer 405, 415, 425, and a tunnel layer 409, 407, 408 are below the word line. Each charge trapping layer 404, 414, 421 extends continuously in a corresponding NAND string. The planar configuration of the control gate can be made thinner than the floating gate. In addition, the memory cells can be placed closer together.

[0070] Figure 4B Shows Figure 4A435 and SGD transistor 436. The passage in IPD layer 428 in SGS transistor 431 and SGD transistor 436 allows control gate layer 402 and floating gate layer to communicate. For example, control gate layer 402 and floating gate layer can be polysilicon, and tunnel oxide layer can be silicon oxide. IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in NONON configuration.

[0071] The NAND string may be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be directly applied to the channel region of the substrate.

[0072] Figure 5An exemplary block diagram of the sense block SB1 of FIG. 1 is shown. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sense blocks can be used to sense different bit line subsets. This allows the processing load associated with the sense circuit to be divided and processed by the corresponding processor in each sense block. For example, the sense circuit controller 560 in SB1 can communicate with the group of sense circuits and latches. The sense circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, the voltage may be independently provided to each sense circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage may be provided to each sense circuit simultaneously. The sense circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code that can be executed by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with the sense circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing a voltage for setting a precharge level in a sense node of the sense circuits 550a, 551a, 552a, 553a. Further exemplary details of the sense circuit controller 560 and the sense circuits 550a, 551a, 552a, 553a are provided below.

[0073] In some embodiments, the memory cell may include a tag register including a set of latches storing a tag bit. In some embodiments, the number of tag registers may correspond to the number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying the memory cell. In some embodiments, the output of the tag bit may modify the associated logic of the device, such as an address decoding circuit, so that a specified cell block is selected. Body operations (e.g., erase operations, etc.) may be performed using a tag set in a tag register, or a combination of a tag register and an address register, as in implicit addressing, or alternatively performed by direct addressing using only an address register.

[0074] Fig. 6A1 is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. On the substrate are exemplary blocks BLK0, BLK1, BLK2, BLK3 of memory cells (storage elements), and a peripheral region 604 having circuits for use by the blocks BLK0, BLK1, BLK2, BLK3. For example, the circuits may include a voltage driver 605 that may be connected to the control gate layers of the blocks BLK0, BLK1, BLK2, BLK3. In one approach, the control gate layers at a common height in the blocks BLK0, BLK1, BLK2, BLK3 are driven together. The substrate 601 may also carry the circuits below the blocks BLK0, BLK1, BLK2, BLK3, together with one or more lower metal layers that are patterned in conductive paths to carry the signals of the circuits. The blocks BLK0, BLK1, BLK2, BLK3 are formed in the middle region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in a conductive path to carry the signals of the circuit. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, wherein alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has an opposing layered side from which vertical contacts extend upward to the upper metal layer to form a connection with the conductive path. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as examples, two or more blocks extending in the x-direction and / or the y-direction may be used.

[0075] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device.

[0076] Figure 6B Shows Fig. 6A1 is an exemplary cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3. The block includes a stack 610 of alternating conductive layers and dielectric layers. In this example, in addition to data word line layers (word lines) WL0-WL111, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0-DL116. In addition, a region of the stack 610 including a NAND string NS1 and a NAND string NS2 is shown. Each NAND string includes a memory hole 618, 619 filled with material that forms a memory cell adjacent to the word line. Region 622 of the stack 610 is Fig.6D , and are discussed in further detail below.

[0077] The stack 610 includes a substrate 611, an insulating film 612 located on the substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled slits) 617, 620 can be provided periodically across the stack 610 as interconnectors extending through the stack 610, such as to connect the source line to a specific contact line above the stack 610. The contact line connectors 617, 620 can be used during the formation of the word line and subsequently filled with metal. A portion of the bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0078] Figure 6C Shows Figure 6B The vertical axis is plotted against the diameter of the memory holes in the stack. Figure 6B 's stack alignment, and the width (wMH), eg, diameter, of memory hole 618 and memory hole 619 are shown. Fig. 6A The word line layers WL0-WL111 of are repeated as examples and are at corresponding heights z0-z111 in the stack. In such memory devices, the memory holes etched through the stack have a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory hole may have a circular cross-section. Due to the etching process, the width of the memory hole may vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, so that the diameter of the memory hole widens slightly before tapering from its top to its bottom.

[0079] Due to the non-uniformity of the memory hole width, the programming speed including the programming slope and the erase speed of the memory cell may vary based on the position of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For memory holes of smaller diameter, the electric field across the tunnel oxide is relatively strong, so that the programming and erase speeds are relatively high. One method is to define a group of adjacent word lines with a similar diameter to the memory hole (e.g., within a defined diameter range) and apply an optimized verification scheme for each word line in the group. Different groups may have different optimized verification schemes.

[0080] Fig.6D Shows Figure 6B 622 of the stack 610 of FIG. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a column formed by the material within the memory hole 630) may include a charge trapping layer or film 663 (such as SiN or other nitride), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / block high-k material 660, a metal barrier layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory hole 630. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form a pillar-shaped active area (AA) of the NAND string.

[0081] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0082] Each of the memory holes 630 may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer. A core region of each of the memory holes 630 is filled with a body material, and the plurality of annular layers are located between the core region and the word line in each of the memory holes 630.

[0083] The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate. In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0084] Fig. 7A Shows Figure 6B 610. As mentioned, a three-dimensional memory device may include a stack of alternating conductive layers and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layers for SG transistors are SG layers, and the layers for memory cells are word line layers. In addition, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack and bit lines are connected to the NAND strings above the stack.

[0085] The block BLK in the three-dimensional memory device can be divided into sub-blocks, each of which includes a NAND string group with a common SGD control line. For example, refer to the SGD line / control gate SGD0, SGD line / control gate SGD1, SGD line / control gate SGD2 and SGD line / control gate SGD3 in sub-block SBa, sub-block SBb, sub-block SBc and sub-block SBd, respectively. In addition, the word line layer in the block can be divided into regions. Each region is in a corresponding sub-block and can extend between contact line connectors (e.g., slits), which are periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The processing may include replacing the sacrificial material of the word line layer with metal. In general, the distance between the contact line connectors should be relatively small to take into account the limitation of the distance that the etchant can travel laterally to remove the sacrificial material, and the metal can travel to fill the gap created by removing the sacrificial material. For example, the distance between the contact line connectors can allow several rows of memory holes to exist between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider the limit on the number of bit lines that can be extended across the area when each bit line is connected to a different memory cell.After processing the word line layer, the contact line connectors can optionally be filled with metal to provide interconnection through the stack.

[0086] In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WL0a, WL0b, WL0c, and WL0d, which are each connected by contact lines 713. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 713 is in turn connected to a voltage driver for the word line layer. Region WL0a has exemplary memory holes 710, 711 along contact line 712. Region WL0b has exemplary memory holes 714, 715. Region WL0c has exemplary memory holes 716, 717. Region WL0d has exemplary memory holes 718, 719. Memory holes are also Figure 7B Each memory hole can be part of a corresponding NAND string. For example, memory hole 710, memory hole 714, memory hole 716, and memory hole 718 can be part of NAND string NS0_SBa, NAND string NS1_SBb, NAND string NS2_SBc, NAND string NS3_SBd, and NAND string NS4_SBe, respectively.

[0087] Each circle represents a cross section of a memory hole at a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cells 720, 721 are in WL0a, memory cells 724, 725 are in WL0b, memory cells 726, 727 are in WL0c, and memory cells 728, 729 are in WL0d. These memory cells are at a common height in the stack.

[0088] Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a-WL0d. The contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a wire above the stack, where the wire is connected to a voltage driver in a peripheral region of the memory device.

[0089] Figure 7B Shows Figure 6B1. A top view of an exemplary top dielectric layer DL116 of a stack of . The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in one region of the word line layer to be programmed simultaneously, where each memory cell is in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or prohibit programming during each programming voltage.

[0090] Region DL116a has exemplary memory holes 710, 711 along contact line 712 that coincides with bit line BL0. Many bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a group of memory holes that includes memory holes 711, 715, 717, 719. Another exemplary bit line BL1 connects to a group of memory holes that includes memory holes 710, 714, 716, 718. Also shown are bits from Fig. 7A The contact line connectors (eg, slots, such as metal filled slots) 701, 702, 703, 704 of the stack are shown as they extend vertically through the stack. The bit lines may be numbered in the order BL0-BL23 across the DL116 layer in the x-direction.

[0091] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, BL20 are connected to memory cells in the first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18, BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19, BL23 are connected to memory cells in the first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17, BL21 are connected to memory cells in the adjacent row of memory cells adjacent to the first row at the left hand edge.

[0092] The memory cells of a memory block may be programmed to store one or more bits of data in a plurality of data states, each of which is associated with a corresponding threshold voltage Vt. For example, Figure 8 Depicted are threshold voltage Vt distributions for a group of memory cells programmed according to a one-bit per memory cell (SLC) storage scheme. In the SLC storage scheme, there are a total of two data states, including an erased state (Er) and a single programmed data state (S1). Fig. 9The threshold voltage Vt distribution for a three-bit per cell (TLC) storage scheme is shown, which includes a total of eight data states, namely an erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1-S7) is associated with a verification voltage (Vv1-Vv7) that is employed during the verification portion of a programming operation. Fig.10 Depicted is a threshold voltage Vt distribution for a four bit per cell (QLC) storage scheme including a total of sixteen data states, namely an erased state (Er) and fifteen programmed data states (S1-S15). Other storage schemes are also available, such as two bits per cell (MLC) with four data states or five bits per cell (PLC) with thirty-two data states.

[0093] In some memory dies, memory blocks can be configured to operate in multiple storage scheme modes (e.g., SLC mode and TLC mode, or SLC mode and QLC mode). The memory device can then be configured to initially write data to the memory block operating in SLC mode, which provides high performance. Then, in background operations when performance is not important, the memory device can program the data into a multi-bit per memory cell format for long-term storage.

[0094] Programming to multiple bits per memory cell typically involves multiple program cycles. Fig.11 Depicted is a waveform 1100 of a voltage applied to a selected word line during an exemplary memory cell programming operation for programming the memory cells of the selected word line to a larger number of bits per memory cell (e.g., TLC or QLC). As depicted, each program loop includes a programming pulse VPGM and one or more verify pulses, depending on which data states are being programmed in a particular program loop. For simplicity, a square wave is depicted for each pulse; however, other shapes are possible, such as a multi-level shape or a ramp shape.

[0095] Incremental step pulse programming (ISPP) is used in this example, which means that the VPGM pulse amplitude is raised or increased in each consecutive program cycle. In other words, the pulse train includes VPGM pulses that increase in amplitude stepwise with each program cycle using a fixed step size (dVPGM). A new pulse train begins at an initial VPGM pulse level VPGMU and ends at a final VPGM pulse level that does not exceed the maximum allowed level. The pulse train 1100 includes a series of VPGM pulses 1101-1115 applied to a selected word line including a group of non-volatile memory cells. As an example, one or more verification voltage pulses 1116-1129 are provided after each VPGM pulse based on the target memory state being verified in the program cycle. The verification voltage corresponds to voltages Vv1-VV7 (e.g., Fig. 9 ). While applying the verification voltage, the sensing operation can determine whether a particular memory cell in the selected word line has a threshold voltage Vt that is higher than the verification voltage associated with the expected data state of the particular memory cell by sensing the current passing through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, so that the threshold voltage Vt of the memory cell is less than the verification voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, so that the threshold voltage Vt of the memory cell is higher than the verification voltage. If the memory cell passes the verification, the programming of the memory cell is completed, and further programming of the memory cell is prohibited for all remaining program cycles by applying a prohibition voltage to the bit line coupled to the memory cell. Programming continues until all memory cells pass the verification for their intended data states (in which case, programming passes), or until a predetermined maximum number of program cycles is exceeded (in which case, programming fails). The memory cells of a word line can be divided into a series of string groups that can be programmed independently of each other or simply divided into strings, and programming can start from one string to another across word lines before proceeding to the next word line in the storage block.

[0096] In some programming operations, a "smart verify operation" is performed during the first pair of program cycles of the programming operation to obtain the optimal starting programming voltage for the word lines in the memory block. Fig.12 and Fig.13 During a smart verify operation, only a portion of a selected word line (e.g., one string) is selected for programming. In a first program loop, a relatively low VPGMU_SV programming pulse is applied to the selected portion of the word line, and then a verify operation is performed to determine whether the number of memory cells that have passed the verify level Vverl is greater than the target number of memory cells. Fig.13 In the example of , after the first program loop, no memory cell has a threshold voltage greater than the verify level Vver1. If the number of memory cells that pass the verify operation is not greater than the target, the programming voltage is raised (VPGM=VPGM+dVPGM) and another program loop begins. This continues for as many program loops as it takes for the target number of memory cells that pass the verify to exceed the verify level Vver1. Fig.12 and Fig.13In the example of , this takes three program cycles. Once a verify operation fails, VPGM or VPGM plus a configurable offset is set to SV_VPGM and stored in the chip's NAND registers. If other strings and word lines in the same memory block are subsequently programmed, the initial programming voltage VPGMU in the first program cycle of those subsequent programming operations is set to SV_VPGM, thereby improving performance by skipping unnecessary program cycles and not overprogramming memory cells.

[0097] exist Fig.12 and Fig.13 In the example shown in Figure 1, the smart verification operation fails in the third smart verification program loop ( Fig.13 The shaded area of ​​the curve in identifies the memory cells that have passed verification). Therefore, the SV_VPGM for subsequent word lines and strings is set to VPGMU plus twice dVPGM, that is, SV_VPGM=VPGMU+2*dVPGM. In other memory blocks in the same chip or in different chips, the number of program cycles that pass smart verification can be less than, equal to, or greater than three, that is, the optimal SV_VPGM is unique for each memory block, and can even be unique for each word line within the same memory block.

[0098] In addition to the verification operations described above, a bit scan operation may also be performed to determine when to first begin programming a group of memory cells to be above the verification level, or when to subsequently complete programming of a group of memory cells later. As used herein, "bit scan" is an operation that focuses on the former and counts the number of memory cells whose programming characteristics have not yet shifted to a specific verification voltage level above a specific memory state. For NAND memory cells, a bit scan is an operation that counts the number of memory cells whose threshold voltage has shifted to a specific verification voltage level above a specific memory state. For example, a state N bit scan is a count of the number of state N memory cells whose threshold voltage has shifted to a verification voltage level above state N. Similarly, a state (N+I) bit scan is a count of the number of state (N+1) memory cells whose threshold voltage has shifted to a verification voltage level above state (N+I), and so on. For simplicity, the following discussion will relate to a bit scan operation of a NAND memory cell. One of ordinary skill in the art will appreciate that a bit scan operation may also be used for other non-volatile memory technologies. The bit scan count may trigger a verify operation to jump to the next programming level in the same programming cycle, however, depending on the timing of certain functions consistent with the bit scan, current consumption may increase during program-verify.

[0099] Fig.14The steps of a conventional program flow 1400 with smart verify are depicted. At step 1402, programming of smart verify acquisition word lines and strings is performed to find the most appropriate VPGM value for each word line or a group of word lines. At step 1404, a smart verify low (SVL) is performed, which SVL includes a verify low reference voltage. At step 1406, a smart verify bit scan operation is performed. If SVL passes, then at step 1412, VPGM is increased by ΔVPGM. If SVL fails, then at step 1410, a smart verify high SVH is performed, which SVH includes a verify high reference voltage (e.g., SVH=SVL+|DVCG_SMART|). The verify low reference voltage is lower in magnitude than the verify high reference voltage.

[0100] At step 1414, a smart verify bit scan operation is performed. If SVH passes, then at step 1422, the acquired SV VPGM equal to the VPGM at the current loop is stored. If SVH fails, then at step 1416, the acquired VPGM equal to the VPGM in the current loop minus 1 / 2DVPGM is stored. At step 1418, the program loop is reset, and at 1420, programming of the SV acquisition word line and string is completed. At step 1424, programming of the SV application WL / string is initiated, for example, with the acquired VPGM+SV_VPGM_MLC. At step 1426, the state list to be verified is initialized with the A state only. At step 1428, a programming pulse is applied, and at step 1430, the state from the program-verify list is verified. At step 1432, it is determined whether programming is complete. If "yes", at step 1440, the next word line / string is programmed. If "no", then at step 1434, a smart program count verify (sPCV) bit scan is used for the highest state N being verified. If the bit scan passes, then at step 1436, the loop is incremented. If the bit scan fails, then at step 1438, state N+1 is added to the list of states to be verified in the next loop.

[0101] The embodiments described herein utilize sPCV to avoid over-programming during infrequent smart verification acquisition. sPCV involves using an sPCV bit scan on the highest state being verified to check when verification of the next state should begin. For example, assuming that once the bit scan of state N fails, state N+1 should begin verification in the next cycle. The number of cycles to wait can be adjusted by a parameter.

[0102] For example, if the first pulse of the 'A' state PsCV bit scan fails on the SV application word line, then the word line is more likely to suffer from over programming later. Therefore, according to the embodiments described herein, SV_VPGM_MLC will need to be reduced for future word lines and strings. Specifically, SV_VPGM_MLC can be reduced for the next string or only for the future physical word line, because the memory hole diameter narrowing trend usually occurs on the next word line.

[0103] To help illustrate the foregoing, Fig.15 The steps of the smart verification over-programming protection process 1500 are depicted. Fig.14 In the example, flow 1500 includes executing the SV for obtaining the acquired VPGM and scanning the sPCV bit for the highest state being verified. Fig.15 , flow 1500 also includes determining whether the highest state being verified is the 'A' data state and whether the current program loop is the first of multiple program loops of a programming operation at step 1502. If "yes", then at step 1504, SV_VPGM_MLC is reduced for future word lines. Alternatively, if "no", then at step 1438, state N+1 is added to the list of states to be verified in the next loop.

[0104] In other embodiments, it may be determined whether an sPCV bit scan "failure" is a strong fail (e.g., with many high Vth bits) or a weak fail (e.g., with only a few high Vt bits). A strong fail may be an indication that over-programming is about to occur on the next word line and SV_VPGM_MLC should be reduced. Additionally, to maintain the additional tPROG benefit, SV_VPGM_MLC may not be reduced for weak fails. Instead of increasing the SV acquisition frequency, the embodiments described herein may improve over-programming issues without too much tPROG penalty to improve reliability.

[0105] To help illustrate the foregoing, Fig.16 The steps of the smart verification over-programming protection process 1600 are depicted. Fig.14 In step 1600, the process 1600 includes executing SV to obtain the acquired VPGM, and at step 1602, performing a sPCV bit scan for the highest state being verified. Fig.16 , if the bit scan result is a strong fail, then at step 1604 it is determined whether the highest state being verified is the 'A' data state and whether the current program loop is the first of multiple program loops for a programming operation. If "yes", then at step 1606, SV_VPGM_MLC is decreased for future word lines. Alternatively, if "no", then at step 1438, state N+1 is added to the list of states to be verified in the next loop. Fig.16In step 1606, if the bit scan result is a weak fail, state N+1 is added to the state list to be verified in the next cycle.

[0106] To explore the following in more detail, we will now describe Fig.17 . Fig.17 A method 1700 is depicted depicting steps of a smart verification over-programming protection flow according to embodiments described herein. In some embodiments, the method 1700 may be implemented by a controller, a control circuit, a processor, etc., as described in other sections of this document. Fig.17 As shown, method 1700 starts at step 1702. In step 1702, a smart verification operation is performed to obtain an initial programming voltage. Figure 1A and Figure 1B , the control circuit 110 can perform a smart verification operation to obtain an initial programming voltage.

[0107] exist Fig.17 In step 1704, the programming of the word line where the smart verification operation is performed is completed. Figure 1A and Figure 1B , the control circuit 110 can complete the programming of the word line where the smart verification operation is performed.

[0108] exist Fig.17 In step 1706, a programming operation is performed on the selected word line with an initial programming voltage. Figure 1A and Figure 1B , the control circuit 110 may start performing a programming operation on the selected word line at an initial programming voltage.

[0109] exist Fig.17 In step 1708, a bit scan operation is performed on the highest state being verified. Figure 1A and Figure 1B , the control circuit 110 may perform a bit scan operation on the highest state being verified.

[0110] exist Fig.17 In step 1710, based on the result of the bit scan operation, the initial programming voltage for programming the subsequent word line is adjusted. Figure 1A and Figure 1B , the control circuit 110 may adjust an initial programming voltage for programming a subsequent word line based on the result of the bit scanning operation.

[0111] Various terms are used herein to refer to specific system components. Different companies may refer to the same or similar components by different names, and this document is not intended to distinguish components that are different in name but not in function. Insofar as the various functional units described in the following disclosure are referred to as "modules", this characterization is intended to not overly limit the scope of possible implementation mechanisms. For example, a "module" may be implemented as a hardware circuit including a custom very large scale integration (VLSI) circuit or gate array, or a ready-made semiconductor including a logic chip, a transistor or other discrete components. In another example, a module may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic unit, a programmable logic device, etc. In addition, a module may also be implemented at least in part by software executed by various types of processors. For example, a module may include an executable code segment that constitutes one or more physical or logical blocks of computer instructions that are converted into an object, process or function. In addition, the executable portions of such modules are not required to be physically located together, but may include different instructions that are stored in different locations and, when executed together, constitute the identified module and achieve the purpose of the module. Executable code may include only a single instruction or a collection of multiple instructions, and may be distributed across different code segments, or between different programs, or across several memory devices, etc. In the specific implementation of software or a portion of a software module, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor-based systems, devices or equipment, or any suitable combination thereof. In general, for the purposes of this disclosure, a computer-readable and / or executable storage medium may include any tangible and / or non-transitory medium capable of containing and / or storing a program for use by or in conjunction with an instruction execution system, device, processor or device.

[0112] Similarly, for the purposes of this disclosure, the term "component" may be composed of any tangible, physical, and non-transient device. For example, a component may be in the form of a hardware logic circuit composed of a custom VLSI circuit, a gate array, or other integrated circuit, or composed of an off-the-shelf semiconductor including a logic chip, a transistor, or other discrete component, or any other suitable mechanical and / or electronic device. In addition, a component may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic component, a programmable logic device, or the like. In addition, a component may be composed of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are in an electrically connected configuration with one or more other components via electrical conductors such as a printed circuit board (PCB). Therefore, a module as defined above may be embodied or implemented as a component in certain embodiments, and in some cases, the terms module and component may be used interchangeably.

[0113] Where the term "circuit" is used herein, it includes one or more electrical and / or electronic components that constitute one or more conductive paths that allow current to flow. The circuit may be in the form of a closed loop configuration or an open loop configuration. In a closed loop configuration, the circuit components may provide a return path for the current. In contrast, in an open loop configuration, the circuit components therein may be considered to form a circuit, although the return path of the current is not included. For example, whether or not the integrated circuit is grounded (as a return path for the current), the integrated circuit is referred to as a circuit. In certain exemplary embodiments, the circuit may include a group of integrated circuits, a unique integrated circuit, or a portion of an integrated circuit. For example, the circuit may include a custom VLSI circuit, a gate array, a logic circuit, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, the circuit may include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are in an electrically connected configuration with one or more other components via electrical conductors such as a printed circuit board (PCB). The circuit may also be implemented as a composite circuit relative to a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic component, and / or a programmable logic device. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices).Thus, in certain embodiments, the modules as defined above may be embodied or implemented as circuits.

[0114] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions, which control one or more microprocessors to implement some, most or all of the functions disclosed herein in combination with certain non-processor circuits and other elements. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions or in one or more application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), where each function or some combination of certain functions is implemented as custom logic. Combinations of these methods may also be used. In addition, references to "controller" hereinafter should be defined as including separate circuit components, application specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0115] Additionally, the terms "couple," "couple," or "connect" as used herein are intended to represent either a direct or indirect connection. Thus, if a first device couples or is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices (or components) and connections.

[0116] With regard to the use of terms such as "embodiment", "one embodiment", "exemplary embodiment", "specific embodiment" or other similar terms in this article, these terms are intended to indicate that the specific features, structures, functions, operations or characteristics described in conjunction with the embodiment are present in at least one embodiment of the present disclosure. Therefore, the appearance of phrases such as "in one embodiment", "in an embodiment", "in an embodiment", etc. may but do not necessarily all refer to the same embodiment, but to "one or more but not all embodiments", unless otherwise explicitly stated. In addition, the terms "comprising", "having", "including" and variations thereof are used in an open manner, and therefore should be interpreted as meaning "including but not limited to ...", unless otherwise explicitly stated. In addition, the elements preceded by "including ..." do not exclude the presence of additional identical elements in the subject process, method, system, article or device including the element without more restrictions.

[0117] The terms "a", "an", and "the" also refer to "one or more" unless expressly stated otherwise. In addition, the phrase "at least one of A and B" (whereby A and B are variables indicating specific objects or properties) that may be used herein and / or in the appended claims indicates a selection of either A or B, or a selection of both A and B, similar to the phrase "and / or". In the event that there are more than two variables in such a phrase, the phrase is hereby defined to include only one of the variables, any of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0118] In addition, in the case of use in this article, the term "about" or "approximately" applies to all numerical values, whether or not explicitly indicated. These terms generally refer to numerical ranges that are considered by those skilled in the art to be equivalent to the quoted value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0119] Furthermore, any enumerated list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. In addition, as used herein, the term "group" should be interpreted as meaning "one or more" according to the set theory, and in the case of "multiple groups", it should be interpreted as meaning the plural (multiple) of "one or more" and / or "a plurality or more", unless expressly stated otherwise.

[0120] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed by the invention. Based on the above description, many modifications and variations are possible. The described embodiments are selected to best illustrate the principles of the present technology and its practical application, so as to enable other technical personnel in the field to best use the technology in various embodiments and with various modifications suitable for the specific purpose contemplated. The scope of the present technology is defined by the appended claims.

Claims

1. A method for programming a memory device, the method comprising the steps of: Performing a smart verification operation to obtain an initial programming voltage; Starting to perform a programming operation on the selected word line with the initial programming voltage; performing a bit scan operation on the highest state being verified; as well as Based on the results of the bit scan operation, the initial programming voltage used for programming a subsequent word line is adjusted.

2. The method according to claim 1, further comprising the steps of: In response to the result that the bit scan operation fails, the value of the initial program voltage used for programming a subsequent word line is reduced.

3. The method according to claim 1, further comprising the steps of: Responsive to the result that the bit scan operation failed, verifying a next data state is initiated in a next program cycle of a plurality of program cycles of the programming operation.

4. The method according to claim 1, further comprising the steps of: In response to the result of the bit scanning operation being passed, the value of the initial programming voltage used for programming of a subsequent word line is maintained.

5. The method according to claim 1, further comprising the steps of: In response to the result that the bit scan operation failed, determining whether the highest state is an 'S1' data state and whether a current program loop is a first loop of a plurality of program loops of the programming operation; In response to determining that the highest state is the 'S1' data state and the current program loop is the first loop, a value of the initial program voltage used for programming of a subsequent word line is reduced.

6. The method according to claim 1, further comprising the steps of: Based on the number of high threshold bit fails, the value of the initial programming voltage used for programming of a subsequent word line is reduced.

7. The method according to claim 1, further comprising the steps of: Based on the number of upper threshold bit fails, verifying the next data state is initiated in a next program cycle of the plurality of program cycles of the programming operation.

8. A memory device, comprising: at least one memory block, the at least one memory block comprising a plurality of memory cells arranged in a plurality of word lines; A control circuit configured to program the memory cells of the at least one storage block in a plurality of program cycles, the control circuit configured to: Performing a smart verification operation to obtain an initial programming voltage; Starting to perform a programming operation on the selected word line with the initial programming voltage; performing a bit scan operation on the highest state being verified; as well as Based on the results of the bit scan operation, the initial programming voltage used for programming a subsequent word line is adjusted.

9. The memory device of claim 8, wherein the control circuit is further configured to: In response to the result that the bit scan operation fails, the value of the initial program voltage used for programming a subsequent word line is reduced.

10. The memory device of claim 8, wherein the control circuit is further configured to: Responsive to the result that the bit scan operation failed, verifying a next data state is initiated in a next program cycle of a plurality of program cycles of the programming operation.

11. The memory device of claim 8, wherein the control circuit is further configured to: In response to the result of the bit scanning operation being passed, the value of the initial programming voltage used for programming of a subsequent word line is maintained.

12. The memory device of claim 8, wherein the control circuit is further configured to: In response to the result that the bit scan operation failed, determining whether the highest state is an 'S1' data state and whether a current program loop is a first loop of a plurality of program loops of the programming operation; In response to determining that the highest state is the 'S1' data state and the current program loop is the first loop, a value of the initial program voltage used for programming of a subsequent word line is reduced.

13. The memory device of claim 8, wherein the control circuit is further configured to: Based on the number of high threshold bit fails, the value of the initial programming voltage used for programming of a subsequent word line is reduced.

14. The memory device of claim 8, wherein the control circuit is further configured to: Based on the number of upper threshold bit fails, verifying the next data state is initiated in a next program cycle of the plurality of program cycles of the programming operation.

15. A device, comprising: at least one memory block, the at least one memory block comprising a plurality of memory cells arranged in a plurality of word lines; Programming means for programming user data into the plurality of memory cells and configured to program the memory cells of the at least one memory block in a plurality of program cycles, the programming means being configured to; Performing a smart verification operation to obtain an initial programming voltage; Starting to perform a programming operation on the selected word line with the initial programming voltage; performing a bit scan operation on the highest state being verified; as well as Based on the results of the bit scan operation, the initial programming voltage used for programming a subsequent word line is adjusted.

16. The apparatus of claim 15, wherein the control circuit is further configured to: In response to the result that the bit scan operation fails, the value of the initial program voltage used for programming a subsequent word line is reduced.

17. The apparatus of claim 15, wherein the control circuit is further configured to: Responsive to the result that the bit scan operation failed, verifying a next data state is initiated in a next program cycle of a plurality of program cycles of the programming operation.

18. The apparatus of claim 15, wherein the control circuit is further configured to: In response to the result of the bit scanning operation being passed, the value of the initial programming voltage used for programming of a subsequent word line is maintained.

19. The apparatus of claim 15, wherein the control circuit is further configured to: In response to the result that the bit scan operation failed, determining whether the highest state is an 'S1' data state and whether a current program loop is a first loop of a plurality of program loops of the programming operation; In response to determining that the highest state is the 'S1' data state and the current program loop is the first loop, a value of the initial program voltage used for programming of a subsequent word line is reduced.

20. The apparatus of claim 15, wherein the control circuit is further configured to: Based on the number of high threshold bit fails, the value of the initial programming voltage used for programming of a subsequent word line is reduced.

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