Method of forming pattern and method of manufacturing semiconductor device using the same

Abstract

A method of forming a pattern and a method of manufacturing a semiconductor device using the same are provided. The method of forming a pattern includes: forming a first recess in a substrate; forming a first mask layer extending into the first recess on the substrate; performing a heat treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask including a lower portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask including a material having a greater tolerance than that of the first mask with respect to the etching process; and performing an etching process on the substrate using the second mask as an etching mask to form a pattern on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0085257 filed in the Korean Intellectual Property Office on June 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method for forming a pattern and a method for manufacturing a semiconductor device using the same. More specifically, the present disclosure relates to a method for forming a pattern and a method for manufacturing a dynamic random access memory (DRAM) device using the same. Background Art

[0004] In a method for manufacturing a semiconductor device, a mask layer can be formed on a target layer, a photoresist layer can be formed on the mask layer, a photo process can be performed on the photoresist layer to transform the photoresist layer into a photoresist pattern, an etching process can be performed on the mask layer using the photoresist pattern as an etching mask to transform the mask layer into a mask, and an etching process can be performed on the target layer using the mask as an etching mask to form a pattern in the target layer.

[0005] If the upper surface of the target layer does not have a uniform height, a defocus phenomenon may occur when a photo process is performed on the photoresist layer, and cause the photoresist pattern to not have a desired shape. Summary of the invention

[0006] One or more example embodiments provide a method of forming a pattern having improved characteristics.

[0007] One or more example embodiments provide a method of manufacturing a semiconductor device having improved characteristics.

[0008] According to an example embodiment, a method of forming a pattern includes: forming a first recess in a substrate; forming a first mask layer extending into the first recess on the substrate; performing a heat treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask including a lower portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask including a material having greater tolerance to an etching process than that of the first mask; and performing an etching process on the substrate using the second mask as an etching mask to form a pattern on the substrate.

[0009] According to an example embodiment, a method for forming a pattern includes: forming a recess in a substrate; forming a first mask layer on the substrate extending into the recess, wherein an upper surface of the first mask layer is closer to the substrate on a portion of the substrate having the recess thereon than on a portion of the substrate spaced apart from the recess; removing an upper portion of the first mask layer to form a first mask in the recess, the first mask including a portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask including a material different from that of the first mask, an upper surface of the second mask having a uniform height relative to the substrate; and performing an etching process on the substrate using the second mask as an etching mask to form a pattern on the substrate.

[0010] According to example embodiments, a method for manufacturing a semiconductor device includes: forming a first recess in a first region of a substrate, the substrate including a first region and a second region; forming a first mask layer extending into the first recess on the substrate; performing a heat treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask including a portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask including a material having a greater tolerance than that of the first mask with respect to an etching process; performing an etching process on the substrate and the first mask using the second mask as an etching mask to form a second recess and a third recess in the first region and the second region of the substrate, respectively, a first active pattern being defined by the first recess and the second recess on the first region of the substrate, and a second active pattern being defined by the third recess on the second region of the substrate; forming an isolation structure in the first to third recesses; forming a gate structure passing through the first active pattern and the isolation structure in the first region of the substrate; forming a bit line structure on a portion of the first active pattern and a portion of the isolation structure; forming a contact plug structure on the portion of the first active pattern; and forming a capacitor on the contact plug structure.

[0011] According to example embodiments, a semiconductor device includes: a substrate defining a first recess; a first mask provided in the first recess, the first mask including a spin-on hard mask (SOH) subjected to a heat treatment; and a second mask provided on an active pattern of the substrate adjacent to the first mask. An upper surface of the first mask is coplanar with an upper surface of the second mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages will become more apparent from the following description of example embodiments with reference to the accompanying drawings, in which:

[0013] Figures 1 to 12 are a plan view and a cross-sectional view illustrating a method of forming a pattern according to example embodiments; and

[0014] Figure 13 to Figure 51are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0015] With reference to the accompanying drawings, the above and other aspects and features of the semiconductor device and the method for forming the semiconductor device according to the example embodiments will become easily understood from the following detailed description. It will be understood that although the terms "first", "second" and / or "third" can be used here to describe various materials, layers (films), regions, electrodes, pads, patterns, structures and processes, these materials, layers (films), regions, electrodes, pads, patterns, structures and processes should not be limited by these terms. These terms are only used to distinguish one material, layer (film), region, electrode, pad, pattern, structure and process from another material, layer (film), region, electrode, pad, pattern, structure and process. Therefore, the first material, layer (film), region, electrode, pad, pattern, structure and process discussed below can be referred to as the second or third material, layer (film), region, electrode, pad, pattern, structure and process without departing from the present disclosure. It is not excluded that each example embodiment provided in the following description is associated with one or more features of another example or another example embodiment that is also provided here or not provided here but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" another element or layer, or "coupled to" another element or layer, it may be directly on the other element or layer, directly connected to the other element or layer, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on" another element or layer, "directly connected to" another element or layer, or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Statements such as "at least one of" when following a list of elements modify the entire list of elements without modifying the individual elements of the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will also be understood that even if a certain step or operation of manufacturing a device or structure is described before another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0016] Hereinafter, two directions among the horizontal directions substantially parallel to the upper surface of the substrate may be respectively referred to as a first direction D1 and a second direction D2, and a direction among the horizontal directions having an acute angle with respect to the first direction D1 and the second direction D2 may be referred to as a third direction D3. A direction substantially perpendicular to the upper surface of the substrate may be referred to as a vertical direction.

[0017] Figures 1 to 12 1 is a plan view and a cross-sectional view showing a method of forming a pattern according to an example embodiment. Specifically, Figure 1 and Fig.10 It is a floor plan. Figure 2 , Figure 8 and Fig.11 are sectional views taken along the line AA' of the corresponding plane view, Figure 3-7 , Fig. 9 and Fig.12 They are respectively cross-sectional views taken along line CC' of the corresponding plan view.

[0018] Reference Figures 1 to 3 , a first mask 10 may be formed on the substrate 100 , and an etching process may be performed using the first mask 10 as an etching mask to remove an upper portion of the substrate 100 , thereby forming a plurality of first recesses 102 .

[0019] The substrate 100 may include silicon, germanium, silicon-germanium, or a III-V compound semiconductor such as GaP, GaAs, or GaSb. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0020] The substrate 100 may include a first region I and a second region II. In example embodiments, the first region I of the substrate 100 may be a cell region in which a memory cell is formed, and the second region II of the substrate 100 that may surround the first region I may be a peripheral circuit region in which a peripheral circuit pattern for driving the memory cell is formed. However, example embodiments are not limited thereto. A portion of the first region I of the substrate 100 and a portion of the second region II of the substrate 100 adjacent to the first region I are shown in the drawings.

[0021] In example embodiments, a plurality of first recesses 102 may be spaced apart from each other along a first direction D1 on a first region I of a substrate 100, and each of the plurality of first recesses 102 may extend in a third direction D3. As the plurality of first recesses 102 are formed, a preliminary first active pattern 103 may be formed on the first region I of the substrate 100.

[0022] In example embodiments, the first mask 10 may include oxide, for example, silicon oxide.

[0023] Reference Figure 4 A second mask layer 20 may be formed on the first region I and the second region II of the substrate 100 on which the preliminary first active pattern 103 and the first mask 10 are formed, and the second mask layer 20 may have an upper surface higher than that of the first mask 10. The second mask layer 20 may fill the plurality of first recesses 102.

[0024] In example embodiments, the second mask layer 20 may include, for example, a spin-on hard mask (SOH), and may be formed by a spin coating process. Thus, the second mask layer 20 may fill the plurality of first recesses 102 on the first region I of the substrate 100, and the height of the upper surface of the portion of the second mask layer 20 on the first region I of the substrate 100 may be lower than the height of the upper surface of the portion of the second mask layer 20 on the second region II of the substrate 100.

[0025] Reference Figure 5 , a thermal treatment process, such as a baking process, may be performed on the second mask layer 20 .

[0026] In example embodiments, the heat treatment process may be performed at a temperature of about 145° C. to about 155° C. for about 60 seconds to about 150 seconds. As the heat treatment process is performed, portions of the second mask layer 20 in the plurality of first recesses 102 may be at least partially cured to be converted into the second mask 25, and portions of the second mask layer 20 on the first mask 10 and above the plurality of first recesses 102 may be converted into the sacrificial mask 27.

[0027] Reference Figure 6 , an etching process (eg, a rinsing process using an organic solvent) may be performed to remove the sacrificial mask 27 .

[0028] After removing the sacrificial mask 27, the upper surface of the remaining second mask 25 may be substantially coplanar with the upper surface of the first mask 10. That is, the upper surfaces of the first mask 10 and the second mask 25 on the substrate 100 may have a uniform height.

[0029] Reference Figure 7 , a third mask layer 30 may be formed on the first mask 10 and the second mask 25 .

[0030] In example embodiments, third mask layer 30 may include a material having higher resistance than second mask 25 with respect to an etching process, such as an amorphous carbon layer (ACL), and may be formed by a deposition process, such as a chemical vapor deposition (CVD) process.

[0031] The third mask layer 30 may be formed on the upper surfaces of the first mask 10 and the second mask 25 having a uniform height, and thus the upper surface of the third mask layer 30 may also have a uniform height.

[0032] Reference Figure 8 and Fig. 9 , a fourth mask layer may be formed on the third mask layer 30 , and a fifth mask layer may be formed on the fourth mask layer.

[0033] In example embodiments, the fourth mask layer may include silicon nitride or silicon oxynitride, and the fifth mask layer may be a photoresist layer.

[0034] A photo process (ie, an exposure process and a development process) may be performed on the fifth mask layer to form a fifth mask 50 , and the fourth mask layer may be patterned using the fifth mask 50 as an etching mask to form a fourth mask 40 .

[0035] During the etching process, a portion of the fifth mask 50 may be removed, and the remaining portion of the fifth mask 50 may be removed by, for example, an ashing process and / or a stripping process.

[0036] The third mask layer 30 may be patterned using the fourth mask 40 as an etching mask to form a third mask 35. During the etching process, a portion of the fourth mask 40 may be removed.

[0037] The first and second masks 10 and 25 , the preliminary first active pattern 103 , and an upper portion of the second region II of the substrate 100 may be etched through an etching process using the third mask 35 as an etching mask.

[0038] As the etching process is performed, the preliminary first active pattern 103 between the first recesses 102 and the upper portion of the first region I of the substrate 100 thereunder may be partially removed to form a second recess 104 on the first region I of the substrate 100, and thus the preliminary first active pattern 103 may be divided into a plurality of first active patterns 101 spaced apart from each other in the third direction D3.

[0039] In addition, as the etching process is performed, an upper portion of the second region II of the substrate 100 may be removed to form a third recess 106 , and a second active pattern 105 surrounded by the third recess 106 may be formed.

[0040] In example embodiments, the width and depth of the second recess 104 may be respectively greater than the width and depth of the first recess 102 , and the width and depth of the third recess 106 may be respectively greater than the width and depth of the second recess 104 .

[0041] During the etching process, the remaining fourth mask 40 may be removed, and at least a portion of the third mask 35 may be removed. For example, at least a lower portion of the third mask 35 may remain.

[0042] Reference Figures 10 to 12, the first to third masks 10, 25 and 35 may be removed.

[0043] Each of the second mask 25 and the third mask 35 may be removed by, for example, an ashing process and / or a stripping process, and the first mask 10 may be removed by, for example, a wet etching process or a dry etching process.

[0044] Through the above processes, the first active pattern 101 and the second active pattern 105 may be formed on the first region I and the second region II of the substrate 100 , respectively.

[0045] As described above, when the first recess 102 is formed on the first region I of the substrate 100 and the second mask layer 20 is formed on the first region I and the second region II of the substrate 100 to fill the first recess 102, the upper surface of the portion of the second mask layer 20 on the second region II of the substrate 100 may be higher than the upper surface of the portion of the second mask layer 20 on the first region I of the substrate 100.

[0046] Therefore, if a fourth mask layer and a fifth mask layer are formed directly on the second mask layer 20 and an exposure process is performed on the fifth mask layer, the upper surface of the fifth mask layer does not have a uniform height, and therefore, during the exposure process, the focus of light may not be aligned between the first region I and the second region II of the substrate 100, so that the fifth mask 50 may not have a desired shape.

[0047] Furthermore, after patterning the fourth mask layer to form the fourth mask, when patterning the second mask layer 20 to form the second mask by an etching process using the fourth mask as an etching mask, the second mask layer 20 does not have a uniform thickness, and thus the second mask may not be well formed at the boundary between the first region I and the second region II of the substrate 100. Therefore, when the upper portion of the substrate 100 and the first mask 10 are etched by an etching process using the second mask as an etching mask, the upper portion of the second region II of the substrate 100 and the upper portion of the boundary between the first region I and the second region II of the substrate 100 may not be properly removed, and as a result, the first active pattern 101 and the second active pattern 105 may not have desired shapes and layouts on the first region I and the second region II of the substrate 100, respectively.

[0048] However, in example embodiments, a heat treatment process may be performed on the second mask layer 20 to convert the lower and upper portions of the second mask layer 20 into the second mask 25 and the sacrificial mask 27, respectively, the sacrificial mask 27 may be removed by an etching process, and the third mask layer 30 may be formed by a deposition process on the first mask 10 and the second mask 25. Since the upper surfaces of the first mask 10 and the second mask 25 have a uniform height, the third mask layer 30 may have a uniform thickness, and each of the fourth and fifth mask layers that may be formed on the third mask layer 30 may also have a uniform thickness.

[0049] Therefore, during the exposure process of the fifth mask layer, the defocusing phenomenon between the first region I and the second region II of the substrate 100 can be prevented, and during the etching process using the third mask 35 as an etching mask, the upper portion of the second region II of the substrate 100 and the upper portion of the boundary between the first region I and the second region II of the substrate 100 can be easily removed.

[0050] The third mask 35 on the first mask 10 and the second mask 25 may include, for example, ACL, which may have a higher tolerance with respect to the etching process than the tolerance of the SOH included in the second mask 25. Therefore, even if the third recess 106 is formed to have a relatively large depth by an etching process using the third mask 35 as an etching mask, the third mask 35 may not be completely removed by the etching process, and at least a lower portion of the third mask 35 may remain. Therefore, the third recess 106 and the second active pattern 105 may be formed to have a desired width, depth, and / or shape.

[0051] Figure 13 to Figure 51 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig.13 , Fig.16 , Fig.19 , Fig.25 , Fig.30 , Fig.37 , Fig.41 , Fig.45 and Fig.48 It is a floor plan. Fig.14 , Fig.17 , Fig. 20 , Fig.23 , Fig.26 , Fig.29 , Fig.31 , Fig.34 , Fig.38 , Figure 42-43 , Fig.46 and Fig.49 are sectional views taken along the line AA' of the corresponding plane view, Fig.21 , Fig.24 , Fig. 27 , Fig.32 , Fig.35 , Figure 39-40 , Fig.44 , Fig.47 and Fig.50 are sectional views taken along the line BB' of the corresponding plane view, Fig.15 , Fig.18 , Fig. 22 , Fig.28 , Fig.33 and Fig.51 are sectional views taken along the line CC' of the corresponding plane view, Fig.36 It is a cross-sectional view taken along the line EE' corresponding to the plan view.

[0052] This method can be a reference Figures 1 to 12 The method of forming a pattern is applied to a method of forming a first active pattern and a second active pattern of a dynamic random access memory (DRAM) device, and repeated description is omitted here.

[0053] Reference Figures 13 to 15 , can be executed and referenced Figures 1 to 12 The processes shown are substantially the same or similar processes to form the first active pattern 101 and the second active pattern 105 on the first region I and the second region II of the substrate 100, respectively.

[0054] The isolation structure 110 may be formed to cover sidewalls of the first and second active patterns 101 and 105 .

[0055] In example embodiments, the isolation structure 110 may include a first isolation pattern 112, a second isolation pattern 114, and a third isolation pattern 116 sequentially stacked on an inner wall of the third recess 106. In example embodiments, the first isolation pattern 112 and the second isolation pattern 114 may be formed in the second recess 104 having a width smaller than that of the third recess 106, and the first isolation pattern 112 may be formed in a plurality of first recesses 102 having a width smaller than that of the second recess 104.

[0056] Each of the first isolation pattern 112 and the third isolation pattern 116 may include an oxide, for example, silicon oxide, and the second isolation pattern 114 may include an insulating nitride, for example, silicon nitride.

[0057] Reference Figures 16 to 18 The first active pattern 101 and the isolation structure 110 formed on portions of the first and second regions I and II adjacent to the first region I may be etched through an etching process to form a fourth recess 740 extending in the first direction D1.

[0058] In example embodiments, during the etching process, the first active pattern 101 including a semiconductor material may be etched less than the isolation structure 110 including an insulating material. Therefore, the fourth recess 740 may have a lower surface that is not flat in the first direction D1 but is recessed upward on the upper surface of the first active pattern 101.

[0059] A first gate insulating layer and a first conductive layer may be sequentially stacked on the inner wall of the fourth recess 740 and the upper surfaces of the first active pattern 101, the second active pattern 105, and the isolation structure 110. The first gate insulating layer and the first conductive layer may be planarized until the upper surfaces of the first active pattern 101, the second active pattern 105, and the isolation structure 110 are exposed, and an upper portion of the first conductive layer may be removed by, for example, an etch-back process.

[0060] The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0061] As the planarization process is performed, the first gate insulating pattern 120 may be formed on the inner wall of the fourth recess 740 , and as the etch-back process is performed, the first conductive pattern 140 may be formed on the first gate insulating pattern 120 to fill the lower portion of the fourth recess 740 .

[0062] A second conductive pattern 150 may be formed on the first conductive pattern 140, a first gate mask layer may be formed on the second conductive pattern 150, the first and second active patterns 101 and 105, and the isolation structure 110 to fill the fourth recess 740, and the first gate mask layer may be planarized until upper surfaces of the first and second active patterns 101 and 105 and the isolation structure 110 are exposed to form a first gate mask 160 in an upper portion of the fourth recess 740. The first conductive pattern 140 and the second conductive pattern 150 may jointly form a gate electrode, and a first barrier pattern may be further formed between the first gate insulating pattern 120 and the first conductive pattern 140.

[0063] The first gate insulating pattern 120 may include an oxide (e.g., silicon oxide), the first barrier pattern may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.), the first conductive pattern 140 may include a metal (e.g., tungsten), a metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal silicide, or doped polysilicon, the second conductive pattern 150 may include, for example, doped polysilicon, and the first gate mask 160 may include a nitride (e.g., silicon nitride).

[0064] The first gate insulating pattern 120, the first barrier pattern, the first conductive pattern 140, the second conductive pattern 150, and the first gate mask 160 in the fourth recess 740 may collectively form a first gate structure 170. In example embodiments, the first gate structure 170 may extend along the first direction D1 on a portion of the first region I of the substrate 100 and the second region II of the substrate 100 adjacent to the first region I in the first direction D1, and a plurality of first gate structures 170 may be spaced apart from each other in the second direction D2. Ends of the first gate structures 170 in the first direction D1 may be aligned with each other in the second direction D2 on the portion of the second region II of the substrate 100.

[0065] Reference Figures 19 to 22 , an insulating layer structure 210 may be formed on the first region I and the second region II of the substrate 100, and a portion of the insulating layer structure 210 on the second region II of the substrate 100 (except for a portion of the second region II adjacent to the first region I) may be removed. The insulating layer structure 210 may include a first insulating layer 180, a second insulating layer 190, and a third insulating layer 200 stacked in sequence.

[0066] For example, a thermal oxidation process may be performed on the second active pattern 105 on the second region II of the substrate 100 to form the second gate insulating layer 220 .

[0067] The insulating layer structure 210 may be patterned, and the first active pattern 101, the isolation structure 110, and the first gate mask 160 of the first gate structure 170 may be partially etched by an etching process using the patterned insulating layer structure 210 as an etching mask to form a first opening 230. In example embodiments, the insulating layer structure 210 remaining after the etching process may have a shape such as a circle or an ellipse in a plan view, and a plurality of insulating layer structures 210 may be spaced apart from each other along the first direction D1 and the second direction D2 on portions of the first region I and the second region II adjacent to the first region I. Each insulating layer structure 210 may overlap ends of adjacent first active patterns 101 in the third direction D3, respectively.

[0068] Reference Fig.23 and Fig.24 A third conductive layer 240, a second barrier layer 250, a fourth conductive layer 260, and a sixth mask layer 270 may be sequentially stacked on the insulating layer structure 210, the first active pattern 101 exposed by the first opening 230 on the first region I of the substrate 100, the isolation structure 110, and the first gate structure 170, and the second gate insulating layer 220 and the isolation structure 110 on the second region II of the substrate 100 to form a conductive structure layer together. The third conductive layer 240 may fill the first opening 230.

[0069] The third conductive layer 240 may include, for example, doped polysilicon, the second barrier layer 250 may include metal silicon nitride (eg, titanium silicon nitride), the fourth conductive layer 260 may include metal (eg, tungsten), and the sixth mask layer 270 may include nitride (eg, silicon nitride).

[0070] Reference Figure 25 to Figure 28 , the conductive structure layer may be patterned to form a second gate structure 330 on the second region II of the substrate 100 .

[0071] The second gate structure 330 may include a second gate insulating pattern 280, a third conductive pattern 290, a second barrier pattern 300, a fourth conductive pattern 310, and a second gate mask 320 sequentially stacked in a vertical direction on the substrate 100. The sequentially stacked third conductive pattern 290, the second barrier pattern 300, and the fourth conductive pattern 310 may collectively form a second gate electrode.

[0072] The second gate structure 330 may at least partially overlap the second active pattern 105 in a vertical direction on the second region II of the substrate 100 .

[0073] In addition, a portion of the conductive structure layer on the edge portion of the first region I of the substrate 100 adjacent to the second region II of the substrate 100 can be removed to partially expose the insulating layer structure 210 and the upper surfaces of the first active pattern 101, the isolation structure 110 and the first gate structure 170 under the first opening 230.

[0074] A first spacer structure may be formed on the sidewall of the second gate structure 330, and a second spacer structure may be formed on the sidewall of the portion of the conductive structure layer remaining on the first region I of the substrate 100. The first spacer structure may include a first gate spacer 340 and a third gate spacer 350 sequentially stacked from the sidewall of the second gate structure 330 in a horizontal direction, and the second spacer structure may include a second gate spacer 345 and a fourth gate spacer 355 sequentially stacked from the sidewall of the conductive structure layer in a horizontal direction.

[0075] The first spacer 340 and the second spacer 345 may be formed by forming a first spacer layer on the substrate 100 having the conductive structure layer and the second gate structure 330 thereon and anisotropically etching the first spacer layer. The third spacer 350 and the fourth spacer 355 may be formed by forming a second spacer layer on the substrate 100 having the conductive structure layer, the second gate structure 330, and the first spacer 340 and the second spacer 345 and anisotropically etching the second spacer layer.

[0076] The first spacer 340 and the second spacer 345 may include nitride (eg, silicon nitride), and the third spacer 350 and the fourth spacer 355 may include oxide (eg, silicon oxide).

[0077] However, example embodiments are not limited thereto, and each of the first spacer structure and the second spacer structure may include a single spacer, or include more than two spacers sequentially stacked.

[0078] A first etch stop layer 360 may be formed on the substrate 100 having thereon the conductive structure layer, the second gate structure 330, the first and second spacer structures, and the isolation structure 110. The first etch stop layer 360 may include nitride (eg, silicon nitride).

[0079] Reference Fig.29 A first insulating interlayer 370 can be formed on the first etch stop layer 360, an upper portion of the first insulating interlayer 370 can be flattened until portions of the first etch stop layer 360 on the upper surface of the second gate structure 330 and the upper surface of the conductive structure layer are exposed, and a capping layer 380 can be formed on the first insulating interlayer 370 and the first etch stop layer 360.

[0080] Therefore, the first insulating interlayer 370 may fill the space between the first spacer structures on the corresponding sidewalls of the second gate structure 330 and the space between the first spacer structures on the sidewalls of the second gate structure 330 and the second spacer structures on the sidewalls of the conductive structure layer.

[0081] The first insulating interlayer 370 may include oxide (eg, silicon oxide), and the capping layer 380 may include nitride (eg, silicon nitride).

[0082] Reference Figure 30 to Figure 33 , a portion of the capping layer 380 on the first region I of the substrate 100 can be removed to form a first capping pattern 385, and the first capping pattern 385 can be used as an etching mask to sequentially etch the first etch stop layer 360, the sixth mask layer 270, the fourth conductive layer 260, the second barrier layer 250 and the third conductive layer 240.

[0083] In example embodiments, on the first region I of the substrate 100 , the first capping pattern 385 may extend in the second direction D2 , and a plurality of first capping patterns 385 may be spaced apart from each other along the first direction D1 . The capping layer 380 may remain on the second region II of the substrate 100 .

[0084] Through the etching process, on the first area I of the substrate 100, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the sixth mask 275, the first etch stop pattern 365 and the first cover pattern 385 can be stacked in sequence on the first opening 230, and the third insulating pattern 205, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the sixth mask 275, the first etch stop pattern 365 and the first cover pattern 385 can be stacked in sequence on a portion of the second insulating layer 190 outside the first opening 230.

[0085] Hereinafter, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the sixth mask 275, the first etch stop pattern 365, and the first capping pattern 385, which are sequentially stacked, may be collectively referred to as a bit line structure 395. In example embodiments, on the first region I of the substrate 100, the bit line structure 395 may extend in the second direction D2, and a plurality of the bit line structures 395 may be spaced apart from each other along the first direction D1.

[0086] A dummy bit line structure 397 extending along the second direction D2 and including a seventh conductive pattern 247, a fourth barrier pattern 257, an eighth conductive pattern 267, a seventh mask 277, a second etch pattern 367, and a second capping pattern 387 stacked in sequence may be formed on a portion of the first region I of the substrate 100 adjacent to the second region II of the substrate 100 in the first direction D1, and the first etch stop layer 360 may remain on the second gate structure 330, the first and second spacer structures, a portion of the insulating layer structure 210, the second active pattern 105, and the isolation structure 110. In addition, a capping layer 380 may remain on a portion of the first etch stop layer 360 on an upper surface of the second gate structure 330 and the first insulating interlayer 370.

[0087] Reference Fig.34 and Fig.35 A fifth spacer layer may be formed on the substrate 100 having the bit line structure 395 , the dummy bit line structure 397 , and the capping layer 380 thereon, and a fourth insulating layer and a fifth insulating layer may be sequentially formed on the fifth spacer layer.

[0088] The fifth spacer layer may cover a sidewall of the third insulation pattern 205 below a portion of the bit line structure 395 on the second insulation layer 190 , and the fifth insulation layer may fill a remaining portion of the first opening 230 .

[0089] The fifth spacer layer may include nitride (eg, silicon nitride), the fourth insulating layer may include oxide (eg, silicon oxide), and the fifth insulating layer may include nitride (eg, silicon nitride).

[0090] The fourth insulating layer and the fifth insulating layer may be removed by an etching process. In example embodiments, the etching process may include using an etching solution (eg, H 2 PO 3 , SCI and HF), and all portions of the fourth insulating layer and the fifth insulating layer except portions of the fourth insulating layer and the fifth insulating layer in the first opening 230 may be removed. Therefore, most of the surface of the fifth spacer layer, that is, all portions of the surface of the fifth spacer layer except the portion of the surface of the fifth spacer layer in the first opening 230 may be exposed, and portions of the fourth insulating layer and the fifth insulating layer remaining in the first opening 230 may form a fourth insulating pattern 410 and a fifth insulating pattern 420, respectively.

[0091] A sixth spacer layer may be formed on the exposed surfaces of the fifth spacer layer and the fourth and fifth insulating patterns 410 and 420 in the first opening 230, and the sixth spacer layer may be anisotropically etched to form a sixth spacer 430 on the surfaces of the fifth spacer layer and the fourth and fifth insulating patterns 410 and 420, thereby covering the sidewalls of the bit line structure 395. The sixth spacer 430 may also be formed on the sidewalls of the dummy bit line structure 397. The sixth spacer 430 may include an oxide (e.g., silicon oxide).

[0092] For example, a dry etching process may be further performed to form a second opening 440 exposing the upper surface of the first active pattern 101 , and upper surfaces of the isolation structure 110 and the first gate mask 160 may also be exposed by the second opening 440 .

[0093] By dry etching, the portion of the fifth spacer layer on the capping layer 380, the first capping pattern 385 and the second capping pattern 387 and the second insulating layer 190 can be removed, and the fifth spacer 400 can be formed on the sidewall of the bit line structure 395. The fifth spacer 400 can also cover the sidewall of the dummy bit line structure 397.

[0094] During the dry etching process, the first and second insulating layers 180 and 190 may also be partially removed, leaving first and second insulating patterns 185 and 195 respectively under the bit line structure 395. The first to third insulating patterns 185, 195, and 205 under the bit line structure 395 may collectively form an insulating pattern structure 215.

[0095] Reference Fig.36A seventh spacer layer may be formed on the upper surfaces of the capping layer 380 and the first and second capping patterns 385 and 387, the outer sidewalls of the sixth spacer 430, portions of the upper surfaces of the fourth and fifth insulating patterns 410 and 420, and the upper surfaces of the first active pattern 101, the isolation structure 110, and the first gate mask 160 exposed by the second opening 440, and the seventh spacer layer may be anisotropically etched to form a seventh spacer 450 covering the outer sidewalls of the sixth spacer 430 on the sidewalls of the bit line structure 395 and the dummy bit line structure 397. The seventh spacer 450 may include a nitride (e.g., silicon nitride).

[0096] The fifth to seventh spacers 400 , 430 , and 450 sequentially stacked on the sidewalls of the bit line structure 395 in a horizontal direction on the first region I of the substrate 100 may be referred to as a preliminary third spacer structure 460 .

[0097] A lower contact plug layer may be formed on the first region I of the substrate 100 to fill the second opening 440 , and may be planarized until upper surfaces of the capping layer 380 and the first and second capping patterns 385 and 387 are exposed to form a lower contact plug 475 .

[0098] The lower contact plugs 475 may extend in the second direction D2 between the bit line structures 395 adjacent in the first direction D1 and between the bit line structures 395 and the dummy bit line structures 397, and a plurality of the lower contact plugs 475 may be spaced apart from each other in the first direction D1. Each lower contact plug 475 may contact an upper surface of an end portion of the corresponding first active pattern 101 in the third direction D3.

[0099] Reference Figure 37 to Figure 39 An etching mask having third openings spaced apart from each other in the second direction D2 may be formed on the capping layer 380, the bit line structure 395, the dummy bit line structure 397, and the lower contact plug 475, each third opening may extend in the first direction, and the etching mask may be used to etch the lower contact plug 475 to form a fourth opening 445.

[0100] In example embodiments, each third opening may overlap the first gate structure 170 in a vertical direction, and thus an upper surface of the first gate mask 160 of the first gate structure 170 may be exposed through the fourth opening 445. As the fourth opening 445 is formed, the lower contact plug 475 extending in the second direction D2 may be divided into a plurality spaced apart from each other in the second direction D2.

[0101] After removing the etching mask, a fence pattern 480 may be formed in the fourth opening 445. In example embodiments, a plurality of fence patterns 480 may be spaced apart from one another along the second direction D2 between adjacent bit line structures 395 in the first direction D1 among the bit line structures 395 and between the bit line structures 395 and the dummy bit line structures 397. The fence pattern 480 may include an insulating nitride (e.g., silicon nitride).

[0102] By forming lower contact plugs 475 extending along the second direction D2 between bit line structures 395 adjacent along the first direction D1 in the bit line structure 395, forming fourth openings 445 spaced apart from each other along the second direction D2 through the lower contact plugs 475, and forming fence patterns 480 respectively in the fourth openings 445, the lower contact plugs 475 and the fence patterns 480 may be alternately arranged in the second direction D2, however example embodiments are not limited thereto.

[0103] In another example embodiment, the lower contact plugs 475 and the fence patterns 480 may be alternately arranged in the second direction D2 by forming a fence layer extending along the second direction D2 between bit line structures 395 adjacent along the first direction D1 in the bit line structure 395, forming fifth openings spaced apart from each other along the second direction D2 through the fence layer, and forming lower contact plugs 475 respectively in the fifth openings.

[0104] In another example embodiment, the lower contact plugs 475 and the fence patterns 480 may be alternately arranged in the second direction D2 by forming a sacrificial layer extending along the second direction D2 between bit line structures 395 adjacent along the first direction D1 in the bit line structure 395, forming fence patterns 480 spaced apart from each other in the second direction D2 through the sacrificial layer, removing the sacrificial layer to form sixth openings, and forming lower contact plugs 475 respectively in the sixth openings.

[0105] Reference Fig.40 , the upper portion of the lower contact plug 475 may be removed to expose the upper portion of the preliminary third spacer structure 460 on the sidewalls of the bit line structure 395 and the dummy bit line structure 397, and the upper portions of the sixth spacer 430 and the seventh spacer 450 of the exposed preliminary third spacer structure 460 may be removed.

[0106] An upper portion of the lower contact plug 475 may be further removed. Therefore, an upper surface of the lower contact plug 475 may be lower than uppermost surfaces of the sixth spacer 430 and the seventh spacer 450 .

[0107] An eighth spacer layer may be formed on the bit line structure 395, the dummy bit line structure 397, the preliminary third spacer structure 460, the fence pattern 480, the capping layer 380, and the lower contact plug 475, and the eighth spacer layer may be anisotropically etched to form an eighth spacer 490 that covers an upper portion of the preliminary third spacer structure 460 on each of opposite sidewalls in the first direction D1 of the bit line structure 395. Thus, the upper surface of the lower contact plug 475 may be exposed.

[0108] An ohmic contact pattern 500 may be formed on the exposed upper surface of the lower contact plug 475. In example embodiments, the ohmic contact pattern 500 may be formed by forming a first metal layer on the first and second capping patterns 385 and 387, the fence pattern 480, the capping layer 380, the eighth spacer 490, and the lower contact plug 475, and performing a heat treatment process on the first metal layer. Unreacted portions of the first metal layer may be removed. The ohmic contact pattern 500 may include a metal silicide (e.g., cobalt silicide, nickel silicide, titanium silicide, etc.).

[0109] Reference Fig.41 and Fig.42 A seventh opening 520 may be formed through a portion of the capping layer 380 on a portion of the second region II of the substrate 100 adjacent to the first region I of the substrate 100 in the first direction D1 and the first insulating interlayer 370, the first etch stop layer 360, the insulating pattern structure 215, the isolation structure 110, the first gate mask 160, and the second conductive pattern 150 below the portion of the capping layer 380 to expose the first conductive pattern 140. The seventh opening 520 may also expose the first gate insulating pattern 120 on the sidewall of the first conductive pattern 140.

[0110] Reference Fig.43 and Fig.44 A fifth barrier layer 530 can be formed on the first cover pattern 385 and the second cover pattern 387, the fence pattern 480, the eighth spacer 490, the ohmic contact pattern 500 and the lower contact plug 475 on the first region I of the substrate 100, and the cover layer 380 on the second region II of the substrate 100 and the isolation structure 110 exposed by the seventh opening 520, the first conductive pattern 140 and the first gate insulation pattern 120, and a second metal layer 540 can be formed on the fifth barrier layer 530 to fill the space between the bit line structures 395, the space between the bit line structure 395 and the dummy bit line structure 397, and the seventh opening 520.

[0111] Reference Figure 45 to Figure 47 , the second metal layer 540 and the fifth barrier layer 530 may be patterned.

[0112] Thus, an upper contact plug 549 may be formed on the first region I of the substrate 100, and a second wiring 605 may be formed on the second region II of the substrate 100. In addition, a first wiring 600 may be formed on a portion of the second region II of the substrate 100 adjacent to the first region I of the substrate 100, and a third wiring 607 may be formed on a portion of the first region I of the substrate 100 adjacent to the second region II of the substrate 100. An eighth opening 547 may be formed between the upper contact plug 549 and adjacent ones of the first to third wirings 600, 605, and 607.

[0113] The eighth opening 547 can be formed by partially removing not only the second metal layer 540 and the fifth barrier layer 530 but also the first cap pattern 385 and the second cap pattern 387, the fence pattern 480, the cap layer 380, the preliminary third spacer structure 460, the eighth spacer 490, the first etch stop layer 360, the first etch stop pattern 365 and the sixth mask 275, thereby exposing the upper surface of the sixth spacer 430.

[0114] As the eighth opening 547 is formed, on the first region I of the substrate 100, the second metal layer 540 and the fifth barrier layer 530 may be transformed into a first metal pattern 545 and a fifth barrier pattern 535 covering a lower surface of the first metal pattern 545, respectively, and the first metal pattern 545 and the fifth barrier pattern 535 may collectively form an upper contact plug 549. In example embodiments, a plurality of upper contact plugs 549 may be spaced apart from each other along the first direction D1 and the second direction D2 on the first region I of the substrate 100 and may be arranged in a honeycomb pattern. Each upper contact plug 549 may have a shape, for example, circular, elliptical, or polygonal.

[0115] The lower contact plug 475 , the ohmic contact pattern 500 , and the upper contact plug 549 may collectively form a first contact plug structure on the first region I of the substrate 100 .

[0116] The first wiring 600 may include a third metal pattern 590 and a seventh barrier pattern 580 covering a lower surface of the third metal pattern 590. A second contact plug 570 including a second metal pattern 560 and a sixth barrier pattern 550 may be formed in the seventh opening 520. The second wiring 605 may include a fourth metal pattern 595 and an eighth barrier pattern 585 covering a lower surface of the fourth metal pattern 595. The third wiring 607 may include a fifth metal pattern 597 and a ninth barrier pattern 587 covering a lower surface of the fifth metal pattern 597.

[0117] In example embodiments, the first wiring 600 may overlap the seventh opening 520 in the vertical direction, and a plurality of first wirings 600 may be spaced apart from each other in the second direction D2. The first wiring 600 may be electrically connected to the first conductive pattern 140 through the second contact plug 570, and thus an electrical signal may be applied to the first gate structure 170. The second wiring 605 may overlap the second gate structure 330 in the vertical direction. The third wiring 607 may overlap the dummy bit line structure 397 in the vertical direction.

[0118] Reference Figures 48 to 51 , the sixth spacer 430 may be removed to form an air gap 435 connected to the eighth opening 547. The sixth spacer 430 may be removed by, for example, a wet etching process.

[0119] In example embodiments, not only the portion of the sixth spacer 430 directly exposed by the eighth opening 547 but also other portions of the sixth spacer 430 parallel thereto in a horizontal direction may be removed by the wet etching process. That is, not only the portion of the sixth spacer 430 exposed by the eighth opening 547 so as not to be covered by the upper contact plug 549 but also the portion of the sixth spacer 430 covered by the upper contact plug 549 may be removed by the wet etching process.

[0120] A second insulating interlayer may be formed to fill the eighth opening 547 .

[0121] In example embodiments, the second insulating interlayer may include a sixth insulating layer 610 and a seventh insulating layer 620 stacked in sequence. The sixth insulating layer 610 may be formed using an insulating material having a poor gap filling property, and thus the air gap 435 below the eighth opening 547 may not be filled. The air gap 435 may also be referred to as an air spacer 435, and the fifth spacer 400 and the seventh spacer 450 and the air spacer 435 may together form a third spacer structure 465. The air gap 435 may be a spacer including air. The seventh insulating layer 620 may include an oxide (e.g., silicon oxide) or an insulating nitride (e.g., silicon nitride).

[0122] The capacitor 670 may be formed to contact an upper surface of the upper contact plug 549 .

[0123] That is, a second etch stop layer 630 and a mold layer may be formed on the upper contact plug 549, the second insulating interlayer, and the first to third wirings 600, 605, and 607, and the second etch stop layer 630 and the mold layer may be partially etched to form a ninth opening exposing the upper surface of the upper contact plug 549. The second etch stop layer 630 may include an insulating nitride (e.g., silicon nitride).

[0124] A lower electrode layer may be formed on the exposed upper surface of the upper contact plug 549 and the mold layer to fill the ninth opening, and the lower electrode layer may be planarized until the upper surface of the mold layer is exposed to segment the lower electrode layer. For example, a wet etching process may be performed to remove the mold layer, and a lower electrode 640 having a columnar shape may be formed on the upper surface of the upper contact plug 549. Alternatively, the lower electrode 640 may be formed to have a cylindrical shape in the ninth opening. The lower electrode 640 may include, for example, a metal, a metal nitride, a metal silicide, doped polysilicon, and the like.

[0125] A dielectric layer 650 may be formed on the lower electrode 640 and the second etch stop layer 630 , and an upper electrode 660 may be formed on the dielectric layer 650 to form a capacitor 670 including the lower electrode 640 , the dielectric layer 650 , and the upper electrode 660 on the first region I of the substrate 100 .

[0126] The dielectric layer 650 may include, for example, a metal oxide, and the upper electrode 660 may include, for example, a metal, a metal nitride, a metal silicide, doped polysilicon, doped silicon germanium, or the like.

[0127] A contact plug and an upper wiring may be further formed to be electrically connected to the capacitor 670 , the bit line structure 395 , and the first to third wirings 600 , 605 , and 607 , so that the manufacture of the semiconductor device may be completed.

[0128] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for forming a pattern, the method comprising: forming a first recess in the substrate; forming a first mask layer extending into the first recess on the substrate; performing a thermal treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask including a lower portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask comprising a material having greater resistance to an etching process than the first mask; as well as An etching process is performed on the substrate using the second mask as an etching mask to form the pattern on the substrate.

2. The method according to claim 1, wherein: The first mask layer includes a spin-on hard mask (SOH), and Wherein, the second mask includes an amorphous carbon layer (ACL).

3. The method according to claim 1, wherein: The thermal treatment process includes performing a baking process at a temperature of about 145° C. to about 155° C. for about 60 seconds to about 150 seconds.

4. The method according to claim 1, wherein: Removing the upper portion of the first mask layer includes performing a rinsing process using an organic solvent.

5. The method according to claim 1, wherein: Forming the second mask includes: performing a deposition process on the substrate and the first mask layer to form a second mask layer; and The second mask layer is patterned to form the second mask.

6. The method according to claim 5, wherein: an upper surface of the first mask layer is closer to the substrate at a portion of the substrate having the first recess thereon than at a portion of the substrate spaced apart from the first recess, and Wherein, an upper surface of the second mask layer has a uniform height relative to the substrate.

7. The method according to claim 5, further comprising: stacking a third mask layer and a fourth mask layer in sequence on the second mask layer; performing a photo process on the fourth mask layer to form a fourth mask; performing an etching process on the third mask layer using the fourth mask as an etching mask to form a third mask; as well as An etching process is performed on the second mask layer using the third mask as an etching mask to form the second mask.

8. The method according to claim 7, wherein: The third mask layer includes silicon nitride, and Wherein, the fourth mask layer includes a photoresist layer.

9. The method according to claim 1, wherein: Forming the first recess in the substrate includes: forming a third mask on the substrate; and performing an etching process using the third mask as an etching mask to remove an upper portion of the substrate, wherein the first mask layer is formed on the third mask layer, and Wherein, an upper surface of the first mask is substantially coplanar with an upper surface of the third mask.

10. The method according to claim 1, wherein: The substrate includes a first region and a second region surrounding the first region, wherein the first recess extends into the substrate in the first region, and Wherein, performing the etching process on the substrate includes forming a second recess in the substrate extending to the second region.

11. The method according to claim 10, wherein: The width and depth of the second recess are respectively greater than the width and depth of the first recess.

12. The method according to claim 10, wherein: forming the first recess includes forming a plurality of first recesses that are spaced apart from each other and extend into the substrate, the first recess being one of the plurality of first recesses, and Wherein, performing the etching process on the substrate includes forming a third recess between adjacent first recesses among the plurality of first recesses on the first region of the substrate, the third recess having a width and a depth respectively greater than a width and a depth of each of the plurality of first recesses.

13. A method for forming a pattern, the method comprising: forming a recess in the substrate; forming a first mask layer on the substrate extending into the recess, wherein an upper surface of the first mask layer is closer to the substrate at a portion of the substrate having the recess thereon than at a portion of the substrate spaced apart from the recess; removing an upper portion of the first mask layer to form a first mask in the recess, the first mask comprising a portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask including a material different from that of the first mask, an upper surface of the second mask having a uniform height relative to the substrate; and An etching process is performed on the substrate using the second mask as an etching mask to form the pattern on the substrate.

14. The method according to claim 13, wherein: The first mask layer includes a spin-on hard mask (SOH), and Wherein, the second mask includes an amorphous carbon layer (ACL).

15. The method according to claim 13, wherein: Removing the upper portion of the first mask layer includes performing a rinsing process using an organic solvent.

16. The method according to claim 15, further comprising: Before removing the upper portion of the first mask layer, a thermal treatment process is performed on the first mask layer.

17. A method for manufacturing a semiconductor device, the method comprising: forming a first recess in a first region of a substrate, the substrate comprising the first region and a second region; forming a first mask layer extending into the first recess on the substrate; performing a thermal treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask comprising a portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask comprising a material having greater resistance to an etching process than the first mask; performing an etching process on the substrate and the first mask using the second mask as an etching mask to form a second recess and a third recess in the first region and the second region of the substrate, respectively, a first active pattern being defined by the first recess and the second recess on the first region of the substrate, and a second active pattern being defined by the third recess on the second region of the substrate; forming an isolation structure in the first recess to the third recess; forming a gate structure passing through the first active pattern and the isolation structure in the first region of the substrate; forming a bit line structure on a portion of the first active pattern and a portion of the isolation structure; forming a contact plug structure on the portion of the first active pattern; as well as A capacitor is formed on the contact plug structure.

18. The method according to claim 17, wherein: The first mask layer includes a spin-on hard mask (SOH), and Wherein, the second mask includes an amorphous carbon layer (ACL).

19. The method according to claim 17, wherein: Forming the second mask includes: performing a deposition process on the substrate and the first mask layer to form a second mask layer; and patterning the second mask layer to form the second mask, wherein the upper surface of the first mask layer is closer to the substrate at the first region of the substrate than at the second region of the substrate spaced apart from the first recess, and Wherein, an upper surface of the second mask layer has a uniform height relative to the substrate.

20. The method according to claim 17, wherein: forming the first recess includes forming a plurality of first recesses that are spaced apart from each other and extend into the substrate, the first recess being one of the plurality of first recesses, and Wherein, performing the etching process using the second mask includes forming the second recess between adjacent first recesses among the plurality of first recesses, the second recess having a width and a depth respectively greater than a width and a depth of each of the plurality of first recesses.

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