Method of manufacturing an IGBT device

Abstract

The application belongs to the technical field of IGBT devices, and particularly discloses a manufacturing method of an IGBT device, which comprises the following steps: forming a plurality of first grooves in an n-type semiconductor layer; forming a channel injection area on one side of the first grooves in the n-type semiconductor layer through inclined ion implantation, and forming a p-type body area through twice inclined ion implantation; forming an n-type charge storage area through vertical ion implantation; forming an n-type source area through inclined ion implantation; forming a first gate and a second groove through a self-alignment process; and forming a second gate in the second groove. The application can reduce the number of photolithography processes in the manufacturing process of the IGBT device, and reduce the manufacturing cost of the IGBT device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of IGBT devices, and particularly relates to a manufacturing method of an IGBT device. BACKGROUND

[0002] An insulated gate bipolar transistor (IGBT) is a device combined by a MOS transistor and a bipolar transistor, the input terminal of which is a MOS transistor and the output terminal of which is a PNP transistor. The IGBT combines the advantages of the two types of devices, has the advantages of small driving power and fast switching speed of the MOS transistor, and has the advantages of low saturation voltage drop and large capacity of the bipolar transistor. The IGBT has been widely used in modern power electronics technology, and particularly occupies a dominant position in high-frequency and medium-power tube applications. In the manufacturing process of the IGBT device in the prior art, multiple photolithography processes are required, and the cost of the photolithography process is high, so that the manufacturing cost of the IGBT device is difficult to reduce. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a manufacturing method of an IGBT device to reduce the manufacturing cost of the IGBT device.

[0004] To achieve the above-mentioned purpose of the present application, the present application provides a manufacturing method of an IGBT device, comprising:

[0005] forming a first insulating layer on a provided n-type semiconductor layer, etching the first insulating layer and the n-type semiconductor layer to form a plurality of first grooves in the n-type semiconductor layer;

[0006] performing inclined ion implantation to one side of the first grooves to form a channel implantation region located at one side of the first grooves in the n-type semiconductor layer;

[0007] performing inclined ion implantation to both sides of the first grooves to form p-type body regions located at both sides of the first grooves in the n-type semiconductor layer;

[0008] performing vertical ion implantation to form an n-type charge storage region located below the first grooves in the n-type semiconductor layer;

[0009] forming a gate dielectric layer on the surface of the first grooves, then forming a first conductive layer and performing etching back, and the upper surface of the first conductive layer remaining after etching back is lower than the upper surface of the n-type semiconductor layer;

[0010] performing inclined ion implantation to both sides of the first grooves to form n-type source regions in the p-type body regions;

[0011] forming a second insulating layer and etching back, side walls on the first conductive layer are formed on both sides of the first trench respectively, the first conductive layer is etched with the first insulating layer and the side walls as masks, and the first conductive layer remaining after etching forms a first gate on both sides of the first trench respectively;

[0012] The gate dielectric layer and the n-type semiconductor layer are etched with the first insulating layer and the side walls as masks, and a second trench is formed in the n-type semiconductor layer;

[0013] The formed structure is covered with a third insulating layer, and then a second conductive layer is formed and etched back, and the second conductive layer remaining after etching forms a second gate in the second trench.

[0014] Optionally, the bottom of the second trench is lower than the bottom of the n-type charge storage region.

[0015] Optionally, the first insulating layer is silicon oxide, silicon nitride or a mixed layer of silicon oxide and silicon nitride.

[0016] Optionally, the second insulating layer is silicon oxide or silicon nitride.

[0017] Optionally, the third insulating layer is silicon oxide.

[0018] Optionally, an interlayer insulating layer, a source metal and a gate metal are formed on the surface of the n-type semiconductor layer.

[0019] Optionally, the method for manufacturing the IGBT device further comprises: forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer.

[0020] Optionally, the method for manufacturing the IGBT device further comprises: forming a collector metal on the bottom surface of the n-type semiconductor layer.

[0021] Optionally, the second gate extends upward into the first trench.

[0022] Optionally, the channel implant region is n-type or p-type.

[0023] The method for manufacturing the IGBT device provided by the application does not need photolithography process in the manufacturing processes of the channel implant region, the p-type body region, the n-type source region, the first gate, the second trench and the second gate after forming the first trench through one-time photolithography process, thereby reducing the number of photolithography processes in the manufacturing process of the IGBT device and effectively reducing the manufacturing cost of the IGBT device. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the example embodiments of the present application, the following briefly introduces the drawings needed in the description of the embodiments.

[0025] Figures 1 to 9 is a schematic diagram of the main structure in the manufacturing process of one embodiment of the manufacturing method of the IGBT device provided by the present application. DETAILED DESCRIPTION

[0026] The technical solutions of the present application will be described in detail below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the terms such as "have", "contain" and "include" used in the present application do not exclude the presence or addition of one or more other elements or combinations thereof. At the same time, in order to clearly illustrate the specific embodiments of the present application, the thickness of the layers and regions described in the drawings of the present application is exaggerated, and the size of the listed figures does not represent the actual size.

[0027] Figures 1 to 9 is a schematic diagram of the main structure in the manufacturing process of one embodiment of the manufacturing method of the IGBT device provided by the present application.

[0028] First, as shown in Figure 1 , a first insulating layer 41 is formed on the provided n-type semiconductor layer 20, and the first insulating layer 41 is usually silicon oxide, silicon nitride or a mixed layer of silicon oxide and silicon nitride. The position of the first trench is defined by a photolithography process, and then the first insulating layer 41 and the n-type semiconductor layer 20 are etched to form a plurality of first trenches 51 arranged in sequence in the n-type semiconductor layer 20. The material of the n-type semiconductor layer 20 is usually silicon. The number of the first trenches 51 is determined by the specific device design, and only two first trenches 51 are exemplarily shown in the embodiment of the present application.

[0029] Next, as shown in Figure 2As shown, inclined ion implantation is performed to one side of the first trench 51 to form a channel implant region 42 on the one side of the first trench 51 in the n-type semiconductor layer 20. The channel implant region 42 can be of n-type or p-type. The channel implant region 42 is used to adjust the doping concentration of a channel region in a subsequently formed p-type body region. When the channel implant region 42 is of n-type, the p-type ion doping concentration of the channel region in the subsequently formed p-type body region can be reduced, which lowers the threshold voltage at which the channel region is turned on. When the channel implant region 42 is of p-type, the doping concentration of the channel region in the subsequently formed p-type body region can be increased, which raises the threshold voltage at which the channel region is turned on. Forming the channel implant region 42 on only one side of the first trench 51 allows the p-type doping concentration of the channel region at the two sidewalls of the first trench 51 to be different, i.e. the IGBT device has different threshold voltages Vth, which in turn reduces the off-state loss of the IGBT device.

[0030] Next, as shown in FIG. 4B, vertical ion implantation is performed to form an n-type charge storage region 22 under the first trench 51 in the n-type semiconductor layer 20. Figure 3 Next, as shown in FIG. 4C, inclined ion implantation is performed to both sides of the first trench 51 to form a p-type body region 21 on both sides of the first trench 51 in the n-type semiconductor layer 20.

[0031] Next, as shown in FIG. 4D, vertical ion implantation is performed to form an n-type charge storage region 22 under the first trench 51 in the n-type semiconductor layer 20. Figure 4 Next, as shown in FIG. 4E, a gate dielectric layer 23 is formed on the surface of the first trench, which is usually formed by a thermal oxidation process. Then a first conductive layer 24 is formed and etched back, and the upper surface of the remaining first conductive layer 24 is lower than the upper surface of the n-type semiconductor layer 20, which makes it easier to form the n-type source region later.

[0032] Figure 5 Next, as shown in FIG. 4F, inclined ion implantation is performed to both sides of the first trench to form an n-type source region 25 in the p-type body region 21. In this way, the n-type source region 25 is formed without a separate photolithography process.

[0033] Next, as shown in FIG. 4G, inclined ion implantation is performed to both sides of the first trench to form an n-type source region 25 in the p-type body region 21. In this way, the n-type source region 25 is formed without a separate photolithography process. Figure 6 Next, as shown in FIG. 4H, inclined ion implantation is performed to both sides of the first trench to form an n-type source region 25 in the p-type body region 21. In this way, the n-type source region 25 is formed without a separate photolithography process.

[0034] Figure 7 ​​As shown, a second insulating layer is formed and etched back to form sidewall spacers 26 on both sides of the first trench on the first conductive layer. The first conductive layer is then etched using the first insulating layer 41 and the sidewall spacers 26 as masks. The remaining first conductive layer after etching forms first gates 27 on both sides of the first trench. The first gates 27 are formed using a self-aligned process, and no separate photolithography process is required. The second insulating layer can be silicon oxide or silicon nitride.

[0035] Next, if Figure 8 As shown, the gate dielectric layer and the n-type semiconductor layer 20 are etched using the first insulating layer 41 and the sidewall spacer 26 as masks to form second trenches 52 in the n-type semiconductor layer 20. The bottom of the optional second trenches 52 can be lower than the bottom of the n-type charge storage region 22, so that the n-type charge storage region 22 is located between adjacent second trenches 52.

[0036] Next, if Figure 9 As shown, a third insulating layer 28 is formed to cover the formed structure, and then a second conductive layer is formed and etched back. The remaining second conductive layer after etching forms a second gate 29 in the second trench. Optionally, the second gate 29 extends upward into the first trench. The third insulating layer 28 is typically silicon oxide.

[0037] Finally, an IGBT device can be formed through conventional processes, including: forming an interlayer insulating layer, a source metal, and a gate metal on the surface of the n-type semiconductor layer; forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer; and forming a collector metal on the bottom surface of the n-type semiconductor layer. These processes are conventional manufacturing processes in the industry and will not be described in detail in the embodiments of the present invention.

[0038] The above specific implementation methods and examples are specific support for the technical ideas of the present invention and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing an IGBT device, characterized in that: include: forming a first insulating layer on the provided n-type semiconductor layer, etching the first insulating layer and the n-type semiconductor layer to form a plurality of first trenches in the n-type semiconductor layer; Performing an inclined ion implantation toward one side of the first trench to form a channel implantation region located on one side of the first trench in the n-type semiconductor layer; Performing inclined ion implantation on both sides of the first trench to form p-type body regions located on both sides of the first trench in the n-type semiconductor layer; Performing vertical ion implantation to form an n-type charge storage region located below the first trench in the n-type semiconductor layer; forming a gate dielectric layer on the surface of the first trench, and then forming a first conductive layer and etching back the first conductive layer, wherein the upper surface of the remaining first conductive layer after etching back is lower than the upper surface of the n-type semiconductor layer; Performing inclined ion implantation on both sides of the first trench to form an n-type source region in the p-type body region; forming a second insulating layer and etching back the layer, forming sidewalls on both sides of the first trench and located above the first conductive layer, etching the first conductive layer using the first insulating layer and the sidewalls as masks, and forming first gates on both sides of the first trench with the remaining first conductive layer after etching; Etching the gate dielectric layer and the n-type semiconductor layer using the first insulating layer and the sidewall spacer as masks to form a second trench in the n-type semiconductor layer; A third insulating layer is formed to cover the formed structure, and then a second conductive layer is formed and etched back. The remaining second conductive layer after etching forms a second gate in the second trench.

2. The method for manufacturing an IGBT device according to claim 1, wherein: The bottom of the second trench is lower than the bottom of the n-type charge storage region.

3. The method for manufacturing an IGBT device according to claim 1, wherein: The first insulating layer is silicon oxide, silicon nitride, or a mixed layer of silicon oxide and silicon nitride.

4. The method for manufacturing an IGBT device according to claim 1, wherein: The second insulating layer is silicon oxide or silicon nitride.

5. The method for manufacturing an IGBT device according to claim 1, wherein: The third insulating layer is silicon oxide.

6. The method for manufacturing an IGBT device according to claim 1, wherein: Also includes: An interlayer insulating layer, a source metal and a gate metal are formed on the surface of the n-type semiconductor layer.

7. The method for manufacturing an IGBT device according to claim 1, wherein: Also includes: An n-type field stop region and a p-type collector region are formed at the bottom of the n-type semiconductor layer.

8. The method for manufacturing an IGBT device according to claim 7, wherein: Also includes: A collector metal is formed on the bottom surface of the n-type semiconductor layer.

9. The method for manufacturing an IGBT device according to claim 1, wherein: The second gate extends upward into the first trench.

10. The method for manufacturing an IGBT device according to claim 1, wherein: The doping type of the channel injection region is n-type or p-type.

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