Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. In one embodiment, after a gate replacement process in which a polysilicon dummy gate structure of a semiconductor device is replaced by a metal gate structure, a CMODE structure may be formed in the semiconductor device by continuously diffusing a metal on edge (CMODE). The CMODE process described herein includes removing a portion of the metal gate structure (compared to removing a portion of the polysilicon dummy gate structure) to enable CMODE structures to be formed in recesses created after removing the portion of the metal gate structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor device manufacturing advances and technology process node sizes shrink, transistors may be affected by short channel effects (SCE), such as hot carrier degradation, barrier degradation, and quantum confinement. In addition, as the gate length of transistors shrinks to achieve smaller technology nodes, the source / drain (S / D) electron tunneling effect increases, which in turn increases the transistor's off current (the current flowing through the transistor channel when the transistor is off). Silicon (Si) / silicon germanium (SiGe) nanostructured transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidate devices configured to overcome short channel effects in smaller technology nodes. Nanostructured transistors are highly efficient structures that can reduce SCE and enhance carrier mobility relative to other types of transistors. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a plurality of nanostructure layers above a semiconductor substrate along a direction perpendicular to the semiconductor substrate, and the nanostructure layers include a plurality of sacrificial layers alternating with a plurality of channel layers; forming a dummy gate structure above the nanostructure layers; removing a portion of the nanostructure layers to form one or more grooves adjacent to one or more sides of the dummy gate structure; forming one or more source / drain regions in the one or more grooves; after forming the one or more source / drain regions, replacing the dummy gate structure and a plurality of portions of the sacrificial layer below the dummy gate structure with a metal gate structure, and the metal gate structure surrounds at least three sides of the channel layer; after replacing the dummy gate structure and a portion of the sacrificial layer below the dummy gate structure with the metal gate structure, forming an active region isolation groove, and forming the active region isolation groove includes removing: a portion of the metal gate structure, a plurality of portions of the channel layer surrounded by the metal gate structure, and a platform region below a portion of the channel layer and extending above the semiconductor substrate; and forming an active region isolation structure in the active region isolation groove.

[0004] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a plurality of nanostructure layers above a semiconductor substrate along a direction perpendicular to the semiconductor substrate, wherein the plurality of nanostructure layers include a plurality of sacrificial layers alternating with a plurality of channel layers; forming a plurality of dummy gate structures above the plurality of nanostructure layers; removing portions of the plurality of nanostructure layers to form one or more grooves adjacent to one or more sides of a dummy gate structure among the plurality of dummy gate structures; forming one or more source / drain regions in the one or more grooves; replacing the dummy gate structures and portions of the sacrificial layers below the dummy gate structures with a plurality of metal gate structures after forming the one or more source / drain regions, wherein the plurality of metal gate structures surround at least three sides of the channel layer; forming a plurality of gate isolation structures spanning the metal gate structures after replacing the dummy gate structures and portions of the sacrificial layers below the dummy gate structures with the metal gate structures; removing portions of a metal gate structure of the plurality of metal gate structures, portions of the channel layer surrounded by the metal gate structures, and a platform region below portions of the channel layer and extending above the semiconductor substrate between the gate isolation structures to form an active region isolation groove; and forming an active region isolation structure in the active region isolation groove between the gate isolation structures.

[0005] Some embodiments of the present disclosure provide a semiconductor device, and the semiconductor device includes a plurality of first nanostructure channels above a first platform region and extending above a semiconductor substrate, and the first nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate; includes a plurality of second nanostructure channels arranged above a second platform region and extending above the semiconductor substrate, and the second nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate; includes a first metal gate structure surrounding each of the first nanostructure channels; includes a second metal gate structure surrounding each of the second nanostructure channels; includes a gate isolation structure arranged between the first metal gate structure and the second metal gate structure; and includes an active region isolation structure arranged between the gate isolation structure and the second metal gate structure, and the dielectric liner of the active region isolation structure is directly included on the sidewall of the gate isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A schematic diagram of an exemplary environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of an exemplary semiconductor device described in the present disclosure;

[0009] Figure 3A and Figure 3B is a schematic diagram of an exemplary embodiment of a fin formation process described in the present disclosure;

[0010] Figure 4A and Figure 4B is a schematic diagram of an exemplary embodiment of a shallow trench isolation (STI) process described in the present disclosure;

[0011] Figure 5 and Figure 6 is a schematic diagram of an exemplary dummy gate structure formation process described in the present disclosure;

[0012] FIG. 7A to FIG. 7D is a schematic diagram of an exemplary embodiment of a source / drain recess forming process and an inner spacer forming process described in the present disclosure;

[0013] Figure 8 is a schematic diagram of an exemplary embodiment of a source / drain region formation process described in the present disclosure;

[0014] Fig. 9 is a schematic diagram of an exemplary embodiment of a process for forming an interlayer dielectric layer described in the present disclosure;

[0015] FIG. 10A to FIG. 10C is a schematic diagram of an exemplary embodiment of a replacement gate process described in the present disclosure;

[0016] FIG. 11A to FIG. 11I is a schematic diagram of an exemplary embodiment of forming an active region isolation structure described in the present disclosure;

[0017] Fig. 12A and Fig. 12B is a schematic diagram of an exemplary embodiment of a semiconductor device described in the present disclosure;

[0018] Fig.13 is a schematic diagram of exemplary components of one or more devices described in the present disclosure;

[0019] Fig.14 and Fig.15 is a flow chart of an exemplary process associated with forming the semiconductor device described in the present disclosure; and

[0020] FIG. 16A to FIG. 16E FIG. 4 is a schematic diagram of an exemplary embodiment of forming an active region isolation structure described in the present disclosure.

[0021]

Explanation of symbols

[0022] 100: Environment

[0023] 102,104,106,108,110,112:Semiconductor processing tools

[0024] 102:Deposition tools

[0025] 104:Exposure Tools

[0026] 106: Development Tools

[0027] 108: Etching tools

[0028] 110: Flattening tool

[0029] 112:Electroplating tools

[0030] 114: Wafer / bare crystal transport tool

[0031] 200:Semiconductor devices

[0032] 205:Semiconductor substrate

[0033] 210: Platform area

[0034] 210a: First platform area

[0035] 210b: Second platform area

[0036] 215: Shallow trench isolation area / STI area

[0037] 220: Nanostructured Channels

[0038] 220a: first nanostructure channel

[0039] 220b: Second nanostructure channel

[0040] 220c: Nanostructured channels

[0041] 225: Source / drain region

[0042] 230: Buffer

[0043] 235: Covering layer

[0044] 240: Gate structure

[0045] 240a: first gate structure / gate structure

[0046] 240b: second gate structure / gate structure

[0047] 245:Internal spacer

[0048] 250: Interlayer dielectric layer / ILD layer

[0049] 300, 400, 500, 600: Exemplary Embodiments

[0050] 305: Layer Stacking

[0051] 310: First floor

[0052] 315: Second floor

[0053] 320: Hard mask layer

[0054] 325: Covering layer

[0055] 330: Oxide layer

[0056] 335: Nitride layer

[0057] 340: Part

[0058] 345,345a,345b: Fin structure

[0059] 405:Padding

[0060] 410: Dielectric layer

[0061] 505: Virtual gate structure

[0062] 510: Gate electrode layer

[0063] 515: Hard mask layer

[0064] 520: Spacer layer

[0065] 525: Gate dielectric layer

[0066] 700, 800, 900: Exemplary Embodiments

[0067] 705: Source / drain groove

[0068] 710: Cavity

[0069] 715: Insulation layer

[0070] 1000, 1100, 1200: Exemplary Embodiment

[0071] 1003: Opening

[0072] 1005: Opening

[0073] 1010: High-k dielectric liner

[0074] 1105: Hard mask layer

[0075] 1110: Gate isolation structure

[0076] 1110a: first gate isolation structure / gate isolation structure

[0077] 1110b: second gate isolation structure / gate isolation structure

[0078] 1115: Active area isolation structure

[0079] 1120: Patterned stack

[0080] 1125: Bottom

[0081] 1130: Middle layer

[0082] 1135: Top floor

[0083] 1140: Pattern

[0084] 1145: Active area isolation groove

[0085] 1150: Groove extension

[0086] 1155: Dielectric liner

[0087] 1160: Dielectric layer

[0088] 1300: Equipment

[0089] 1310: Bus

[0090] 1320: Processor

[0091] 1330:Memory

[0092] 1340: Input component

[0093] 1350: Output component

[0094] 1360: Communication Components

[0095] 1400,1500: Crafts

[0096] 1410, 1420, 1430, 1440, 1450, 1460, 1470: Steps 1510, 1520, 1530, 1540, 1550, 1560, 1570, 1580: Step 1600: Exemplary Embodiment

[0097] 1605,1610: Segmentation

[0098] AA,BB,CC: Section lines

[0099] D1,D2,D3,D4,D5,D6: Dimensions

[0100] D7,D8,D9,D10,D11,D12: Dimensions

[0101] X,Y,Z: Direction DETAILED DESCRIPTION

[0102] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0103] Additionally, for ease of description, spatially relative terms (e.g., "underlying," "beneath," "bottom," "overlying," "upper," and the like) may be used in the present disclosure to describe the relationship of one component or feature to another component or feature as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure should be interpreted accordingly.

[0104] A continuous polysilicon on diffusion edge (CPODE) process may be performed to remove a portion of a polysilicon dummy gate structure and replace the portion of the polysilicon dummy gate structure with a CPODE structure. The CPODE structure includes an isolation structure formed in a recess behind the portion of the polysilicon dummy gate structure. The CPODE structure may extend to a silicon fin below the polysilicon dummy gate structure. The formation of the CPODE structure may provide isolation (e.g., electrical isolation and / or physical isolation) between regions of a semiconductor device, such as between device regions of a semiconductor device, between active regions of a semiconductor device, and / or between transistors of a semiconductor device.

[0105] In some embodiments, the CPODE process may cause one or more layout dependent effects (LDE) in the semiconductor device. For example, the portion of the polysilicon dummy gate structure removed to form the CPODE structure may be adjacent to one or more source / drain regions of a transistor of the semiconductor device, and the etching process to remove the portion of the polysilicon dummy gate structure may cause critical dimension (CD) loading and epitaxial (EPI) damage to the source / drain region. In another example, depth loading may occur during the etching process, wherein an insufficient amount of silicon fins is removed to form the CPODE structure to a sufficient depth to provide electrical isolation between the source / drain regions. This may result in an increased likelihood of leakage between the source / drain regions (e.g., through the silicon fins and / or through the underlying substrate). In another example, the CPODE structure may cause gate deformation of the polysilicon dummy gate structure and / or other polysilicon dummy gate structures. This may result in a threshold voltage (Vt) shift and a change in the threshold voltage of the transistor of the semiconductor device. The variation in threshold voltage may result in variation in transistor switching speed, variation in power consumption, and / or degradation in device performance of the transistor of the semiconductor device.

[0106] Some embodiments described herein provide a continuous metal on diffusion edge (CMODE) process, wherein a polysilicon dummy gate structure of a semiconductor device is replaced by a metal gate structure after a replacement gate process (RPG) is performed to form a CMODE structure. Thus, the CMODE process described herein includes removing a portion of the metal gate structure (as opposed to removing a portion of the polysilicon dummy gate structure) to enable the CMODE structure to be formed in a recess created by removing the portion of the metal gate structure.

[0107] The material used for the metal gate structure of the semiconductor device can be stronger and can better withstand the stress and strain of etching and forming the CMODE structure of the semiconductor device. Therefore, the CMODE process described in the present disclosure can reduce the possibility of stress loss in the source / drain region on the opposite side of the CMODE structure, can reduce the possibility of deep loading in the semiconductor, and / or can reduce the possibility of gate deformation in the semiconductor device, etc. Therefore, the CMODE process described in the present disclosure can reduce the possibility of stress release to the source / drain region, can reduce leakage between the source / drain region, and / or can reduce the possibility of threshold voltage shift of the transistor of the semiconductor device. The reduction in the possibility of threshold voltage shift can provide more uniform and / or faster switching speeds for transistors, provide more uniform and / or lower power consumption for transistors, and / or improve device performance for transistors.

[0108] Figure 1 1 is a schematic diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the exemplary environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or other types of semiconductor processing tools. The tools included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor processing plant, a semiconductor processing equipment, and / or a manufacturing equipment.

[0109] The deposition tool 102 is a semiconductor processing tool, and the deposition tool 102 includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, deposition tool 102 includes an epitaxial tool, and the epitaxial tool is configured to form layers and / or regions of a device formed by epitaxial growth. In some embodiments, exemplary environment 100 includes multiple types of deposition tools 102.

[0110] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, etc.), an x-ray source, and / or an electron beam (e-beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0111] The developing tool 106 is a semiconductor processing tool that can develop the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer by the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portion of the photoresist layer.

[0112] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool and / or a dry etching tool, etc. In some embodiments, the etching tool 108 includes a reaction chamber that can be filled with an etchant, and the substrate is placed in the reaction chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 uses plasma etching or plasma assisted etching to etch one or more portions of the substrate, and such etching may involve using an ionized gas to etch the one or more portions isotropically or directionally. In some embodiments, the etching tool 108 includes a plasma-based plasma stripper (asher) to remove photoresist material and / or another material.

[0113] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that grind or planarize layers or surfaces of deposited or plated materials. The planarization tool 110 can combine chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or planarize the surface of a semiconductor device. The planarization tool 110 can be combined with a grinding pad and a wafer retaining ring (e.g., typically having a larger diameter than the semiconductor device), and use nano-abrasives and corrosive chemical polishing fluid. The grinding pad and the semiconductor device can be pressed down together by a dynamic grinding head and maintained in position by a wafer retaining ring. The dynamic grinding head can be rotated by different rotation axes to remove material and planarize any irregular morphology of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0114] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver and / or tin-lead, etc.) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or the like.

[0115] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or other types of devices. The wafer / die transporter 114 is configured to transfer substrates and / or semiconductor devices between semiconductor processing tools 102-112, to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or to transfer substrates and / or semiconductor devices to and from other locations, such as wafer racks and / or storage spaces. In some embodiments, the wafer / die transporter 114 can be configured with a program device that moves along a specific path, and / or a program device that can operate semi-autonomously or autonomously. In some embodiments, the exemplary environment 100 includes multiple wafer / die transporters 114.

[0116] For example, the wafer / die transporter 114 may be included in a cluster tool (including multiple processing chambers) and configured to transfer substrates and / or semiconductor devices between multiple processing chambers, transfer substrates and / or semiconductor devices between a processing chamber and a buffer, transfer substrates and / or semiconductor devices between a processing chamber and an interface tool (e.g., an Equipment Front End Module (EFEM)), and / or transfer substrates and / or semiconductor devices between a processing chamber and a Front Opening Unified Pod (FOUP), etc. In some embodiments, the wafer / die transporter 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning chamber (e.g., for cleaning or removing oxides, oxidation contaminants or byproducts from substrates and / or semiconductor devices, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices), and multiple types of deposition chambers (e.g., chambers for depositing different types of materials, chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 114 is configured to transfer substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between processing chambers and / or between process operations, as described herein.

[0117] As described herein, semiconductor processing tools 102-112 may combine multiple operations to form one or more portions of a nanostructure transistor. In some embodiments, the combination of multiple operations includes forming multiple nanostructure layers above a semiconductor substrate in a direction perpendicular to the semiconductor substrate, and the multiple nanostructure layers include multiple sacrificial layers alternating with multiple channel layers; forming a dummy gate structure above the multiple nanostructure layers; removing portions of the multiple nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure; forming one or more source / drain regions in the one or more recesses; replacing the dummy gate structure and multiple portions of the sacrificial layers below the dummy gate structure with a metal gate structure after forming the one or more source / drain regions, wherein the metal gate structure surrounds at least three sides of the channel layer; after replacing the dummy gate structure and multiple portions of the sacrificial layers below the dummy gate structure with the metal gate structure, removing a portion of the metal gate structure, a portion of the metal gate structure surrounded by the channel layer, and a terrace region below the multiple portions of the channel layer and extending above the semiconductor substrate to form an active region isolation recess gate structure; and / or forming an active region isolation structure in the active region isolation recess, etc.

[0118] In some embodiments, a combination of multiple operations includes forming multiple nanostructure layers above a semiconductor substrate along a direction perpendicular to the semiconductor substrate, wherein the multiple nanostructure layers include multiple sacrificial layers alternating with multiple channel layers; forming multiple dummy gate structures above the multiple nanostructure layers; removing portions of the multiple nanostructure layers to form one or more grooves adjacent to one or more sides of a dummy gate structure in the multiple dummy gate structures; forming one or more source / drain regions in the one or more grooves; replacing the multiple dummy gate structures and multiple portions of the sacrificial layers located below the multiple dummy gate structures with multiple metal gate structures after forming the one or more source / drain regions, wherein the multiple metal gate structures surround at least three sides of the channel layer; forming a gate isolation structure spanning the multiple metal gate structures after replacing the dummy gate structures and multiple portions of the sacrificial layers located below the dummy gate structures with the metal gate structures; removing a portion of the metal gate structures in the multiple metal gate structures located between the gate isolation structures, a portion of the channel layer surrounded by the metal gate structures, and a portion located below the channel layer and extending to a platform region above the semiconductor substrate to form an active region isolation groove; and / or forming an active region isolation structure in the active region isolation groove between the gate isolation structures.

[0119] In some embodiments, combining multiple operations includes combining FIG. 3A to FIG. 11I One or more operations of one or more instructions in .

[0120] As one or more examples, Figure 1 The number and arrangement of devices are shown. In practice, there may be more Figure 1 Additional devices, fewer devices, different devices, or devices in a different configuration as shown in . In addition, Figure 1 Two or more devices shown in FIG. 1 may be combined in a single device or as shown in FIG. Figure 1 The single device shown is implemented as multiple distributed devices. Additionally or alternatively, one or more functions of one set of devices (eg, one or more devices) of the exemplary environment 100 may be performed by another set of devices of the exemplary environment 100.

[0121] Figure 2 is a schematic diagram of an exemplary semiconductor device 200 described in the present disclosure. The semiconductor device 200 includes one or more transistors. The one or more transistors may include nanostructure transistors, such as nanowire transistors, nanosheet transistors, gate all around (GAA) transistors, multi-bridge channel field effect transistors, nanoribbon transistors, and / or other types of nanostructure transistors. The semiconductor device 200 may include Figure 2 For example, the semiconductor device 200 may include additional layers and / or a bare die formed on the semiconductor device 200. Figure 2 Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of an electronic device or integrated circuit (IC), wherein the electronic device or integrated circuit includes, for example, Figure 2 A semiconductor device 200 is shown. FIG. 3A to FIG. 12B One or more of may include Figure 2 The cross-sectional views of various portions of the semiconductor device 200 are shown, corresponding to various process stages of forming a nanostructure transistor of the semiconductor device 200 .

[0122] The semiconductor device 200 includes a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon (Si) substrate, a substrate formed of a silicon material, and a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates). The semiconductor substrate 205 may include various layers (including a conductive layer or an insulating layer formed on the semiconductor substrate). The semiconductor substrate 205 may include a compound semiconductor and / or an alloy semiconductor. The semiconductor substrate 205 may include various doping profiles to meet one or more design parameters. For example, multiple regions may be designed on the semiconductor substrate 205 to form different doping profiles (e.g., n-well, p-well) according to different device types (e.g., p-type metal-oxide semiconductor (PMOS) nanostructure transistor, n-type metal-oxide semiconductor (NMOS) nanostructure transistor). Suitable doping may include ion implantation and / or diffusion processes of dopants. In addition, the semiconductor substrate 205 may include an epitaxial layer (epi layer), may enhance performance through strain, and / or may have other suitable enhancements. The semiconductor substrate 205 may include a portion of a semiconductor wafer formed on other semiconductor devices.

[0123] The mesa region 210 is included above (and / or extends above) the semiconductor substrate 205. The mesa region 210 provides structures for forming nanostructures of the semiconductor device 200, such as nanostructure channels, nanostructure gate portions surrounding each nanostructure channel, and / or sacrificial nanostructures, etc. In some embodiments, one or more mesa regions 210 are formed in and / or formed by fin structures (e.g., silicon fin structures) in the semiconductor substrate 205. The mesa region 210 may include the same material as the semiconductor substrate and be formed by the semiconductor substrate 205. In some embodiments, the mesa region 210 is doped to form different types of nanostructure transistors, such as p-type nanostructure transistors and / or n-type nanostructure transistors. In some embodiments, the terrace region 210 includes a silicon (Si) material or another elemental semiconductor material (e.g., germanium (Ge). In some embodiments, the terrace region 210 includes an alloy semiconductor material, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (AlInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0124] The platform region 210 is manufactured by appropriate semiconductor process technology, such as masking, lithography and / or etching processes. In one example, a portion of the semiconductor substrate 205 can be etched to form a groove in the semiconductor substrate 205 to form a fin structure. Then, the groove can be filled with an isolation material, and the isolation material can be recessed or etched back to form a shallow trench isolation (STI) region 215 above the semiconductor substrate 205 and between the fin structures. Source / drain grooves can be formed in the fin structure, so that the platform region 210 is formed between the source / drain grooves. In addition, the STI region 215 and / or the platform region 210 can use other manufacturing technologies.

[0125] The STI region 215 may electrically isolate adjacent fin structures and may provide a layer for forming other layers and / or structures of the semiconductor device 200. The STI region 215 may include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric material and / or other suitable insulating materials. The STI region 215 may include a multi-layer structure, for example, having one or more liner layers.

[0126] The semiconductor device 200 includes a plurality of nanostructure channels 220, and the nanostructure channels 220 extend between source / drain regions 225 and are electrically coupled to the source / drain regions 225. The source / drain regions 225 may refer to a source or a drain individually or collectively depending on the context. The nanostructure channels 220 are arranged along a direction substantially perpendicular to the semiconductor substrate 205. That is, the nanostructure channels 220 are vertically arranged or stacked above the semiconductor substrate 205.

[0127] The nanostructure channel 220 includes a silicon-based nanostructure (e.g., a nanosheet or a nanowire, etc.) as a semiconductor channel of a nanostructure transistor of the semiconductor device 200. In some embodiments, the nanostructure channel 220 may include silicon germanium (SiGe) or another silicon-based material. The source / drain region 225 includes silicon (Si) with one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), etc.), an n-type material (e.g., phosphorus (P) or arsenic (As), etc.) and / or another type of dopant, etc. Therefore, the semiconductor device 200 may include a p-type metal oxide semiconductor (PMOS) nanostructure transistor including a p-type source / drain region 225, an n-type metal oxide semiconductor (NMOS) nanostructure transistor including an n-type source / drain region 225, and / or other types of nanostructure transistors.

[0128] In some embodiments, the buffer region 230 is included below the source / drain region 225 and between the source / drain region 225 and the fin structure above the semiconductor substrate 205. The buffer region 230 can provide isolation between the source / drain region 225 and the mesa region 210. By including the buffer region 230, electrons can be reduced, minimized, and / or prevented from passing through the mesa region 210 (e.g., not passing through the nanostructure channel 220, thereby reducing leakage), and / or, dopants can be reduced, minimized, and / or prevented from entering the mesa region 210 from the source / drain region 225 (thus reducing short channel effects).

[0129] A capping layer 235 may be included above and / or on the source / drain regions 225. The capping layer 235 may include silicon, silicon germanium, doped silicon, doped silicon germanium, and / or other materials. The capping layer 235 may reduce dopant diffusion and protect the source / drain regions 225 during semiconductor process operations of the semiconductor device 200 before contact formation. In addition, the capping layer 235 may facilitate the formation of a metal-semiconductor (e.g., silicide) alloy.

[0130] At least a subset of the nanostructure channels 220 extend through one or more gate structures 240. The gate structures 240 may be formed of one or more metal materials, one or more high dielectric constant (high-k) materials, and / or one or more other types of materials. In some embodiments, a dummy gate structure (e.g., a polysilicon (PO) gate structure or other type of gate structure) is formed in the location of the gate structure 240 (e.g., before forming the gate structure 240), so that one or more other layers and / or structures of the semiconductor device 200 are formed before forming the gate structure 240. In this way, damage to the gate structure 240 caused by forming one or more layers and / or structures is reduced and / or prevented. A replacement gate process (RGP) is then performed to remove the dummy gate structure and replace the dummy gate structure with the gate structure 240 (e.g., the replacement gate structure).

[0131] Further Figure 2 As shown, portions of the gate structure 240 are formed between pairs of nanostructure channels 220 in an alternating vertical arrangement. In other words, the semiconductor device 200 includes one or more nanostructure channels 220 and portions of the gate structure 240 that are vertically alternately stacked. Figure 2 As shown. Accordingly, the gate structure 240 surrounds multiple sides of the corresponding nanostructure channel 220, thereby increasing the control of the nanostructure channel 220, increasing the driving current of the nanostructure transistor of the semiconductor device 200, and reducing the short channel effect (SCE) of the nanostructure transistor of the semiconductor device 200.

[0132] Portions of the source / drain regions 225 and gate structures 240 may be shared between two or more nanoscale transistors of the semiconductor device 200. In these embodiments, one or more source / drain regions 225 and gate structures 240 may be connected or coupled to multiple nanostructure channels 220, such as Figure 2 As shown, the plurality of nanostructure channels 220 can be controlled by a single gate structure 240 and a pair of source / drain regions 225 .

[0133] An inner spacer (InSP) 245 may be included between the source / drain region 225 and the adjacent gate structure 240. Specifically, the inner spacer 245 may be included between the source / drain region 225 and a portion of the gate structure 240 surrounding the plurality of nanostructure channels 220. The inner spacer 245 is included on an end portion of a portion of the gate structure 240 surrounding the plurality of nanostructure channels 220. The inner spacer 245 is included in a cavity formed between the end portions. By means of the inner spacer 245, parasitic capacitance may be reduced and the source / drain region 225 may be protected from being etched during a nanosheet release operation to remove sacrificial nanosheets between the nanostructure channels 220. The inner spacer 245 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and / or other dielectric materials.

[0134] The semiconductor device 200 may further include an interlayer dielectric (ILD) layer 250 located above the STI region 215. The ILD layer 250 may be referred to as an ILD0 layer. The ILD layer 250 surrounds the gate structure 240 to provide electrical isolation and / or insulation between the gate structure 240 and / or the source / drain region 225. A conductive structure (e.g., a contact and / or an interconnect structure) may be formed through the ILD layer 250 and reach the source / drain region 225 and the gate structure 240 to control the source / drain region 225 and the gate structure 240.

[0135] As mentioned above, Figure 2 As one example, other examples may be related to Figure 2 Said differently.

[0136] Figure 3A and Figure 3B is a schematic diagram of an exemplary embodiment 300 of a fin formation process described in the present disclosure. Exemplary embodiment 300 includes an example of forming a fin structure in semiconductor device 200 or a portion of semiconductor device 200. Semiconductor device 200 may include Figure 3A and Figure 3B One or more additional devices, structures and / or layers not shown. The semiconductor device 200 may include a Figure 3A and Figure 3B Additional layers and / or dies on layers above and / or below the portion of the semiconductor device 200 are shown. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of an electronic device including the semiconductor device 200.

[0137] Figure 3A A perspective view of the semiconductor device 200 and a cross-sectional view along the AA cross-sectional line in the perspective view are shown. Figure 3A , a process for forming the semiconductor device 200 with respect to the semiconductor substrate 205. A layer stack 305 is formed on the semiconductor substrate 205. The layer stack 305 may be referred to as a superlattice. In some embodiments, before forming the layer stack 305, one or more processes related to the semiconductor substrate 205 are performed, for example, an anti-punch through (APT) implantation process may be performed, i.e., an APT implantation process may be performed in one or more regions on the semiconductor substrate 205 where the nanostructure channel 220 will be formed. The APT implantation process is performed, for example, to reduce and / or prevent punch-through or unnecessary diffusion into the semiconductor substrate 205.

[0138] The layer stack 305 includes a plurality of alternating layers arranged along a direction substantially perpendicular to the semiconductor substrate 205. For example, the layer stack 305 includes vertically alternating layers of a first layer 310 and a second layer 315 above the semiconductor substrate 205. Figure 3A The number of first layers 310 and second layers 315 shown is only an example, and other numbers of first layers 310 and second layers 315 are also within the scope of the present disclosure. In some embodiments, the thickness of the first layer 310 and the second layer 315 formed are different. For example, the thickness formed by the second layer 315 can be greater than the thickness formed by the first layer 310. In some embodiments, the thickness formed by the first layer 310 (or a subset of the first layer 310) is about 4 nanometers to about 7 nanometers. In some embodiments, the thickness formed by the second layer 315 (or a subset of the second layer 315) is about 8 nanometers to about 12 nanometers. However, other thicknesses of the first layer 310 and the second layer 315 are also within the scope of the present disclosure.

[0139] The first layer 310 includes a first material composition, and the second layer 315 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As one example, the first layer 310 may include silicon germanium (SiGe), and the second layer 315 may include silicon (Si). In some embodiments, the first material composition and the second material composition have different oxidation rates and / or etching selectivities.

[0140] As described in the present disclosure, the second layer 315 can be processed to form a nanostructure channel 220 (formed in a subsequent step) configured as a nanostructure transistor of the semiconductor device 200. The first layer 310 will eventually be removed and configured to serve as a sacrificial nanostructure and to define a vertical distance between adjacent nanostructure channels 220 in a gate structure 240 of the subsequently formed semiconductor device 200. Therefore, the first layer 310 is referred to as a sacrificial layer in the present disclosure, and the second layer 315 can be referred to as a channel layer.

[0141] The deposition tool 102 deposits and / or grows alternating layers of the layer stack 305 on the semiconductor substrate 205 to include nanostructures (e.g., nanosheets). For example, the deposition tool 102 grows the alternating layers by epitaxial growth. However, other processes may also be used to form the alternating layers of the layer stack 305. The epitaxial growth of the alternating layers of the layer stack 305 may be performed by a molecular beam epitaxy (MBE) process, metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers (e.g., the second layer 315) include the same material as the material of the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 include a material different from the material of the semiconductor substrate 205. As previously described, in some embodiments, the first layer 310 includes an epitaxially grown silicon germanium (SiGe) layer and the second layer 315 includes an epitaxially grown silicon (Si) layer. Alternatively, the first layer 310 and / or the second layer 315 may include other materials, such as germanium (Ge), compound semiconductor materials (such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (IAs), indium antimonide (InSb)), alloy semiconductors (such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP)) and / or combinations thereof. The material of the first layer 310 and / or the material of the second layer 315 may be selected based on providing different oxidation characteristics, different etching selectivity characteristics and / or other different characteristics.

[0142] Furthermore, if Figure 3AAs shown, deposition tool 102 may form one or more additional layers above and / or on layer stack 305. For example, a hard mask (HM) layer 320 may be formed above and / or on layer stack 305 (e.g., on the topmost second layer 315 of layer stack 305). In another example, a capping layer 325 may be formed above and / or on hard mask layer 320. In yet another example, another hard mask layer including an oxide layer 330 and a nitride layer 335 may be formed above and / or on the capping layer. One or more hard mask (HM) layers 320, 325, and 330 may be used to form one or more structures of semiconductor device 200. Oxide layer 330 may serve as an adhesion layer between layer stack 305 and nitride layer 335, and oxide layer 330 may serve as an etch stop layer for etching nitride layer 335. One or more hard mask layers 320, 325, and 330 may include silicon germanium (SiGe), silicon nitride (Si x N y ), silicon oxide (SiO x ) and / or other materials. The capping layer 325 may include silicon (Si) and / or other materials. In some embodiments, the capping layer 325 is formed of the same material as the semiconductor substrate 205. In some embodiments, one or more additional layers are formed by thermal growth, by CVD, PVD, ALD deposition, and / or by other deposition techniques.

[0143] Figure 3B A perspective view of the semiconductor device 200 and a cross-sectional view along the AA cross-sectional line in the perspective view are shown. Figure 3BAs shown, the layer stack 305 and the semiconductor substrate 205 are etched to remove portions of the layer stack 305 and portions of the semiconductor substrate 205. The portions remaining after the etching process, the portion 340 of the layer stack 305 and the terrace region 210 (also referred to as a silicon terrace or terrace portion) are referred to as a fin structure 345 located above the semiconductor substrate 205 in the semiconductor device 200. The fin structure 345 includes the portion 340 of the layer stack 305 above and / or on the terrace region 210, wherein the terrace region 210 is formed in and / or above the semiconductor substrate 205. The fin structure 345 may be formed by any suitable semiconductor processing technique. For example, the fin structure 345 may be formed by performing one or more lithography processes (including double patterning or multi-patterning processes) in the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108. In general, the double patterning or multi-patterning process combines the lithography process with a self-alignment process, thereby allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct lithography process. For example, a sacrificial layer may be placed over the substrate and patterned using a lithography process, and spacers may be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer may then be removed, and the remaining spacers may be used to pattern the fin structure.

[0144] In some embodiments, deposition tool 102 forms a photoresist layer above and / or on the hard mask layer including oxide layer 330 and nitride layer 335, exposure tool 104 exposes the photoresist layer to radiation (e.g., deep ultraviolet (UV) radiation or extreme ultraviolet (EUV) radiation), performs a post-exposure bake process (e.g., to remove residual solvent from the photoresist layer), and development tool 106 develops the photoresist layer to form a mask element (or pattern) in the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element is performed using an electron beam (e-beam) lithography process. Furthermore, the mask element can be configured to protect portions of semiconductor substrate 205 and portions of layer stack 305 during an etching step, so that portions of semiconductor substrate 205 and portions of layer stack 305 remain unetched to form fin structure 345. Unprotected portions of the substrate and unprotected portions of layer stack 305 are etched (e.g., by etching tool 108) to form trenches in semiconductor substrate 202. The etching tool 108 may etch the unprotected portions of the semiconductor substrate 205 and the unprotected portions of the layer stack 305 by dry etching techniques (eg, reactive ion etching), wet etching techniques, and / or combinations thereof.

[0145] In some embodiments, another fin formation technique is used to form the fin structure 345. For example, the fin region may be defined (e.g., by masking or isolation regions), and the portion 340 may be formed by epitaxial growth to form the fin structure 345. In some embodiments, forming the fin structure 345 includes a trimming process to reduce the width of the fin structure 345. The trimming process may include a wet, dry etching process, and / or other possible trimming processes.

[0146] Furthermore, if Figure 3B As shown, the fin structures 345 may be formed according to different types of nanostructure transistors in the semiconductor device 200. Specifically, a first subset of the fin structures 345a may be formed according to p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of the fin structures 345b may be formed according to n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). The second subset of the fin structures 345b may be doped with a p-type dopant (e.g., boron (B) and / or germanium (Ge), etc.), while the first subset of the fin structures 345a may be doped with an n-type dopant (e.g., phosphorus (P) and / or arsenic (As), etc.). Additionally or optionally, a p-type source / drain region 225 may be formed based on subsequently formed p-type nanostructure transistors (including a first subset of fin structures 345a) (i.e., the p-type source / drain region 225 is a source / drain formed in conjunction with a p-type nanostructure transistor, rather than a p-type doped source / drain), and an n-type source / drain region 225 may be formed based on subsequently formed n-type nanostructure transistors (a second subset of fin structures 345b) (i.e., the n-type source / drain region 225 is a source / drain formed in conjunction with an n-type nanostructure transistor, rather than an n-type doped source / drain).

[0147] A first subset of fin structures 345a (e.g., subsequently provided to PMOS fin structures) and a second subset of fin structures 345b (e.g., subsequently provided to NMOS fin structures) can be formed to include similar characteristics and / or different characteristics. For example, the first subset of fin structures 345a can be formed to a first height and the second subset of fin structures 345b can be formed to a second height, where the first height is different from the second height. In another example, the first subset of fin structures 345a can be formed to a first width and the second subset of fin structures 345b can be formed to a second width, where the first width is different from the second width. Figure 3B In the example shown, the second width of the second subset of fin structures 345b (eg, subsequently provided to NMOS nanostructure transistors) is greater than the first width of the first subset of fin structures 345a (eg, subsequently provided to PMOS nanostructure transistors). However, other examples are also within the scope of the present disclosure.

[0148] As mentioned above, Figure 3A and Figure 3B This is just an example, and other Figure 3A and Figure 3B The exemplary embodiment 300 may include information related to Figure 3A and Figure 3B More steps, fewer steps, different steps and / or a different order of steps may be described.

[0149] Figure 4A and Figure 4B is a schematic diagram of an exemplary embodiment 400 of an STI formation process described in the present disclosure. Exemplary embodiment 400 includes an example of forming STI region 215 between fin structures 345 of semiconductor device 200 or a portion between fin structures 345 of semiconductor device 200. Semiconductor device 200 may include Figure 4A and Figure 4B One or more additional devices, structures and / or layers not shown in the figure. The semiconductor device 200 may include a Figure 4A and Figure 4B Additional layers and / or bare die on layers above and / or below the portion of semiconductor device 200 shown. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of an electronic device including semiconductor device 200. In some embodiments, the steps described in the exemplary embodiment 400 are described in Figure 3A and Figure 3B Execute after the relevant description steps.

[0150] Figure 4A A perspective view of the semiconductor device 200 and a cross-sectional view along the AA cross-sectional line in the perspective view are shown. Figure 4A As shown, a liner 405 and a dielectric layer 410 are formed over the semiconductor substrate 205 and interposed between the fin structures 345 (e.g., formed between the fin structures 345). The deposition tool 102 may deposit the liner 405 and the dielectric layer 410 over the semiconductor substrate 205. The deposition tool 102 may form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is approximately the same as the height of the top surface of the nitride layer 335.

[0151] Alternatively, the deposition tool 102 may form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is greater than the height of the top surface of the nitride layer 335, that is, Figure 4AAs shown. In this way, the trenches between the fin structures 345 will be overfilled by the dielectric layer 410 to ensure that the trenches are completely filled with the dielectric layer 410. Subsequently, the planarization tool 110 can perform a planarization or grinding process (e.g., a CMP process) to planarize the dielectric layer 410. The nitride layer 335 of the hard mask layer can serve as a CMP stop layer in this process. In other words, the planarization tool 110 planarizes the dielectric layer 410 until the nitride layer 335 of the hard mask layer. Therefore, after this process, the height of the top surface of the dielectric layer 410 is substantially equal to the height of the top surface of the nitride layer 335.

[0152] The deposition tool 102 may use a conformal deposition technique to deposit the liner 405. The deposition tool 102 may use a CVD technique (e.g., a flowable CVD (FCVD) technique or other CVD techniques), a PVD technique, an ALD technique, and / or other deposition techniques to deposit the dielectric layer 410. In some embodiments, after the liner 405 is deposited, the semiconductor device 200 is annealed, for example, to improve the quality of the liner 405.

[0153] The liner 405 and the dielectric layer 410 each include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric materials and / or other suitable insulating materials. In some embodiments, the dielectric layer 410 may include a multi-layer structure, for example, a liner layer having one or more layers.

[0154] Figure 4B A perspective view of the semiconductor device 200 and a cross-sectional view along the AA cross-sectional line in the perspective view are shown. Figure 4B As shown, an etch-back process is performed to remove a portion of the liner 405 and a portion of the dielectric layer 410 to form the STI region 215. In the etch-back process, the etching tool 108 may etch the liner 405 and the dielectric layer 410 to form the STI region 215. The etching tool 108 etches the liner 405 and the dielectric layer 410 according to the hard mask layer (e.g., the hard mask layer including the oxide layer 330 and the nitride layer 335). The liner 405 and the dielectric layer 410 are etched by the etching tool 108 so that the height of the STI region 215 is less than the bottom of the portion 340 of the layer stack 305, or is approximately equal to the height of the bottom of the portion 340 of the layer stack 305. Therefore, the layer stack 305 extends above the STI region 215. In some embodiments, the liner 405 and the dielectric layer 410 are etched so that the height of the STI region 215 is less than the height of the top surface of the mesa region 210.

[0155] In some embodiments, the etching tool 108 uses a dry etching technique to etch the liner 405 and the dielectric layer 410. Ammonia (NH3), hydrofluoric acid (HF) and / or another etchant may be used. The plasma-based dry etching technique may cause the etchant to react with the materials of the liner 405 and the dielectric layer 410, including:

[0156] SiO2+4HF→SiF4+2H2O

[0157] The silicon dioxide (SiO2) of the liner 405 and the dielectric layer 410 reacts with the hydrofluoric acid to form byproducts including silicon tetrafluoride (SiF4) and water (H2O). The silicon tetrafluoride is further decomposed by the hydrofluoric acid and ammonia to form ammonium fluorosilicate ((NH4)2SiF6) byproduct:

[0158] SiF4+2HF+2NH3→(NH4)2SiF6

[0159] The by-product ammonium fluorosilicate is removed from the process chamber of the etch tool 108. After the ammonium fluorosilicate is removed, a post-processing temperature of about 100°C to about 250°C is used to sublime the ammonium fluorosilicate into components of silicon tetrafluoride and hydrofluoric acid.

[0160] In some embodiments, the etching tool 108 etches the liner 405 and the dielectric layer 410 such that the height of the STI regions 215 between the first subset of fin structures 345a (e.g., subsequently provided to PMOS nanostructure transistors) is greater than the height of the STI regions 215 between the second subset of fin structures 345b (e.g., subsequently provided to NMOS nanostructure transistors). This is primarily because the width of the fin structure 345b is greater than the width of the fin structure 345a. In addition, this may cause the top surface of the STI region 215 between the fin structure 345a and the fin structure 345b to be tilted or skewed (e.g., as shown in FIG. 1 ). Figure 4BAs shown, it slopes downward from fin structure 345a to fin structure 345b). Due to the van der Waals force between the etchant and the surface of the pad 405 and the surface of the dielectric layer 410, the etchant used to etch the pad 405 and the dielectric layer 410 will first undergo physical adsorption (for example, physically bonded to the pad 405 and the dielectric layer 410). The etchant will be captured by the dipole moment. The etchant will then adhere to the dangling bonds of the pad 405 and the dielectric layer 410 and begin to undergo chemical adsorption. At this point, the etchant is chemically adsorbed on the surface of the pad 405 and the surface of the dielectric layer 410 to etch the pad 405 and the dielectric layer 410. The grooves between the second subset of fin structures 345b have a larger width, thereby providing a larger surface area where chemical adsorption can occur, which results in a faster etching rate between the second subset of fin structures 345b. The faster etch rate causes the height of the STI regions 215 between the second subset of fin structures 345 b to be less than the height of the STI regions 215 between the first subset of fin structures 345 a .

[0161] As mentioned above, Figure 4A and Figure 4B This is just an example, and other Figure 4A and Figure 4B The exemplary embodiment 400 may include information related to Figure 4A and Figure 4B More steps, fewer steps, different steps and / or a different order of steps may be described.

[0162] Figure 5 is a schematic diagram of an exemplary embodiment 500 of a dummy gate formation process described in the present disclosure. Exemplary embodiment 500 includes an example of forming a dummy gate structure of semiconductor device 200 or a portion of semiconductor device 200. Semiconductor device 200 may include Figure 5 One or more additional devices, structures and / or layers not shown in the figure. The semiconductor device 200 may include a semiconductor device formed on a substrate such as Figure 5 Additional layers and / or bare die on layers above and / or below the portion of semiconductor device 200 shown. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of an electronic device including semiconductor device 200. In some embodiments, the steps described in the exemplary embodiment 500 are described in FIG. 3A to FIG. 4B Execute after the relevant description steps.

[0163] Figure 5 FIG. 2 shows a perspective view of a semiconductor device 200. Figure 5As shown, a dummy gate structure 505 (also referred to as a dummy gate stack or a temporary gate structure) is formed above the fin structure 345. The dummy gate structure 505 is a sacrificial structure, and the dummy gate structure 505 will be replaced by a replacement gate structure or a replacement gate stack (e.g., gate structure 240) in a subsequent process stage of the semiconductor device 200. The portion of the fin structure 345 located below the dummy gate structure 505 can be referred to as a channel region. The dummy gate structure 505 can also define a source / drain (S / D) region of the fin structure 345, such as a region of the fin structure 345 adjacent to and located on opposite sides of the channel region.

[0164] The dummy gate structure 505 may include a gate electrode layer 510, a hard mask layer 515 located above and / or on the gate electrode layer 510, and a spacer layer 520, wherein the spacer layer 520 is located on opposite sides of the gate electrode layer 510 and on opposite sides of the hard mask layer 515. The dummy gate structure 505 may be formed on a gate dielectric layer 525 between the topmost second layer 315 and the dummy gate structure 505. The gate electrode layer 510 includes polysilicon (polysilicon or PO) or other materials. The hard mask layer 515 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or other materials) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer that may include silicon nitride (e.g., Si3N4 or other materials)). The spacer layer 520 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 525 may include silicon oxide (e.g., SiO x , such as SiO2), silicon nitride (such as Si x N y , such as Si3N4), high-K dielectric materials and / or other suitable materials.

[0165] The layers of the dummy gate structure 505 may be formed using various semiconductor process techniques, such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and development tool 106), and / or etching (e.g., by etching tool 108), etc. Examples include CVD, PVD, ALD, thermal oxidation, electron beam evaporation, lithography, electron beam lithography, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), dry etching (e.g., reactive ion etching), and / or wet etching, etc.

[0166] In some embodiments, the gate dielectric layer 525 is conformally deposited on the semiconductor device 200, and then the gate dielectric layer 525 is selectively removed from a portion of the semiconductor device 200 (e.g., the source / drain region). Then, the gate electrode layer 510 is deposited on the remaining portion of the gate dielectric layer 525. Then, the hard mask layer 515 is deposited on the gate electrode layer 510. The spacer layer 520 can be conformally deposited and etched back in a manner similar to the gate dielectric layer 525, so that the spacer layer 520 remains on the sidewall of the dummy gate structure 505. In some embodiments, the spacer layer 520 includes multiple types of spacer layers. For example, the spacer layer 520 can include a sealing spacer layer formed on the sidewall of the dummy gate structure 505 and a body spacer layer formed on the sealing spacer layer. The sealing spacer layer and the body spacer layer can be formed of similar materials or different materials. In some embodiments, the sealing spacer layer is formed by plasma surface treatment, and the body spacer layer is not formed by plasma surface treatment. In some embodiments, the body spacer layer is formed to a thickness greater than the sealing spacer layer. In some embodiments, the gate dielectric layer 525 is omitted from the dummy gate structure formation process and is formed in a replacement gate process.

[0167] Figure 5 Reference cross-sectional lines used in the following figures in the present disclosure are illustrated. Cross-sectional line AA is located in the xz plane (referred to as the y-plane) across the fin structure 345 in the source / drain region of the semiconductor device 200. Cross-sectional line BB is located in the yz plane (referred to as the x-plane) perpendicular to cross-sectional line AA and across the dummy gate structure 505 in the source / drain region of the semiconductor device 200. Cross-sectional line CC is located in the xz plane parallel to cross-sectional line AA and perpendicular to cross-sectional line BB and along the dummy gate structure 505. For clarity, these reference cross-sectional lines will be used in the following figures. In order to facilitate the description of the figures, some reference numerals for components or features in the figures may be omitted in some figures to avoid obscuring other components or features.

[0168] As mentioned above, Figure 5 This is just an example, and other Figure 5 The exemplary embodiment 500 may include information related to Figure 5 More steps, fewer steps, different steps and / or a different order of steps may be described.

[0169] Figure 6 is a schematic diagram of an exemplary embodiment 600 of the semiconductor device 200 described in the present disclosure. Figure 6 Including along Figure 5 The cross-sectional views along the AA, BB and CC sections are shown. Figure 6As shown by the BB and CC cross-sectional lines of FIG. 1 , the dummy gate structure 505 is formed above the fin structure 345. Figure 6 As shown in the CC cross-sectional line of , due to the removal of the hard mask layer 320 , a portion of the gate dielectric layer 525 and a portion of the gate electrode layer 510 are formed in the groove above the fin structure 345 .

[0170] As mentioned above, Figure 6 This is just an example, and other Figure 6 The exemplary embodiment 600 may include information related to Figure 6 More steps, fewer steps, different steps and / or a different order of steps may be described.

[0171] FIG. 7A to FIG. 7D FIG. 2 is a schematic diagram of an exemplary embodiment 700 of a source / drain trench formation process and an inner spacer formation process described in the present disclosure. The exemplary embodiment 700 includes an example of forming source / drain trenches 705 and an inner spacer 245 of the semiconductor device 200 . FIG. 7A to FIG. 7D is based on Figure 5 The multiple cross-sectional lines shown include Figure 5 The perspective view of the AA section line is drawn according to Figure 5 The perspective view of the BB section line and the Figure 5 In some embodiments, the steps of the exemplary embodiment 700 are described in Figures 3A to 6 Execute after the relevant description steps.

[0172] like Fig. 7A In the cross-sectional view shown by the AA section line and the BB section line of FIG. 3 , in the etching process, a source / drain recess 705 is formed in the portion 340 of the fin structure 345. The source / drain recess 705 is formed to provide a space on the opposite side of the dummy gate structure 505, and the source / drain region 225 is formed in the space. The etching process can be performed by an etching tool 108 and can be referred to as a strained source / drain (SSD) etching process. In some embodiments, the etching process includes a plasma etching technique, a wet chemical etching technique, and / or other types of etching techniques.

[0173] The source / drain recess 705 also extends to a portion of the terrace region 210 of the fin structure 345. In this way, a plurality of terrace regions 210 are formed in each fin structure 345, wherein the sidewalls of the portion of each source / drain recess 705 located below the portion 340 correspond to the sidewalls of the terrace region 210. The source / drain recess 705 may penetrate into a well portion (e.g., a p-well, an n-well) of the fin structure 345. In some embodiments, the semiconductor substrate 205 includes a silicon (Si) material having a (100) lattice orientation, and a (111) crystal plane is formed at the bottom of the source / drain recess 705, thereby forming a V-shaped or triangular cross-section at the bottom of the source / drain recess 705. In some embodiments, the V-shaped profile is formed by wet etching using tetramethylammonium hydroxide (TMAH) and / or chemical dry etching using hydrogen chloride (HCl). However, the cross-section of the bottom of the source / drain recess 705 may include other shapes, such as a circle or a semicircle.

[0174] like Fig. 7A In the cross-sectional view shown by the BB section line and the CC section line of FIG. 3 , after the source / drain recesses 705 are formed by the etching process, a portion of the first layer 310 and a portion of the second layer 315 of the layer stack 305 remain below the dummy gate structure 505. The portion of the second layer 315 located below the dummy gate structure 505 forms a nanostructure channel 220 of the nanostructure transistor of the semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain recesses 705.

[0175] like Figure 7BIn the cross-sectional view shown along the BB section line of FIG. 1 , during the etching process, the first layer 310 is laterally etched (e.g., in a direction substantially parallel to the longitudinal direction of the first layer 310) to form a cavity 710 between portions of the nanostructure channel 220. Specifically, the etching tool 108 forms the cavity 710 between the ends of the nanostructure channel 220 by laterally etching the ends of the first layer 310 below the dummy gate structure 505 in the source / drain recess 705. In an embodiment where the first layer 310 is silicon germanium (SiGe) and the second layer 315 is silicon (Si), the etching tool 108 can selectively etch the first layer 310 using a wet etchant, wherein the mixed solution of the wet etchant includes, for example, hydrogen peroxide (H2O2), acetic acid (CH3COOH) and / or hydrogen fluoride (HF), followed by a water (H2O) rinse. The mixed solution and water can be provided into the source / drain recess 705 to etch the first layer 310 in the source / drain recess 705. In some embodiments, etching by the mixed solution and cleaning by water are repeated about 10 to about 20 times. In some embodiments, the etching time of the mixed solution is about 1 minute to about 2 minutes. The use temperature of the mixed solution can be about 60° C. to about 90° C. However, other parameter values ​​of the etching process are also within the scope of the present disclosure.

[0176] The cavity 710 may be formed into an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or other shapes. In some embodiments, the depth of one or more cavities 710 (e.g., the size of the cavity from the source / drain recess 705 to the first layer 310) is about 0.5 nanometers to about 5 nanometers. In some embodiments, the depth of one or more cavities 710 is about 1 nanometer to about 3 nanometers. However, other values ​​of the depth of the cavity 710 are also within the scope of the present disclosure. In some embodiments, the etching tool 108 forms the cavity 710 into a length (e.g., the size of the cavity extending from the nanostructure channel 220 below the first layer 310 to another nanostructure channel 220 above the first layer 310) so that the cavity 710 partially extends to the side of the nanostructure channel 220 (e.g., so that the width or length of the cavity 710 is greater than the thickness of the first layer 310). In this way, the inner spacer to be formed in the cavity 710 later can extend to a portion of the end of the nanostructure channel 220.

[0177] like Figure 7C In the cross-sectional view shown by the AA section line and the BB section line of FIG. 700 , the insulating layer 715 is conformally deposited along the bottom and sidewalls of the source / drain recess 705. The insulating layer 715 further extends along the spacer layer 520. The deposition tool 102 can use CVD technology, PVD technology, ALD technology and / or other deposition technology to deposit the insulating layer 715. The insulating layer 715 includes silicon nitride (Si xN y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials. The insulating layer 715 may include a material different from that of the spacer layer 520 .

[0178] The deposition tool 102 forms the insulating layer 715 to a thickness sufficient to fill the cavities 710 between the nanostructure channels 220 with the insulating layer 715. For example, the insulating layer 715 is formed to a thickness of about 1 nanometer to about 10 nanometers. In another example, the insulating layer 715 is formed to a thickness of about 2 nanometers to about 5 nanometers. However, other values ​​of the thickness of the insulating layer 715 are also within the scope of the present disclosure.

[0179] like Fig.7D In the cross-sectional view shown along the AA section line and the BB section line, the insulating layer 715 is partially removed so that the remaining portion of the insulating layer 715 corresponds to the inner spacer 245 in the cavity 710. The etching tool 108 may perform an etching process to partially remove the insulating layer 715.

[0180] In some embodiments, the etching process may cause the surface of the inner spacer 245 facing the source / drain groove 705 to be curved or recessed. The depth of the recess in the inner spacer 245 may be about 0.2 nanometers to about 3 nanometers. In another example, the depth of the recess in the inner spacer 245 may be about 0.5 nanometers to about 2 nanometers. In yet another example, the depth of the recess in the inner spacer 245 may be less than about 0.5 nanometers. In some embodiments, the surface of the inner spacer 245 facing the source / drain groove 705 is substantially flat, so that the surface of the inner spacer 245 is approximately flat and flush with the surface of the end of the nanostructure channel 220.

[0181] As mentioned above, FIG. 7A to FIG. 7D This is just an example, and other FIG. 7A to FIG. 7D The exemplary embodiment 700 may include information related to FIG. 7A to FIG. 7D More steps, fewer steps, different steps and / or a different order of steps may be described.

[0182] Figure 8 FIG. 8 is a schematic diagram of an exemplary embodiment 800 of a source / drain region formation process described in the present disclosure. The exemplary embodiment 800 includes an example of forming a source / drain region 225 in a source / drain recess 705 of a semiconductor device 200 . FIG. 7A to FIG. 7D is based on Figure 5 The multiple cross-sectional lines shown include Figure 5 The perspective view of the AA section line is drawn according to Figure 5The perspective view of the BB section line and the Figure 5 In some embodiments, the steps of the exemplary embodiment 800 are described in FIG. 3A to FIG. 7D Execute after the relevant description steps.

[0183] like Figure 8 , the source / drain recess 705 is filled with one or more layers to form a source / drain region 225 in the source / drain recess 705. For example, the deposition tool 102 may deposit a buffer 230 at the bottom of the source / drain recess 705, the deposition tool 102 may deposit the source / drain region 225 on the buffer 230, and the deposition tool 102 may deposit a capping layer 235 on the source / drain region 225. The buffer 230 may include silicon (Si), boron-doped (SiB) or other doped silicon and / or other materials. By including the buffer 230, dopant migration and / or leakage from the source / drain region 225 to the adjacent platform region 210 may be reduced, minimized and / or prevented, otherwise, short channel effects may result in the semiconductor device 200. Therefore, the buffer 230 may improve the performance of the semiconductor device 200 and / or improve the yield of the semiconductor device 200.

[0184] The source / drain region 225 may include one or more layers of epitaxially grown material. For example, the deposition tool 102 may epitaxially grow a first layer of source / drain region 225 above the buffer region 230, and may epitaxially grow a second layer of source / drain region 225 above the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P) and / or other dopants) and may be included as a barrier layer to reduce short channel effects in the semiconductor device 200 and reduce dopants from being squeezed out or migrated into the nanostructure channel 220. The second layer may include highly doped silicon or highly doped silicon germanium. The second layer may be included to provide compressive stress in the source / drain region 225 to reduce boron loss.

[0185] As mentioned above, Figure 8 This is just an example, and other Figure 8 The exemplary embodiment 800 may include information related to Figure 8 More steps, fewer steps, different steps and / or a different order of steps may be described.

[0186] Fig. 9 is a schematic diagram of an exemplary embodiment 900 of an ILD formation process described in the present disclosure. Fig. 9 is based on Figure 5 The multiple cross-sectional lines shown include Figure 5 The perspective view of the AA section line is drawn according to Figure 5The perspective view of the BB section line and the Figure 5 In some embodiments, the steps of the exemplary embodiment 900 are described in FIG. 3A to FIG. 8 Execute after the relevant description steps.

[0187] like Fig. 9 In the cross-sectional view shown by the AA section line and the BB section line of FIG. 5 , an ILD layer 250 is formed over the source / drain region 225. The ILD layer 250 fills the area between the dummy gate structures 505 and over the source / drain region 225. The ILD layer 250 is formed to reduce and / or prevent the possibility of damage to the source / drain region 225 during the replacement gate process. The ILD layer 250 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0188] In some embodiments, before forming the ILD layer 250, a contact etch stop layer (CESL) is conformally deposited (e.g., by deposition tool 102) over the source / drain regions 225, over the dummy gate structure 505, and on the spacer layer 520. Next, the ILD layer 250 is formed on the CESL. The CESL can provide a mechanism to stop the etching process when forming contacts or vias to the source / drain regions 225. The CESL can be formed of a dielectric material with a different etch selectivity than adjacent layers or components. The CESL can include or can be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. In addition, the CESL can include or can be silicon nitride (Si x N y ), silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or a combination thereof. CESL can be deposited using a deposition process such as ALD, CVD, or other deposition techniques.

[0189] As mentioned above, Fig. 9 The number and arrangement of steps and devices shown are provided as one or more examples. Fig. 9 There may be additional steps and devices, fewer steps and devices, different steps and devices, or differently arranged steps and devices than those shown.

[0190] FIG. 10A to FIG. 10C 1 is a schematic diagram of an exemplary embodiment 1000 of a replacement gate (RPG) process described herein. Exemplary embodiment 1000 includes an example of a replacement gate process for replacing a dummy gate structure 505 with a gate structure 240 (eg, a replacement gate structure) of a semiconductor device 200 . FIG. 10A to FIG. 10C is based on Figure 5 The multiple cross-sectional lines shown include Figure 5 The perspective view of the AA section line is drawn according to Figure 5The perspective view of the BB section line and the Figure 5 In some embodiments, the steps of the exemplary embodiment 1000 are described in FIG. 3A to FIG. 9 Execute after the relevant description steps.

[0191] like Fig. 10A Referring to the cross-sectional view shown by the BB section line and the CC section line of FIG. 2 , a replacement gate process is performed (e.g., by one or more of the semiconductor processing tools 102-112) to remove the dummy gate structure 505 from the semiconductor device 200. The dummy gate structure 505 is removed to form an opening (or recess) 1003 between the ILD layer 250 above the source / drain region 225. The dummy gate structure 505 may be removed by one or more etching processes. The etching process may include a plasma etching technique, a wet chemical etching technique, and / or other types of etching techniques.

[0192] like Fig. 10B In the cross-sectional view shown by the BB section line and the CC section line of FIG. 1 , a nanostructure release process (e.g., a SiGe release process) is performed to remove the first layer 310 (e.g., a silicon germanium layer). In this way, an opening 1005 between the nanostructure channels 220 (e.g., an area around the nanostructure channels 220) is formed. The nanostructure release process may include removing the first layer 310 based on the etching selectivity difference between the material of the first layer 310 and the material of the nanostructure channels 220, and based on the etching selectivity difference between the material of the first layer 310 and the inner spacer 245. The inner spacer 245 can serve as an etching stop layer in the etching process to protect the source / drain region 225 from being etched.

[0193] like Fig. 10CThe replacement gate process is continued as shown in the cross-sectional view of the BB section line and the CC section line of FIG. 1 , wherein the gate structure (e.g., replacement gate structure) 240 is formed in the opening 1005 between the source / drain regions 225 by the deposition tool 102 and / or the electroplating tool 112. Specifically, the gate structure 240 fills the area between and around the nanostructure channel 220 occupied by the first layer 310 described above, so that the gate structure 240 surrounds the nanostructure channel 220. The gate structure 240 completely covers the nanostructure channel 220 and surrounds all four sides of the nanostructure channel 220. The gate structure 240 may include a metal gate structure. Before forming the gate structure 240, a conformal high-k dielectric liner 1010 may be deposited on the nanostructure channel 220 and on the sidewalls of the nanostructure channel 220. The high-k dielectric liner 1010 may be a gate dielectric layer between the gate structure 240 and the nanostructure channel 220. The gate structure 240 may include additional layers, such as an interface layer, a work function adjustment layer, and / or a metal electrode structure.

[0194] As mentioned above, FIG. 10A to FIG. 10C The number and arrangement of steps and devices shown are provided as one or more examples. FIG. 10A to FIG. 10C There may be additional steps and devices, fewer steps and devices, different steps and devices, or differently arranged steps and devices than those shown.

[0195] FIG. 11A to FIG. 11I 1 is a schematic diagram of an exemplary embodiment 1100 of forming an active region isolation structure as described in the present disclosure. Exemplary embodiment 1100 includes an example of forming an active region isolation structure (e.g., a CMODE structure) in semiconductor device 200 after a replacement gate process in which a dummy gate structure 505 is replaced by a gate structure 240. The active region isolation structure can be formed along the gate structure 240 to establish an electrically isolated region in a stack of one or more mesa regions 210 and / or one or more nanostructure channels 220 below the gate structure 240. Thus, the active region isolation structure enables the nanostructure channel 220 below the active region isolation structure to be divided into a plurality of (electrically isolated) nanostructure channels 220.

[0196] FIG. 11A to FIG. 11I is based on Fig. 7A The multiple cross-sectional lines shown include Fig. 7A BB cross-sectional line perspective view (eg, across multiple gate structures 240), and according to Fig. 7A 1000 (eg, along gate structure 240). In some embodiments, the related description steps of exemplary embodiment 1000 are shown in FIG. FIG. 3A to FIG. 10CExecute after the relevant description steps.

[0197] like Fig.11A As shown, a hard mask layer 1105 may be formed above and / or on the semiconductor device 200. Forming the hard mask layer 1105 may enable etching the gate structure 240 through a pattern to form a recess in which an active region isolation structure will be formed. The hard mask layer 1105 may include a dielectric material, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), high-k dielectric materials and / or other suitable dielectric materials. The deposition tool 102 for depositing the hard mask layer 1105 can be PVD technology, ALD technology, CVD technology, oxidation technology, Figure 1 In some embodiments, the planarization tool 110 can be used to planarize the hard mask layer 1105 after the hard mask layer 1105 is deposited.

[0198] Furthermore, if Fig.11A As shown, the gate isolation structure 1110 passes through the gate structure 240 to segment or divide the gate structure 240 into a plurality of gate structures 240 that are electrically isolated from each other. The gate isolation structure 1110 enables each gate structure 240 to operate independently and enables a plurality of transistors to be formed along the gate structure 240. The gate isolation structure 1110 may extend in a direction (e.g., a Y direction) substantially perpendicular to the gate structure 240 (e.g., an X direction). The gate isolation structure 1110 may include a cut metal gate (CMG) isolation structure, a cut polysilicon gate isolation structure, and / or other types of gate isolation structures.

[0199] In order to form the gate isolation structure 1110, a gate isolation groove can be formed through the gate structure 240 and penetrate into one or more STI regions 215 below the gate structure 240. In some embodiments, the gate structure 240 and the STI region 215 are etched using a pattern in the photoresist layer to form the gate isolation groove. In these embodiments, the deposition tool 102 can be configured to form a photoresist layer on the gate structure 240. The exposure tool 104 can be configured to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be configured to develop and remove a portion of the photoresist layer to expose the pattern. The etching tool 108 can be configured to etch the gate structure 240 and the STI region 215 based on the pattern to form a gate isolation groove in the gate structure 240 and the STI region 215. In some embodiments, the etching process includes a plasma etching process, a wet chemical etching process, and / or another type of etching process. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based formation of gate isolation recesses.

[0200] The deposition tool 102 may be Figure 1 The PVD technique, ALD technique, CVD technique, oxidation technique and / or other deposition techniques are used to deposit the material of the gate isolation structure 1110 in the gate isolation groove. In some embodiments, the gate isolation structure 1110 and the hard mask layer 1105 can be formed in the same set of deposition steps, so the gate isolation structure 1110 and the hard mask layer 1105 can be formed of the same material. For example, the deposition tool 102 can deposit the material of the gate isolation structure 1110 in the gate isolation groove, and, after filling the gate isolation groove, continue to deposit an excess amount of the material to form the hard mask layer 1105.

[0201] like Fig. 11BAs shown, a patterned stack 1120 may be formed above and / or on the hard mask layer 1105. The patterned stack 1120 may be configured to pattern the hard mask layer 1105 to form an active region isolation groove between the gate isolation structures 1110. The patterned stack 1120 may include one or more mask layers, such as a bottom layer 1125, an intermediate layer 1130, and a top layer 1135. The bottom layer 1125 may include a carbon-containing material and / or other suitable materials. The intermediate layer 1130 may include an oxide-containing material and / or other suitable materials. The top layer 1135 may include a photoresist layer configured to transfer the pattern 1140 to the bottom layer 1125 and the intermediate layer 1130. The different materials of the bottom layer 1125 and the intermediate layer 1130 provide an etching selectivity between the bottom layer 1125 and the intermediate layer 1130, so that the aspect ratio of the pattern 1140 can be strictly controlled.

[0202] The deposition tool 102 may be Figure 1 The above-mentioned PVD technique, ALD technique, CVD technique, oxidation technique and / or other suitable deposition techniques are used to deposit the bottom layer 1125 and the middle layer 1130. In some embodiments, the planarization tool 110 can be configured to planarize the bottom layer 1125 and / or the middle layer 1130 after depositing the bottom layer 1125 and / or the middle layer 1130. The deposition tool 102 can deposit the top layer 1135 by spin coating technique and / or other suitable deposition techniques.

[0203] Furthermore, if Fig. 11B As shown, pattern 1140 may be formed in top layer 1135. In some embodiments, a wet cleaning step may be performed before forming pattern 1140. Top layer 1135 may be exposed to a radiation source by exposure tool 104 to form pattern 1140, and a portion of top layer 1135 may be developed and removed by development tool 106 to expose pattern 1140. Pattern 1140 may be formed over a portion of gate structure 240 between gate isolation structures 1110.

[0204] like Fig. 11C As shown, pattern 1140 is transferred to bottom layer 1125 and middle layer 1130 of patterned stack 1120. Pattern 1140 is transferred to bottom layer 1125 and middle layer 1130 according to pattern 1140 in top layer 1135, and etching tool 108 can be configured to etch bottom layer 1125 and middle layer 1130 according to pattern 1140. In some embodiments, the etching process includes dry etching (e.g., plasma etching process). In some embodiments, the etching process includes other types of etching processes, such as wet chemical etching process.

[0205] Furthermore, if Fig. 11CAs shown, the pattern 1140 in the bottom layer 1125 and the middle layer 1130 can be configured to form an active region isolation groove 1145 (e.g., a CMODE groove) in the hard mask layer 1105. The etching tool 108 can be configured to etch the hard mask layer 1105 according to the pattern 1140 in the bottom layer 1125 and the middle layer 1130 to form the active region isolation groove 1145. In some embodiments, the etching process includes dry etching (e.g., a plasma etching process). In some embodiments, the etching process includes other types of etching processes, such as a wet chemical etching process. The etching can stop on the gate structure 240. In some embodiments, after the active region isolation groove 1145 is formed, the remaining portion of the patterned stack 1120 can be removed by a photoresist removal tool (e.g., using a chemical stripper, plasma ashing and / or other techniques). In some embodiments, after the active region isolation groove 1145 is formed, a wet cleaning step can be performed.

[0206] like Fig.11D As shown, the gate structure 240 may be etched to extend the active region isolation recess 1145 downward to the STI region 215 below the gate structure 240. The active region isolation recess 1145 may pass through the gate structure 240 and be formed between the gate isolation structures 1110. The etching process may further remove a portion of the high-k dielectric liner 1010 located between the gate isolation structures 1110.

[0207] The gate isolation structure 1110 and the hard mask layer can be used as a self-aligned pattern to etch the gate structure 240 according to the etching selectivity between the gate structure 240 and the gate isolation structure 1110 and the hard mask layer. In other words, no additional mask / patterning layer is required, and the etching position of the gate structure 240 can be controlled by the hard mask layer 1105 and the gate isolation structure 1110. The gate structure 240 and the high-k dielectric liner 1010 can be etched using an etching tool 108. In some embodiments, the etching process includes dry etching (e.g., a plasma etching process). In some embodiments, the etching process includes other types of etching processes, such as a wet chemical etching process.

[0208] After etching the gate structure 240 and the high-k dielectric liner 1010, the nanostructure channel 220 between the gate isolation structures 1110 is exposed in the active region isolation groove 1145. In addition, a portion of the terrace region 210 below the nanostructure channel 220 is exposed in the active region isolation groove 1145. In some embodiments, a wet cleaning step may be performed after etching the gate structure 240 and the high-k dielectric liner 1010.

[0209] The material (e.g., metal material) forming the gate structure 240 may be a material that can better withstand the stress and strain applied to the semiconductor device 200 during the etching of the gate structure 240 than the material of the dummy gate structure 505. Therefore, after replacing the dummy gate structure 505 with the gate structure 240, performing the CMODE process may reduce layout effects, such as gate deformation, on the semiconductor device 200. Therefore, after replacing the dummy gate structure 505 with the gate structure 240, the threshold voltage shift in the semiconductor device 200 may be reduced or minimized.

[0210] The material of the gate structure 240 may have a greater Young's modulus than the material of the dummy gate structure 505, and therefore, may be better resistant to deformation than the dummy gate structure 505. For example, the gate structure 240 may include tungsten (W) (Young's modulus of about 400 gigapascals (GPa) to about 420 GPa), titanium nitride (TiN) (Young's modulus of about 260 GPa to about 600 GPa), titanium aluminide (TiAl) (Young's modulus of about 236 GPa to about 270 GPa), and / or hafnium oxide (HfO2) (Young's modulus of about 160 GPa to about 200 GPa), while the dummy gate structure 505 may include, for example, silicon (Si) (Young's modulus of about 140 GPa to about 180 GPa) and / or silicon nitride (Si3N4) (Young's modulus of about 280 GPa to about 290 GPa). Since the tensile stress (σ) of the material of the gate structure 240 is higher, the Young's modulus of the material of the gate structure 240 may be greater than the Young's modulus of the material of the dummy gate structure 505 , making the gate structure 240 less susceptible to deformation than the dummy gate structure 505 .

[0211] like Fig.11E As shown, after etching the gate structure 240 and the high-k dielectric liner 1010, the nanostructure channel 220 between the gate isolation structures 1110 (exposed in the active region isolation groove 1145) can be removed. In addition, the platform region 210 below the nanostructure channel 220 (exposed in the active region isolation groove 1145) is removed, so that a groove extension 1150 is generated between the STI regions 215 between the gate isolation structures 1110. Therefore, the active region isolation groove 1145 extends downward, and in some embodiments, the active region isolation groove 1145 extends downward to the semiconductor substrate 205 below the STI region 215. The nanostructure channel 220 and the corresponding platform region 210 below the nanostructure channel 220 are removed, so that the nanostructure channel 220 and the corresponding platform region 210 are divided into multiple parts in the Y direction. In this way, the nanostructure channel 220 and the corresponding platform region 210 can be electrically isolated, and thus a plurality of active regions can be included in the nanostructure channel 220 and the corresponding platform region 210 .

[0212] In some embodiments, an inductively coupled plasma (ICP) is configured to etch the nanostructure channel 220 and the platform region 210. The plasma can be a hydrogen bromide (HBr)-based plasma etchant, a chlorine (Cl2)-based plasma etchant, a boron trichloride (BCl3)-based plasma etchant, and / or other plasma-based etchants containing oxygen (O2) and / or carbon dioxide (CO2). The concentration of BCl3 and / or Cl2 in the plasma-based etchant can be low to provide high etching selectivity between the platform region 210 (e.g., silicon) and the STI region 215 (e.g., silicon dioxide) between the gate isolation structure 1110.

[0213] The plasma may be generated using an etching tool 108, such as an inductively coupled plasma (ICP) tool, a resonant antenna plasma source driven by a radio frequency (RF) power generator, and / or other types of plasma-based etching tools. A frequency of multiples of 13.56 megahertz (MHz) (e.g., 13.56 MHz, 27 MHz) may be configured in the RF power generator. The RF power generator may provide a power supply including from about 100 watts to about 2500 watts, however, other numerical ranges are also within the scope of the present disclosure. Pulsed plasma etching may be performed with a duty cycle of about 10% to about 100%, however, other numerical ranges are also within the scope of the present disclosure. The RF bias power of the pedestal in the processing chamber of the etching tool 108 may be from about 10 watts to about 2000 watts, however, other numerical ranges are also within the scope of the present disclosure. The pressure of the processing chamber of the etching tool 108 may be operated at about 3 mTorr to about 150 mTorr, however, other numerical ranges are also within the scope of the present disclosure. The temperature of the processing chamber of the etch tool 108 may be operated at a temperature of about 20° C. to about 150° C., however, other ranges are also within the scope of the present disclosure.

[0214] like Fig.11FAs shown, the dielectric liner 1155 of the active region isolation structure 1115 can be formed in the active region isolation groove 1145. The dielectric liner 1155 can be conformally deposited on the sidewalls of the active region isolation groove 1145 (corresponding to the sidewalls of the gate isolation structure 1110 exposed in the active region isolation groove 1145), on the bottom surface of the active region isolation groove 1145 (corresponding to the top surface of the STI region 215 exposed in the active region isolation groove 1145), and on the surface of the groove extension 1150 of the active region isolation groove 1145 (corresponding to the sidewalls of the STI region 215 and a portion of the semiconductor substrate 205). The deposition tool 102 can be formed by PVD technology, ALD technology, CVD technology, oxidation technology, etc. Figure 1 The above-described deposition techniques and / or other deposition techniques are used to deposit the dielectric liner 1155. The dielectric liner 1155 may include a dielectric material, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), high-k dielectric materials and / or other suitable dielectric materials.

[0215] like Fig.11G As shown, a dielectric layer 1160 is filled in the active region isolation recess 1145 above and / or on the dielectric liner 1155 of the active region isolation structure 1115. The dielectric layer 1160 may be overfilled in the active region isolation recess 1145 to ensure that the active region isolation recess 1145 is completely filled with the dielectric layer 1160 and to minimize the formation of gaps or voids in the active region isolation structure 1115. The deposition tool 102 may be formed by PVD technology, ALD technology, CVD technology, oxidation technology, etc. Figure 1 The above-described deposition techniques and / or other deposition techniques are used to deposit the dielectric liner 1155. The dielectric liner 1155 may include a dielectric material, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), high-k dielectric materials and / or other suitable dielectric materials.

[0216] like Fig.11H As shown, after forming the layers of the active area isolation structure 1115, a planarization step may be performed to planarize the semiconductor device 200. The planarization tool 110 may be used to planarize the semiconductor device 200 to remove the hard mask layer 1105, remove excess material of the dielectric liner 1155, and / or remove excess material of the dielectric layer 1160.

[0217] The semiconductor device 200 may include a plurality of first nanostructure channels 220a located above a first platform region 210a extending above a semiconductor substrate 205, and a plurality of second nanostructures located above a second platform region 210b extending above the semiconductor substrate 205. The plurality of first nanostructure channels 220a and the plurality of second nanostructures are arranged along a direction perpendicular to the semiconductor substrate 205 (e.g., a Z direction). The semiconductor device 200 may include a first gate structure 240a surrounding each of the first nanostructure channels 220a, and a second gate structure 240b surrounding each of the second nanostructure channels 220b. The semiconductor device 200 may include a first gate isolation structure 1110a and a second gate isolation structure 1110b located between the first gate structure 240a and the second gate structure 240b. The semiconductor device 200 may include an active region isolation structure 1115 (e.g., a CMODE structure) located between the gate isolation structures 1110a and 1110b. The active region isolation structure 1115 may be located between the first gate structure 240a and the second gate structure 240b, and between the first gate isolation structure 1110a and the second gate isolation structure 1110b. The dielectric liner 1155 of the active region isolation structure 1115 is directly included on the sidewall of the first gate isolation structure 1110a, and directly included on the sidewall of the second gate isolation structure 1110b. The first gate structure 240a may be in direct contact with the sidewall of the first gate isolation structure 1110a, and the second gate structure 240b may be in direct contact with the sidewall of the second gate isolation structure 1110b. The dielectric liner 1155 may be located between the dielectric layer 1160 of the active region isolation structure 1115 and the gate isolation structures 1110a and 1110b.

[0218] Fig.11I FIG. 2 shows a top view of a semiconductor device 200 . Fig.11IAs shown, the nanostructure channels 220 may extend along the Y direction in the semiconductor device 200, and the gate structures 240 may extend along the X direction in the semiconductor device. The source / drain regions 225 may be recessed in one or more of the nanostructure channels 220, such that the source / drain regions 225 are adjacent to the ends of one or more sets of nanostructure channels 220. The gate isolation structures 1110a and 1110b may extend in the Y direction and may extend across one or more of the gate structures 240. The gate isolation structures 1110a and 1110b may divide one or more of the gate structures 240 into a plurality of gate structures, such as the gate structure 240a and the gate structure 240b. The active region isolation structure 1115 may be included between the gate isolation structures 1110a and 1110b and replace the location where a portion of the gate structure 240 (and the nanostructure channels 220 and the platform region 210 below) is removed. The active region isolation structure 1115 divides the one or more nanostructure channels 220 c into a plurality of portions located on opposite sides of the active region isolation structure 1115 .

[0219] As mentioned above, FIG. 11A to FIG. 11I The number and arrangement of steps and devices shown are provided as one or more examples. FIG. 11A to FIG. 11I There may be additional steps and devices, fewer steps and devices, different steps and devices, or differently arranged steps and devices than those shown.

[0220] Fig. 12A and Fig. 12B is a schematic diagram of an exemplary embodiment 1200 of a semiconductor device 200 described in the present disclosure. Fig. 12A is an exemplary embodiment of a sparsely patterned CMODE region (eg, isolation region / ISO region) of the semiconductor device 200, and Fig. 12B is an exemplary embodiment of a densely patterned CMODE region of a semiconductor device 200 , wherein the semiconductor device 200 includes a plurality of active region isolation structures 1115 .

[0221] like Fig. 12A As shown, the semiconductor device 200 may include one or more dimensions, such as dimension D1, dimension D2, dimension D3, dimension D4, dimension D5, and / or dimension D6, in the sparsely patterned CMODE region.

[0222] Dimension D1 may correspond to the width of the active region isolation structure 1115 at the height of the top of the gate structure 240 (corresponding to the bottom of the hard mask layer 1105) (occasionally referred to as the "critical dimension" or "CD"). In some embodiments, dimension D1 may be about 23 nanometers to about 24 nanometers, however, other values ​​and / or other ranges of dimension D1 are also within the scope of the present disclosure.

[0223] Dimension D2 may correspond to the width of the active region isolation structure 1115 at the topmost height of the nanostructure channel 220. In some embodiments, dimension D2 may be about 20 nanometers to about 21 nanometers, however, other values ​​and / or other ranges of dimension D2 are also within the scope of the present disclosure.

[0224] Dimension D3 may correspond to the width of the active region isolation structure 1115 at the height of the middle of the nanostructure channel 220. In some embodiments, dimension D3 may be about 18 nanometers to about 20 nanometers, however, other values ​​and / or other ranges of dimension D3 are also within the scope of the present disclosure.

[0225] Dimension D4 may correspond to the width of the active region isolation structure 1115 at the height of the bottom of the nanostructure channel 220. In some embodiments, dimension D4 may be about 18 nanometers to about 20 nanometers, however, other values ​​and / or other ranges of dimension D4 are also within the scope of the present disclosure.

[0226] Dimension D5 may correspond to the depth, height or thickness from the active region isolation structure 1115 to the top of the nanostructure channel 220. In some embodiments, dimension D5 may be about 114 nm to about 115 nm, however, other values ​​and / or other ranges of dimension D5 are also within the scope of the present disclosure.

[0227] Dimension D6 may correspond to the angle of gate structure 240 relative to the topmost surface of nanostructure channel 220. In some embodiments, dimension D6 may be about 90 degrees to about 92 degrees, however, other values ​​and / or other ranges of dimension D6 are also within the scope of the present disclosure.

[0228] In some embodiments, the ratio of dimension D1 to dimension D2 is about 1.09:1 to about 1.2:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D1 to dimension D3 is about 1.15:1 to about 1.33:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D1 to dimension D4 is about 1.15:1 to about 1.33:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D2 to dimension D3 is about 1:1 to about 1.17:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D2 to dimension D4 is about 1:1 to about 1.17:1, however, other numerical ranges are also within the scope of the present disclosure.

[0229] In some embodiments, the ratio of dimension D5 to dimension D1 is about 4.75:1 to about 5:1, however, other values ​​are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D5 to dimension D2 is about 5.42:1 to about 5.75:1, however, other values ​​are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D5 to dimension D3 is about 5.7:1 to about 6.39:1, however, other values ​​are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D5 to dimension D4 is about 5.7:1 to about 6.39:1, however, other values ​​are also within the scope of the present disclosure.

[0230] like Fig. 12B As shown, the semiconductor device 200 may include one or more dimensions, such as dimension D7 , dimension D8 , dimension D9 , dimension D10 , dimension D11 , and / or dimension D12 , in the densely patterned CMODE region.

[0231] Dimension D7 may correspond to the width of the active region isolation structure 1115 at the height of the top of the gate structure 240 (corresponding to the bottom of the hard mask layer 1105). In some embodiments, dimension D7 may be about 20.5 nanometers to about 25.3 nanometers, however, other values ​​and / or other ranges of dimension D7 are also within the scope of the present disclosure.

[0232] Dimension D8 may correspond to the width of the active region isolation structure 1115 at the topmost height of the nanostructure channel 220. In some embodiments, dimension D8 may be about 18.8 nanometers to about 21.9 nanometers, however, other values ​​of dimension D8 are also within the scope of the present disclosure.

[0233] Dimension D9 may correspond to the width of the active region isolation structure 1115 at the height of the middle of the nanostructure channel 220. In some embodiments, dimension D9 may be about 16.2 nm to about 19.6 nm, however, other values ​​and / or other ranges of dimension D9 are also within the scope of the present disclosure.

[0234] Dimension D10 may correspond to the width of the active region isolation structure 1115 at the height of the bottom of the nanostructure channel 220. In some embodiments, dimension D10 may be about 15.3 nm to about 18.9 nm, however, other values ​​and / or other ranges of dimension D10 are also within the scope of the present disclosure.

[0235] Dimension D11 may correspond to the depth, height or thickness from the active region isolation structure 1115 to the topmost portion of the nanostructure channel 220. In some embodiments, dimension D11 may be about 99.4 nanometers to about 154.9 nanometers, however, other values ​​and / or other ranges of dimension D11 are also within the scope of the present disclosure.

[0236] Dimension D12 may correspond to the angle of gate structure 240 relative to the topmost surface of nanostructure channel 220. In some embodiments, dimension D12 may be about 88.2 degrees to about 92 degrees, however, other values ​​and / or other ranges of dimension D12 are also within the scope of the present disclosure.

[0237] In some embodiments, the ratio of dimension D7 to dimension D8 is from about 0.93:1 to about 1.35:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D7 to dimension D9 is from about 1.04:1 to about 1.56:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D7 to dimension D10 is from about 1.08:1 to about 1.65:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D8 to dimension D9 is from about 0.961 to about 1.35:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D8 to dimension D10 is from about 1:1 to about 1.43:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D9 to dimension D10 is from about 0.086:1 to about 1.28:1, however, other numerical ranges are also within the scope of the present disclosure.

[0238] In some embodiments, the ratio of dimension D11 to dimension D7 is about 3.92:1 to about 7.56:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D11 to dimension D8 is about 4.53:1 to about 8.24:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D11 to dimension D9 is about 5.07:1 to about 9.56:1, however, other numerical ranges are also within the scope of the present disclosure. In some embodiments, the ratio of dimension D11 to dimension D10 is about 5.25:1 to about 10.13:1, however, other numerical ranges are also within the scope of the present disclosure.

[0239] As mentioned above, Fig. 12A and Fig. 12B This is just an example, other Fig. 12A and Fig. 12B Different examples are also described in Fig. 12A and Fig. 12B within the scope of disclosure.

[0240] Fig.13 1 is a schematic diagram of exemplary components of the apparatus 1300 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may include one or more of the apparatus 1300 and / or one or more components of the apparatus 1300. Fig.13 As shown, device 1300 may include a bus 1310 , a processor 1320 , a memory 1330 , an input component 1340 , an output component 1350 , and / or a communication component 1360 .

[0241] The bus 1310 may include one or more components configured for wired and / or wireless communication between components of the device 1300. The bus 1310 may include: Fig.13 Two or more components of are coupled together, for example, via operational coupling, communication coupling, electronic coupling and / or electrical coupling. For example, bus 1310 may include electrical connections (e.g., wires, traces and / or conductors) and / or wireless buses. Processor 1320 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, a specific application integrated circuit and / or other types of processing components. Processor 1320 may be implemented by hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1320 may include one or more processors that can be programmed to perform one or more steps or processes described elsewhere in the present disclosure.

[0242] Memory 1330 may include volatile and / or non-volatile memory. For example, memory 1330 may include random access memory (RAM), read only memory (ROM), hard disk and / or other types of memory (e.g., flash memory, disk and / or optical memory). Memory 1330 may include internal memory (e.g., RAM, ROM or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1330 may be a non-transitory computer-readable medium. Memory 1330 may store information related to the processing of device 1300, one or more instructions and / or software (e.g., one or more software applications). In some embodiments, memory 1330 may include one or more memories coupled (communicatively coupled) to one or more processors (e.g., processor 1320), for example via bus 1310. The communicative coupling between processor 1320 and memory 1330 may enable processor 1320 to read and / or process information stored in memory 1330 and / or store information in memory 1330 .

[0243] Input component 1340 can enable device 1300 to receive input signals, such as user input signals and / or sensed input signals. For example, input component 1340 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a GPS sensor, a GNSS sensor, an accelerometer, a gyroscope and / or an actuator. Output component 1350 can enable device 1300 to provide output signals, such as via a display, a speaker and / or a light emitting diode. Communication component 1360 can enable device 1300 to communicate with other devices via wired connection and / or wireless connection. For example, communication component 1360 can include a receiver, a transmitter, a transceiver, a modem, a network interface card and / or an antenna.

[0244] Device 1300 can perform one or more processes or techniques described in the present disclosure. For example, a non-transitory computer-readable medium (e.g., memory 1330) can store a set of instructions (e.g., one or more instructions or program codes) for execution by processor 1320. Processor 1320 can execute the set of instructions to perform one or more processes or techniques described in the present disclosure. In some embodiments, the execution of the set of instructions by one or more processors 1320 causes one or more processors 1320 and / or device 1300 to perform one or more processes or techniques described in the present disclosure. In some embodiments, hardware wiring circuits can be used to replace instructions or in combination with instructions to perform one or more processes or techniques described in the present disclosure. Additionally or optionally, processor 1320 can be configured to perform one or more processes or techniques described in the present disclosure. Therefore, the embodiments described in the present disclosure are not limited to any specific combination of hardware circuits and software.

[0245] Fig.13 The number and arrangement of components shown are examples only. Device 1300 may include Fig.13 More components, fewer components, different components, or differently arranged components are shown. Additionally or alternatively, one set of components (eg, one or more components) of device 1300 may perform one or more functions described as being performed by another set of components of device 1300.

[0246] Fig.14 FIG. 1 is a flow chart of an exemplary process 1400 for forming a semiconductor device according to the present disclosure. In some embodiments, one or more semiconductor processing tools (eg, one or more of the semiconductor processing tools 102-112) are used to perform Fig.14 Additionally or alternatively, Fig.14 One or more steps of may be performed by one or more components of device 1300 , such as processor 1320 , memory 1330 , input component 1340 , output component 1350 , and / or communication component 1360 .

[0247] like Fig.14 As shown, process 1400 may include forming a plurality of nanostructure layers along a direction perpendicular to the semiconductor substrate over a semiconductor substrate (step 1410). For example, a plurality of nanostructure layers (e.g., layer stack 305) may be formed over a semiconductor substrate 205 along a direction perpendicular to the semiconductor substrate (e.g., a Z direction) by one or more of semiconductor processing tools 102-112 as described in the present disclosure. In some embodiments, the plurality of nanostructure layers include a plurality of sacrificial layers (e.g., first layer 310) alternating with a plurality of channel layers (e.g., second layer 315).

[0248] Furthermore, if Fig.14 As shown, process 1400 may include forming a dummy gate structure over the plurality of nanostructure layers (step 1420). For example, dummy gate structure 505 may be formed over the plurality of nanostructure layers by one or more of semiconductor processing tools 102-112, as described herein.

[0249] Furthermore, if Fig.14 As shown, process 1400 may include removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure (step 1430). For example, portions of the plurality of nanostructure layers may be removed by one or more of the semiconductor processing tools 102-112 to form one or more recesses (e.g., source / drain recesses 705) adjacent to one or more sides of the dummy gate structure 505, as described herein.

[0250] Furthermore, if Fig.14 As shown, process 1400 may include forming one or more source / drain regions in one or more recesses (step 1440). For example, one or more source / drain regions 225 may be formed in one or more recesses (e.g., source / drain recesses 705) by one or more of semiconductor processing tools 102-112, as described in the present disclosure.

[0251] Furthermore, if Fig.14 As shown, process 1400 may include replacing the dummy gate structure and the portion of the sacrificial layer below the dummy gate structure with a metal gate structure after forming the one or more source / drain regions (step 1450). For example, after forming the one or more source / drain regions 225, the dummy gate structure 505 and the portion of the sacrificial layer below the dummy gate structure 505 may be replaced with a metal gate structure (e.g., gate structure 240) by one or more of the semiconductor processing tools 102-112, as described in the present disclosure. In some embodiments, the metal gate structure surrounds at least three sides of the channel layer.

[0252] Furthermore, if Fig.14 As shown, process 1400 may include removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region below the portion of the channel layer and extending above the semiconductor substrate to form an active region isolation groove (step 1460) after replacing the dummy gate structure and the portion of the sacrificial layer below the dummy gate structure with the metal gate structure. For example, after replacing the dummy gate structure and the portion of the sacrificial layer below the dummy gate structure with the metal gate structure, one or more of the semiconductor processing tools 102-112 may be used to remove a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region 210 below the portion of the channel layer 340 and extending above the semiconductor substrate 205 to form an active region isolation groove 1145, as described in the present disclosure.

[0253] Furthermore, if Fig.14 As shown, the process 1400 may include forming an active region isolation structure in the active region isolation cavity (step 1470). For example, the active region isolation structure 1115 may be formed in the active region isolation cavity 1145 by one or more of the semiconductor processing tools 102-112, as described herein.

[0254] Process 1400 may include other embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0255] In a first embodiment, process 1400 includes removing another portion of the metal gate structure to form a gate isolation groove in the metal gate structure before removing a portion of the metal gate structure to form an active region isolation groove 1145, and forming a gate isolation structure 1110 in the gate isolation groove before removing a portion of the metal gate structure to form the active region isolation groove 1145.

[0256] In the second embodiment (implemented alone or in combination with the first embodiment), removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210 includes removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210 based on the gate isolation structure 1110. In other words, removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210 includes removing a portion of the metal gate structure located between the gate isolation structures 1110, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210.

[0257] In a third embodiment (implemented alone or in combination with one or more of the first and second embodiments), process 1400 includes removing other portions of multiple metal gate structures to form multiple gate isolation grooves in the metal gate structure before removing portions of the metal gate structure to form active region isolation grooves 1145, and forming multiple gate isolation structures 1110 in the multiple gate isolation grooves before removing portions of the metal gate structure to form active region isolation grooves 1145.

[0258] In a fourth embodiment (implemented alone or in combination with one or more of the first to third embodiments), removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform region 210 includes removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform region 210 from between a plurality of gate isolation structures 1110.

[0259] In the fifth embodiment (implemented alone or in combination with one or more of the first to fourth embodiments), forming the active region isolation structure 1115 includes forming a dielectric liner 1155 on the sidewalls of multiple gate isolation structures 1110 in the active region isolation groove 1145, and filling the active region isolation groove 1145 with a dielectric layer 1160 above the dielectric liner 1155.

[0260] In a sixth embodiment (implemented alone or in combination with one or more of the first to fifth embodiments), forming a plurality of gate isolation structures 1110 includes forming a plurality of gate isolation structures 1110 such that the plurality of gate isolation structures 1110 extend across the metal gate structure in a first direction (e.g., the X direction), and forming an active region isolation structure 1115 includes forming an active region isolation structure 1115 such that the active region isolation structure 1115 extends along a second direction (e.g., the Y direction), and the metal gate structure extends along the second direction.

[0261] Although Fig.14 Exemplary steps of process 1400 are disclosed, but in some embodiments, process 1400 includes Fig.14 The more steps, fewer steps, different steps, or differently arranged steps. Additionally or alternatively, two or more steps of process 1400 may be performed together.

[0262] Fig.15 FIG. 1 is a flow chart of an exemplary process 1500 for forming a semiconductor device according to the present disclosure. In some embodiments, the process 1500 is performed by one or more semiconductor processing tools (eg, one or more of the semiconductor processing tools 102-112). Fig.15 Additionally or alternatively, Fig.15One or more steps of may be performed using one or more components of device 1300 , such as processor 1320 , memory 1330 , input component 1340 , output component 1350 , and / or communication component 1360 .

[0263] like Fig.15 As shown, process 1500 may include forming a plurality of nanostructure layers along a direction perpendicular to the semiconductor substrate over a semiconductor substrate (step 1510). For example, a plurality of nanostructure layers (e.g., layer stack 305) may be formed over a semiconductor substrate 205 along a direction perpendicular to the semiconductor substrate 205 (e.g., a Z direction) by one or more of semiconductor processing tools 102-112 as described in the present disclosure. In some embodiments, the plurality of nanostructure layers include a plurality of sacrificial layers (e.g., first layer 310) alternating with a plurality of channel layers (e.g., second layer 315).

[0264] Furthermore, if Fig.15 As shown, process 1500 may include forming a plurality of dummy gate structures over the plurality of nanostructure layers (step 1520). For example, a plurality of dummy gate structures 505 may be formed over the plurality of nanostructure layers by one or more of semiconductor processing tools 102-112, as described herein.

[0265] Furthermore, if Fig.15 As shown, process 1500 may include removing portions of multiple nanostructure layers to form one or more grooves adjacent to one or more sides of a virtual gate structure in a plurality of virtual gate structures (step 1530). For example, portions of multiple nanostructure layers may be removed by one or more of the semiconductor processing tools 102-112 to form one or more grooves (e.g., source / drain grooves 705) adjacent to one or more sides of a virtual gate structure 505 in a plurality of virtual gate structures 505, as described in the present disclosure.

[0266] Furthermore, if Fig.15 As shown, process 1500 may include forming one or more source / drain regions in one or more recesses (step 1540). For example, one or more source / drain regions 225 may be formed in one or more recesses (e.g., source / drain recesses 705) by one or more of semiconductor processing tools 102-112, as described in the present disclosure.

[0267] Furthermore, if Fig.15As shown, process 1500 may include replacing the plurality of dummy gate structures and portions of the sacrificial layer below the plurality of dummy gate structures with the plurality of metal gate structures after forming the one or more source / drain regions (step 1550). For example, after forming the one or more source / drain regions 225, the plurality of dummy gate structures 505 and portions of the sacrificial layer below the plurality of dummy gate structures 505 may be replaced with the plurality of metal gate structures (e.g., gate structures 240) by one or more of the semiconductor processing tools 102-112, as described herein. In some embodiments, the plurality of metal gate structures surround at least three sides of the channel layer.

[0268] Furthermore, if Fig.15 As shown, process 1500 may include forming a plurality of gate isolation structures spanning the plurality of metal gate structures after replacing the dummy gate structures and the portion of the sacrificial layer below the dummy gate structures with the metal gate structures (step 1560). For example, after replacing the dummy gate structures 505 and the portion of the sacrificial layer below the dummy gate structures 505, a plurality of gate isolation structures 1110 spanning the plurality of metal gate structures may be formed by one or more of semiconductor processing tools 102-112, as described in the present disclosure.

[0269] Furthermore, if Fig.15 As shown, the process 1500 may include removing a portion of a metal gate structure among the plurality of metal gate structures, a portion of a channel layer surrounded by the metal gate structure, and a platform region located below the portion of the channel layer and extending above the semiconductor substrate between the gate isolation structures to form an active region isolation recess (step 1570). For example, a portion of a metal gate structure among the plurality of metal gate structures, a portion of a channel layer surrounded by the metal gate structure, and a platform region 210 located below the portion of the channel layer and extending above the semiconductor substrate may be removed between the gate isolation structures 1110 by one or more of the semiconductor processing tools 102-112 to form an active region isolation recess 1145, as described in the present disclosure.

[0270] Furthermore, if Fig.15 As shown, the process 1500 may include forming an active region isolation structure in an active region isolation recess between gate isolation structures (step 1580). For example, an active region isolation structure 1115 may be formed in an active region isolation recess 1145 between gate isolation structures 1110 by one or more of the semiconductor processing tools 102-112, as described in the present disclosure.

[0271] Process 1500 may include other embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0272] In the first embodiment, removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210 includes: using the gate isolation structure 1110 as a self-aligned mask to etch a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210.

[0273] In a second embodiment (implemented alone or in combination with the first embodiment), removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform area 210 includes: performing a first etching step to remove the portion of the metal gate structure, and after the first etching step, performing a second etching step to remove the portion of the channel layer 340 surrounded by the metal gate structure and the platform area 210.

[0274] In a third embodiment (implemented alone or in combination with one or more of the first and second embodiments), process 1500 includes performing a third etching step to remove a portion of the hard mask layer 1105 over a portion of the metal gate structure prior to the first etching step.

[0275] In a fourth embodiment (implemented alone or in combination with one or more of the first to third embodiments), process 1500 includes forming a hard mask layer 1105 over the gate isolation structure 1110 before removing a portion of the metal gate structure, a portion of the channel layer 340 surrounded by the metal gate structure, and the platform region 210.

[0276] In the fifth embodiment (implemented alone or in combination with one or more of the first to fourth embodiments), forming the active region isolation structure 1115 includes: forming a dielectric liner 1155 in the active region isolation groove 1145, and filling the active region isolation groove 1145 with a dielectric layer 1160 above the dielectric liner 1155.

[0277] In a sixth embodiment (implemented alone or in combination with one or more of the first to fifth embodiments), forming the dielectric liner 1155 includes: forming the dielectric liner 1155 such that the dielectric liner 1155 is in direct contact with a sidewall of the gate isolation structure 1110 .

[0278] Although Fig.15 Exemplary steps of process 1500 are disclosed, but in some embodiments, process 1500 includes Fig.15 The more steps, fewer steps, different steps, or differently arranged steps. Additionally or alternatively, two or more steps of process 1500 may be performed together.

[0279] FIG. 16A to FIG. 16E1 is a schematic diagram of an exemplary embodiment 1600 of forming an active region isolation structure as described in the present disclosure. Exemplary embodiment 1600 includes an example of replacing a dummy gate structure 505 with a gate structure 240 (metal gate structure) of a semiconductor device 200 to form an active region isolation structure (e.g., a CMODE structure) in a semiconductor device 200 after a replacement gate process. An active region isolation structure 1115 may be formed along the gate structure 240 to establish an electrically isolated region in a stack of one or more mesa regions 210 and / or one or more nanostructure channels 220 below the gate structure 240. Thus, the active region isolation structure 1115 enables the underlying nanostructure channel 220 to be divided into a plurality of nanostructure channels 220 (electrically isolated from each other).

[0280] FIG. 16A to FIG. 16E is based on Fig. 7A The multiple cross-sectional lines shown include Fig. 7A BB cross-sectional line perspective view (eg, across multiple gate structures 240), and according to Fig. 7A 1000 (eg, along gate structure 240). In some embodiments, the related description steps of exemplary embodiment 1000 are shown in FIG. FIG. 3A to FIG. 10C Execute after the relevant description steps.

[0281] like Fig.16A As shown, FIG. 11A to FIG. 16D One or more steps described in the above may be performed to form an active region isolation recess 1145 between the gate isolation structures 1110. After etching the gate structure 240 and the high-k dielectric liner 1010, the nanostructure channel 220 between the gate isolation structures 1110 is exposed in the active region isolation recess 1145. In addition, after etching the gate structure 240 and the high-k dielectric liner 1010, a portion of the terrace region 210 below the nanostructure channel 220 between the gate isolation structures 1110 is exposed in the active region isolation recess 1145. In some embodiments, after etching the gate structure 240 and the high-k dielectric liner 1010, a wet cleaning step may be performed.

[0282] like Fig. 16B As shown, after etching the gate structure 240 and the high-k dielectric liner 1010, the nanostructure channel 220 between the gate isolation structures 1110 exposed in the active region isolation groove 1145 can be removed. In addition, the platform region 210 located below the nanostructure channel 220 in the active region isolation groove 1145 can be removed. FIG. 11A to FIG. 11I , the STI region 215 located between the gate isolation structures 1110 is also removed in the exemplary embodiment 1600, that is, Fig. 16BThis is because a low-selectivity etching technique is used, while the exemplary embodiment 1100 includes a high-selectivity etching technique, and therefore, in the exemplary embodiment 1100 , the STI region 215 between the gate isolation structures 1110 is retained.

[0283] The active region isolation groove 1145 extends downward and extends into the semiconductor substrate 205. Fig. 16B As shown, the bottom surface of the active region isolation recess 1145 can have regions with different profiles or segments. For example, segment 1605 can be raised above segment 1610, which may be caused by different etching rates between the platform region 210 and the STI region 215. In some embodiments, a RIE-coupled photolithography (RCP) process is configured to form the active region isolation recess 1145. The plasma can be a hydrogen bromide (HBr)-based plasma etchant, a chlorine (Cl2)-based plasma etchant, a boron trichloride (BCl3)-based plasma etchant, and / or other plasma-based etchants containing oxygen (O2) and / or carbon dioxide. Compared to the exemplary embodiment 1100, the concentration of BCl3 and / or Cl2 can be increased to reduce the etching selectivity between the platform region 210 (e.g., silicon) and the STI region 215 (e.g., silicon dioxide).

[0284] The plasma can be generated by an etching tool 108, such as an ICP tool, a resonant antenna plasma source driven by an RF power generator, and / or other types of plasma-based etching tools. A frequency of multiples of 13.56 MHz (e.g., 13.56 MHz, 27 MHz) can be configured in the RF power generator. The RF power generator can provide a power supply including about 100 watts to about 2500 watts, however, other numerical ranges are also within the scope of the present disclosure. Pulsed plasma etching can be performed with a duty cycle of about 10% to about 100%, however, other numerical ranges are also within the scope of the present disclosure. The RF bias power of the pedestal in the processing chamber of the etching tool 108 can be about 10 watts to about 2000 watts, however, other numerical ranges are also within the scope of the present disclosure. The pressure of the processing chamber of the etching tool 108 can be operated at about 3 mTorr to about 150 mTorr, however, other numerical ranges are also within the scope of the present disclosure. The temperature of the processing chamber of the etching tool 108 can be operated at about 20°C to about 150°C, however, other numerical ranges are also within the scope of the present disclosure.

[0285] like Fig. 16CAs shown, a dielectric liner 1155 of the active region isolation structure 1115 can be formed in the active region isolation groove 1145. The dielectric liner 1155 can be conformally deposited on the sidewalls of the active region isolation groove 1145 (corresponding to the sidewalls of the gate isolation structure 1110 that are exposed in the active region isolation groove 1145 and located below the active region isolation structure 1110) and on the bottom surface of the active region isolation groove 1145 (corresponding to the top surface of the semiconductor substrate 205). The deposition tool 102 can be used to use PVD technology, ALD technology, CVD technology, oxidation technology, such as Figure 1 The dielectric liner 1155 may be deposited by the other deposition techniques described above and / or other suitable deposition techniques. The dielectric liner 1155 may include a dielectric material, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a high-k dielectric material and / or another suitable dielectric material.

[0286] like Fig.16D As shown, a dielectric layer 1160 is filled in the active region isolation recess 1145 above and / or on the dielectric liner 1155 of the active region isolation structure 1115. The dielectric layer 1160 may be overfilled in the active region isolation recess 1145 to ensure that the active region isolation recess 1145 is completely filled with the dielectric layer 1160 and to minimize the formation of gaps or voids in the active region isolation structure 1115. The deposition tool 102 may be formed by PVD technology, ALD technology, CVD technology, oxidation technology, etc. Figure 1 The dielectric liner 1155 may be deposited by using the other deposition techniques and / or other deposition techniques described above. The dielectric liner 1155 may include a dielectric material, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), high-k dielectric materials and / or other suitable dielectric materials.

[0287] like Fig.16E As shown, after forming the layers of the active region isolation structure 1115, a planarization operation may be performed to planarize the semiconductor device 200. The planarization tool 110 may be used to planarize the semiconductor device 200 to remove the hard mask layer 1105, remove excess material of the dielectric liner 1155, and / or remove excess material of the dielectric layer 1160.

[0288] As mentioned above, FIG. 16A to FIG. 16EThe number and arrangement of steps and devices shown are provided as one or more examples. FIG. 16A to FIG. 16E There may be additional steps and devices, fewer steps and devices, different steps and devices, or differently arranged steps and devices than those shown.

[0289] In this way, after replacing the polysilicon dummy gate structure of the semiconductor device with a metal gate structure in the replacement gate process, a CMODE process can be performed to form a CMODE structure in the semiconductor device. The CMODE process described in the present disclosure includes removing a portion of the metal gate structure (as opposed to removing a portion of the polysilicon dummy gate structure) so that the CMODE structure can be formed in the groove created by removing the portion of the metal gate structure. The material used for the metal gate structure of the semiconductor device can be stronger and can better withstand the stress and strain when etching and forming the CMODE structure of the semiconductor device. Therefore, the CMODE process described in the present disclosure can reduce the possibility of stress release in the source / drain regions on the opposite sides of the CMODE structure, can reduce the possibility of deep loading in the semiconductor device, and / or can reduce the possibility of gate deformation, etc.

[0290] As described in more detail above, some embodiments described in the present disclosure provide a method for manufacturing a semiconductor device. The method includes forming a plurality of nanostructure layers above a semiconductor substrate in a direction perpendicular to the semiconductor substrate, wherein the nanostructure layers include a plurality of sacrificial layers alternating with a plurality of channel layers. The method includes forming a dummy gate structure above the plurality of nanostructure layers. The method includes removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure. The method includes forming one or more source / drain regions in the one or more recesses. The method includes replacing the dummy gate structure and portions of the sacrificial layer below the dummy gate structure with a metal gate structure after forming the one or more source / drain regions, wherein the metal gate structure surrounds at least three sides of the channel layer. The method includes removing a portion of the metal gate structure, portions of the channel layer surrounded by the metal gate structure, and a platform region below the portion of the channel layer and extending above the semiconductor substrate after replacing the dummy gate structure and portions of the sacrificial layer below the dummy gate structure with the metal gate structure to form an active region isolation recess. The method includes forming an active region isolation structure in the active region isolation recess. In some embodiments, the method further comprises the following steps: before removing a portion of the metal gate structure to form an active region isolation groove, removing another portion of the metal gate structure to form a gate isolation groove in the metal gate structure; and before removing a portion of the metal gate structure to form an active region isolation groove, forming a gate isolation structure in the gate isolation groove. In some embodiments, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region comprises: based on the gate isolation structure, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region. In some embodiments, the method further comprises the following steps: before removing a portion of the metal gate structure to form an active region isolation groove, removing multiple other portions of the metal gate structure to form multiple gate isolation grooves in the metal gate structure; and before removing a portion of the metal gate structure to form an active region isolation groove, forming multiple gate isolation structures in the gate isolation groove. In some embodiments, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region comprises: removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and a platform region from between the gate isolation structures. In some embodiments, forming the active region isolation structure includes: forming a dielectric liner on the sidewalls of some gate isolation structures in the active region isolation groove; and filling the active region isolation groove with a dielectric layer above the dielectric liner.In some embodiments, forming a gate isolation structure includes: forming a gate isolation structure so that the gate isolation structure extends in a first direction and crosses a metal gate structure; and, wherein forming an active region isolation structure includes: forming the active region isolation structure so that the active region isolation structure extends along a second direction and the metal gate structure extends along the second direction.

[0291] As described in more detail above, some embodiments described in the present disclosure provide a method for manufacturing a semiconductor device. The method includes forming a plurality of nanostructure layers above a semiconductor substrate in a direction perpendicular to the semiconductor substrate, wherein the plurality of nanostructure layers include a plurality of sacrificial layers alternating with a plurality of channel layers. The method includes forming a plurality of virtual gate structures above the plurality of nanostructure layers. The method includes removing portions of the plurality of nanostructure layers to form one or more grooves adjacent to one or more sides of a virtual gate structure among the plurality of virtual gate structures. The method includes forming one or more source / drain regions in the one or more grooves. The method includes replacing the virtual gate structure and a plurality of portions of the sacrificial layer located below the virtual gate structure with a plurality of metal gate structures after forming the one or more source / drain regions, wherein the plurality of metal gate structures surround at least three sides of the channel layer. The method includes forming a plurality of gate isolation structures spanning the metal gate structure after replacing the virtual gate structure and a portion of the sacrificial layer below the virtual gate structure with a metal gate structure. The method includes removing a portion of a metal gate structure of a plurality of metal gate structures, a plurality of portions of a channel layer surrounded by the metal gate structure, and a platform region located below a portion of the channel layer and extending above a semiconductor substrate between gate isolation structures to form an active region isolation groove. The method includes forming an active region isolation structure in an active region isolation groove located between gate isolation structures. In some embodiments, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and the platform region includes: etching a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and the platform region using the gate isolation structure as a self-aligned mask. In some embodiments, removing a portion of the metal gate structure, a portion of the channel layer surrounded by the metal gate structure, and the platform region includes: performing a first etching step to remove a portion of the metal gate structure; and, after the first etching step, performing a second etching process to remove a portion of the channel layer surrounded by the metal gate structure and the platform region. In some embodiments, the method further includes: performing a third etching step to remove a portion of the hard mask layer above a portion of the metal gate structure before the first etching step. In some embodiments, the method further comprises: forming a hard mask layer over the gate isolation structure before removing the portion of the metal gate structure, the portion of the channel layer surrounded by the metal gate structure, and the terrace region. In some embodiments, forming the active region isolation structure comprises: forming a dielectric liner in the active region isolation groove; and filling the active region isolation groove with a dielectric layer over the dielectric liner. In some embodiments, forming the dielectric liner comprises: forming the dielectric liner so that the dielectric liner is in direct contact with the sidewall of the gate isolation structure.

[0292] As described in more detail above, some embodiments described in the present disclosure provide a semiconductor device. The semiconductor device includes a plurality of first nanostructure channels extending above a first platform region and above a semiconductor substrate, wherein the plurality of first nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate. The semiconductor device includes a plurality of second nanostructure channels arranged above a second platform region and above the semiconductor substrate, wherein the plurality of second nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate. The semiconductor device includes a first metal gate structure surrounding each of the first nanostructure channels. The semiconductor device includes a second metal gate structure surrounding each of the second nanostructure channels. The semiconductor device includes a gate isolation structure arranged between the first metal gate structure and the second metal gate structure. The semiconductor device includes an active region isolation structure arranged between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on a sidewall of the gate isolation structure. In some embodiments, the first metal gate structure is in direct contact with another sidewall of the gate isolation structure. In some embodiments, the semiconductor device further includes another gate isolation structure, and is arranged between the active region isolation structure and the second metal gate structure. In some embodiments, the second metal gate structure is in direct contact with a sidewall of another gate isolation structure. In some embodiments, the dielectric liner of the active region isolation structure is in direct contact with another sidewall of another gate isolation structure. In some embodiments, the dielectric liner is located between the dielectric layer of the active region isolation structure and the gate isolation structure.

[0293] As used in the present disclosure, "satisfying a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold or not equal to a threshold, etc., depending on the context.

[0294] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced in the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A plurality of nanostructure layers are formed on a semiconductor substrate along a direction perpendicular to the semiconductor substrate. wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers; forming a dummy gate structure above the plurality of nanostructure layers; removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of the dummy gate structure; forming one or more source / drain regions in the one or more recesses; After forming the one or more source / drain regions, replacing the dummy gate structure and portions of the sacrificial layers below the dummy gate structure with a metal gate structure, wherein the metal gate structure surrounds at least three sides of each channel layer; After replacing the dummy gate structure and the portions of the sacrificial layer below the dummy gate structure with the metal gate structure, an active region isolation recess is formed, and forming the active region isolation recess includes removing: A portion of the metal gate structure, Portions of the plurality of channel layers surrounded by the metal gate structure, and a terrace region located below the portions of the channel layers and extending above the semiconductor substrate; as well as An active region isolation structure is formed in the active region isolation groove.

2. The method according to claim 1, characterized in that Further including: Before removing the portion of the metal gate structure to form the active region isolation groove, removing another portion of the metal gate structure to form a gate isolation groove in the metal gate structure; as well as Before removing the portion of the metal gate structure to form the active region isolation groove, a gate isolation structure is formed in the gate isolation groove.

3. The method according to claim 1, characterized in that Further including: Before removing the portion of the metal gate structure to form the active region isolation groove, removing a plurality of other portions of the metal gate structure to form a plurality of gate isolation grooves in the metal gate structure; as well as Before removing the portion of the metal gate structure to form the active region isolation groove, a plurality of gate isolation structures are formed in the plurality of gate isolation grooves.

4. A method for manufacturing a semiconductor device, characterized in that: include: A plurality of nanostructure layers are formed on a semiconductor substrate along a direction perpendicular to the semiconductor substrate. wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers; forming a plurality of dummy gate structures above the plurality of nanostructure layers; removing portions of the plurality of nanostructure layers to form one or more recesses adjacent to one or more sides of a dummy gate structure among the plurality of dummy gate structures; forming one or more source / drain regions in the one or more recesses; After forming the one or more source / drain regions, replacing the plurality of dummy gate structures and portions of the plurality of sacrificial layers below the plurality of dummy gate structures with a plurality of metal gate structures, wherein the plurality of metal gate structures surround the plurality of channel layers; After replacing the dummy gate structure and the portions of the sacrificial layers below the dummy gate structure with the metal gate structure, forming a plurality of gate isolation structures spanning the plurality of metal gate structures; Forming an active region isolation recess includes removing between the plurality of gate isolation structures: a portion of a metal gate structure of the plurality of metal gate structures, Portions of the plurality of channel layers surrounded by the metal gate structure, and a terrace region located below the portions of the channel layers and extending above the semiconductor substrate; as well as An active region isolation structure is formed in the active region isolation groove between the plurality of gate isolation structures.

5. The method according to claim 4, characterized in that The removal of the portion of the metal gate structure, the portions of the channel layers surrounded by the metal gate structure, and the platform region comprises: The portion of the metal gate structure, the portions of the channel layers surrounded by the metal gate structure, and the terrace region are etched using the gate isolation structures as a self-aligned mask.

6. The method according to claim 4, characterized in that The removal of the portion of the metal gate structure, the portions of the channel layers surrounded by the metal gate structure, and the platform region comprises: performing a first etching step to remove the portion of the metal gate structure; and After the first etching step, a second etching process is performed to remove the portions of the channel layers surrounded by the metal gate structure and the terrace region.

7. The method according to claim 4, characterized in that The active region isolation structure is formed by: forming a dielectric liner in the active region isolation groove; and The active region isolation groove is filled with a dielectric layer above the dielectric liner.

8. A semiconductor device, characterized in that: include: A plurality of first nanostructure channels are disposed above a first platform region and extend above a semiconductor substrate; wherein the plurality of first nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate; A plurality of second nanostructure channels are disposed above a second platform region and extend above the semiconductor substrate; wherein the plurality of second nanostructure channels are arranged along a direction perpendicular to the semiconductor substrate; a first metal gate structure surrounding each of the first nanostructure channels; a second metal gate structure surrounding each of the second nanostructure channels; a gate isolation structure disposed between the first metal gate structure and the second metal gate structure; and An active region isolation structure is disposed between the gate isolation structure and the second metal gate structure, wherein a dielectric liner of the active region isolation structure is directly included on a side wall of the gate isolation structure.

9. The semiconductor device according to claim 8, wherein: The first metal gate structure is in direct contact with another sidewall of the gate isolation structure.

10. The semiconductor device according to claim 8, wherein Further including: Another gate isolation structure is disposed between the active region isolation structure and the second metal gate structure.

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