Integrated chip and forming method thereof

Abstract

Various embodiments of the present disclosure are directed to an integrated chip having an interconnect structure over a substrate. The interconnect structure includes a conductive line disposed in the dielectric structure. The wire includes a body structure. A passivation structure overlies the interconnect structure. A bond pad is over the passivation structure. The bond pad includes an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive line. The lower bonding structures each include a vertical bonding structure and a diffusion barrier layer disposed along a lower surface and opposite sidewalls of the vertical bonding structure. The upper pad structure includes a first conductive layer vertically stacked with a second conductive layer. The embodiment of the invention also relates to an integrated chip and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated chip and a method for forming the same. Background Art

[0002] The semiconductor industry has been continuously improving the processing power and power consumption of integrated chips by reducing the minimum component size. However, in recent years, process limitations have made it difficult to continue to reduce the minimum component size. Stacking two-dimensional (2D) integrated chips into three-dimensional (3D) integrated chips has become a potential method for continuing to improve the processing power and power consumption of integrated chips. Bonding pads are used to electrically couple the stacked 2D integrated chips together. Summary of the invention

[0003] Some embodiments of the present application provide an integrated chip, comprising: an interconnect structure, located on a substrate and comprising a conductive line arranged in a dielectric structure, wherein the conductive line comprises a main structure; a passivation structure, located on the interconnect structure; and a bonding pad, located above the passivation structure, wherein the bonding pad comprises an upper pad structure located on the passivation structure and a plurality of lower bonding structures extending through the passivation structure to the conductive line, wherein the lower bonding structures respectively comprise a vertical bonding structure and a diffusion barrier layer arranged along a lower surface and relative side walls of the vertical bonding structure, wherein the upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer.

[0004] Other embodiments of the present application provide an integrated chip, comprising: a semiconductor device, disposed on a semiconductor substrate; an interconnect structure, located above the semiconductor substrate, wherein the interconnect structure comprises a conductive line electrically coupled to the semiconductor device; a passivation structure, located above the interconnect structure; and a bonding pad, disposed on the passivation structure and electrically coupled to the conductive line, wherein the bonding pad comprises an upper pad structure and a plurality of lower bonding structures disposed in the passivation structure, wherein the upper pad structure comprises a first conductive layer and a second conductive layer located above the first conductive layer, wherein the lower bonding structure comprises a vertical bonding structure and a diffusion barrier layer laterally surrounding the vertical bonding structure, wherein the first conductive layer directly contacts the top surfaces of the vertical bonding structure and the diffusion barrier layer, and wherein the vertical bonding structure comprises copper.

[0005] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming an interconnect structure above a semiconductor substrate, wherein the interconnect structure includes a conductive line; depositing a passivation structure above the interconnect structure; patterning the passivation structure to form a plurality of openings in the passivation structure above the conductive line; depositing a diffusion barrier layer lining the openings above the passivation structure; forming a vertical bonding structure filling the openings above the diffusion barrier layer, wherein the diffusion barrier layer laterally wraps the vertical bonding structure, wherein the vertical bonding structure and the conductive line include a first material; and forming an upper pad structure above the vertical bonding structure, wherein the upper pad structure includes a first conductive layer located on the vertical bonding structure and a second conductive layer located above the first conductive layer, wherein an outer sidewall of the first conductive layer is aligned with an outer sidewall of the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip including a bonding pad having an upper pad structure and a plurality of lower bonding structures configured to reduce contact resistance and increase reliability of the integrated chip are shown.

[0008] FIG. 2A to FIG. 2D Shows Figure 1 Cross-sectional views of some other embodiments of integrated chips.

[0009] Figure 2E Shows Figure 2D A top view of some embodiments of an integrated chip.

[0010] Figure 3A and Figure 3B Cross-sectional views of some embodiments of an integrated chip including a plurality of bonding pads disposed over an interconnect structure are shown.

[0011] Figure 4A and Figure 4B Cross-sectional views of some embodiments of a stacked integrated chip structure with an upper semiconductor die bonded to a bond pad of the semiconductor die are shown.

[0012] Figures 5 to 16 Cross-sectional views of some embodiments of methods of forming an integrated chip including a bonding pad having an upper pad structure and a plurality of lower bonding structures configured to reduce contact resistance and increase reliability of the integrated chip are shown.

[0013] Figures 17 to 20 Cross-sectional views of some embodiments of methods of forming a stacked integrated chip structure having an upper semiconductor die bonded to a bonding pad of the semiconductor die are shown.

[0014] Fig.21 A flow chart illustrating some embodiments of a method of forming a stacked integrated chip structure having an upper semiconductor die bonded to a bond pad of the semiconductor die. DETAILED DESCRIPTION

[0015] The present disclosure provides many different embodiments or examples for realizing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] Typically, the semiconductor die includes an interconnect structure located above the substrate. A passivation structure is located above the interconnect structure, and a plurality of bonding pads are disposed within the passivation structure and coupled to wires in the interconnect structure. One or more semiconductor devices (e.g., transistors, varactors, resistors, capacitors, etc.) are disposed in, on, or above the substrate and are electrically coupled to the bonding pads through the interconnect structure. The bonding pads are configured to facilitate electrical coupling to a printed circuit board (PCB), a micro light emitting diode (LED) die, or another semiconductor die through, for example, a metal bonding process.

[0018] Each bonding pad may include an upper pad structure and one or more lower bonding structures. The upper pad structure is arranged along the upper surface of the passivation structure. One or more lower bonding structures extend from the upper pad structure through the passivation structure to the corresponding line in the interconnect structure. The bonding pad may have a variety of different configurations. For example, the upper pad structure and one or more lower bonding structures of the bonding pad are a single continuous structure including a first material (e.g., aluminum). However, in such a configuration, the upper pad structure is too thick for applications requiring a low profile (e.g., too thick for micro-LED applications). In addition, when exposed to an etchant (e.g., steam hydrogen fluoride) for preparing a bonding pad for a metal bonding process, the first material (e.g., aluminum) is prone to delamination and / or stress. For example, before the metal bonding process, the etchant may be used to remove the dielectric above and / or around the bonding pad. In another example, one or more lower bonding structures of the bonding pad may include a second material (e.g., tungsten), which may be different from the material of the upper pad structure. However, in such embodiments, the second material (e.g., tungsten) has a relatively high resistance (e.g., greater than the resistance of the wire), which increases the contact resistance between the one or more semiconductor devices and the PCB, the micro-LED die, or another semiconductor die, thereby reducing the performance and reliability of the semiconductor die.

[0019] Various embodiments of the present application are directed to an integrated chip including a bonding pad configured to reduce the contact resistance and height of the integrated chip. The integrated chip includes one or more semiconductor devices disposed on and / or within a substrate. The interconnect structure is located above the substrate and electrically coupled to the one or more semiconductor devices. The passivation structure is located above the interconnect structure. The bonding pad is disposed in the passivation structure and electrically coupled to the interconnect structure. The bonding pad includes an upper pad structure above the passivation structure and a lower bonding structure extending from the upper pad structure to a line in the interconnect structure. The lower bonding structure includes a vertical bonding structure and a diffusion barrier layer disposed along the relative sidewalls and lower surface of the vertical bonding structure, respectively. The vertical bonding structure includes a first conductive material (e.g., copper) having a relatively low resistance (e.g., lower than the resistance of tungsten). The vertical bonding structure having a relatively low resistance reduces the contact resistance between the bonding pad and another semiconductor structure (e.g., a micro LED die, another semiconductor die, etc.) bonded to the bonding pad. This increases the performance and reliability of the integrated chip.

[0020] In addition, the upper pad structure includes multiple conductive layers having one or more second conductive materials (e.g., titanium, tantalum nitride) different from the first conductive material. The upper pad structure having a conductive layer helps to reduce the height of the bonding pad. In addition, when exposed to an etchant (e.g., vapor hydrogen fluoride) used to prepare the bonding pad for the bonding process, the one or more second conductive materials of the conductive layer are not prone to delamination and / or stress. Therefore, the bonding pad helps to reduce the overall height of the integrated chip for applications requiring a low profile (e.g., in micro LED applications), and further increases the stability and reliability of the integrated chip.

[0021] Figure 1 Cross-sectional views of some embodiments of an integrated chip 100 are shown that include a bonding pad 120 having an upper pad structure 124 and a plurality of lower bonding structures 122 configured to reduce contact resistance and increase reliability of the integrated chip 100 .

[0022] The integrated chip 100 includes a semiconductor device 104 disposed in and / or on a semiconductor substrate 102 (e.g., a silicon substrate). An interconnect structure 106 is disposed on a front side surface 102f of the semiconductor substrate 102. The semiconductor device 104 may be or include, for example, a transistor, a varactor, a resistor, a capacitor, a doped active region of the semiconductor substrate 102, or some other suitable semiconductor device.

[0023] The interconnect structure 106 includes a plurality of conductive interconnect layers arranged within an interconnect dielectric structure 108. The plurality of conductive interconnect layers include a plurality of conductive contacts 110, a plurality of conductive lines 112, and a plurality of conductive vias 113 stacked vertically on each other. The conductive lines 112 are configured to provide lateral connections (i.e., connections parallel to the upper surface of the semiconductor substrate 102), while the conductive vias 113 and the conductive contacts 110 are configured to provide vertical connections between the conductive lines 112. The interconnect structure 106 includes a topmost conductive line 112t having a top surface aligned with a top surface of the interconnect dielectric structure 108. The semiconductor device 104 is electrically coupled to the interconnect layers of the interconnect structure 106.

[0024] The passivation structure 114 is disposed along the upper surface of the interconnect structure 106. The passivation structure 114 includes a first passivation layer 116 vertically stacked with a second passivation layer 118. The bonding pad 120 is located above the interconnect structure 106. The bonding pad 120 includes an upper pad structure 124 disposed on the top surface of the passivation structure 114 and a plurality of lower bonding structures 122 extending continuously from the upper pad structure 124 to the conductive structure in the interconnect structure 106. In some embodiments, the plurality of lower bonding structures 122 directly contact the topmost wire 112t and are electrically coupled to the topmost wire 112t. The bonding pad 120 is configured to electrically couple the semiconductor device 104 to another semiconductor die (not shown). The protective layer 134 is disposed along the top surface of the passivation structure 114 and along the opposite sidewalls of the upper pad structure 124.

[0025] The passivation structure 114 includes a pair of opposing sidewalls defining a trench extending through the height of the passivation structure 114. The lower bonding structure 122 is disposed within a corresponding trench in the passivation structure 114. In addition, the lower bonding structure 122 includes a vertical bonding structure 128 and a diffusion barrier layer 126, respectively. The diffusion barrier layer 126 is disposed around the lower surface and opposing sidewalls of the vertical bonding structure 128. In various embodiments, the vertical bonding structure 128 includes a first conductive material (e.g., copper) having a relatively low resistivity. In some embodiments, the resistivity of the first conductive material is less than the resistivity of tungsten (e.g., less than 5.6*10 -8 Ohm-meter (Ω·m). The lower bonding structure 122 including the vertical bonding structure 128 having a relatively low resistivity reduces the contact resistance between the bonding pad 120 and another semiconductor die (not shown). This increases the performance and reliability of the integrated chip 100. In addition, the diffusion barrier layer 126 is configured to mitigate the diffusion of the first conductive material (e.g., copper) from the vertical bonding structure 128 to adjacent structures of the integrated chip 100. Therefore, the stability and reliability of the integrated chip 100 are increased.

[0026] In some embodiments, the upper pad structure 124 includes a first conductive layer 130 vertically stacked with a second conductive layer 132. The first conductive layer 130 includes a second conductive material (e.g., titanium nitride, tantalum nitride) configured to mitigate the diffusion of the first conductive material (e.g., copper) from the lower bonding structure 122. In various embodiments, the bottom surface of the first conductive layer 130 directly contacts the top surface of the vertical bonding structure 128 and the top surface of the diffusion barrier layer 126. In some embodiments, the first conductive layer 130 can be configured as and / or referred to as an upper diffusion barrier layer. In addition, the second conductive layer 132 includes a third conductive material (e.g., titanium, platinum) different from the first conductive material and the second conductive material. The second conductive layer 132 is configured to mitigate damage to the underlying layers and / or structures of the bonding pad 120 from an etchant (e.g., vapor hydrogen fluoride) used to prepare the integrated chip 100 for the bonding process. This partially mitigates delamination and / or stress on the layers of the bonding pad 120. In addition, the upper pad structure 124 having the first conductive layer 130 and the second conductive layer 132 helps to precisely control and / or reduce the height of the bonding pad 120. Therefore, since the bonding pad 120 has the lower bonding structure 122 with relatively low resistivity and the upper pad structure 124 configured to reduce the diffusion of the first material (e.g., copper) and mitigate damage from the etchant during the manufacturing process, the contact resistance of the integrated chip 100 is reduced, and the performance and reliability of the integrated chip are increased.

[0027] Figure 2A Shows the corresponding Figure 1 200 a of some embodiments of the integrated chip 100 of some other embodiments.

[0028] The integrated chip 200a includes an interconnect structure 106 located above a semiconductor substrate 102. The semiconductor substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), silicon, germanium, silicon germanium, one or more epitaxial silicon layers, a silicon-on-insulator (SOI) substrate, or some other suitable substrate. The semiconductor device 104 is disposed in and / or on the semiconductor substrate 102. In some embodiments, the semiconductor device 104 may be configured as a transistor. In such an embodiment, the semiconductor device 104 includes a source / drain region 202 disposed in the semiconductor substrate 102, a gate electrode 206 above the semiconductor substrate 102 between the source / drain regions 202, a gate dielectric layer 204 below the gate electrode 206, and a sidewall spacer structure 208 disposed along the sidewalls of the gate electrode 206 and the gate dielectric layer 204. The source / drain region may refer to a source or a drain, individually or collectively depending on the context.

[0029] The interconnect structure 106 is disposed along the front side surface 102f of the semiconductor substrate 102. The interconnect structure 106 includes a plurality of conductive contacts 110, a plurality of conductive wires 112, and a plurality of conductive vias 113 disposed within an interconnect dielectric structure 108. The plurality of conductive wires 112 include a topmost conductive wire 112t. The plurality of conductive wires 112, the plurality of conductive vias 113, and the plurality of conductive contacts may be, for example, or include copper, aluminum, aluminum copper, tungsten, some other conductive material, etc. The interconnect dielectric structure 108 includes a plurality of dielectric layers stacked vertically on each other. The plurality of dielectric layers may be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, silicon nitride, silicon carbide, another dielectric material, or any combination of the foregoing materials.

[0030] The passivation structure 114 is located above the interconnect structure 106. The passivation structure 114 includes a first passivation layer 116 disposed on the interconnect structure 106 and a second passivation layer 118 above the first passivation layer 116. The first passivation layer 116 may be, for example, or include silicon nitride, silicon carbide, another dielectric material, or any combination of the above materials. In some embodiments, the thickness of the first passivation layer 116 is about 3000 angstroms, in the range of about 2500 to 3500 angstroms, or some other suitable value. The second passivation layer 118 may be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, another dielectric material, or any combination of the above materials. In various embodiments, the thickness of the second passivation layer 118 is about 5500 angstroms, in the range of about 5000 to 6000 angstroms, or some other suitable value.

[0031] The bonding pad 120 is located above the passivation structure 114 and contacts the topmost wire 112t. The bonding pad 120 is configured to electrically couple the semiconductor device 104 to another semiconductor die (not shown) through the interconnect structure 106. The bonding pad 120 includes an upper pad structure 124 disposed along the passivation structure 114 and a plurality of lower bonding structures 122 extending from the upper pad structure 124 to the interconnect structure 106. The bonding pad 120 and the semiconductor device 104 are disposed in the semiconductor die region of the semiconductor substrate 102. The isolation trench 218 is adjacent to the semiconductor die region and extends through the passivation structure 114, the interconnect structure 106, and at least a portion of the semiconductor substrate 102. In some embodiments, the isolation trench 218 is disposed along and / or defines a scribe line, wherein a segmentation process may be performed along the isolation trench 218 to segment the semiconductor die region. The protective layer 134 is disposed along the sidewalls of the upper pad structure 124 and lines the isolation trench 218. In a further embodiment, a dielectric layer 220 is located above the protective layer 134 and fills the isolation trench 218. The dielectric layer 220 may be, for example, or include an oxide such as silicon dioxide or some other suitable material. In a further embodiment, the dielectric layer 220 may be omitted (not shown). The protective layer 134 may be, for example, or include a metal oxide such as aluminum oxide or some other dielectric material. The thickness of the protective layer 134 may be, for example, about 400 angstroms, in the range of about 350 to 450 angstroms, or some other suitable value.

[0032] The lower bonding structure 122 includes a vertical bonding structure 128 and a diffusion barrier layer 126. In some embodiments, the diffusion barrier layer 126 continuously and laterally wraps around the periphery of the vertical bonding structure 128. In further embodiments, when viewed in cross section, the diffusion barrier layer 126 is U-shaped and extends along the opposite sidewalls and bottom surface of the vertical bonding structure 128. In further embodiments, the top surface of the vertical bonding structure 128 is vertically aligned with the top surface of the diffusion barrier layer 126 and the top surface of the passivation structure 114. The vertical bonding structure 128 includes a relatively low resistivity (e.g., less than about 5.6*10 -8 Ω·m). The vertical bonding structure 128 with relatively low resistivity reduces the contact resistance between the bonding pad 120 and another semiconductor die (not shown), thereby increasing the performance of the integrated chip. In some embodiments, the vertical bonding structure 128 is composed of copper or substantially composed of copper. In various embodiments, the vertical bonding structure 128 is a single structure including a single continuous material (e.g., copper). In some embodiments, the conductive line 112 and the conductive via 113 include a first conductive material (e.g., copper).

[0033] In some embodiments, the first conductive material (e.g., copper) of the vertical bonding structure 128 may have a high probability of outward diffusion to adjacent structures (e.g., the passivation structure 114). The diffusion of the first conductive material away from the lower bonding structure 122 may result in leakage current, degradation of adjacent dielectric materials, and reduced stability and reliability. In various embodiments, the diffusion barrier layer 126 includes a second conductive material configured to mitigate the diffusion of the first conductive material from the vertical bonding structure 128. Therefore, the diffusion barrier layer 126 including the second conductive material and disposed around and below the vertical bonding structure 128 mitigates or prevents the diffusion of the first conductive material from the vertical bonding structure 128, thereby increasing the stability and reliability of the integrated chip. In some embodiments, the second conductive material of the diffusion barrier layer 126 may be, for example, or include tantalum, tantalum nitride, titanium, titanium nitride, some other conductive material, or any combination of the foregoing materials. In further embodiments, the first conductive material of the vertical bonding structure 128 is different from the second conductive material of the diffusion barrier layer 126.

[0034] The thickness 216 of the diffusion barrier layer 126 is, for example, about 50 angstroms, in the range of about 10 to 250 angstroms, or some other suitable value. The height 214 of the vertical bonding structure 128 is, for example, in the range of about 8,000 to 10,000 angstroms, or some other suitable value. In some embodiments, the height 214 of the vertical bonding structure 128 is greater than 8,000 angstroms to maintain or increase the structural integrity of the bonding pad 120. In further embodiments, the height 214 of the vertical bonding structure 128 is less than 10,000 angstroms to help the lower bonding structure 122 provide a good vertical electrical connection between the interconnect structure 106 and the upper pad structure 124, while helping the height 215 of the bonding pad 120 to be relatively low for applications requiring a low profile. In addition, the diffusion barrier layer 126 has a thickness 216 along the opposite sidewalls of the vertical bonding structure 128. In some embodiments, the width of the vertical bonding structure 128 is greater than the thickness 216 of the diffusion barrier layer 126. This helps the overall resistivity of the lower bonding structure 122 to be relatively low. In some embodiments, the height 215 of the bonding pad 120 is in the range of about 8,300 to 14,250 angstroms or some other suitable value. In further embodiments, the height 211 of the lower bonding structure 122 is greater than the height 213 of the upper pad structure 124. Thus, a good vertical electrical connection between the interconnect structure 106 and the bonding pad 120 can be achieved while reducing the height 215 of the bonding pad 120.

[0035] In some embodiments, the upper pad structure 124 includes a first conductive layer 130 above the lower bonding structure 122 and a second conductive layer 132 located above the first conductive layer 130. In some embodiments, the outer sidewall of the first conductive layer 130 is aligned with the outer sidewall of the second conductive layer 132. The first conductive layer 130 includes a third conductive material, and the second conductive layer 132 includes a fourth conductive material. In some embodiments, the third conductive material is different from the fourth conductive material. In various embodiments, the first conductive layer 130 directly contacts the entire top surface of the lower bonding structure 122 and extends continuously above the entire top surface of the lower bonding structure 122. The first conductive layer 130 is configured to mitigate the diffusion of the first conductive material (e.g., copper) from the vertical bonding structure 128, thereby further increasing the reliability and durability of the integrated chip. The second conductive layer 132 is configured to mitigate damage to the underlying layers and / or structures of the bonding pad 120 from an etchant (e.g., vapor hydrogen fluoride) used to prepare the bonding pad 120 for the bonding process. In addition, the protective layer 134 extending along the opposite sidewalls of the upper pad structure 124 and including a metal oxide (e.g., aluminum oxide) further reduces damage to the bonding pad 120 from the etchant. Therefore, damage (e.g., delamination and / or stress) to the bonding pad 120 is reduced, thereby further increasing the reliability and durability of the integrated chip. Therefore, the bonding pad 120 including the upper pad structure 124 and the lower bonding structure 122 configured as shown and / or described above increases the overall performance of the integrated chip.

[0036] The third conductive material of the first conductive layer 130 may be, for example, or include tantalum, tantalum nitride, titanium, titanium nitride, some other conductive material, or any combination of the foregoing materials. In various embodiments, the third conductive material of the first conductive layer 130 is the same as the second conductive material of the diffusion barrier layer 126. The fourth conductive material of the second conductive layer 132 may be, for example, or include titanium, platinum, or some other suitable conductive material. In various embodiments, the first conductive material is different from the second conductive material, the third conductive material, and the fourth conductive material. In further embodiments, the fourth conductive material is different from the second conductive material and the third conductive material. In some embodiments, the resistivity of the vertical bonding structure 128 is less than the total resistivity of the upper pad structure 124. In further embodiments, the total resistivity of the lower bonding structure 122 is less than the total resistivity of the upper pad structure 124.

[0037] The thickness 212 of the first conductive layer 130 is, for example, about 600 angstroms, in the range of about 200 to 1000 angstroms, or some other suitable value. In some embodiments, the thickness 212 being greater than 200 angstroms helps the first conductive layer 130 mitigate the diffusion of the first conductive material from the vertical bonding structure 128. In further embodiments, the thickness 212 being less than about 1000 angstroms helps the bonding pad 120 have a relatively low total resistivity. The thickness 210 of the second conductive layer 132 is, for example, about 500 angstroms, in the range of about 100 to 1000 angstroms, or some other suitable value. In various embodiments, the thickness 210 being greater than 100 angstroms helps mitigate damage to the layer of the bonding pad 120 below the second conductive layer 132 from an etchant (e.g., vapor hydrogen fluoride). In further embodiments, the thickness 210 being less than 1000 angstroms helps the bonding pad 120 have a relatively low total resistivity. In some embodiments, the thickness 212 of the first conductive layer 130 is greater than the thickness 210 of the second conductive layer 132. In further embodiments, the height 214 of the vertical bonding structure 128 is greater than the height of the upper pad structure 124 .

[0038] Figure 2B Shows the corresponding Figure 2A 200a of the integrated chip 200a and some other embodiments of the integrated chip 200b, wherein the semiconductor device 104 is or includes a device structure 222 disposed in and / or on the semiconductor substrate 102. In various embodiments, the device structure 222 may be or include one or more doped regions disposed in the semiconductor substrate 102 (e.g., doped contact regions or doped regions of the semiconductor device 104, such as doped capacitor regions, doped source / drain regions, doped waveguide regions, etc.), semiconductor materials disposed in the semiconductor substrate 102 (e.g., germanium, epitaxial silicon, etc.), etc.

[0039] Figure 2C Shows the corresponding Figure 2A 200a of the integrated chip 200c of some other embodiments, wherein the upper pad structure also includes a third conductive layer 224 disposed between the first conductive layer 130 and the second conductive layer 132. In some embodiments, the third conductive layer 224 may be, for example, or include titanium nitride, tantalum, copper, silver, another conductive material, or any combination of the above materials. The thickness 226 of the third conductive layer 224 may be, for example, about 100 angstroms, in the range of about 100 to 1000 angstroms, or some other suitable value. In various embodiments, the thickness 210 of the second conductive layer 132 is in the range of about 300 to 1000 angstroms or some other suitable value. In some embodiments, the thickness 212 of the first conductive layer 130 is less than the thickness 210 of the second conductive layer 132, and the thickness 212 of the first conductive layer 130 is greater than the thickness 226 of the third conductive layer 224.

[0040] Figure 2D and Figure 2E Shows the corresponding Figure 2A sectional views and top views of some other embodiments of the integrated chip 200a and some embodiments of the integrated chip 200d. Figure 2D Shown along Figure 2E The top view is a cross-sectional view of the integrated chip taken along the line A-A'. Figure 2E In the top view of FIG. 1 , the upper pad structure 124 is represented by a dotted box.

[0041] like Figure 2D As seen in the cross-sectional view of FIG. 1 , the protection layer 134 extends continuously along the top surface of the upper pad structure 124, and the dielectric layer 220 is located above the bonding pad 120. In addition, the width of the topmost conductive line 112t is smaller than the width of the upper pad structure 124. Figure 2E As seen in the top view of FIG. 1 , the diffusion barrier layer 126 continuously laterally wraps around the periphery of the vertical bonding structure 128. Furthermore, in some embodiments, when viewed in the top view, the vertical bonding structure 128 is elongated in a first direction (e.g., along the y-axis), such that a length 230 of the vertical bonding structure 128 is greater than a width 232 of the vertical bonding structure 128.

[0042] Figure 3A FIG. 4 shows a cross-sectional view of some embodiments of an integrated chip 300a including a plurality of bonding pads 120 disposed above an interconnect structure 106. The bonding pads 120 may be as shown in FIG. Figure 1 , Figure 2A , Figure 2B , Figure 2C or Figure 2D The configuration shown and / or described in .

[0043] The integrated chip 300a includes a semiconductor die 301, wherein a plurality of bonding pads 120 and a semiconductor device 104 are part of the semiconductor die 301. In addition, the semiconductor die 301 is spaced apart between isolation trenches 218, wherein other semiconductor dies (not shown) are disposed on the semiconductor substrate 102 on opposite sides of the semiconductor die 301. In various embodiments, the isolation trenches 218 are disposed along and / or define spaced apart scribe lines on opposite sides of the semiconductor die 301. The protection layer 134 lines the isolation trenches 218, and the dielectric layer 220 fills the isolation trenches 218 and is located above the bonding pads 120.

[0044] The interconnect structure 106 is disposed on the semiconductor substrate 102 and electrically couples the semiconductor device 104 to a plurality of bonding pads 120. The interconnect structure 106 includes a plurality of conductive interconnect layers arranged within an interconnect dielectric structure. The interconnect dielectric structure includes an interlayer dielectric (ILD) layer 302, a plurality of intermetallic dielectric (IMD) layers 304, and a plurality of etch stop layers 306. The ILD layer 302 and the IMD layer 304 may be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, low-k dielectric material, some other dielectric material, or any combination of the above materials. The etch stop layer 306 may be, for example, or include silicon nitride, silicon carbide, another dielectric material, etc.

[0045] The plurality of conductive interconnect layers include a plurality of conductive contacts 110, a plurality of conductive lines 112, and a plurality of conductive vias 113 stacked vertically on each other. The conductive lines 112 and the conductive vias 113 include a conductive body 310 and a lower diffusion barrier layer 308 disposed along the sidewalls and lower surfaces of the conductive body 310, respectively. The interconnect structure 106 includes a topmost conductive line 112t disposed at the top of the interconnect structure 106. The conductive body 310 may be, for example, or include copper, aluminum, aluminum copper, tungsten, some other conductive material, etc. The lower diffusion barrier layer 308 may be, for example, or include tantalum, tantalum nitride, titanium, titanium nitride, some other conductive material, or any combination of the above materials.

[0046] In some embodiments, both the electrical conductor 310 and the vertical bonding structure 128 include a first material (e.g., copper). In further embodiments, the vertical bonding structure 128 includes a first material (e.g., copper), and the electrical conductor 310 includes a second material (e.g., aluminum) different from the first material. In such embodiments, the resistivity of the vertical bonding structure 128 is less than the resistivity of the electrical conductor 310. In various embodiments, both the diffusion barrier layer 126 and the lower diffusion barrier layer 308 include a third material (e.g., titanium nitride or tantalum nitride). In still further embodiments, the diffusion barrier layer 126 includes a third material (e.g., titanium nitride), and the lower diffusion barrier layer 308 includes a fourth material (e.g., tantalum nitride) different from the third material.

[0047] Figure 3B Shows the corresponding Figure 3A sectional views of some other embodiments of the integrated chip 300a and some embodiments of the integrated chip 300b, wherein the dielectric layer ( Figure 3A In some embodiments, the protection layer 134 is offset relative to the top surface of the bonding pad 120.

[0048] Figure 4A A cross-sectional view of some embodiments of a stacked integrated chip structure 400a having an upper semiconductor die 404 bonded to a semiconductor die 301 is shown. In some embodiments, the semiconductor die 301 is Figure 3A or Figure 3B The configuration shown and / or described in .

[0049] In some embodiments, the upper semiconductor die 404 is configured as a micro LED die and may include a plurality of LEDs disposed on an upper substrate (not shown), a plurality of vertical cavity surface emitting lasers (VCSELs) disposed on an upper substrate (not shown), other suitable light emitting devices, or any combination thereof. A plurality of bonding bumps 402 are disposed between the upper semiconductor die 404 and the bonding pad 120. The bonding bumps 402 help to bond the upper semiconductor die 404 to the plurality of bonding pads 120. The device (not shown) of the upper semiconductor die 404 is electrically coupled to the semiconductor device 104 via the bonding bumps 402 and the bonding pads 120. In various embodiments, the bonding bumps 402 directly contact the top surface of the corresponding bonding pads 120. The plurality of bonding bumps 402 may be solder bumps or solder balls. In some embodiments, the bonding bumps 402 may be, for example, or include gold, silver, tin, lead, some other suitable material, or any combination thereof. In various embodiments, the protective layer 134 directly contacts the sidewalls of the bonding bumps 402.

[0050] Figure 4B Shows the corresponding Figure 4A 1 and 10. In various embodiments, the semiconductor die 301 is singulated from other semiconductor dies (not shown) disposed in other regions of the semiconductor substrate 102. In some embodiments, after the singulation process, at least a portion of the protection layer 134 extends vertically along opposite sidewalls of the passivation structure 114, opposite sidewalls of the interconnect structure 106, and opposite sidewalls of the semiconductor substrate 102.

[0051] Figures 5 to 16 Cross-sectional views 500-1600 of some embodiments of methods of forming an integrated chip including a bonding pad having an upper pad structure and a plurality of lower bonding structures configured to reduce contact resistance and increase reliability of the integrated chip are shown. Figures 5 to 16 The cross-sectional views 500-1600 shown in the drawings are described with reference to the method, but it should be understood that Figures 5 to 16 The structure shown in is not limited to this method, but can exist independently of this method. Figures 5 to 16 Described as a series of steps, it should be understood that these steps are not limiting, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0052] like Figure 5As shown in the cross-sectional view 500 of FIG. 1 , a semiconductor device 104 is formed in and / or on the semiconductor substrate 102. In some embodiments, the semiconductor device 104 may be or include, for example, a transistor, a varactor, a resistor, a capacitor, a doped region of the semiconductor substrate 102, or some other suitable semiconductor device. In various embodiments, the semiconductor device 104 includes a device structure 222 disposed in and / or on the semiconductor substrate 102. In some embodiments, the semiconductor device 104 is formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, one or more doping processes, some other suitable manufacturing process, or any combination of the above processes. In further embodiments, the semiconductor device 104 may be configured as follows: Figure 2A The transistor shown and / or described in .

[0053] like Figure 6 As shown in the cross-sectional view 600 of , an interconnect structure 106 is formed on the front side surface 102f of the semiconductor substrate 102. The interconnect structure 106 includes a plurality of conductive interconnect layers arranged in an interconnect dielectric structure. The interconnect dielectric structure includes an interlayer dielectric (ILD) layer 302, a plurality of intermetallic dielectric (IMD) layers 304, and a plurality of etch stop layers 306. The plurality of conductive interconnect layers include a plurality of conductive contacts 110, a plurality of conductive wires 112, and a plurality of conductive vias 113 stacked vertically on each other. The conductive wires 112 and the conductive vias 113 include a conductive body 310 and a lower diffusion barrier layer 308 disposed along the sidewalls and lower surfaces of the conductive body 310, respectively. The interconnect structure 106 includes a topmost conductive wire 112t disposed at the top of the interconnect structure 106.

[0054] In some embodiments, the ILD layer 302, the IMD layer 304, and the etch stop layer 306 may each be formed over the semiconductor substrate 102 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable deposition or growth process. In various embodiments, the layers of the plurality of conductive contacts 110, the plurality of conductive lines 112, and the plurality of conductive vias 113 may be formed by a single damascene process, a dual damascene process, other suitable manufacturing processes, or the like.

[0055] like Figure 7As shown in the cross-sectional view 700 of FIG. 1 , a passivation structure 114 is formed on the interconnect structure 106. In some embodiments, the passivation structure 114 includes a first passivation layer 116 vertically stacked with a second passivation layer 118. In various embodiments, the first passivation layer 116 and the second passivation layer 118 can be formed, for example, by CVD, PVD, ALD, or some other suitable growth or deposition process. The first passivation layer 116 can be, for example, or include silicon nitride, silicon carbide, etc., and can be formed to a thickness of about 3000 angstroms, in a range of about 2500 to 3500 angstroms, or some other suitable value. The second passivation layer 118 can be, for example, or include silicon dioxide, silicon glass, undoped silicon glass, etc., and can be formed to a thickness of about 5500 angstroms, in a range of about 5000 to 6000 angstroms, or some other suitable value.

[0056] like Figure 8 As shown in the cross-sectional view 800 of FIG. 1 , a patterning process is performed on the passivation structure 114 to form a trench 804 in the passivation structure 114. In some embodiments, the patterning process includes: forming a masking layer 802 above the passivation structure 114; and performing an etching process (e.g., a plasma etching process, a reactive ion etching process, etc.) on the passivation structure 114 according to the masking layer 802. In various embodiments, the masking layer 802 can be removed by a removal process (not shown) during or after the etching process. In further embodiments, the patterning process exposes the upper surface of the topmost conductive line 112t.

[0057] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a liner trench ( Figure 8 804) and depositing a conductive structure 902 on the diffusion barrier layer 126. The diffusion barrier layer 126 is formed, for example, by CVD, PVD, ALD, electroplating, or some other suitable growth or deposition process. The conductive structure 902 is formed, for example, by CVD, PVD, electroplating, or some other suitable growth or deposition process. The diffusion barrier layer 126 may be, for example, or include tantalum nitride, tantalum, titanium nitride, titanium, some other conductive material, or any combination of the above materials. The diffusion barrier layer 126 is formed to a thickness 216, which is, for example, about 50 angstroms, in a range of about 10 to 250 angstroms, or some other suitable value. The conductive structure 902 may be, for example, or include copper, etc. In some embodiments, the conductive structure 902 is composed of copper or substantially composed of copper. In various embodiments, the conductive structure 902 and the conductor 310 include the same first conductive material (e.g., copper).

[0058] like Fig.10 As shown in the cross-sectional view 1000, the diffusion barrier layer 126 and the conductive structure ( Fig. 9902) implements a planarization process to define a vertical bonding structure 128 and a plurality of lower bonding structures 122 in the passivation structure 114. The plurality of lower bonding structures 122 respectively include a vertical bonding structure 128 and a diffusion barrier layer 126 disposed along opposite sidewalls and a lower surface of the vertical bonding structure 128. In some embodiments, the vertical bonding structure 128 is formed to a height 214, which may be, for example, in the range of about 8000 to 10000 angstroms or some other suitable value. The planarization process may, for example, be or include a chemical mechanical planarization (CMP) process or some other suitable planarization process.

[0059] like Fig.11 As shown in the cross-sectional view 1100 of , a first conductive layer 130 and a second conductive layer 132 are formed over a plurality of lower bonding structures 122. In addition, a masking layer 1102 is formed over the second conductive layer 132. The first conductive layer 130 and the second conductive layer 132 may each be deposited over the lower bonding structure 122 by, for example, CVD, PVD, ALD, electroplating, chemical plating, or some other suitable growth or deposition process. In some embodiments, the first conductive layer 130 may be, for example, or include tantalum nitride, tantalum, titanium nitride, titanium, some other conductive material, or any combination of the above materials. In various embodiments, the first conductive layer 130 and the diffusion barrier layer 126 include the same second conductive material (e.g., tantalum nitride, tantalum, titanium nitride, titanium, etc.). In further embodiments, the second conductive layer 132 may be, for example, or include titanium, platinum, etc. The first conductive layer 130 is formed to a thickness 212, which may be, for example, about 600 angstroms, in a range of about 200 to 1000 angstroms, etc. The second conductive layer 132 is formed to a thickness 210 , which may be, for example, about 500 angstroms, in a range of about 100 to 1000 angstroms, or the like.

[0060] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a patterning process is performed on the first conductive layer 130 and the second conductive layer 132 to define the upper pad structure 124 and the bonding pad 120. In some embodiments, the upper pad structure 124 includes the first conductive layer 130 and the second conductive layer 132, and the bonding pad 120 includes the upper pad structure 124 and the vertical bonding structure 128. In further embodiments, the process for forming the bonding pad 120 includes Figures 8 to 12 In various embodiments, the patterning process includes: Fig.11 1102) performs an etching process (eg, a plasma etching process, a reactive ion etching process, etc.) on the first conductive layer 130 and the second conductive layer 132.

[0061] like Fig.13As shown in the cross-sectional view 1300 of FIG. 1 , a patterning process is performed on the passivation structure 114, the interconnect structure 106, and the semiconductor substrate 102 to form one or more isolation trenches 218 extending from the passivation structure 114 to the semiconductor substrate 102. In some embodiments, the patterning process includes: forming a masking layer 1302 over the passivation structure 114; and performing an etching process (e.g., a plasma etching process, a reactive ion etching process, etc.) based on the masking layer 1302. In various embodiments, the one or more isolation trenches 218 are disposed between adjacent semiconductor dies over the semiconductor substrate 102.

[0062] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , a protective layer 134 is deposited over the semiconductor substrate 102. The protective layer 134 may be formed, for example, by CVD, PVD, ALD, or some other suitable growth or deposition process. The protective layer 134 may be, for example, or include a metal oxide such as aluminum oxide, or some other suitable material, and is formed to a thickness of about 400 angstroms, in a range of about 300 to 500 angstroms, or some other suitable value. The protective layer 134 extends along the sidewalls of the passivation structure 114, the sidewalls of the interconnect structure 106, and the sidewalls and lower surface of the semiconductor substrate 102 that define one or more isolation trenches 218. In addition, the protective layer 134 extends along the top surface and the opposite sidewalls of the upper pad structure 124.

[0063] like Fig.15 As shown in cross-sectional view 1500 of , a dielectric layer 220 is formed over the semiconductor substrate 102. The dielectric layer 220 may be formed, for example, by CVD, PVD, ALD, or some other suitable growth or deposition process. The dielectric layer 220 is located above the protective layer 134 and fills the one or more isolation trenches 218. In some embodiments, the dielectric layer 220 may be, for example, or include an oxide such as silicon dioxide or some other dielectric material. In various embodiments, the dielectric layer 220 is configured to provide structural support to the layers of the interconnect structure 106, the semiconductor substrate 102, and / or the passivation structure 114. For example, the semiconductor substrate 102 and / or the layers of the interconnect structure 106 and the passivation structure 114 may be susceptible to damage (e.g., warping, delamination, etc.) at areas around the one or more isolation trenches 218. This may occur when the semiconductor substrate 102 is moved between processing chambers and / or during processing. Fig.15 When the structure of Fig.16 Therefore, forming the dielectric layer 220 over the semiconductor substrate 102 and within the one or more isolation trenches increases the Fig.15The dielectric layer 220 may provide protection for underlying layers from contaminants during subsequent processing steps and / or when transferring the semiconductor substrate 102 (e.g., transferring the semiconductor substrate 102 between processing chambers).

[0064] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 16 , a planarization process is performed on the dielectric layer 220 and the protective layer 134. In some embodiments, the planarization process is a CMP process, an etching process, or some other suitable planarization process, and the upper surface of the bonding pad 120 may be exposed. In various embodiments, the planarization process may be omitted. Fig.16 The planarization process is performed so that the dielectric layer 220 and the protection layer 134 remain above the bonding pad 120.

[0065] Figures 17 to 20 Cross-sectional views 1700-2000 of some embodiments of methods of forming a stacked integrated chip structure having an upper semiconductor die bonded to a bonding pad of a semiconductor die are shown. Figures 17 to 20 The cross-sectional views 1700-2000 shown in the reference method are described, but it should be understood that Figures 17 to 20 The structure shown in is not limited to this method, but can exist independently of this method. Figures 17 to 20 Described as a series of steps, it should be understood that these steps are not limiting, because the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described can be omitted in whole or in part.

[0066] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , an integrated chip 1702 including a plurality of bonding pads 120 is formed. In various embodiments, the integrated chip 1702 may be Figures 5 to 15The integrated chip 1702 includes a semiconductor device 104 formed in and / or on a semiconductor substrate 102. An interconnect structure 106 and a passivation structure 114 are formed above the semiconductor substrate 102. A plurality of bonding pads 120 are formed above the interconnect structure 106 and are electrically coupled to the interconnect structure 106. The integrated chip 1702 includes a semiconductor die 301, wherein the plurality of bonding pads 120 and the semiconductor device 104 are part of the semiconductor die 301. In addition, the semiconductor die 301 is spaced apart between isolation trenches 218, wherein other semiconductor dies (not shown) are disposed on the semiconductor substrate 102 on opposite sides of the semiconductor die 301. In various embodiments, the isolation trenches 218 are disposed along and / or define spaced apart scribe lines on opposite sides of the semiconductor die 301. The protection layer 134 lines the isolation trenches 218, and the dielectric layer 220 fills the isolation trenches 218.

[0067] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 18 , an etching process is performed on the integrated chip 1702 to remove the dielectric layer ( Fig.17 220). In various embodiments, the etching process includes: Fig.17 The structure is exposed to an etchant (e.g., vaporized hydrogen fluoride) to remove the dielectric layer ( Fig.17 220). Since the protection layer 134 extends along the sidewalls and top surface of the upper pad structure 124, damage to the bonding pad 120 is reduced. In addition, in some embodiments, the top surface of the upper pad structure 124 can be exposed during the etching process. The second conductive layer 132 includes a conductive material (e.g., titanium or platinum) with low reactivity to the etchant, thereby reducing damage to the bonding pad 120.

[0068] like Fig.19 As shown in cross-sectional view 1900 of , an upper semiconductor die 404 bonded to a plurality of bonding pads 120 is provided. In some embodiments, bonding the upper semiconductor die 404 to the plurality of bonding pads 120 includes: etching (e.g., by plasma etching, reactive ion etching, etc.) the protective layer 134 to expose the top surface of the bonding pads 120; forming a plurality of bonding bumps 402 above the bonding pads 120; and performing a metal bonding process to bond the upper semiconductor die 404 to the bonding pads 120. In various embodiments, instead of etching the protective layer 134, a planarization process (e.g., a CMP process) may be performed on the protective layer 134 before forming the plurality of bonding bumps 402. In some embodiments, the aforementioned planarization process may be performed on the protective layer 134. Fig.18In a further embodiment, a plurality of bonding bumps 402 are formed on the upper semiconductor die 404 before bonding the upper semiconductor die 404 to the plurality of bonding pads 120 .

[0069] like Fig. 20 As shown in the cross-sectional view 2000, along the plurality of isolation trenches ( Fig.19 218) performs a singulation process to singulate the semiconductor die 301. In some embodiments, the singulation process includes using a saw blade (not shown) to cut along the isolation trench ( Fig.19 218) Cutting Fig.19 In various embodiments, the saw blade may be attached to a housing (not shown) that houses a motor (not shown) that drives a rotor that holds the saw blade. In further embodiments, the segmentation process may be implemented by a diamond saw blade cutting process, a laser cutting process, a plasma etching process, some other suitable segmentation process, or any combination of the above processes.

[0070] Fig.21 A method 2100 for forming a stacked integrated chip structure having an upper semiconductor die with a bonding pad bonded to a semiconductor die is shown. Although method 2100 shows and / or describes a series of steps or events, it should be understood that method 2100 is not limited to the order or steps shown. Therefore, in some embodiments, the steps may be performed in a different order than shown and / or may be performed simultaneously. In addition, in some embodiments, the steps or events shown may be subdivided into multiple steps or events, which may be performed at a separate time or simultaneously with other steps or sub-steps. In some embodiments, some of the steps or events shown may be omitted, and other steps or events not shown may be included.

[0071] In step 2102, a semiconductor device is formed on and / or within a semiconductor substrate. Figure 5 A cross-sectional view 500 corresponding to various embodiments of step 2102 is shown.

[0072] In step 2104, an interconnect structure is formed on a semiconductor substrate, wherein the interconnect structure includes a conductive line disposed in a dielectric structure. Figure 6 A cross-sectional view 600 corresponding to various embodiments of step 2104 is shown.

[0073] In step 2106, a passivation structure is formed over the interconnect structure. Figure 7 A cross-sectional view 700 corresponding to various embodiments of step 2106 is shown.

[0074] In step 2108, a plurality of lower bonding structures are formed in the passivation structure and on the conductive lines. The lower bonding structures respectively include a vertical bonding structure and a diffusion barrier layer disposed along the sidewalls and the bottom surface of the vertical bonding structure. Figures 8 to 10 Cross-sectional views 800 - 1000 corresponding to various embodiments of step 2108 are shown.

[0075] In step 2110, an upper pad structure is formed over the plurality of lower bonding structures, thereby defining bonding pads over the interconnect structure. Fig.11 and Fig.12 Cross-sectional views 1100 and 1200 corresponding to various embodiments of step 2110 are shown.

[0076] In step 2112, an isolation trench is formed extending through the passivation structure and the interconnect structure to the semiconductor substrate. Fig.13 A cross-sectional view 1300 corresponding to various embodiments of step 2112 is shown.

[0077] In step 2114, a dielectric layer is deposited over the bond pads and within the isolation trenches. Fig.15 A cross-sectional view 1500 corresponding to various embodiments of step 2114 is shown.

[0078] In step 2116, an etching process is performed to remove the dielectric layer from over the bond pad and within the isolation trench. Fig.18 A cross-sectional view 1800 corresponding to various embodiments of step 2116 is shown.

[0079] In step 2118 , the upper semiconductor die is bonded to the bond pad. Fig.19 A cross-sectional view 1900 corresponding to various embodiments of step 2118 is shown.

[0080] In step 2120 , a singulation process is performed along the isolation trenches to singulate the semiconductor dies. Fig. 20 A cross-sectional view 2000 corresponding to various embodiments of step 2120 is shown.

[0081] Therefore, in some embodiments, the disclosed embodiments are directed to an integrated chip including a bonding pad having an upper pad structure and a plurality of lower bonding structures, wherein the lower bonding structures respectively include vertical bonding structures configured to reduce a contact resistance of the bonding pad.

[0082] In some embodiments, the present application provides an integrated chip, comprising: an interconnect structure located on a substrate and comprising a conductive line disposed in a dielectric structure, wherein the conductive line comprises a main body structure; a passivation structure located on the interconnect structure; and a bonding pad located above the passivation structure, wherein the bonding pad comprises an upper pad structure located on the passivation structure and a plurality of lower bonding structures extending through the passivation structure to the conductive line, wherein the lower bonding structures respectively comprise a vertical bonding structure and a diffusion barrier layer disposed along the lower surface and the opposite sidewall of the vertical bonding structure, wherein the upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer. In an embodiment, the main body structure and the vertical bonding structure comprise a first material, wherein the conductivity of the first material is greater than the conductivity of tungsten. In an embodiment, the main body structure and the vertical bonding structure comprise copper. In an embodiment, the first conductive layer directly contacts the top surface of the vertical bonding structure and the top surface of the diffusion barrier layer, wherein the first conductive layer and the second conductive layer comprise different materials. In an embodiment, the main body structure and the vertical bonding structure comprise a first material, wherein the first conductive layer and the diffusion barrier layer comprise a second material different from the first material. In an embodiment, the thickness of the first conductive layer is greater than the thickness of the second conductive layer. In an embodiment, the upper pad structure further includes a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the material of the third conductive layer is different from the material of the first conductive layer and the second conductive layer. In an embodiment, the conductive wire further includes a lower diffusion barrier layer disposed along the opposite sidewalls and the lower surface of the main structure, wherein the lower diffusion barrier layer and the diffusion barrier layer include a material different from that of the main structure and the vertical bonding structure. In an embodiment, the integrated chip further includes: a micro light emitting diode (LED) die disposed on the bonding pad, wherein the micro LED die is electrically coupled to the interconnect structure through the bonding pad; and a bonding bump disposed between the micro LED die and the bonding pad.

[0083] In some embodiments, the present application provides an integrated chip, including: a semiconductor device, arranged on a semiconductor substrate; an interconnection structure, located on the semiconductor substrate, wherein the interconnection structure includes a wire electrically coupled to the semiconductor device; a passivation structure, located on the interconnection structure; and a bonding pad, arranged on the passivation structure and electrically coupled to the wire, wherein the bonding pad includes an upper pad structure arranged in the passivation structure and a plurality of lower bonding structures, wherein the upper pad structure includes a first conductive layer and a second conductive layer located above the first conductive layer, wherein the lower bonding structure includes a vertical bonding structure and a diffusion barrier layer that laterally surrounds the vertical bonding structure, wherein the first conductive layer directly contacts the top surface of the vertical bonding structure and the diffusion barrier layer, and wherein the vertical bonding structure includes copper. In an embodiment, the integrated chip also includes: a groove, extending to the semiconductor substrate through the passivation structure and the interconnection structure; and a protective layer, arranged along the sidewall of the upper pad structure and lining the groove, wherein the protective layer extends laterally from the upper pad structure to the groove continuously. In an embodiment, the height of the upper pad structure is less than the height of the plurality of lower bonding structures. In an embodiment, the diffusion barrier layer and the first conductive layer are respectively configured to mitigate diffusion of copper from the vertical bonding structure. In an embodiment, the second conductive layer comprises titanium or platinum. In an embodiment, the upper pad structure further comprises a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the thickness of the first conductive layer is less than the thickness of the second conductive layer, and wherein the thickness of the third conductive layer is less than the thickness of the first conductive layer.

[0084] In some embodiments, the present application provides a method for forming an integrated chip, the method comprising: forming an interconnect structure above a semiconductor substrate, wherein the interconnect structure comprises a conductive line; depositing a passivation structure above the interconnect structure; patterning the passivation structure to form a plurality of openings in the passivation structure above the conductive line; depositing a diffusion barrier layer lining the openings above the passivation structure; forming a vertical bonding structure filling the openings above the diffusion barrier layer, wherein the diffusion barrier layer laterally wraps the vertical bonding structure, wherein the vertical bonding structure and the conductive line comprise a first material; and forming an upper pad structure above the vertical bonding structure, wherein the upper pad structure comprises a first conductive layer located on the vertical bonding structure and a second conductive layer located above the first conductive layer, wherein an outer sidewall of the first conductive layer is aligned with an outer sidewall of the second conductive layer. In an embodiment, the resistivity of the vertical bonding structure is less than the total resistivity of the upper pad structure. In an embodiment, the method further comprises: performing a patterning process to form a trench extending through the passivation structure and the interconnect structure to the semiconductor substrate; depositing a protective layer over the passivation structure, wherein the protective layer lines the trench and is disposed along opposite sidewalls of the upper pad structure; and depositing a dielectric layer over the upper pad structure and in the trench. In an embodiment, the method further comprises: performing an etching process to remove the dielectric layer from over the passivation structure and in the trench; and bonding the upper semiconductor die to the upper pad structure. In an embodiment, the method further comprises: performing a segmentation process along the trench to segment the semiconductor die.

[0085] Some embodiments of the present application provide an integrated chip, comprising: an interconnect structure, located on a substrate and comprising a conductive line arranged in a dielectric structure, wherein the conductive line comprises a main structure; a passivation structure, located on the interconnect structure; and a bonding pad, located above the passivation structure, wherein the bonding pad comprises an upper pad structure located on the passivation structure and a plurality of lower bonding structures extending through the passivation structure to the conductive line, wherein the lower bonding structures respectively comprise a vertical bonding structure and a diffusion barrier layer arranged along a lower surface and relative side walls of the vertical bonding structure, wherein the upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer.

[0086] In some embodiments, the main body structure and the vertical bonding structure include a first material, wherein the electrical conductivity of the first material is greater than the electrical conductivity of tungsten. In some embodiments, the main body structure and the vertical bonding structure include copper. In some embodiments, the first conductive layer directly contacts the top surface of the vertical bonding structure and the top surface of the diffusion barrier layer, wherein the first conductive layer and the second conductive layer include different materials. In some embodiments, the main body structure and the vertical bonding structure include a first material, wherein the first conductive layer and the diffusion barrier layer include a second material different from the first material. In some embodiments, the thickness of the first conductive layer is greater than the thickness of the second conductive layer. In some embodiments, the upper pad structure further includes a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the material of the third conductive layer is different from the material of the first conductive layer and the second conductive layer. In some embodiments, the conductive line further includes a lower diffusion barrier layer disposed along the opposite sidewalls and the lower surface of the main body structure, wherein the lower diffusion barrier layer and the diffusion barrier layer include a material different from the material of the main body structure and the vertical bonding structure. In some embodiments, the integrated chip further includes: a micro light emitting diode (LED) die disposed on the bonding pad, wherein the micro light emitting diode die is electrically coupled to the interconnect structure through the bonding pad; and a bonding bump disposed between the micro light emitting diode die and the bonding pad.

[0087] Other embodiments of the present application provide an integrated chip, comprising: a semiconductor device, disposed on a semiconductor substrate; an interconnect structure, located above the semiconductor substrate, wherein the interconnect structure comprises a conductive line electrically coupled to the semiconductor device; a passivation structure, located above the interconnect structure; and a bonding pad, disposed on the passivation structure and electrically coupled to the conductive line, wherein the bonding pad comprises an upper pad structure and a plurality of lower bonding structures disposed in the passivation structure, wherein the upper pad structure comprises a first conductive layer and a second conductive layer located above the first conductive layer, wherein the lower bonding structure comprises a vertical bonding structure and a diffusion barrier layer laterally surrounding the vertical bonding structure, wherein the first conductive layer directly contacts the top surfaces of the vertical bonding structure and the diffusion barrier layer, and wherein the vertical bonding structure comprises copper.

[0088] In some embodiments, the integrated chip further includes: a groove extending through the passivation structure and the interconnect structure to the semiconductor substrate; and a protective layer disposed along the sidewall of the upper pad structure and lining the groove, wherein the protective layer extends laterally from the upper pad structure to the groove continuously. In some embodiments, the height of the upper pad structure is less than the height of the plurality of lower bonding structures. In some embodiments, the diffusion barrier layer and the first conductive layer are respectively configured to mitigate the diffusion of copper from the vertical bonding structure. In some embodiments, the second conductive layer includes titanium or platinum. In some embodiments, the upper pad structure further includes a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the thickness of the first conductive layer is less than the thickness of the second conductive layer, and wherein the thickness of the third conductive layer is less than the thickness of the first conductive layer.

[0089] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming an interconnect structure above a semiconductor substrate, wherein the interconnect structure includes a conductive line; depositing a passivation structure above the interconnect structure; patterning the passivation structure to form a plurality of openings in the passivation structure above the conductive line; depositing a diffusion barrier layer lining the openings above the passivation structure; forming a vertical bonding structure filling the openings above the diffusion barrier layer, wherein the diffusion barrier layer laterally wraps the vertical bonding structure, wherein the vertical bonding structure and the conductive line include a first material; and forming an upper pad structure above the vertical bonding structure, wherein the upper pad structure includes a first conductive layer located on the vertical bonding structure and a second conductive layer located above the first conductive layer, wherein an outer sidewall of the first conductive layer is aligned with an outer sidewall of the second conductive layer.

[0090] In some embodiments, the resistivity of the vertical bonding structure is less than the total resistivity of the upper pad structure. In some embodiments, the method further comprises: performing a patterning process to form a groove extending through the passivation structure and the interconnect structure to the semiconductor substrate; depositing a protective layer over the passivation structure, wherein the protective layer lines the groove and is disposed along opposite sidewalls of the upper pad structure; and depositing a dielectric layer over the upper pad structure and within the groove. In some embodiments, the method further comprises: performing an etching process to remove the dielectric layer from over the passivation structure and within the groove; and bonding an upper semiconductor die to the upper pad structure. In some embodiments, the method further comprises: performing a segmentation process along the groove to segment the semiconductor die.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated chip, comprising: an interconnect structure located on the substrate and comprising a conductive line disposed in a dielectric structure, wherein the conductive line comprises a main body structure; a passivation structure located on the interconnect structure; and A bonding pad is located above the passivation structure, wherein the bonding pad includes an upper pad structure located on the passivation structure and a plurality of lower bonding structures extending through the passivation structure to the conductive line, wherein the lower bonding structures respectively include vertical bonding structures and diffusion barrier layers arranged along the lower surface and relative side walls of the vertical bonding structures, and wherein the upper pad structure includes a first conductive layer vertically stacked with a second conductive layer.

2. The integrated chip according to claim 1, wherein: The main body structure and the vertical bonding structure include a first material, wherein the electrical conductivity of the first material is greater than the electrical conductivity of tungsten.

3. The integrated chip according to claim 1, wherein: The body structure and the vertical bonding structure include copper.

4. The integrated chip according to claim 1, wherein: The first conductive layer directly contacts a top surface of the vertical junction structure and a top surface of the diffusion barrier layer, wherein the first conductive layer and the second conductive layer include different materials.

5. The integrated chip according to claim 4, wherein: The main body structure and the vertical bonding structure include a first material, wherein the first conductive layer and the diffusion barrier layer include a second material different from the first material.

6. The integrated chip according to claim 4, wherein: The thickness of the first conductive layer is greater than the thickness of the second conductive layer.

7. The integrated chip according to claim 4, wherein: The upper pad structure further includes a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein a material of the third conductive layer is different from a material of the first conductive layer and the second conductive layer.

8. The integrated chip according to claim 1, wherein: The conductive line further includes a lower diffusion barrier layer disposed along opposite sidewalls and a lower surface of the main structure, wherein the lower diffusion barrier layer and the diffusion barrier layer include a material different from that of the main structure and the vertical bonding structure.

9. An integrated chip, comprising: A semiconductor device is disposed on a semiconductor substrate; an interconnect structure located on the semiconductor substrate, wherein the interconnect structure includes a conductive line electrically coupled to the semiconductor device; a passivation structure located on the interconnect structure; and A bonding pad is arranged on the passivation structure and electrically coupled to the conductive line, wherein the bonding pad includes an upper pad structure and a plurality of lower bonding structures arranged in the passivation structure, wherein the upper pad structure includes a first conductive layer and a second conductive layer located above the first conductive layer, wherein the lower bonding structure includes a vertical bonding structure and a diffusion barrier layer laterally surrounding the vertical bonding structure, wherein the first conductive layer directly contacts the top surfaces of the vertical bonding structure and the diffusion barrier layer, and wherein the vertical bonding structure includes copper.

10. A method for forming an integrated chip, comprising: forming an interconnect structure over a semiconductor substrate, wherein the interconnect structure comprises a conductive line; depositing a passivation structure over the interconnect structure; patterning the passivation structure to form a plurality of openings in the passivation structure over the conductive lines; depositing a diffusion barrier layer lining the opening over the passivation structure; forming a vertical bonding structure filling the opening over the diffusion barrier layer, wherein the diffusion barrier layer laterally wraps the vertical bonding structure, wherein the vertical bonding structure and the conductive line comprise a first material; and An upper pad structure is formed above the vertical bonding structure, wherein the upper pad structure includes a first conductive layer located on the vertical bonding structure and a second conductive layer located above the first conductive layer, wherein an outer sidewall of the first conductive layer is aligned with an outer sidewall of the second conductive layer.

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