Conductive wire with conductive metal gasket for advanced integrated circuit structure fabrication

Abstract

The invention relates to a conductive line with conductive metal pads for advanced integrated circuit structure fabrication. The embodiment of the invention relates to the field of integrated circuit structure manufacturing. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in the second dielectric layer, the conductive line including a conductive pad having a conductive barrier therein, the conductive barrier having a conductive filler therein, where the conductive pad is directly on the conductive via.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of advanced integrated circuit structure fabrication, and more particularly to the field of conductive line schemes for integrated circuit structure fabrication and the resulting structures. Background Art

[0002] Over the past several decades, feature shrinkage in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables an increase in the density of functional units on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory devices or logic devices to be included on a chip, thereby enabling the manufacture of products with increased capacity. However, the drive for ever-larger capacities is not without its problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] Fluctuations in conventional and currently known manufacturing processes may limit the possibility of further extending them to the 15 nm node or sub-15 nm node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new technologies or integration of new technologies into current manufacturing processes, or the replacement of current manufacturing processes with new technologies or integration of new technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A A cross-sectional view of an integrated circuit structure having a conductive line with a barrier layer on a conductive via is shown.

[0005] Figure 1B A cross-sectional view of an integrated circuit structure having a conductive line with a conductive liner on a conductive via according to an embodiment of the present disclosure is shown.

[0006] Figure 1C FIG. 4 is a schematic diagram showing the current density of a conductive line / conductive via / conductive line structure including a conductive pad according to an embodiment of the present disclosure.

[0007] Figure 2A , Figure 2B and Figure 3 Detailed description is provided of oblique cross-sectional views representing various operations in a method of fabricating a metallization structure including differentiated conductive lines in accordance with an embodiment of the present disclosure.

[0008] Figures 4A-4E and Figure 5 Cross-sectional views representing various operations in a dielectric plug manufacturing scheme are illustrated in accordance with an embodiment of the present disclosure.

[0009] Figure 6FIG. 4 is a schematic diagram of a pitch quartering scheme for manufacturing trenches of an interconnect structure according to an embodiment of the present disclosure.

[0010] Fig. 7A A cross-sectional view of a metallization layer fabricated using a pitch quartering scheme according to an embodiment of the present disclosure is shown.

[0011] Figure 7B A cross-sectional view of a metallization layer fabricated using a pitch-halving scheme over a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure is shown.

[0012] Fig. 8A A cross-sectional view of an integrated circuit structure having a metallization layer having one metal line composition over a metallization layer having a different metal line composition is shown according to an embodiment of the present disclosure.

[0013] Figure 8B A cross-sectional view of an integrated circuit structure having a metallization layer having one metal line composition coupled to a metallization layer having a different metal line composition is shown according to an embodiment of the present disclosure.

[0014] Fig. 9 It is shown that the embodiment of the present disclosure is suitable for combining Fig. 8A and Figure 8B A cross-sectional view of an individual interconnect line of the structure with a conductive capping structural arrangement.

[0015] Fig.10 A cross-sectional view of an integrated circuit structure having four metallization layers of one metal line composition and one pitch over two metallization layers of different metal line composition and smaller pitch is shown according to an embodiment of the present disclosure.

[0016] Fig.11A A plan view of a metallization layer according to an embodiment of the present disclosure and a corresponding cross-sectional view taken along the aa′ axis of the plan view of the metallization layer are shown.

[0017] Fig. 11B A cross-sectional view of a wire end or plug is shown according to an embodiment of the present disclosure.

[0018] Fig. 11C Another cross-sectional view of a wire end or plug is shown according to an embodiment of the present disclosure.

[0019] Figures 12A-12F Shown are plan views and corresponding cross-sectional views representing various operations in a plug finishing scheme according to an embodiment of the present disclosure.

[0020] Fig.13A A cross-sectional view of a conductive wire plug having a seam therein is shown according to an embodiment of the present disclosure.

[0021] Fig. 13B A cross-sectional view of a metallization layer stack including a conductive line plug at an underlying metal line location according to an embodiment of the present disclosure is shown.

[0022] Fig.14 A computing device according to one embodiment of the present disclosure is shown.

[0023] Fig.15 An interposer including one or more embodiments of the present disclosure is shown.

[0024] Fig.16 is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, the mobile computing platform employing an IC manufactured according to one or more processes described herein or including one or more features described herein.

[0025] Fig.17 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Conductive line schemes and resulting structures for integrated circuit structure fabrication are described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented without these specific details. In other cases, well-known features such as integrated circuit design layouts are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be recognized that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0027] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as an exemplary embodiment is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background technology, summary of the invention or the following detailed description.

[0028] This description includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0029] With respect to terminology, the following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0030] Regarding "comprising", the term is open ended. As used in the appended claims, the term does not exclude additional structures or operations.

[0031] With respect to "configured to," various units or components may be described or claimed as being "configured to" perform a task or tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform one or more of those tasks during operation. Thus, even when the specified unit or component is not currently in operation (e.g., not turned on or active), the unit or component may be said to be configured to perform a task. The recitation that a unit or circuit or component is "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, with respect to that unit or component.

[0032] Regarding "first," "second," etc., as used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (eg, spatial, temporal, logical, etc.).

[0033] With respect to "coupling", the following description refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0034] In addition, certain terms are used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings for which reference is provided. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of portions of a component within a consistent but arbitrary reference system, as may be clearly understood by reference to the text describing the component in question and the associated drawings. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0035] With respect to "inhibit," as used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent a result, consequence, or future state. Additionally, "inhibit" may also refer to reducing or mitigating a consequence, manifestation, or effect that would otherwise occur. Thus, when a component, element, or feature is said to inhibit an effect or state, it does not necessarily completely prevent or eliminate that effect or state.

[0036] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses every operation up to (but not including) metal interconnect layer deposition. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0037] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on a wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0038] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL processing and structures and BEOL processing and structures. Specifically, although the exemplary processing schemes may be illustrated using FEOL processing scenarios, such schemes may also be applicable to BEOL processing. Similarly, although the exemplary processing schemes may be illustrated using BEOL processing scenarios, such schemes may also be applicable to FEOL processing.

[0039] It should be recognized that the FEOL is a technology driver for a given process. In other embodiments, FEOL considerations are driven by BEOL 10 nm or sub-10 nm processing requirements. For example, material selection and layout for FEOL layers and devices may need to accommodate BEOL processing. In one such embodiment, material selection and gate stack architecture are selected to accommodate high density metallization of BEOL layers, for example, to reduce fringe capacitance in transistor structures formed in the FEOL layers but coupled together by high density metallization of the BEOL layers.

[0040] The back-end of the line (BEOL) layer of an integrated circuit typically includes a conductive microelectronic structure, which is referred to as a via in the prior art, to electrically connect a metal line or other interconnect above the via to a metal line or other interconnect below the via. The via can be formed by a photolithography process. Typically, a photoresist layer can be spun on top of the dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer can be developed to form an opening in the photoresist layer. Next, an opening for the via can be etched in the dielectric layer by using the opening in the photoresist layer as an etching mask. This opening is referred to as a via opening. Finally, the via opening can be filled with one or more metals or other conductive materials to form a via.

[0041] The size and spacing of vias have been gradually reduced, and it is expected that in the future, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.), the size and spacing of vias will continue to be gradually reduced. When very small vias with very small pitches are patterned by such photolithographic processes, several challenges exist in themselves. One such challenge is the overlap between the via and the interconnect above, and the overlap between the via and the landing interconnect below, which typically need to be controlled to a high tolerance on the order of one-quarter the via pitch. As the via pitch becomes smaller over time, the overlap tolerance tends to shrink at a rate greater than the rate that the photolithographic equipment can keep up with.

[0042] Another such challenge is that the critical dimensions of via openings generally tend to shrink faster than the resolution capability of the lithography scanner. Several scaling techniques exist to shrink the critical dimensions of via openings. However, the amount of scaling is often limited by the minimum via pitch and by the ability of the scaling process to make the optical proximity correction (OPC) sufficiently neutral without significantly affecting linewidth roughness (LWR) or critical dimension uniformity (CDU) or both. Yet another such challenge is that the LWR or CDU characteristics of the photoresist, or both, generally need to be improved as the critical dimensions of the via openings are reduced in order to maintain the same overall fraction of the critical dimension budget.

[0043] The above factors are also relevant in considering the placement and reduction of non-conductive spaces or breaks between metal lines (referred to as "plugs," "dielectric plugs," or "metal line ends" between metal lines in back-end-of-line (BEOL) metal interconnect structures). Thus, improvements are needed in the art of back-end-of-line metallization manufacturing for fabricating metal lines, metal vias, and dielectric plugs.

[0044] One or more embodiments described herein relate to structures, such as BEOL structures, that exhibit reduced metal-to-contact resistance using liners.

[0045] To provide background, the contact resistance between conductive lines and conductive vias in a BEOL structure can affect overall performance.

[0046] According to embodiments of the present disclosure, for example, by adding a conductive liner under a copper structure, the contact resistance between the conductive line and the conductive via is reduced, thereby improving performance.

[0047] As a comparison structure, Figure 1A A cross-sectional view of an integrated circuit structure having a conductive line with a barrier layer on a conductive via is shown.

[0048] refer to Figure 1A , BEOL interconnect structure 100 includes a conductive line / via pair 102. The conductive line / via pair 102 includes a conductive via 106 in a dielectric layer 104. The conductive line / via pair 102 also includes a conductive line 110 / 112 in a dielectric layer 108. The conductive line 110 / 112 includes a conductive barrier 110 having a conductive filler 112 therein. The conductive barrier 110 is directly on the conductive via 106, which may result in a relatively higher contact resistance.

[0049] and Figure 1A compared to, Figure 1B A cross-sectional view of an integrated circuit structure having a conductive line with a conductive pad on a conductive via according to an embodiment of the present disclosure is shown.

[0050] refer to Figure 1B , the BEOL interconnect structure 120 includes a conductive line / via pair 122. The conductive line / via pair 122 includes a conductive via 126 in a dielectric layer 124. The conductive line / via pair 122 also includes a conductive line 130 / 132 / 134 in a dielectric layer 128. The conductive line 130 / 132 / 134 includes a conductive liner 134 having a conductive barrier 130 therein, and the conductive barrier 130 has a conductive filler 132 therein. The conductive liner 134 is directly on the conductive via 126, which may achieve a relatively lower contact resistance.

[0051] In one embodiment, the conductive via is or includes a metal, such as, but not limited to, W, Mo, or Ru. In one embodiment, the conductive liner 134 is or includes a metal, such as, but not limited to, Ta or Ti, and may have a thickness in the range of 2-5 nanometers. In one embodiment, the conductive barrier 130 includes a metal nitride, such as, but not limited to, TaN (e.g., including tantalum and nitrogen), and may have a thickness in the range of 2-5 nanometers. In one embodiment, the conductive filler 132 is or includes copper. In one embodiment, the conductive liner 134 has a greater conductivity (lower resistance) than the conductive barrier 130.

[0052] Figure 1C is a schematic diagram illustrating current density of conductive line 152 / conductive via 154 / conductive line 156 of structure 150 including conductive pad 158 at the interface between conductive line 156 / conductive via 154 according to an embodiment of the disclosure.

[0053] refer to Figure 1C , including a conductive pad at the interface of the conductive line 156 / conductive via 154 , e.g. Figure 1B With the conductive liner 134, it is possible to obtain a relatively reduced resistance, for example, a contact resistance reduction of a scale of 20-25%. For example, an increase in current density of the structure 150 may be observed, for example, a current density increase of a scale of 20-25%.

[0054] In another aspect, one or more embodiments described herein relate to structures, such as BEOL structures, including mixed metal layers.

[0055] To provide context, with each technology node, the demand for finer features, such as thinner metal lines and vias spaced at fine pitches, continues to exist. A combination of optics and self-aligned schemes has been supporting the industry by providing both the required lithography schemes and patterning schemes for the lines. Extreme ultraviolet (EUV) technology has recently enabled a dramatic change in printable via and pattern sizes. Even so, EUV printing may not be sufficient to meet the demand for shrinking technology nodes. Deposition and / or etch-based schemes may be needed that can complement EUV printing and fill the technology gap.

[0056] To provide background, for a metal layer containing metal lines of multiple widths, sometimes one metal may not provide optimal performance on both narrow and wide metal lines, and it may be beneficial to use two different metals to achieve optimal performance. For example, for narrower lines, a non-copper conductive line without a barrier layer may be optimal, while for wider lines, a tungsten conductive line with a molybdenum barrier layer, such as described above, may be optimal.

[0057] According to one or more embodiments of the present disclosure, Co or Ru is used for the initial metallization of all wide and narrow metal lines. A patterning process is then used to recess the first metal deposit for the wider lines and backfill the recess with a tungsten conductive line with a molybdenum barrier layer.

[0058] As an exemplary process flow, Figure 2A , Figure 2B and Figure 3 Detailed description is provided of oblique cross-sectional views representing various operations in a method of fabricating a metallization structure including differentiated conductive lines in accordance with an embodiment of the present disclosure.

[0059] refer to Figure 2A , the starting structure 200 includes a conductive line layer 207 over a conductive via layer 203 over a substrate or underlying metallization structure 202. The conductive via layer 203 includes one or more conductive vias 206 in a dielectric layer 204 (e.g., an interlayer dielectric (ILD) layer). As shown, an etch stop layer 209 (e.g., a silicon nitride etch stop layer) can be between the conductive line layer 207 and the conductive via layer 203. The combination of the conductive line layer 207 and the conductive via layer 203 can be referred to as a metallization layer of the BEOL portion of the integrated circuit structure.

[0060] Reference again Figure 2A , the conductive line layer 207 includes a plurality of conductive lines 210 / 212 on the same level and along the same direction. A first conductive line 210 of the plurality of conductive lines 210 / 212 has a first width (W1) and a first component. A second conductive line 212 of the plurality of conductive lines 210 / 212 has a second width (W2) and a second component. In one embodiment, the second width (W2) is greater than the first width (W1). In one embodiment, the second component is the same as the first component. The conductive line layer 207 also includes an ILD structure 208 having a portion between adjacent conductive lines of the plurality of conductive lines 210 / 212.

[0061] In one embodiment, the first conductive line 210 of the plurality of conductive lines 210 / 212 includes a first conductive filler without a conductive barrier. The second conductive line 212 of the plurality of conductive lines 210 / 212 includes a first conductive filler without a conductive barrier. In one embodiment, the first conductive filler includes W, Co, or Ru.

[0062] In one embodiment, a first conductive line 210 of the plurality of conductive lines 210 / 212 has a break therein. A first dielectric plug 214A is located at the location of the break in the first conductive line 210 of the plurality of conductive lines 210 / 212. A second conductive line 212 of the plurality of conductive lines 210 / 212 has a break therein. A second dielectric plug 214B is located at the location of the break in the second conductive line 212 of the plurality of conductive lines 210 / 212.

[0063] refer to Figure 2B , a mask layer 250 is formed to cover the narrower conductive lines 210 of the plurality of conductive lines 210 / 212. The mask 250 exposes the wider conductive lines 212 of the plurality of conductive lines 212 / 212. An etching process is used to remove the exposed wider conductive lines 212 of the plurality of conductive lines 210 / 212 or at least substantially recess the exposed wider conductive lines 212 of the plurality of conductive lines 210 / 212 (e.g., reduce the thickness of the exposed wider conductive lines 212 by 90%-100%), thereby forming trenches 252. In one such embodiment, the exposed wider conductive lines 212 of the plurality of conductive lines 210 / 212 are not completely removed, and a layer 212A of the first conductive fill material remains, as shown.

[0064] refer to Figure 3 , remove the mask 250. Figure 2B A conductive line 302 is formed in the trench 252. In one embodiment, the conductive line 302 includes a conductive liner / conductive barrier pair 304 and a second conductive filler 306. In one embodiment, the second conductive filler 306 is different from the first conductive filler. In one embodiment, the second conductive filler 306 includes Cu. In one embodiment, the conductive liner / conductive barrier pair 304 includes a Ta or Ti conductive liner and a TaN conductive barrier.

[0065] Reference again Figure 2A , Figure 2B and Figure 3 According to an embodiment of the present disclosure, an integrated circuit structure 300 includes a plurality of conductive lines 210 / 302 on the same level and along the same direction. A first conductive line 210 of the plurality of conductive lines 210 / 302 has a first width (W1) and a first component. A second conductive line 302 of the plurality of conductive lines 210 / 302 has a second width (W2) and a second component. In one embodiment, the second width (W2) is greater than the first width (W1). In one embodiment, the second component is different from the first component. The integrated circuit structure 300 also includes an interlayer dielectric (ILD) structure 208 having a portion between adjacent conductive lines of the plurality of conductive lines 210 / 302.

[0066] In one embodiment, a first conductive line 210 of the plurality of conductive lines 210 / 302 includes a first conductive filler without a conductive barrier. A second conductive line 302 of the plurality of conductive lines 210 / 302 includes a conductive liner / conductive barrier pair 304 and a second conductive filler 306. The second conductive filler 306 is different from the first conductive filler. In one embodiment, the conductive barrier 304 of the second conductive line 302 of the plurality of conductive lines 210 / 302 is on a conductive layer 212B having the same composition as the first conductive filler. In one embodiment, the first conductive filler includes W, Co, or Ru, and the second conductive filler 306 includes Cu.

[0067] In one embodiment, a first conductive line 210 in the plurality of conductive lines 210 / 302 has a break therein. A first dielectric plug 214A is located at the location of the break in the first conductive line 210 in the plurality of conductive lines 210 / 302. A second conductive line 302 in the plurality of conductive lines 210 / 302 has a break therein. A second dielectric plug 214B is located at the location of the break in the second conductive line 302 in the plurality of conductive lines 210 / 302.

[0068] In one embodiment, a first conductive line 210 in the plurality of conductive lines 210 / 302 has a break therein, and the ILD structure has a dielectric plug portion at the location of the break in the first conductive line 210 in the plurality of conductive lines 210 / 302. The dielectric plug portion of the ILD structure is continuous with one or more portions of the ILD structure between adjacent conductive lines in the plurality of conductive lines 210 / 302. Figure 5 An exemplary such structure is described, which may be a representative structure of a plurality of relatively narrow ( W1 ) conductive lines 210 .

[0069] In another aspect, one or more embodiments described herein relate to a scheme for implementing a cut plug for metal and inter-layer dielectric (ILD) last process flow for metal process and process window applications.

[0070] The embodiments described herein may include a process initiated by creating a grating in which metal lines will eventually be fabricated. The process includes cutting the grating that will create metal plugs, adding shrink liners to increase the metal line CD to the desired size, backfilling with dielectric, and removing the dummy grating and replacing it with the final metal. The various embodiments may be implemented to achieve extremely small plug CDs that would otherwise be impossible.

[0071] The embodiments described herein may be implemented to achieve a higher scaling plug process (smaller plug CD may be achieved using the process described herein). The embodiments described herein may be implemented to provide a larger plug to metal edge placement error (EPE) margin (process robustness and yield).

[0072] As an exemplary processing scheme and as an exemplary resulting structure, Figures 4A-4E and Figure 5 1 shows a cross-sectional view representing various operations in a dielectric plug manufacturing scheme according to an embodiment of the present disclosure. It should be appreciated that the scheme described below can be used to manufacture a dielectric plug. Figure 3 At least a portion of the conductive line 210 / 302 , for example, the narrower ( W1 ) line 210 .

[0073] The grid can be generated where metal lines will eventually be formed. The critical dimension (CD) of the grid can be reduced to allow the grid to be cut with greater margin. Figure 4A , a starting structure 400 includes a grating 404 on a hard mask layer 403 on an underlying substrate or dielectric layer 402 (e.g., an underlying metallization layer or a layer in which a via structure is formed). In one embodiment, the grating 404 is formed by a pitch halving or spacer division scheme, in which an initial amorphous carbon backbone grating of, for example, 48nm pitch is pitch halved by forming amorphous silicon spacers on the backbone, and then removing the backbone to provide an amorphous silicon grating. In one embodiment, the grating 404 defines the location of the final metal lines, and the size reduction provides edge placement error (EPE) margin for subsequent operations.

[0074] refer to Figure 4B , a cutting process is performed on the grid 404. For example, a masking layer may be formed over the structure 400, and an etching process may be performed to provide a cut grid 404A having gaps 406 therein. In one embodiment, the etching process is performed at locations where dielectric plugs for metal lines will eventually be formed.

[0075] After the cutting process, the grid size can be increased using the same or similar material as the initial grid material to achieve a grid CD equal to the final metal width. The increase in grid CD can also reduce the final plug CD. Figure 4C, a deposition process is performed on grid 404A to perform effective growth, thereby forming grid 404B. In one embodiment, this process operation can be referred to as forming an EPE liner / CD adjustment liner (and can be the same material as 404). In one embodiment, this process operation returns the CD to the target value for both the plug size and the metal line size.

[0076] After the growth process, the grid may be backfilled with a dielectric material (eg, an interlayer dielectric material) and polished to expose the sacrificial grid. Figure 4D ,exist Figure 4C A dielectric material is formed over the structure of planarized grid 404C and the resulting structure is planarized to provide planarized grid 404C having dielectric structures 408 therein. Dielectric structures 408 occupy locations between features of planarized grid 404C and plug locations 406 to form plugs 410.

[0077] The sacrificial grid can then be replaced with the final metal material. Figure 4E , the planarization grid 404C is removed so that the dielectric structure 408 remains. In addition, the exposed portion of the hard mask 403 can be removed to form a patterned hard mask 403A, as shown.

[0078] refer to Figure 5 , for example, by forming conductive structures 502 at locations previously occupied by planarization grid 404C by deposition and planarization processes, thereby providing structure 500. In one embodiment, conductive structure 502 includes conductive barriers 504 and conductive fillers 506. In one embodiment, conductive structure 502 is a plurality of conductive lines in the same direction. Some of the conductive lines may have interruptions due to being interrupted by portions of dielectric structure 408, which effectively act as dielectric plugs 410 at those locations. Although not shown, in one embodiment, the conductive lines are aligned with underlying vias in the underlying metallization layer.

[0079] In another aspect, a pitch-quartering scheme is implemented to pattern trenches in a dielectric layer to facilitate forming BEOL interconnect structures. According to embodiments of the present disclosure, pitch-quartering is applied in a BEOL manufacturing scheme to manufacture metal lines. Embodiments may be able to continuously reduce the pitch of metal layers beyond the resolution capability of prior art lithographic equipment.

[0080] Figure 6 FIG. 6 is a schematic diagram of a pitch quadrant scheme 600 for manufacturing a trench of an interconnect structure according to an embodiment of the present disclosure. It should be appreciated that the scheme described below can be used to manufacture Figure 3 At least a portion of the conductive line 210 / 302 , for example, the narrower ( W1 ) line 210 .

[0081] refer to Figure 6 In operation (a), a backbone feature 602 is formed using direct photolithography. For example, a photoresist layer or stack may be patterned and the pattern may be transferred to a hard mask material to ultimately form the backbone feature 602. The photoresist layer or stack used to form the backbone feature 602 may be patterned using standard photolithography processing techniques (e.g., 193 immersion lithography). Then, a first spacer feature 604 is formed adjacent to the sidewalls of the backbone feature 602.

[0082] In operation (b), the backbone features 602 are removed to leave only the first spacer features 604. At this stage, the first spacer features 604 are effectively half-pitch masks, thereby representing, for example, a pitch-halving process. The first spacer features 604 can be used directly in a pitch-quartering process, or the pattern of the first spacer features 604 can first be transferred to a new hard mask material, the latter of which is shown in the figure.

[0083] At operation (c), the pattern of the first spacer feature 604 is transferred to a new hard mask material to form a first spacer feature 604'. A second spacer feature 606 is then formed adjacent to the sidewalls of the first spacer feature 604'.

[0084] At operation (d), the first spacer features 604' are removed to leave only the second spacer features 606. At this stage, the second spacer features 606 are effectively a quarter pitch mask, thereby representing, for example, a pitch quartering process.

[0085] In operation (e), the second spacer feature 606 is used as a mask to pattern a plurality of trenches 608 in the dielectric or hard mask layer. The trenches may eventually be filled with a conductive material to form conductive interconnects in the metallization layer of the integrated circuit. The trenches 608 labeled "B" correspond to the backbone features 602. The trenches 608 labeled "S" correspond to the first spacer features 604 or 604'. The trenches 608 labeled "C" correspond to the complementary regions 607 between the backbone features 602.

[0086] It should be recognized that due to Figure 6 The individual grooves in the grooves 608 have a shape corresponding to Figure 6 The patterning origin of the backbone feature 602, the first spacer feature 604 or 604', or one of the complementary regions 607, and thus the difference in width and / or pitch of such features in the conductive interconnects ultimately formed in the metallization layers of the integrated circuit may appear as an artifact of the pitch quartering process. As an example, Fig. 7AA cross-sectional view of a metallization layer fabricated using a pitch quartering scheme according to an embodiment of the present disclosure is shown. In one embodiment, a conductive metal pad conductive line scheme (e.g., such as a combination of Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig. 7A interconnect layer.

[0087] refer to Fig. 7A , the integrated circuit structure 700 includes an interlayer dielectric (ILD) layer 704 above a substrate 702. A plurality of conductive interconnects 706 are in the ILD layer 704, and individual conductive interconnects in the plurality of conductive interconnects 706 are separated from each other by portions of the ILD layer 704. Individual conductive interconnects in the plurality of conductive interconnects 706 include a conductive barrier layer 708 and a conductive fill material 710.

[0088] refer to Figure 6 and Fig. 7A Both, conductive interconnect 706B is formed in trenches where the pattern is derived from backbone features 602. Conductive interconnect 706S is formed in trenches where the pattern is derived from first spacer features 604 or 604'. Conductive interconnect 706C is formed in trenches where the pattern is derived from complementary regions 607 between backbone features 602.

[0089] Reference again Fig. 7A In one embodiment, the plurality of conductive interconnects 706 include a first interconnect 706B having a width (W1). A second interconnect 706S is adjacent to the first interconnect 706B, and the second interconnect 706S has a width (W2) that is different from the width (W1) of the first interconnect 706B. A third interconnect 706C is adjacent to the second interconnect 706S, and the third interconnect 706C has a width (W3). A fourth interconnect (second 706S) is adjacent to the third interconnect 706C, and the fourth interconnect has a width (W2) that is the same as the width (W2) of the second interconnect 706S. A fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S), and the fifth interconnect (second 706B) has a width (W1) that is the same as the width (W1) of the first interconnect 706B.

[0090] In one embodiment, the width (W3) of the third interconnect line 706C is different from the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different from the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S. In another embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W1) of the first interconnect line 706B.

[0091] In one embodiment, the spacing (P1) between the first interconnection line 706B and the third interconnection line 706C is the same as the spacing (P2) between the second interconnection line 706S and the fourth interconnection line (the second 706S). In another embodiment, the spacing (P1) between the first interconnection line 706B and the third interconnection line 706C is different from the spacing (P2) between the second interconnection line 706S and the fourth interconnection line (the second 706S).

[0092] Reference again Fig. 7A In another embodiment, the plurality of conductive interconnects 706 include a first interconnect 706B having a width (W1). A second interconnect 706S is adjacent to the first interconnect 706B, and the second interconnect 706S has a width (W2). A third interconnect 706C is adjacent to the second interconnect 706S, and the third interconnect 706C has a width (W3) that is different from the width (W1) of the first interconnect 706B. A fourth interconnect (second 706S) is adjacent to the third interconnect 706C, and the fourth interconnect has a width (W2) that is the same as the width (W2) of the second interconnect 706S. A fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S), and the fifth interconnect (second 706B) has a width (W1) that is the same as the width (W1) of the first interconnect 706B.

[0093] In one embodiment, the width (W2) of the second interconnect line 706S is different from the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different from the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S.

[0094] In one embodiment, the width (W2) of the second interconnect line 706S is the same as the width (W1) of the first interconnect line 706B. In one embodiment, the spacing (P1) between the first interconnect line 706B and the third interconnect line 706C is the same as the spacing (P2) between the second interconnect line 706S and the fourth interconnect line (the second 706S). In one embodiment, the spacing (P1) between the first interconnect line 706B and the third interconnect line 706C is different from the spacing (P2) between the second interconnect line 706S and the fourth interconnect line (the second 706S).

[0095] Figure 7B A cross-sectional view of a metallization layer fabricated using a pitch-halving scheme over a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure is shown. In one embodiment, a conductive metal pad conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Figure 7B interconnect layer.

[0096] refer to Figure 7B , the integrated circuit structure 750 includes a first interlayer dielectric (ILD) layer 754 above a substrate 752. A first plurality of conductive interconnects 756 are in the first ILD layer 754, and individual conductive interconnects in the first plurality of conductive interconnects 756 are spaced apart from each other by portions of the first ILD layer 754. Individual conductive interconnects in the plurality of conductive interconnects 756 include a conductive barrier layer 758 and a conductive fill material 760. The integrated circuit structure 750 also includes a second interlayer dielectric (ILD) layer 774 above the substrate 752. A second plurality of conductive interconnects 776 are in the second ILD layer 774, and individual conductive interconnects in the second plurality of conductive interconnects 776 are spaced apart from each other by portions of the second ILD layer 774. Individual conductive interconnects in the plurality of conductive interconnects 776 include a conductive barrier layer 778 and a conductive fill material 780.

[0097] According to the embodiments of the present disclosure, referring again to Figure 7B , a method of manufacturing an integrated circuit structure includes forming a first plurality of conductive interconnect lines 756 spaced apart by a first interlayer dielectric (ILD) layer 754 in a first interlayer dielectric (ILD) layer 754 over a substrate 752. Using a spacer-based pitch quadrature process (e.g., in combination with Figure 6A first plurality of conductive interconnects 756 are formed in a second ILD layer 774 over the first ILD layer 754 and separated by the second ILD layer 774. A spacer-based pitch-halving process (e.g., in combination with Figure 6 A second plurality of conductive interconnect lines 776 is formed by performing the scheme described in operations (a) and (b).

[0098] In one embodiment, the first plurality of conductive interconnects 756 have a pitch (P1) of less than 40 nanometers between immediately adjacent lines. The second plurality of conductive interconnects 776 have a pitch (P2) of 44 nanometers or greater between immediately adjacent lines. In one embodiment, the spacer-based pitch quartering process and the spacer-based pitch halving process are based on an immersion 193 nm lithography process.

[0099] In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 754 include a first conductive barrier layer 758 and a first conductive fill material 760. Individual conductive interconnects in the second plurality of conductive interconnects 756 include a second conductive barrier layer 778 and a second conductive fill material 780. In one such embodiment, the first conductive fill material 760 is different in composition from the second conductive fill material 780. In another embodiment, the first conductive fill material 760 is the same in composition as the second conductive fill material 780.

[0100] Although not shown, in one embodiment, the method further includes forming a third plurality of conductive interconnects separated by the third ILD layer in a third ILD layer over the second ILD layer 774. The third plurality of conductive interconnects is formed without using pitch division.

[0101] Although not shown, in one embodiment, the method further includes: before forming the second plurality of conductive interconnects 776, forming a third plurality of conductive interconnects spaced apart by the third ILD layer in the third ILD layer above the first ILD layer 754. The third plurality of conductive interconnects are formed using a spacer-based pitch quartering process. In one such embodiment, after forming the second plurality of conductive interconnects 776, a fourth plurality of conductive interconnects spaced apart by the fourth ILD layer are formed in the fourth ILD layer above the second ILD layer 774. The fourth plurality of conductive interconnects are formed using a spacer-based pitch halfing process. In one embodiment, such a method further includes forming a fifth plurality of conductive interconnects spaced apart by the fifth ILD layer in the fifth ILD layer above the fourth ILD layer, the fifth plurality of conductive interconnects being formed using a spacer-based pitch halfing process. Then a sixth plurality of conductive interconnects spaced apart by the sixth ILD layer are formed in the sixth ILD layer above the fifth ILD layer, the sixth plurality of conductive interconnects being formed using a spacer-based pitch halfing process. A seventh plurality of conductive interconnect lines are formed in a seventh ILD layer above the sixth ILD layer and spaced apart by the seventh ILD layer. The seventh plurality of conductive interconnect lines are formed without using pitch division.

[0102] In another aspect, the metal line composition varies between metallization layers. Such an arrangement may be referred to as a heterogeneous metallization layer. In one embodiment, tungsten (with a Mo liner) is used as the conductive fill material for larger interconnects, while cobalt is used as the conductive fill material for smaller interconnects. Smaller lines with cobalt as the fill material may provide reduced electromigration while maintaining low resistivity. Using cobalt for smaller interconnects may address issues associated with shrinking, where the conductive barrier consumes a greater amount of interconnect volume and reduces the conductive filler, which substantially obstructs the advantages normally associated with interconnects.

[0103] In the first example, Fig. 8A A cross-sectional view of an integrated circuit structure having a metallization layer with one metal line composition over a metallization layer with a different metal line composition is shown according to an embodiment of the present disclosure. In one embodiment, a conductive metal pad conductive line scheme (e.g., such as in combination with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig. 8A interconnect layer.

[0104] refer to Fig. 8A, the integrated circuit structure 800 includes a first plurality of conductive interconnects 806 in and separated by a first inter-layer dielectric (ILD) layer 804 above a substrate 802. One of the conductive interconnects 806A is shown as having an underlying via 807. Individual conductive interconnects of the first plurality of conductive interconnects 806 include a first conductive barrier material 808 along sidewalls and a bottom of a first conductive fill material 810.

[0105] The second plurality of conductive interconnects 816 are in the second ILD layer 814 above the first ILD layer 804 and are separated by the second ILD layer. One of the conductive interconnects 816A is shown as having a lower via 817. Individual conductive interconnects in the second plurality of conductive interconnects 816 include a second conductive barrier material 818 along the sidewalls and bottom of a second conductive fill material 820. The second conductive fill material 820 is different in composition from the first conductive fill material 810. In one embodiment, a conductive metal liner conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form interconnection lines.

[0106] Reference again Fig. 8A , the second ILD layer 814 is on the etch stop layer 822. The conductive via 817 is in the second ILD layer 814 and in the opening of the etch stop layer 822. In one embodiment, the first ILD layer 804 and the second ILD layer 814 include silicon, carbon, and oxygen, and the etch stop layer 822 includes silicon and nitrogen. In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 806 have a first width (W1), and individual conductive interconnects in the second plurality of conductive interconnects 816 have a second width (W2) greater than the first width (W1).

[0107] In the second example, Figure 8B A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, the integrated circuit structure having a metallization layer having one metal line composition and the metallization layer is coupled to a metallization layer having a different metal line composition. In one embodiment, a conductive metal pad conductive line scheme (e.g., such as in combination with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Figure 8B interconnect layer.

[0108] refer to Figure 8B, the integrated circuit structure 850 includes a first plurality of conductive interconnects 856 in and separated by a first inter-layer dielectric (ILD) layer 854 above a substrate 852. One of the conductive interconnects 856A is shown as having an underlying via 857. Individual conductive interconnects of the first plurality of conductive interconnects 856 include a first conductive barrier material 858 along sidewalls and a bottom of a first conductive fill material 860.

[0109] The second plurality of conductive interconnects 866 are in the second ILD layer 864 above the first ILD layer 854 and are separated by the second ILD layer. One of the conductive interconnects 866A is shown as having a lower via 867. Individual conductive interconnects in the second plurality of conductive interconnects 866 include a second conductive barrier material 868 along the sidewalls and bottom of a second conductive fill material 870. The second conductive fill material 870 is different in composition from the first conductive fill material 860. In one embodiment, a conductive metal liner conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form interconnection lines.

[0110] In one embodiment, the conductive via 867 is on and electrically coupled to an individual conductive interconnect line 856B in the first plurality of conductive interconnect lines 856, electrically coupling an individual conductive interconnect line 866A in the second plurality of conductive interconnect lines 866 to an individual conductive interconnect line 856B in the first plurality of conductive interconnect lines 856. In one embodiment, the individual conductive interconnect lines in the first plurality of conductive interconnect lines 856 are along a first direction 898 (e.g., in and out of the page), and the individual conductive interconnect lines in the second plurality of conductive interconnect lines 866 are along a second direction 899 orthogonal to the first direction 898, as shown. In one embodiment, the conductive via 867 includes a second conductive barrier material 868 along the sidewalls and bottom of the second conductive fill material 870, as shown.

[0111] In one embodiment, the second ILD layer 864 is on the etch stop layer 872 on the first ILD layer 854. The conductive via 867 is in the second ILD layer 864 and in the opening of the etch stop layer 872. In one embodiment, the first ILD layer 854 and the second ILD layer 864 include silicon, carbon, and oxygen, and the etch stop layer 872 includes silicon and nitrogen. In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 856 have a first width (W1), and individual conductive interconnects in the second plurality of conductive interconnects 866 have a second width (W2) greater than the first width (W1).

[0112] In one embodiment, the second conductive fill material 870 consists essentially of tungsten and the first conductive fill material 860 consists essentially of cobalt. In one such embodiment, the first conductive barrier material 858 is compositionally different from the second conductive barrier material 868. In another such embodiment, the first conductive barrier material 858 is compositionally the same as the second conductive barrier material 868.

[0113] Fig. 9 It is shown that the embodiment of the present disclosure is suitable for combining Fig. 8A and Figure 8B A cross-sectional view of an individual interconnect line with a conductive capping structure arrangement is shown in the structure. In one embodiment, a conductive metal pad conductive line scheme (e.g., such as a combination of Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig. 9 interconnect layer.

[0114] refer to Fig. 9 , an interconnect line 900 in a dielectric layer 901 includes a conductive liner 902 having a conductive barrier 903 therein, and the conductive barrier 903 has a conductive filler 904 therein. A conductive cap (eg, a cobalt cap) is on the conductive liner 902, the conductive barrier 903, and the conductive filler 904.

[0115] In one embodiment, the conductive liner 902 is or includes a metal, such as but not limited to Ta or Ti, and may have a thickness in the range of 2-5 nanometers. In one embodiment, the conductive barrier 903 includes a metal nitride, such as but not limited to TaN (e.g., including tantalum and nitrogen), and may have a thickness in the range of 2-5 nanometers. In one embodiment, the conductive filler 904 is or includes copper.

[0116] Fig.10 A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, the integrated circuit structure having four metallization layers with one metal line composition and one pitch, and the four metallization layers are above two metallization layers with different metal line compositions and smaller pitches. In one embodiment, a conductive metal pad conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig.10 interconnect layer.

[0117] refer to Fig.10, the integrated circuit structure 1000 includes a first plurality of conductive interconnects 1004 in and separated by a first inter-layer dielectric (ILD) layer 1002 over a substrate 1001. Individual conductive interconnects of the first plurality of conductive interconnects 1004 include a first conductive barrier material 1006 along sidewalls and a bottom of a first conductive fill material 1008. Individual conductive interconnects of the first plurality of conductive interconnects 1004 are arranged along a first direction 1098 (e.g., into and out of the page).

[0118] The second plurality of conductive interconnects 1014 are in and spaced apart from each other in the second ILD layer 1012 above the first ILD layer 1002. Individual conductive interconnects in the second plurality of conductive interconnects 1014 include the first conductive barrier material 1006 along the sidewalls and bottom of the first conductive fill material 1008. Individual conductive interconnects in the second plurality of conductive interconnects 1014 are along a second direction 1099 that is orthogonal to the first direction 1098.

[0119] The third plurality of conductive interconnects 1024 are in and spaced apart by the third ILD layer 1022 above the second ILD layer 1012. Individual conductive interconnects of the third plurality of conductive interconnects 1024 include a second conductive barrier material 1026 along sidewalls and a bottom of a second conductive fill material 1028. The second conductive fill material 1028 is different in composition from the first conductive fill material 1008. Individual conductive interconnects of the third plurality of conductive interconnects 1024 are along a first direction 1098.

[0120] The fourth plurality of conductive interconnects 1034 are in and spaced apart by the fourth ILD layer 1032 over the third ILD layer 1022. Individual conductive interconnects of the fourth plurality of conductive interconnects 1034 include the second conductive barrier material 1026 along sidewalls and bottoms of the second conductive fill material 1028. Individual conductive interconnects of the fourth plurality of conductive interconnects 1034 are along the second direction 1099.

[0121] The fifth plurality of conductive interconnects 1044 are in and spaced apart by the fifth ILD layer 1042 over the fourth ILD layer 1032. Individual conductive interconnects of the fifth plurality of conductive interconnects 1044 include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028. Individual conductive interconnects of the fifth plurality of conductive interconnects 1044 are along the first direction 1098.

[0122] The sixth plurality of conductive interconnects 1054 are in and spaced apart by the sixth ILD layer 1052 over the fifth ILD layer 1042. Individual conductive interconnects of the sixth plurality of conductive interconnects 1054 include the second conductive barrier material 1026 along sidewalls and a bottom of the second conductive fill material 1028. Individual conductive interconnects of the sixth plurality of conductive interconnects 1054 are along the second direction 1099.

[0123] In one embodiment, the second conductive fill material 1028 consists essentially of tungsten and the first conductive fill material 1008 consists essentially of cobalt.

[0124] In one embodiment, the first conductive barrier material 1006 is different in composition from the second conductive barrier material 1026. In another embodiment, the first conductive barrier material 1006 and the second conductive barrier material 1026 have the same composition.

[0125] In one embodiment, the first conductive via 1019 is on and electrically coupled to the individual conductive interconnect 1004A in the first plurality of conductive interconnects 1004. The individual conductive interconnect 1014A in the second plurality of conductive interconnects 1014 is on and electrically coupled to the first conductive via 1019.

[0126] The second conductive via 1029 is on and electrically coupled to the individual conductive interconnect 1014B in the second plurality of conductive interconnects 1014. The individual conductive interconnect 1024A in the third plurality of conductive interconnects 1024 is on and electrically coupled to the second conductive via 1029.

[0127] The third conductive via 1039 is on and electrically coupled to the individual conductive interconnect 1024B in the third plurality of conductive interconnects 1024. The individual conductive interconnect 1034A in the fourth plurality of conductive interconnects 1034 is on and electrically coupled to the third conductive via 1039.

[0128] The fourth conductive via 1049 is on and electrically coupled to the individual conductive interconnect 1034B in the fourth plurality of conductive interconnects 1034. The individual conductive interconnect 1044A in the fifth plurality of conductive interconnects 1044 is on and electrically coupled to the fourth conductive via 1049.

[0129] The fifth conductive via 1059 is on and electrically coupled to the individual conductive interconnect 1044B in the fifth plurality of conductive interconnects 1044. The individual conductive interconnect 1054A in the sixth plurality of conductive interconnects 1054 is on and electrically coupled to the fifth conductive via 1059.

[0130] In one embodiment, the first conductive via 1019 includes the first conductive barrier material 1006 along the sidewalls and bottom of the first conductive filling material 1008. The second conductive via 1029, the third conductive via 1039, the fourth conductive via 1049, and the fifth conductive via 1059 include the second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filling material 1028.

[0131] In one embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 are separated from each other by corresponding etch stop layers 1090 between adjacent ILD layers. In one embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 include silicon, carbon, and oxygen.

[0132] In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 1004 and the second plurality of conductive interconnects 1014 have a first width (W1). Individual conductive interconnects in the third plurality of conductive interconnects 1024, the fourth plurality of conductive interconnects 1034, the fifth plurality of conductive interconnects 1044, and the sixth plurality of conductive interconnects 1054 have a second width (W2) greater than the first width (W1).

[0133] In another aspect, techniques for patterning metal line ends are described. To provide background, in advanced nodes of semiconductor manufacturing, low-level interconnects can be generated by separate patterning processes for line grids, line ends, and vias. However, the fidelity of the composite pattern may tend to degrade as vias erode line ends and line ends erode vias. Embodiments described herein provide line end processes, also referred to as plug processes, that eliminate the associated proximity rule. Embodiments may allow vias to be placed at line ends and allow large vias to be fixed across line ends.

[0134] To provide more context, Fig.11A A plan view of a metallization layer according to an embodiment of the present disclosure and a corresponding cross-sectional view taken along the aa′ axis of the plan view of the metallization layer are shown. Fig. 11BA cross-sectional view of a wire end or plug is shown according to an embodiment of the present disclosure. Fig. 11C Another cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is shown. In one embodiment, a conductive metal pad conductive wire scheme (e.g., such as a combination of Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Figures 11A-11C interconnect layer.

[0135] refer to Fig.11A , the metallization layer 1100 includes a metal line 1102 formed in a dielectric layer 1104. The metal line 1102 can be coupled to a via 1103 below. The dielectric layer 1104 can include a line end or plug region 1105. Fig. 11B , the line end or plug region 1105 of the dielectric layer 1104 can be manufactured by patterning the hard mask layer 1110 on the dielectric layer 1104 and then etching the exposed portion of the dielectric layer 1104. The exposed portion of the dielectric layer 1104 can be etched to a depth suitable for forming the line trench 1106 or further etched to a depth suitable for forming the via trench 1108. Fig. 11C , two vias adjacent to opposite sidewalls of the line end or plug 1105 can be fabricated in a single large exposure 1116 to ultimately form a line trench 1112 and a via trench 1114 .

[0136] However, again referring to Figures 11A-11C , fidelity issues and / or hard mask etch issues may result in imperfect patterning schemes. In contrast, one or more embodiments described herein include implementations of a process flow that includes constructing a line end dielectric (plug) after a trench and via patterning process.

[0137] In one aspect, then, one or more embodiments described herein relate to schemes for constructing non-conductive spaces or breaks (referred to as "line ends," "plugs," or "cuts") between metal lines, and in some embodiments, also constructing associated conductive vias. Conductive vias are defined as landing on previous layer metal patterns. In this way, the embodiments described herein achieve a more robust interconnect manufacturing scheme because there is less reliance on alignment performed by lithographic equipment. Such an interconnect manufacturing scheme can be used to relax constraints on alignment / exposure, can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce overall process operations and processing time; otherwise, patterning such features using conventional schemes would require corresponding process operations and processing time.

[0138] Figures 12A-12FFIG. 1 shows a plan view and corresponding cross-sectional views of various operations in a plug finishing scheme according to an embodiment of the present disclosure. In one embodiment, a conductive metal pad conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Figures 12A-12F interconnect layer.

[0139] refer to Fig. 12A , a method of manufacturing an integrated circuit structure includes forming a line trench 1206 in an upper portion 1204 of an interlayer dielectric (ILD) material layer 1202 formed above a lower metallization layer 1200. A via trench 1208 is formed in a lower portion 1210 of the ILD material layer 1202. The via trench 1208 exposes a metal line 1212 of the lower metallization layer 1200.

[0140] refer to Fig. 12B A sacrificial material 1214 is formed above the ILD material layer 1202 and in the line trench 1206 and the via trench 1208. A hard mask 1215 may be formed on the sacrificial material 1214. Fig. 12B In one embodiment, sacrificial material 1214 includes carbon.

[0141] refer to Fig. 12C The sacrificial material 1214 is patterned to interrupt the continuity of the sacrificial material 1214 in the line trench 1206 , for example, to provide an opening 1216 in the sacrificial material 1214 .

[0142] refer to Fig.12D , the opening 1216 in the sacrificial material 1214 is filled with a dielectric material to form a dielectric plug 1218. In one embodiment, after the opening 1216 in the sacrificial material 1214 is filled with a dielectric material, the hard mask 1215 is removed to provide a dielectric plug 1218 having an upper surface 1220 above an upper surface 1222 of the ILD material 1202, as shown in FIG. Fig.12D The sacrificial material 1214 is removed so that the dielectric plug 1218 remains.

[0143] In one embodiment, filling the opening 1216 of the sacrificial material 1214 with a dielectric material includes filling with a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, filling the opening 1216 of the sacrificial material 1214 with a dielectric material includes filling using atomic layer deposition (ALD).

[0144] refer to Fig.12E, line trench 1206 and via trench 1208 are filled with conductive material 1224. In one embodiment, conductive material 1224 is formed above and over dielectric plug 1218 and ILD layer 1202, as shown.

[0145] refer to Fig.12F , the conductive material 1224 and the dielectric plug 1218 are planarized to provide a planarized dielectric plug 1218 ′, wherein the continuity of the conductive material 1224 in the line trench 1206 is broken.

[0146] Reference again Fig.12F According to an embodiment of the present disclosure, an integrated circuit structure 1250 includes an interlayer dielectric (ILD) layer 1202 above a substrate. A conductive interconnect 1224 is in a trench 1206 in the ILD layer 1202. The conductive interconnect 1224 has a first portion 1224A and a second portion 1224B, the first portion 1224A being laterally adjacent to the second portion 1224B. A dielectric plug 1218' is between and laterally adjacent to the first portion 1224A and the second portion 1224B of the conductive interconnect 1224. Although not shown, in one embodiment, the conductive interconnect 1224 includes a conductive barrier liner and a conductive fill material, exemplary materials for which are described above. In one such embodiment, the conductive fill material includes cobalt.

[0147] In one embodiment, dielectric plug 1218 ′ includes a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, dielectric plug 1218 ′ is in direct contact with first portion 1224A and second portion 1224B of conductive interconnect line 1224 .

[0148] In one embodiment, the dielectric plug 1218′ has a bottom 1218A that is substantially coplanar with the bottom 1224C of the conductive interconnect line 1224. In one embodiment, the first conductive via 1226 is in the trench 1208 in the ILD layer 1202. In one such embodiment, the first conductive via 1226 is below the bottom 1224C of the interconnect line 1224, and the first conductive via 1226 is electrically coupled to the first portion 1224A of the conductive interconnect line 1224.

[0149] In one embodiment, the second conductive via 1228 is in the third trench 1230 in the ILD layer 1202. The second conductive via 122 is below the bottom 1224C of the interconnect line 1224, and the second conductive via 1228 is electrically coupled to the second portion 1224B of the conductive interconnect line 1224.

[0150] The dielectric plug may be formed using a filling process (e.g., a chemical vapor deposition process). Artifacts may remain in the fabricated dielectric plug. As an example, Fig.13A A cross-sectional view of a conductive wire plug having a seam therein according to an embodiment of the present disclosure is shown. In one embodiment, a conductive metal pad conductive wire scheme (e.g., such as a combination of Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig.13A interconnect layer.

[0151] refer to Fig.13A , the dielectric plug 1318 has a substantially vertical seam 1300 that is substantially equally spaced from the first portion 1224A of the conductive interconnect line 1224 and the second portion 1224B of the conductive interconnect line 1224 .

[0152] It should be appreciated that a dielectric plug may be included only on selected metallization layers (e.g., underlying metallization layers) that is different in composition from the ILD material housing the dielectric plug. As an example, Fig. 13B A cross-sectional view of a metallization layer stack including a conductive line plug at the location of an underlying metal line according to an embodiment of the present disclosure is shown. In one embodiment, a conductive metal pad conductive line scheme (e.g., as combined with Figure 1B ) and / or a differentiated conductive line scheme (e.g., as described above in conjunction with Figure 2A , Figure 2B and Figure 3 to form Fig. 13B interconnect layer.

[0153] refer to Fig. 13B , the integrated circuit structure 1350 includes a first plurality of conductive interconnects 1356 in and separated by a first inter-layer dielectric (ILD) layer 1354 over a substrate 1352. Individual conductive interconnects in the first plurality of conductive interconnects 1356 have continuity interrupted by one or more dielectric plugs 1358. In one embodiment, the one or more dielectric plugs 1358 include a different material than the ILD layer 1354. A second plurality of conductive interconnects 1366 are in and separated by a second ILD layer 1364 over the first ILD layer 1354. In one embodiment, individual conductive interconnects in the second plurality of conductive interconnects 1366 have continuity interrupted by one or more portions 1368 of the second ILD layer 1364. It should be appreciated that other metallization layers may be included in the integrated circuit structure 1350 as shown.

[0154] In one embodiment, one or more dielectric plugs 1358 include a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, the first ILD layer 1354 and the second ILD layer 1364 (and therefore, one or more portions 1368 of the second ILD layer 1364) include a carbon-doped silicon oxide material.

[0155] In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 1356 include a first conductive barrier liner 1356A and a first conductive fill material 1356B. Individual conductive interconnects in the second plurality of conductive interconnects 1366 include a second conductive barrier liner 1366A and a second conductive fill material 1366B. In one such embodiment, the first conductive fill material 1356B is different in composition from the second conductive fill material 1366B. In a specific such embodiment, the first conductive fill material 1356B includes cobalt and the second conductive fill material 1366B includes copper (e.g., together with a conductive metal liner).

[0156] In one embodiment, the first plurality of conductive interconnects 1356 have a first pitch (P1, as shown in similar layer 1370). The second plurality of conductive interconnects 1366 have a second pitch (P2, as shown in similar layer 1380). The second pitch (P2) is greater than the first pitch (P1). In one embodiment, individual conductive interconnects in the first plurality of conductive interconnects 1356 have a first width (W1, as shown in similar layer 1370). Individual conductive interconnects in the second plurality of conductive interconnects 1366 have a second width (W2, as shown in similar layer 1380). The second width (W2) is greater than the first width (W1).

[0157] It should be appreciated that the layers and materials described above in conjunction with back-end-of-line (BEOL) structures and processes can be formed on or above a lower semiconductor substrate or structure (e.g., one or more lower device layers of an integrated circuit). In one embodiment, the lower semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. Semiconductor substrates often include wafers, or other bodies of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon on insulator (SOI), as well as similar substrates formed from other semiconductor materials, such as substrates including germanium, carbon, or III-V materials. Depending on the stage of manufacturing, the semiconductor substrate often includes transistors, integrated circuit units, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In addition, the structure shown can be fabricated on an interconnect layer at a lower level below.

[0158] Although the foregoing methods of fabricating a metallization layer or a portion of a metallization layer of a BEOL metallization layer are described in detail with respect to selected operations, it should be appreciated that additional or intervening operations used to perform fabrication may include standard microelectronics fabrication processes, such as photolithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other action associated with microelectronic component fabrication. Furthermore, it should be appreciated that the process operations described with respect to the foregoing process flow may be performed in an alternative order, not every operation need be performed, or additional process operations may be performed, or both.

[0159] In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0160] In one embodiment, as used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. The interconnects can be a single material layer, or can be formed by several layers (including a conductive liner layer and a filling layer). Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnects. In one embodiment, the interconnects are composed of conductive materials (e.g., tantalum or titanium liners, tantalum nitride barriers, and copper fillers). In the art, interconnects are sometimes referred to as traces, wiring, wires, metals, or simply interconnects.

[0161] In one embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metallic substance. For example, a hard mask or other covering material may include a nitride (e.g., titanium nitride) layer of titanium or another metal. In one or more of these layers, potentially smaller amounts of other materials, such as oxygen, may be included. Alternatively, other hard mask layers known in the prior art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0162] In one embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography. Positive tone or negative tone resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0163] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the prior art; for example, integrated circuits or other microelectronic devices are used in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like by one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the solutions disclosed herein.

[0164] Fig.14A computing device 1400 is shown according to one embodiment of the present disclosure. The computing device 1400 houses a board 1402. The board 1402 may include multiple components, including, but not limited to, a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402. In some embodiments, the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In other embodiments, the communication chip 1406 is part of the processor 1404.

[0165] Depending on its application, the computing device 1400 may include other components, which may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0166] The communication chip 1406 is capable of wireless communication for transmitting data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data by using modulated electromagnetic radiation via a non-solid medium. The term does not imply that the associated device does not contain any wiring, although in some embodiments they may not. The communication chip 1406 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, EDCT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher versions. The computing device 1400 may include multiple communication chips 1406. For example, the first communication chip 1406 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1406 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO or others.

[0167] The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of the disclosed embodiments, the integrated circuit die of the processor includes one or more structures, for example, integrated circuit structures constructed according to the disclosed embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0168] The communication chip 1406 also includes an integrated circuit die packaged within the semiconductor chip 1406. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip is constructed according to an embodiment of the present disclosure.

[0169] In other implementations, other components housed within computing device 1400 may include integrated circuit dies constructed in accordance with implementations of embodiments of the present disclosure.

[0170] In various embodiments, computing device 1400 may be a laptop, netbook, notebook, ultrabook, smart phone, tablet computer, personal digital assistant (PDA), ultra mobile PC, cell phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, computing device 1400 may be any other electronic device that processes data.

[0171] Fig.15 An interposer 1500 is shown that includes one or more embodiments of the present disclosure. Interposer 1500 is an intermediate substrate for bridging a first substrate 1502 to a second substrate 1504. The first substrate 1502 can be, for example, an integrated circuit die. The second substrate 1504 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of interposer 1500 is to extend the connection to a wider spacing or to rewire the connection to a different connection. For example, interposer 1500 can couple the integrated circuit die to a ball grid array (BGA) 1506, which in turn can be coupled to the second substrate 1504. In some embodiments, the first and second substrates 1502 / 1504 are attached to opposite sides of interposer 1500. In other embodiments, the first and second substrates 1502 / 1504 are attached to the same side of interposer 1500. And, in other embodiments, three or more substrates are interconnected by interposer 1500.

[0172] The interposer 1500 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material (e.g., polyimide). In other embodiments, the interposer 1500 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0173] The interposer 1500 may include metal interconnects 1508 and vias 1510, including but not limited to through silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 1514, which include both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices may also be formed on the interposer 1500, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be applied to the manufacture of the interposer 1500 or to the manufacture of components included in the interposer 1500.

[0174] Fig.16 is an isometric view of a mobile computing platform 1600 according to an embodiment of the present disclosure, which employs an integrated circuit (IC) manufactured according to one or more processes described herein or includes one or more features described herein.

[0175] The mobile computing platform 1600 can be any portable device configured for electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1600 can be any of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1605, a chip-level (SoC) or package-level integrated system 1610, and a battery 1613. In an exemplary embodiment, the display screen 1605 is a touch screen (capacitive, inductive, resistive, etc.). As shown in the figure, the higher the transistor packaging density can achieve a greater degree of integration in the system 1610, the larger the portion of the mobile computing platform 1600 that can be occupied by the battery 1613 or a non-volatile storage device (e.g., a solid-state drive), or the larger the number of transistor gates used to improve the platform function. Similarly, the greater the carrier mobility of each transistor in the system 1610, the more powerful the function. In this way, the technology described herein can achieve improvements in the performance and form factor of the mobile computing platform 1600.

[0176] The integrated system 1610 is further shown in the expanded view 1620. In an exemplary embodiment, the packaged device 1677 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) that is manufactured according to one or more processes described herein, or includes one or more features described herein. The packaged device 1677 is further coupled to the board 1660 along with one or more of a power management integrated circuit (PMIC) 1615, an RF (wireless) integrated circuit (RFIC) 1625 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module, and also including a power amplifier on the transmit path and a low noise amplifier on the receive path) and its controller 1611. Functionally, the PMIC 1615 performs battery power regulation, DC to DC conversion, etc., and therefore has an input coupled to the battery 1613 and has an output that provides current supply to all other functional modules. As further shown, in an exemplary embodiment, the RFIC 1625 has an output coupled to a provided antenna to implement any of a variety of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, EDCT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher. In alternative embodiments, each of these board-level modules can be integrated into multiple separate ICs coupled to the packaging substrate of the packaged device 1677 or integrated into a single IC (SoC) coupled to the packaging substrate of the packaged device 1677.

[0177] In another aspect, semiconductor packages are used to protect integrated circuit (IC) chips or dies and also provide the die with an electrical interface to external circuit elements. As the demand for smaller electronic devices increases, semiconductor packages are designed to be more compact and must support greater circuit density. In addition, the demand for higher performance devices has led to a need for improved semiconductor packages that can achieve a thin package profile and low overall warpage that is compatible with subsequent assembly processes.

[0178] In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die to a ceramic or organic package substrate. Specifically, a C4 solder ball connection can be implemented to provide a flip chip interconnection between a semiconductor device and a substrate. Flip chip or controlled collapse chip connection (C4) is a type of installation for a semiconductor device that utilizes solder bumps instead of wire bonding, and the semiconductor device is, for example, an integrated circuit (IC) chip, MEMS or component. Solder bumps are deposited on the C4 pads located on the top side of the substrate package. In order to mount the semiconductor device on the substrate, the semiconductor device is turned upside down so that the active side faces the mounting area downward. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0179] Fig.17 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure.

[0180] refer to Fig.17 , device 1700 includes a die 1702, such as an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein. Die 1702 includes metallization pads 1704. Package substrate 1706 (e.g., a ceramic or organic substrate) includes connections 1708 thereon. Die 1702 and package substrate 1706 are electrically connected via solder balls 1710 coupled to metallization pads 1704 and connections 1708. Underfill material 1712 surrounds solder balls 1710.

[0181] Processing a flip chip can be similar to conventional IC manufacturing, but with several additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. Then, small solder dots are deposited on each metallized pad. Then, the chip is cut from the wafer as normal. In order to attach the flip chip to the circuit, the chip is turned upside down to place the solder dots down on the connectors on the underlying electronic device or circuit board. Then, the solder is re-melted to create an electrical connection, usually using ultrasound or alternatively using a reflow soldering process. This also leaves a small space between the circuit elements of the chip and the underlying mounting. In most cases, an electrically insulating adhesive is then "bottom-filled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to the different heating of the chip and the rest of the system.

[0182] In other embodiments, according to embodiments of the present disclosure, updated packaging and die-to-die interconnect schemes, such as through-silicon vias (TSVs) and silicon interposers, are implemented to manufacture high-performance multi-chip modules (MCMs) and systems in packages (SiPs) containing integrated circuits (ICs), wherein the integrated circuits (ICs) are manufactured according to one or more processes described herein, or include one or more features described herein.

[0183] Thus, embodiments of the present disclosure include the fabrication of advanced integrated circuit structures, including conductive line schemes and resulting structures for use in the fabrication of integrated circuit structures.

[0184] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if only a single embodiment is described for a particular feature. Unless otherwise specified, the examples of features provided in the present disclosure are intended to be illustrative rather than limiting. The above description is intended to cover such alternatives, modifications, and equivalents that will be apparent to those skilled in the art with the beneficial effects of the present disclosure.

[0185] The scope of the present disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it alleviates any or all of the problems addressed herein. Accordingly, new claims may be drafted during the prosecution of the present application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features in the dependent claims may be combined with those of the independent claims, and features in the respective independent claims may be combined in any appropriate manner rather than merely by the specific combinations listed in the appended claims.

[0186] The following examples relate to other embodiments. The various features of different embodiments can be combined in various ways with some included features and other features not included to suit various different applications.

[0187] Example embodiment 1: An integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive line includes a conductive pad, the conductive pad has a conductive barrier therein, the conductive barrier has a conductive filler therein, wherein the conductive pad is directly on the conductive via.

[0188] Exemplary Embodiment 2: The integrated circuit structure of Exemplary Embodiment 1, wherein the conductive via comprises a metal selected from the group consisting of W, Mo, and Ru.

[0189] Exemplary Embodiment 3: The integrated circuit structure of Exemplary Embodiment 1 or 2, wherein the conductive pad comprises a metal selected from the group consisting of Ta and Ti.

[0190] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the conductive barrier comprises tantalum and nitrogen.

[0191] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the conductive filler comprises copper.

[0192] Exemplary embodiment 6: An integrated circuit structure includes a plurality of conductive lines on the same level and along the same direction, a first conductive line among the plurality of conductive lines having a first width and a first component, and a second conductive line among the plurality of conductive lines having a second width and a second component. The second width is greater than the first width, and the second component is different from the first component. The second conductive line among the plurality of conductive lines has a conductive pad, a conductive barrier therein, and a conductive filler therein. The integrated circuit structure also includes an interlayer dielectric (ILD) structure, the ILD structure having a portion between adjacent conductive lines among the plurality of conductive lines.

[0193] Exemplary Embodiment 7: The integrated circuit structure of Exemplary Embodiment 6, wherein the second conductive line of the plurality of conductive lines is on a conductive via, the conductive via comprising a metal selected from the group consisting of W, Mo, and Ru.

[0194] Example 8: The integrated circuit structure of Example 6 or 7, wherein the conductive pad comprises a metal selected from the group consisting of Ta and Ti.

[0195] Example 9: The integrated circuit structure of Example 6, 7 or 8, wherein the conductive barrier comprises tantalum and nitrogen.

[0196] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, 8 or 9, wherein the conductive filler comprises copper.

[0197] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive line includes a conductive pad, the conductive pad has a conductive barrier therein, the conductive barrier has a conductive filler therein, wherein the conductive pad is directly on the conductive via.

[0198] Exemplary Embodiment 12: The computing device of Exemplary Embodiment 11, further comprising a memory coupled to the board.

[0199] Exemplary Embodiment 13: The computing device of Exemplary Embodiment 11 or 12, further comprising a communication chip coupled to the board.

[0200] Example Embodiment 14: The computing device of Example Embodiment 11, 12 or 13, further comprising a camera coupled to the board.

[0201] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising a battery coupled to the board.

[0202] Exemplary Embodiment 16: The computing device of Exemplary Embodiment 11, 12, 13 or 15, further comprising a speaker coupled to the board.

[0203] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising a compass coupled to the board.

[0204] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a GPS coupled to the board.

[0205] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a display coupled to the board.

[0206] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: a conductive via in the first dielectric layer; as well as A conductive line in a second dielectric layer, the conductive line comprising a conductive pad having a conductive barrier therein, the conductive barrier having a conductive filler therein, wherein the conductive pad is directly on the conductive via.

2. The integrated circuit structure according to claim 1, wherein: The conductive via includes a metal selected from the group consisting of W, Mo, and Ru.

3. The integrated circuit structure according to claim 1 or 2, wherein: The conductive pad includes a metal selected from the group consisting of Ta and Ti.

4. The integrated circuit structure according to claim 1 or 2, wherein: The conductive barrier includes tantalum and nitrogen.

5. The integrated circuit structure according to claim 1 or 2, wherein: The conductive filler includes copper.

6. An integrated circuit structure comprising: A plurality of conductive lines on the same level and along the same direction, a first conductive line among the plurality of conductive lines having a first width and a first component, and a second conductive line among the plurality of conductive lines having a second width and a second component, the second width being greater than the first width, and the second component being different from the first component, the second conductive line among the plurality of conductive lines having a conductive pad, a conductive barrier therein, and a conductive filler therein; as well as An interlayer dielectric (ILD) structure has a portion between adjacent conductive lines among the plurality of conductive lines.

7. The integrated circuit structure according to claim 6, wherein: The second one of the plurality of conductive lines is on a conductive via comprising a metal selected from the group consisting of W, Mo, and Ru.

8. The integrated circuit structure according to claim 6 or 7, wherein: The conductive pad includes a metal selected from the group consisting of Ta and Ti.

9. The integrated circuit structure according to claim 6 or 7, wherein: The conductive barrier includes tantalum and nitrogen.

10. The integrated circuit structure according to claim 6 or 7, wherein: The conductive filler includes copper.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a conductive via in the first dielectric layer; and A conductive line in a second dielectric layer, the conductive line comprising a conductive pad having a conductive barrier therein, the conductive barrier having a conductive filler therein, wherein the conductive pad is directly on the conductive via.

12. The computing device of claim 11, further comprising: A memory is coupled to the board.

13. The computing device according to claim 11 or 12, further comprising: A communication chip is coupled to the board.

14. The computing device according to claim 11 or 12, further comprising: A camera is coupled to the board.

15. The computing device according to claim 11 or 12, further comprising: A battery is coupled to the board.

16. The computing device according to claim 11 or 12, further comprising: A speaker is coupled to the board.

17. The computing device according to claim 11 or 12, further comprising: A compass is coupled to the board.

18. The computing device according to claim 11 or 12, further comprising: Coupled to the board's GPS.

19. The computing device according to claim 11 or 12, further comprising: A display is coupled to the panel.

20. The computing device according to claim 11 or 12, wherein: The component is a packaged integrated circuit die.

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