Semiconductor device and method of forming an inverse wlb package with a vertical e-bar structure

Abstract

Semiconductor devices and methods of forming an inverted EWLB package having a vertical E-BAR structure are provided. A semiconductor device has an electrical component and an e-bar structure disposed on a side of the electrical component. An encapsulant is deposited over the electrical components and the e-bar structures. The RDL is formed on the electrical component, the encapsulant, and the e-bar structure. The e-bar structure has a core layer, a first conductive layer formed on a first surface of the core layer, and a second conductive layer formed on a second surface of the core layer. The second conductive layer includes a thickness greater than that of the first conductive layer. The RDL has an insulating layer formed on the electrical component and the encapsulant, and a conductive layer formed on the insulating layer. A bump is formed on a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods of forming an inverted eWLB package having a vertical e-bar structure. Background Art

[0002] Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electrical devices, optoelectronic devices, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices typically include a semiconductor die or substrate having an electrical interconnect structure, such as a redistribution layer (RDL) formed on one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. A vertical interconnect structure disposed adjacent to the semiconductor die is electrically connected to the RDL, and an encapsulant covers the vertical interconnect structure and the semiconductor die. The encapsulant and the vertical interconnect structure are typically subjected to a grinding operation to flatten the surface. Over-grinding may reduce the thickness of the vertical interconnect structure, or even remove the contact surface, resulting in defects and reduced manufacturing yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1c shows a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2l shows the process of forming an e-bar substrate;

[0006] Figure 3a-3j An electrical assembly having adjacent e-bar structures covered by a sealant is shown;

[0007] Figure 4a-4e shows a process for forming an embedded wafer level ball grid array; and

[0008] Figure 5 A printed circuit board (PCB) is shown, with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0009] The present invention is described in one or more embodiments in the following description with reference to the accompanying drawings, wherein the same reference numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be understood by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. In the figures, elements with similar functions are given the same reference numerals. The term "semiconductor die" used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0010] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, establish the relationship between voltage and current required to perform the circuit function.

[0011] Back-end manufacturing refers to cutting or dividing the finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to divide the semiconductor dies, the wafer is scribed and broken along the non-functional areas of the wafer (called saw streets or scribe lines). The wafer is divided using a laser cutting tool or a saw blade. After division, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the package. The electrical connection can be made by a conductive layer, a bump, a stud bump, a conductive glue, or a wire bond. An encapsulant or other molding material is deposited on the package to provide physical support and electrical insulation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device can be used for other system components.

[0012] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by passive inter-die wafer regions or saw streets 106. The saw streets 106 provide a dicing area to separate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0013] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0014] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electroplating, chemical plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0015] exist Figure 1c In the process, semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested after singulation to identify known good dies or known good units (KGD / KGU).

[0016] Figure 2aA portion of a base or core layer 120 for an embedded bar (e-bar) wafer or substrate 122 is shown, which contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The core layer 120 can also be a multilayer flexible laminate, ceramic, copper clad laminate (CCL), glass, or epoxy molding compound. In another embodiment, the base core layer 120 can also be any suitable laminate insert, PCB, wafer form, bar insert, lead frame, or other type of substrate. The core layer 120 can include one or more laminate layers of pre-impregnated (prepreg) polytetrafluoroethylene (PTFE), FR-4, FR-1, CEM-1 or CEM-3 in combination with phenolic cotton paper, epoxy resin, resin, woven glass, frosted glass, polyester and other reinforcing fibers or fabrics. Core layer 120 has a thickness T1 of 150.0 micrometers (μm), and includes a first major surface 124 and a second major surface 126 opposite to surface 124 .

[0017] exist Figure 2b In the embodiment, an opening or via 128 is formed in the surface 124 of the core layer 120 using an etching process or laser direct ablation (LDA) using a laser 129 to a depth of about half of T1.

[0018] exist Figure 2c In the embodiment of the present invention, a conductive layer 130 is formed in the opening 128 using PVD, CVD, electroplating, chemical plating or other suitable metal deposition process. The conductive layer 130 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of the conductive layer 130 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0019] exist Figure 2d In the embodiment, a conductive layer 132 is formed on the conductive layer 130 and the surface 124 of the core layer 120 using PVD, CVD, electroplating, chemical plating process or other suitable metal deposition process. The conductive layer 132 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. In one embodiment, the conductive layer 132 has a thickness of 24.0±7.0 μm. Portions of the conductive layer 132 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0020] An insulating or passivation layer 134 is formed on the conductive layer 132 and the surface 124 of the core layer 120 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 134 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. In one embodiment, the insulating layer 134 has a thickness of 64.0 μm. Figure 2e In the embodiment, an etching process or LDA (using a laser such as 129) is used to remove portions of insulating layer 134 to form openings or vias 138 extending to conductive layer 132 for further electrical interconnection.

[0021] exist Figure 2f In the embodiment of the present invention, a conductive layer 140 is formed in the opening 138 using PVD, CVD, electroplating, chemical plating or other suitable metal deposition process. The conductive layer 140 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of the conductive layer 140 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0022] exist Figure 2g In the embodiment, a conductive layer 144 is formed on the conductive layer 140 and the insulating layer 134 using PVD, CVD, electroplating, chemical plating process or other suitable metal deposition process. The conductive layer 144 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 144 operates as a contact pad for the RDL formed later. In one embodiment, the conductive layer 144 has a thickness of 24.0±7.0 μm. Portions of the conductive layer 144 can be electrically shared or electrically isolated, depending on the design and function of the electrical components attached thereto.

[0023] An insulating or passivation layer 146 is formed on the conductive layer 144 and the insulating layer 134 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 146 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. In one embodiment, the insulating layer 146 has a thickness of 15.0±7.5 μm. An etching process or LDA (using a laser such as 129) is used to remove portions of the insulating layer 146 to form openings or vias 148 extending to the conductive layer 144 for further electrical interconnection.

[0024] like Figure 2h As shown, Figure 2gThe partially e-bar substrate is inverted, and an opening or via 150 is formed in the surface 126 of the core layer 120 using an etching process or LDA (using a laser such as 129 ), and the opening or via 150 extends to the conductive layer 130 .

[0025] exist Figure 2i In the embodiment, a conductive layer 152 is formed in the opening 150, similar to Figure 2c . Similar to Figure 2d , forming a conductive layer 154 on the conductive layer 152 and the surface 126 of the core layer 120. In one embodiment, the conductive layer 154 has a thickness of 24.0±7.0 μm. Forming an insulating or passivation layer 156 on the conductive layer 152 and the surface 126 of the core layer 120. In one embodiment, the insulating layer 156 has a thickness of 24.0±7.0 μm. Removing portions of the insulating layer 156 with a laser such as 129 to form openings or vias 158 extending to the conductive layer 152 for further electrical interconnection, similar to Figure 2e .

[0026] exist Figure 2j In the embodiment, a conductive layer 160 is formed in the opening 158, similar to Figure 2f . Similar to Figure 2g , a conductive layer 162 is formed on the conductive layer 160 and the insulating layer 156. Specifically, the conductive layer 162 is made to have a thickness of about 40.0 μm or more, which is significantly thicker than the conductive layers 132, 144 and 154. The conductive layer 162 operates as a contact pad for the bumps formed later. An insulating or passivation layer 164 is formed on the conductive layer 160 and the insulating layer 156. In one embodiment, the insulating layer 164 has a thickness of 15.0±7.5 μm. Portions of the insulating layer 164 are removed with a laser such as 129 to form an opening or through hole 167 extending to the conductive layer 162 for further electrical interconnection.

[0027] The combination of conductive layers 130, 132, 140, 144, 152, 154, 160, and 162 and core layer 120 and insulating layers 134, 146, 156, and 164 constitute an e-bar wafer or substrate 168. Conductive layers 130, 132, 140, 144, 152, 154, 160, and 162 provide vertical electrical interconnections through e-bar substrate 168. Figure 2k is a top view of an e-bar substrate 168 having an array of e-bar structures 170a - 170h with the e-bar structures visible as conductive layer 162 through insulating layer 164 .

[0028] exist Figure 2l, a laser cutting tool or saw blade 172 is used to separate the e-bar substrate 168, leaving individual e-bar structures 170a-170d. After separation, each e-bar structure 170a-170d is made of conductive layers 130, 132, 140, 144, 152, 154, 160 and 162 from the e-bar substrate 168, as well as a portion of the core layer 120 and the insulating layers 134, 146, 156 and 164. In one embodiment, the e-bar substrates 170a-170d have a height H2 of 420μm±35μm, depending on the substrate 120 and the package thickness. With respect to the core layer 120, the e-bar substrates 170a-170d are rigid and generally incompressible to support cover structures, such as RDLs, as described below.

[0029] Figure 3a A temporary substrate or carrier 180 is shown that includes a sacrificial core material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. Substrate 180 has a major surface 182 and a major surface 184 opposite surface 182. In one embodiment, carrier 120 is a support structure having a temporary bonding layer 186 formed on the carrier. Temporary bonding layer 186 can be a film or foil bonded to surface 182.

[0030] exist Figure 3b In the embodiment, the electrical component 188 is disposed on the surface 182 of the substrate 180. The electrical component 188 can be similar to or made similar to Figure 1c The semiconductor die 104 is oriented with the conductive layer 112 toward the surface 182 of the substrate 180. Alternatively, the electrical component 188 may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0031] Electrical component 188 is positioned on substrate 180 using a pick and place operation. Electrical component 188 is in contact with bonding layer 186. E-bar structures 170a-170d, as well as other e-bar structures such as 170e-170h made similar to e-bar structures 170a-170d, are also positioned on and in contact with bonding layer 186 around or near the sides of electrical component 188 in a manner similar to the electrical components. Figure 3c An electrical component 188 and e-bar structures 170a - 170h bonded to substrate 180 near the sides of the electrical component are shown. Figure 3d 1 is a top view of individual e-bar structures 170a - 170h formed on substrate 180 around or near the sides of electrical component 188 .

[0032] In another embodiment, from Figure 2j-2kThe e-bar substrate 168 is disposed on and in contact with the bonding layer 186. In this case, the e-bar structures 170a-170h are not separated into individual units, but remain an integral part of the e-bar substrate 168, such as Figure 3e An opening 190 is formed in the e-bar substrate 168 to accommodate the electrical component 188 .

[0033] Similar to Figure 3b , the electrical component 188 is in contact with the bonding layer 186. Figure 3f , the e-bar substrate 168 is disposed on and in contact with the bonding layer 186 , with the electrical component 188 occupying the opening 190 . Figure 3g An electrical assembly 188 and an e-bar substrate 168 are shown with integrated e-bar structures 170a - 170h bonded to the substrate 180 . Figure 3h is a top view of an e-bar substrate 168 having integrated e-bar structures 170a - 170h disposed on substrate 180 around or adjacent to the sides of electrical components 188 .

[0034] from Figure 3c Or continue for 3 hours, such as Figure 3i As shown, a sealant or molding compound 192 is deposited on and around the electrical components 188 and the e-bar structures 170a-170h (or the e-bar substrate 168) using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 192 can be a liquid or particulate polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 192 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0035] exist Figure 3j In the embodiment, the carrier 180 and the bonding layer 186 are removed by chemical etching, chemical mechanical polishing (CMP), mechanical stripping, mechanical grinding, thermal baking, ultraviolet (UV) light, or wet stripping to expose the conductive layer 112 of the electrical component 188, the conductive layer 144 of the e-bar structure 170a-170h, and the surface 194 of the sealant 192. The reconstructed embedded wafer level package (eWLP) 200 including the electrical component 188, the e-bar structure 170a-170h, and the sealant 192 is ready for a multi-layer RDL build-up interconnect structure on the surface 110 of the electrical component 188, the surface 194 of the sealant 192, and the conductive layer 112 to provide electrical interconnection of the semiconductor die and external electrical components. The reconstructed eWLP 200 operates as a substrate to form a multi-layer RDL build-up interconnect structure.

[0036] Figure 4a-4e The formation of multiple redistribution layer (RDL) interconnect structures is shown. Figure 4a In the embodiment, the eWLP 200 is inverted and an insulating or passivation layer 210 is formed on the surface 194 and the conductive layer 112 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. The insulating layer 210 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. Portions of the insulating layer 210 are removed using an etching process or LDA (with a laser 214) to form openings or vias 218 extending to the conductive layers 112 and 144 for further electrical interconnection.

[0037] exist Figure 4b In the embodiment of the present invention, a conductive layer 220 is formed in the through hole 218 using PVD, CVD, electroplating, chemical plating process or other suitable metal deposition process. The conductive layer 220 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Portions of the conductive layer 220 can be electrically shared or electrically isolated, depending on the design and function of the semiconductor die 104 and other electrical components attached thereto.

[0038] Conductive layer 222 is formed on insulating layer 210 and surface 226 of conductive layer 220 using PVD, CVD, electroplating, electroless plating process, or other suitable metal deposition process. Conductive layer 222 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 222 is an RDL because it redistributes electrical signals across semiconductor die 104 and encapsulant 192. Portions of conductive layer 222 may be electrically common or electrically isolated, depending on the design and function of semiconductor die 104 and other electrical components attached thereto.

[0039] An insulating or passivation layer 228 is formed on the insulating layer 210 and the conductive layer 222 using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 228 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. Additional conductive layers (such as 220 and 222) and the insulating layer 228 may also be formed to form a multi-layer RDL 230.

[0040] exist Figure 4c, surface 232 of encapsulant 192 undergoes a grinding operation of grinder 233 to planarize surface 232, surface 238 of conductive layer 162, and insulating layer 164. In one embodiment, grinder 233 removes approximately 25.0 μm of material from conductive layer 162. Thus, a height H3 of conductive layer 162 of 10.0-15.0 μm should remain after grinding. Figure 4d Planar surface 232 of encapsulant 190 and surface 238 of conductive layer 162 are shown.

[0041] exist Figure 4e In the embodiment, a conductive bump material is deposited on the conductive layer 162 using evaporation, electroplating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 162 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 240. In one embodiment, the bump 240 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. The bump 240 can also be compression bonded or thermocompressed bonded to the conductive layer 162. The bump 240 represents a type of interconnect structure that can be formed on the conductive layer 162. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, micro bumps or other electrical interconnects.

[0042] The combination of the inverted (active surface 110 oriented away from bump 240) electrical component 188, e-bar structure 170a-170h, encapsulant 192, RDL 230 and bump 240 constitutes an embedded wafer level ball grid array (eWLB) 250. Similarly, the thickness of conductive layer 162 is made to be about 40.0 μm or thicker, that is, significantly thicker than conductive layers 132, 144 and 154, to avoid grinding away the contact points of bump 240, which will cause yield loss in the ball drop process. Conductive layer 162 should maintain a thickness of at least 10.0-15.0 μm after grinding. The additional thickness of conductive layer 162 ensures full exposure of surface 238 and improves ball drop yield. The additional thickness of conductive layer 162 is compatible with a wide range of process parameters. The full exposure of conductive layer 162 provides better reliability testing performance.

[0043] Figure 5 An electrical device 400 is shown having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of the PCB 402, including the eWLB 250. The electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0044] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0045] exist Figure 5 In the embodiment of the present invention, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface or within the layers of PCB 402 using evaporation, electroplating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 404 also provide power and ground connections for each semiconductor package.

[0046] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology that mechanically and electrically attaches the semiconductor die to the intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have a first level packaging, in which the die is mechanically and electrically directly disposed on the PCB. For the purpose of illustration, several types of first level packaging are shown on the PCB 402, including a wire bonding package 406 and a flip chip 408. In addition, several types of second level packaging are shown disposed on the PCB 402, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or a SIP module 418, a quad flat no-lead package (QFN) 420, a quad flat package 422, an embedded wafer level ball grid array (eWLB) 424, and a wafer level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level package types and other electrical components can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and simplified manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, thereby reducing costs to the consumer.

[0047] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Electrical components; An e-bar structure provided on the side of the electrical component; sealants deposited on electrical components and e-bar structures; as well as Redistribution layers (RDLs) are formed over the electrical components, encapsulant, and e-bar structures.

2. The semiconductor device according to claim 1, wherein the e-bar structure comprises: Core layer; forming a first conductive layer on the first surface of the core layer; as well as A second conductive layer is formed on the second surface of the core layer, wherein the second conductive layer comprises a thickness greater than the first conductive layer. 3 . The semiconductor device according to claim 1 , further comprising a bump formed on a contact pad of the e-bar structure opposite to the RDL. The semiconductor device according to claim 3 , wherein the contact pad comprises a thickness of 40 micrometers or more.

5. A semiconductor device comprising: Electrical components; e-bar structures placed near electrical components; as well as A redistribution layer (RDL) is formed over the electrical components and e-bar structure.

6. The semiconductor device of claim 5, further comprising an encapsulant deposited over the electrical component and the e-bar structure.

7. The semiconductor device according to claim 5, wherein the e-bar structure comprises: Core layer; forming a first conductive layer on the first surface of the core layer; as well as A second conductive layer is formed on the second surface of the core layer, wherein the second conductive layer comprises a thickness greater than the first conductive layer. 8 . The semiconductor device of claim 5 , further comprising a bump formed on a contact pad of the e-bar structure opposite to the RDL. 9 . The semiconductor device of claim 8 , wherein the contact pad comprises a thickness of 40 micrometers or more.

10. A method for manufacturing a semiconductor device, comprising: Provide electrical components; Position the e-bar structure near electrical components; as well as A redistribution layer (RDL) is formed over the electrical components and the e-bar structure.

11. The method of claim 10, further comprising depositing an encapsulant over the electrical component and the e-bar structure.

12. The method of claim 10, wherein the e-bar structure comprises: Provides the core layer; forming a first conductive layer on the first surface of the core layer; as well as A second conductive layer is formed on the second surface of the core layer, wherein the second conductive layer comprises a thickness greater than the first conductive layer.

13. The method of claim 10, wherein forming the RDL comprises: forming an insulating layer on electrical components; as well as A conductive layer is formed on the insulating layer. 14 . The method of claim 10 , further comprising forming bumps on contact pads of the e-bar structure opposite to the RDL.

15. The method of claim 14, wherein a contact pad of the electrical component is electrically connected to the RDL opposite the bump.

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