Interconnection structure

Abstract

The interconnect structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a super via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connection via. A connection via interconnects the metal plate and the first metal trench. A super-through hole penetrates the third dielectric layer and is connected to the metal plate. The super-vias are at least 1.5 times wider than the connecting vias.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to interconnect structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced tremendous progress over the past few decades and is still experiencing a boom. However, in order to optimize device performance, advances in IC design need to be accompanied by improvements in manufacturing. As an example, the interconnects between different wiring layers and the associated dielectrics play a role in IC performance. Summary of the invention

[0003] One aspect of an embodiment of the present disclosure provides an interconnect structure, comprising: a substrate; a first dielectric layer, disposed above the substrate and formed with a first metal trench; a second dielectric layer, disposed above the first dielectric layer and formed with a metal plate and a connecting via, wherein the connecting via interconnects the metal plate and the first metal trench; a third dielectric layer, disposed above the second dielectric layer; and a super via, penetrating the third dielectric layer and connected to the metal plate; wherein the super via is at least 1.5 times wider than the connecting via.

[0004] Another aspect of an embodiment of the present disclosure provides an interconnect structure, including: a substrate;

[0005] A first metal trench is disposed above the substrate; a metal plate is disposed above the first metal trench and spaced apart from the first metal trench; a connecting via extends between the first metal trench and the metal plate; at least one dielectric layer is disposed above the metal plate; and a super via penetrates the at least one dielectric layer and extends to the metal plate; wherein the super via is at least 1.5 times wider than the connecting via.

[0006] Another aspect of an embodiment of the present disclosure provides an interconnect structure, comprising: a substrate; a plurality of dielectric layers stacked above the substrate; a super via penetrating at least one of the plurality of dielectric layers; a metal plate disposed in one of the plurality of dielectric layers and connected to the bottom of the super via; a connecting via disposed in the one of the plurality of dielectric layers and connected to the bottom of the metal plate; and a first metal trench disposed in another of the plurality of dielectric layers and connected to the bottom of the connecting via; wherein the super via is at least 1.5 times wider than the connecting via, and the bottom of the super via is wider than the first metal trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view showing an interconnection structure according to the first embodiment.

[0009] Figure 2 is a cross-sectional view showing an interconnection structure according to a second embodiment.

[0010] Figure 3 A number of schematic diagrams are shown, each illustrating a top view of a metal plate in an interconnect structure according to some embodiments.

[0011] Figure 4 A plurality of schematic diagrams are shown, each schematic diagram illustrating a connection between one or more regular metal vias and a metal plate in an interconnect structure according to some embodiments.

[0012] Figure 5 is a top view illustrating a circuit layout including an interconnect structure according to some embodiments.

[0013] Figure 6 is a top view illustrating a circuit layout including an interconnect structure according to some embodiments.

[0014] Figure 7 is a top view illustrating a circuit layout including an interconnect structure according to some embodiments.

[0015] Figure 8 is a flow chart illustrating a method for fabricating an interconnect structure according to some embodiments.

[0016] Figures 9 to 17 is a cross-sectional view illustrating an intermediate step of a method for fabricating an interconnect structure according to some embodiments.

[0017] Fig.18 is a cross-sectional view illustrating an interconnect structure according to some embodiments.

[0018] Fig.19 is a cross-sectional view illustrating an interconnect structure according to some embodiments.

[0019] Fig. 20 is a flow chart illustrating a method for fabricating an interconnect structure according to some embodiments.

[0020] Figure 21 to Figure 26 is a cross-sectional view illustrating an intermediate step of a method for fabricating an interconnect structure according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "on," "over," "down," "up," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] For the purposes of this specification and the appended claims, unless otherwise indicated, all numbers used in the specification and claims indicating amounts, sizes, dimensions, ratios, shapes, formulas, parameters, percentages, quantities, features, and other numerical values ​​should be understood to be modified in all cases by the term "about", even though the term "about" may not explicitly display a value, amount, or range. Therefore, unless otherwise indicated, the numerical parameters set forth in the following specification and the appended claims are not and need not be exact, but may be approximate and / or larger or smaller as required, reflecting tolerances, conversion factors, rounding, measurement errors, etc. and other factors known to those skilled in the art, depending on the desired properties sought to be obtained by the subject matter of the present disclosure. For example, when referring to a value, the term "about" may mean to cover variations in a specific amount, in some aspects ±10%, in some aspects ±5%, in some aspects ±2.5%, in some aspects ±1%, in some aspects ±0.5%, and in some aspects ±0.1%, as such variations are suitable for performing the disclosed methods or employing the disclosed components.

[0024] Figure 1A cross-sectional view of an interconnect structure formed above a substrate according to a first embodiment is shown. The substrate may be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate, which may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, or any other suitable layer. The insulator layer may be provided on a suitable substrate such as silicon, glass, etc. The substrate may be made of a suitable semiconductor material, such as silicon, etc. In some embodiments, the substrate is a silicon substrate; and in other embodiments, the substrate is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other suitable materials. In yet other embodiments, the substrate is made of an alloy semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials.

[0025] In some embodiments, the substrate includes various p-type doped regions and / or n-type doped regions, such as p-type wells, n-type wells, p-type source / drain components, and / or n-type source / drain components (source / drain components may refer to sources or drains, individually or collectively depending on the context) formed by suitable processes (such as ion implantation, thermal diffusion, combinations thereof, etc.). In some embodiments, the substrate may include other functional elements, such as resistors, capacitors, diodes, transistors, etc. The transistor is, for example, a field effect transistor (FET), such as a planar FET and / or a 3D FET (e.g., FinFET, GAA FET). The substrate may include lateral isolation components (e.g., shallow trench isolation (STI)) configured to separate various functional elements formed on the substrate and / or various functional elements formed in the substrate.

[0026] According to some embodiments, the substrate may be formed with a plurality of interconnection layers, and the interconnection layers may have the same or different interconnection structures. x-1 To L x+n The interconnect layers L are formed above the substrate and stacked from bottom to top in the given order, where x is an integer greater than 1 and n is a positive integer. x-1 To L x+n Each of the interconnect layers L includes one or more metal trenches (or metal lines) extending in one or more lateral directions in the interconnect layer. x-1 The substrate includes a plurality of metal trenches M connected to circuit components (eg, transistors, diodes, etc., not shown) in the substrate. x-1 , through the etch stop layer (ESL) and the immediately lower interconnect layer L x-1 Separated interconnect layer L x Includes a plurality of metal grooves Mx And the metal groove M x Connect to metal groove M x-1 Multiple metal vias V x Note that the term “immediately adjacent to” is used to indicate that the interconnect layers (eg, interconnect layer L in this article) are adjacent to each other. x and L x-1 ) There is no other interconnection layer between them. x To L x+n The interconnection between the metal trench and the metal via is formed in the interconnection layer L x+n Metal groove M x+n Electrically connected to the interconnect layer L x-1 Metal groove M x-1 and a circuit component in the substrate (the metal trench M x-1 electrically connected to the circuit component).

[0027] Figure 2 1 shows a cross-sectional view of an interconnect structure formed on a substrate 100 according to a second embodiment, wherein the substrate 100 is similar to the substrate of the first embodiment, and therefore its details are omitted here for the sake of brevity. x-1 To L x+n The interconnection layers L are formed above the substrate 100 and are stacked from bottom to top in a given order, where x is an integer greater than 1 and n is a positive integer. x-1 To L x+n Each of the dielectric layers includes a dielectric layer and one or more metal trenches, the one or more metal trenches being formed in the dielectric layer and being in contact with a surface of the substrate 100 (eg, Figure 2 The interconnect layer 100 extends in one or more lateral directions parallel to the top surface of the substrate 100 (not each interconnect layer extends in Figure 2are shown as including one or more metal trenches). The dielectric layer may include elements such as Si, O, C, N, H, other suitable elements, or any combination thereof. According to some embodiments, the dielectric layer may include, for example, silicon oxide, silicon nitride, silicon carbide, low-k material, other suitable materials, or any combination thereof. According to some embodiments, the dielectric layer may have a thickness in the range of from about 200 angstroms to about 2000 angstroms, but the present disclosure is not limited thereto. Between two adjacent interconnect layers is an etch stop layer (ESL), which may have a single-layer structure or a multi-layer structure and include elements such as Si, O, C, N, H, Al, other suitable elements, or any combination thereof. According to some embodiments, the etch stop layer may include, for example, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, aluminum carbide, other suitable materials, or any combination thereof. According to some embodiments, the etch stop layer may have a thickness in the range of from about 5 angstroms to about 200 angstroms, but the present disclosure is not limited thereto.

[0028] In the illustrated embodiment, the interconnect layer L x-1 The metal trench 110 and the interconnect layer L x+n A metal trench 130 is included, and the metal trench 130 is electrically connected to the metal trench 110 through the super metal via 125 , the metal plate 120 , and the regular metal via 115 .

[0029] In detail, the interconnect layer L x-1 The metal trench 110 is formed in the interconnect layer L x-1 The dielectric layer ( Figure 2 ), and in the lateral direction (from Figure 2 The etch stop layer (ESL) is formed on the interconnect layer L. x-1 Above. Interconnect layer L x Set closely on the interconnect layer L x-1 above (as mentioned above, the term "immediately adjacent to" is used to indicate that between the above two interconnection layers (herein, interconnection layer L x and L x-1 ) and includes a dielectric layer 112, a metal plate 120, a regular metal through hole 115, and a liner (or barrier) 114. The metal plate 120 and the regular metal through hole 115 are formed in the dielectric layer 112, and each regular metal through hole 115 extends from the metal plate 120 to the metal trench 110 and penetrates the metal trench 110 disposed in the interconnection layer L. x and L x-1An etch stop layer (ESL) is formed between the metal plate 120 and the metal trench 110 to electrically connect the metal plate 120 to the metal trench 110. According to some embodiments, a single regular metal via 115 or more than two regular metal vias 115 may be formed to electrically interconnect the metal plate 120 and the metal trench 110, and the present disclosure is not limited to the number of regular metal vias 115. In the illustrative embodiment, the regular metal via 115 is similar to Figure 1 Each metal via is only connected between two adjacent interconnect layers (i.e., no other interconnect layers are inserted between them, for example, the interconnect layer L in this article). x and L x-1 ) and does not penetrate the entire single interconnect layer from top to bottom. The liner 114 is disposed between the metal plate 120 and the dielectric layer 112 and between the regular metal vias 115 and the dielectric layer 112 to prevent the metal elements of the metal plate 120 and the regular metal vias 115 from diffusing into the dielectric layer 112. The interconnect layer L x+n The metal trench 130 is formed in the interconnect layer L x+n In the dielectric layer 128, and in another lateral direction (from Figure 2 The super-metal via 125 extends from the metal trench 130 to the metal plate 120 in a straight line (ie, without bending or deformation) and penetrates the interconnect layer L x+1 To L x+n-1 The dielectric layer and interconnect layer L x+1 To L x+n-1 The liner 124 is disposed between the metal trench 130 and the dielectric layer 128, and between the super metal via 125 and the interconnect layer L x+1 To L x+n The metal trenches 110 and 130, the regular metal vias 115, the metal plate 120, and the super metal vias 125 may be formed between the dielectric layers to prevent the metal elements of the metal trenches 130 and the super metal vias 125 from diffusing into the dielectric layers. According to some embodiments, each of the metal trenches 110 and 130, the regular metal vias 115, the metal plate 120, and the super metal vias 125 may include, for example, Cu, Ru, W, Ti, Al, Co, Mo, Ir, Rh, Ta, other suitable materials, or any combination thereof. The metal trenches 110 and 130, the regular metal vias 115, the metal plate 120, and the super metal vias 125 may be made of the same or different materials. According to some embodiments, the liners 114 and 124 may include, for example, Ru, W, Ti, Al, Co, Mo, Ir, Rh, Ta, any nitrides of these metals, other suitable materials, or any combination thereof. According to some embodiments, depending on the bulk metal used in metal trenches 110 and 130 , regular metal vias 115 , metal plate 120 , and super metal vias 125 , liners 114 and 124 may be omitted, and the present disclosure is not limited thereto.

[0030] According to some embodiments, the super-metal via 125 is made tall and wide (at least 1.5 times wider than the regular metal via 115, and in some embodiments, about 2 to 15 times wider than the regular metal via 115 for better resistance), thereby penetrating one or more dielectric layers while having low resistance, and thus achieving better resistance-capacitance delay compared to the first embodiment. In some examples, the super-metal via 125 has a height h1 in a range from about 200 nm to about 900 nm, a top width w1 (i.e., the width of the top of the super-metal via 125) in a range from about 40 nm to about 150 nm, a bottom width w2 (i.e., the width of the bottom of the super-metal via 125) in a range from about 10 nm to about 60 nm, an aspect ratio (i.e., the ratio of the height h1 to the top width w1) in a range from about 3 to about 6, and / or an angle α in a range from about 75 degrees to about 90 degrees, the angle α formed by the side surface of the super-metal via 125 and the top surface of the metal plate 120. In addition to achieving low resistance, the design of the large width of the super-metal via 125 can also reduce the difficulty of forming and filling deep vias to manufacture the super-metal via 125. Satisfying one or more of the above conditions can enable the super-metal via 125 to have acceptable resistance and reduced difficulty in manufacturing. The metal trench 130 and the super-metal via 125 can be formed using a single damascene process or a dual damascene process. According to some embodiments, the metal trench 130 can have a width ranging from about 10 nm to about 200 nm. In the case of forming the metal trench 130 and the super-metal via 125 using a dual damascene process, the metal trench 130 can be wider than the top width w1 of the super-metal via 125.

[0031] According to some embodiments, the interconnect layer L x-1 The line spacing (ie, the distance between two adjacent metal trenches) can be smaller, and if the super metal via 125 is directly located on the interconnect layer L x-1 The bottom of the super metal via 125 may undesirably contact another metal trench ( Figure 2 Therefore, the interconnect layer L x The metal plate 120 in the embodiment is made to serve as a medium for electrically connecting the super metal via 125 to the metal trench 110 through the smaller regular metal via 115. The metal plate 120 is wider than the bottom width w2 of the super metal via 125, so the super metal via 125 can stand completely on the metal plate 120. According to some embodiments, the top surface of the metal plate 120 (i.e., the surface on which the super metal via 125 stands) has a width w3 ranging from about 40 nm to about 150 nm.

[0032] Further references Figure 3, the metal plate 120 is illustrated as having a rectangular top view. Figure 3 The dashed lines in FIG. 1 depict the bottom contours of the super metal via 125 and the surrounding pad 124. It can be seen that the super metal via 125 is completely located on the metal plate 120, and the top surface of the metal plate 120 is larger than the bottom of the super metal via 125. The metal plate 120 is Figure 3 The first length is in a second lateral direction perpendicular to the first lateral direction (e.g., from the vertical direction). Figure 3 It can be seen that each of the first length and the second length is the above-mentioned width w3 of the metal plate 120, and the width w3 is in the range from about 40nm to about 150nm. Figure 3 Parts (a) to (d) of FIG. 1 show different ways in which the metal plate 120 is connected to one or more metal trenches 121 disposed in the same interconnect layer. Figure 3 In part (a), the metal plate 120 is connected to a metal groove 121 at one side of its upper portion, and is connected to another metal groove 121 at the other side of its upper portion. Figure 3 In part (b), the metal plate 120 is connected to the metal groove 121 at one side of the central portion thereof, and is connected to another metal groove 121 at the other side of the central portion thereof. Figure 3 In part (c), the metal plate 120 is connected to only one metal groove 121 at one side of its upper portion. Figure 3 In part (d), the metal plate 120 is connected to only one metal trench 121, and the only metal trench 121 is connected at one side of the central portion of the metal plate 120. According to some embodiments, the metal plate 120 may be connected to more metal trenches at different sides and / or different portions thereof, and the present disclosure is not limited thereto. According to some embodiments, the metal plate 120 may be an independent component that is not connected to the metal trenches in the same interconnect layer, in which case the metal plate 120 is formed for the purpose of supporting the super metal via 125.

[0033] exist Figure 4 In FIG. 1 , the metal plate 120 is also illustrated as having a rectangular top view, and dashed lines are used to illustrate the outline of the top of the regular metal via 115 (ie, the connection between the regular metal via 115 and the metal plate 120 ). Figure 4 In part (a), only one regular metal via 115 is connected to the metal plate 120, and the regular metal via 115 has a square top view. Figure 4 In part (b), only one regular metal via 115 is connected to the metal plate 120, and the regular metal via 115 has a rectangular top view. Figure 4In part (c), a plurality of regular metal vias 115 are connected to the metal plate 120, and each regular metal via 115 has a square top view. Figure 4 In part (d), a plurality of regular metal vias 115 are connected to the metal plate 120, and each regular metal via 115 has a rectangular top view. Note that the one or more regular metal vias 115 are not limited to being located at the center of the metal plate 120 or having any particular arrangement, and may be formed to have a top view of any shape. According to some embodiments, each side of each regular metal via 115 may have a length in a range from about 10 nm to about 100 nm, but the present disclosure is not limited thereto.

[0034] Figure 5 1 shows a first exemplary circuit layout including an interconnect structure according to some embodiments. Metal line 105 is, for example, formed on a substrate (eg, Figure 2 The metal lines 105 are parallel to each other and extend in a first lateral direction (eg, from the top surface of the substrate) parallel to the top surface of the substrate. Figure 5 The metal trench 110 is formed in the first interconnect layer (eg, Figure 2 The interconnect layer L x-1 ) (the first interconnect layer is arranged above the substrate), from Figure 5 The metal grooves 110 may be formed to extend in the left-right direction (from Figure 5 For example, some metal trenches 110 (e.g., Figure 5 The top metal trench and the bottom metal trench 110 in the embodiment of the present invention may have a greater width than the width of other metal trenches 110 fabricated for signal transmission purposes. In a second interconnect layer (e.g., Figure 2 The interconnect layer L x ), a metal plate 120, regular metal vias 115 (drawn using dashed lines within the metal plate 120), a plurality of metal trenches 123, and a plurality of regular metal vias 116 (drawn using dashed lines within the metal trenches 123) are formed in the first interconnect layer. The metal trenches 123 extend in a first lateral direction and are electrically connected to one of the metal trenches 110 in the first interconnect layer through the regular metal vias 116. The metal plate 120 extends in a second lateral direction parallel to the top surface of the substrate (e.g., from Figure 5 The metal groove 123 is spaced apart in a vertical direction perpendicular to the top surface of the substrate (for example, from Figure 5The overlapped portion of the metal plate 120 and the adjacent metal trench 123 is the overlapped portion of the metal plate 120 (hereinafter referred to as the "target metal trench") in the inward-outward direction (into and out of the page) from the perspective of the metal plate 120. Note that there is no particular limit on the distance between the metal plate 120 and the adjacent metal trench 123 as long as the usual minimum spacing rules are met. The regular metal via 115 extends from the overlapped portion of the metal plate 120 to the target metal trench 110. Figure 5 , the chain line is used to draw the outline of the bottom of the super metal via 125, which is wider than the target metal trench 110 and stands on the metal plate 120 and overlaps the regular metal via 115 in the vertical direction. As a result, the super metal via 125 is electrically connected to the target metal trench 110 through the metal plate 120 and the regular metal via 115.

[0035] Figure 6 A second exemplary circuit layout including an interconnect structure according to some embodiments is shown. The second exemplary circuit layout is similar to the first exemplary circuit layout and differs from the first exemplary circuit layout in that the target metal trench 110 is Figure 6 In this case, the target metal trench 110 may be a power line located at the edge of the circuit unit, and thus close to an adjacent circuit unit (not shown) located at the upper side (from the upper side) of the circuit unit including the target metal trench 110. Figure 6 ). If the large-sized super metal via 125 overlaps the target metal trench 110 in the inward-outward direction, the super metal via 125 may occupy part of the adjacent circuit unit, increasing the complexity in the circuit design. To avoid this, the metal plate 120 may be formed to have an edge portion that is offset from the center of the target metal trench 110 and overlaps the target metal trench 110 (i.e., the edge portion is used as the overlapping portion). In this case, the regular metal via 115 extends from the edge portion of the metal plate 120 to the target metal trench 110, and the super metal via 125 stands on the remaining portion of the metal plate 120 that does not overlap the target metal trench 110. Figure 6 As shown, with the help of metal plate 120 , super metal via 125 is not necessarily located directly above target metal trench 110 , but may be located at another position as required, such as a position overlapping another metal trench 110 adjacent to the target metal trench 110 .

[0036] Figure 7A third exemplary circuit layout including an interconnect structure according to some embodiments is shown. The third exemplary circuit layout is similar to the second exemplary circuit layout, and differs from the second exemplary circuit layout in that the target metal trench 110 has a line portion 110A extending in a straight line in the second lateral direction, and a protrusion (also referred to as a runout) 110B extending laterally (e.g., in the first lateral direction) from the line portion 110A. The metal plate 120 has a portion (hereinafter referred to as an "overlapping portion") overlapping with the protruding portion 110B of the target metal trench 110, and the regular metal via 115 extends from the overlapping portion of the metal plate 120 to the protruding portion 110B of the target metal trench 110. With the aid of the protruding portion 110B, the super metal via 125 is not necessarily located directly above the line portion 110A of the target metal trench 110, and the line portion 110A may be located at the edge of the circuit unit and close to the adjacent circuit unit (not shown), thereby preventing the super metal via 125 from partially occupying the adjacent circuit unit.

[0037] Figure 8 is with Figures 9 to 17 Flowchart that cooperates to illustrate steps for forming an interconnect structure including super-metal vias using a dual damascene process in accordance with some embodiments.

[0038] exist Fig. 9 , the first interconnect layer is shown to include a first dielectric layer 301 and a metal trench 303 formed in the first dielectric layer 301; the second interconnect layer is immediately disposed above the first interconnect layer (wherein an etch stop layer 305 is interposed between the first interconnect layer and the second interconnect layer), and includes a second dielectric layer 307 and a plurality of regular metal vias 309 and a metal plate 311 formed in the second dielectric layer 307; and the intermediate interconnect layer is disposed above the second interconnect layer (wherein an etch stop layer 313 is interposed between the second interconnect layer and the intermediate interconnect layer), and includes a third dielectric layer 315 and a metal trench 317 formed in the third dielectric layer 315. The regular metal vias 309 are arranged in a vertical direction (from Fig. 9The metal plate 311 and the metal trench 303 are extended between the metal plate 311 and the metal trench 303 in the perspective of the metal plate 311 and the metal trench 303, and penetrate the etch stop layer 305, thereby electrically interconnecting the metal plate 311 and the metal trench 303. The fourth dielectric layer 321 is disposed above the intermediate interconnect layer, wherein the etch stop layer 319 is interposed between the intermediate interconnect layer and the fourth dielectric layer 321. In the illustrative embodiment, only one intermediate interconnect layer is formed between the fourth dielectric layer 321 and the second dielectric layer 307; in other embodiments, multiple intermediate interconnect layers may be formed between the fourth dielectric layer 321 and the second dielectric layer 307, and the present disclosure is not limited thereto. The metal hard mask layer 325 is disposed above the fourth dielectric layer 321, wherein the capping layer 323 is interposed between the fourth dielectric layer 321 and the metal hard mask layer 325, and the metal hard mask layer 325 is etched to form a metal trench pattern therein. In the illustrative embodiment, the metal hard mask layer 325 is etched into a plurality of segments, thereby forming a plurality of trenches between the segments, and the plurality of trenches cooperatively form a metal trench pattern. According to some embodiments, the metal hard mask layer 325 includes a metal element, such as W, Ti, other suitable metal elements, or any combination thereof, for enhancing resistance to an etchant used to etch the dielectric (e.g., a material used to form the first dielectric layer, the second dielectric layer, the third dielectric layer, and / or the fourth dielectric layer), so that after etching the dielectric, the metal hard mask layer 325 will remain. According to some embodiments, the capping layer 323 may include, for example, Si, O, N, C, other suitable elements, or any combination thereof, for enhancing adhesion between the metal hard mask layer 325 and the fourth dielectric layer 321, so as to avoid the metal hard mask layer 325 from being peeled off from the fourth dielectric layer 321. According to some embodiments, the capping layer 323 may include, for example, Si-based oxides, Si-based nitrides, Si-based carbides, other suitable materials, or any combination thereof.

[0039] refer to Figure 8 and Fig.10, a fifth dielectric layer 327, a first hard mask layer 329, a second hard mask layer 331, and a three-layer photoresist 333 are formed in a given order from bottom to top over the metal hard mask layer 325 and the cap layer 323. The three-layer photoresist 333 includes a bottom layer 333A (e.g., a stripping photoresist layer), an intermediate layer 333B (e.g., a back anti-reflective coating), and a top layer 333C (e.g., a photosensitive layer). The three-layer photoresist 333 is formed with a regular via pattern 335 (step S01), which will be transferred to the second hard mask layer 331 in a subsequent step, wherein the regular via pattern 335 corresponds to a regular metal via to be formed in the fourth dielectric layer 321. In the illustrative embodiment, a portion of the regular via pattern 335 overlaps the metal trench 317 in the vertical direction and corresponds to a regular metal via to be formed and connected to the metal trench 317 later. According to some embodiments, the fifth dielectric layer 327 may include, for example, a polymer, an oxide material, a nitride material, a carbide material, other suitable materials, or any combination thereof. According to some embodiments, each of the first hard mask layer 329 and the second hard mask film 331 may include, for example, a Si-based or metal-based (e.g., W, Ti, Ta or other suitable metal elements) nitride, a Si-based or metal-based carbide, other suitable materials, or any combination thereof. According to some embodiments, the first hard mask layer 329 and the second hard mask layer 331 include different materials in order to achieve etching selectivity therebetween, preventing the first hard mask layer 329 from being removed during etching of the second hard mask layer 331.

[0040] refer to Figure 8 and Fig.11 , in three layers of photoresist 333 (see Fig.10 ) is used as an etching mask, the second hard mask layer 331 is etched so as to form a regular via pattern 335 in the second hard mask layer 331 (step S02). The etching of the second hard mask layer 331 may be performed using, for example, dry etching, wet etching, other suitable etching techniques, or any combination thereof. During the etching of the second hard mask layer 331, the first hard mask layer 329 may also be slightly etched at the top portion of the first hard mask layer 329 so as to ensure that the second hard mask layer 331 is completely removed at the location where the regular via pattern 335 is formed. Since the first hard mask layer 329 and the second hard mask layer 331 are manufactured to have an etching selectivity therebetween, the first hard mask layer 329 is controllably allowed to remain after etching the second hard mask layer 331.

[0041] refer to Figure 8 and Fig.12 , a three-layer photoresist 339 is formed over the second hard mask layer 331 and the first hard mask layer 329. Similar to the three-layer photoresist 333 (see Fig.10), the three-layer photoresist 339 includes a bottom layer 339A (e.g., a stripping photoresist layer), an intermediate layer 339B (e.g., a back anti-reflective coating), and a top layer 339C (e.g., a photosensitive layer). The three-layer photoresist 339 is formed with a super via pattern 341 (step S03), which will be transferred to the first hard mask layer 329 in a subsequent step, wherein the super via pattern 341 corresponds to one or more super metal vias to be formed, which penetrate the fourth dielectric layer 321 and the intermediate interconnect layer and fall on the metal plate 311. In the illustrative embodiment, a portion of the super via pattern 341 overlaps the metal plate 311 in the vertical direction and corresponds to one or more super metal vias to be connected to the metal plate 311.

[0042] refer to Figure 8 and Fig.13 , by forming a three-layer photoresist 339 (see Fig.12 ) is used to etch the dielectric layer between the first hard mask layer 329 and the metal plate 311 (step S04). In detail, with the three-layer photoresist 339 used as an etching mask, the second hard mask layer 331, the first hard mask layer 329, the fifth dielectric layer 327, the capping layer 323, the fourth dielectric layer 321, the etching stop layer 319, and the third dielectric layer 315 are etched. According to some embodiments, etching may be performed using, for example, anisotropic etching, which is suitable for forming deep superconducting vias 343 with a high aspect ratio and a good profile, but the present disclosure is not limited thereto, and other suitable etching techniques may be applied in other embodiments. In an illustrative embodiment, etching of the superconducting via 343 stops halfway through the third dielectric layer 315, and does not reach the metal plate 311 in this step. The remaining thickness of the third dielectric layer 315 will be etched during subsequent etching with respect to the regular via pattern 335, so as to reduce the time required for the etching process.

[0043] refer to Figure 8 and Fig.14 , with the second hard mask layer 331 in which the regular via pattern 335 is formed being used as an etching mask, the first hard mask layer 329 is etched so as to transfer the regular via pattern 335 into the first hard mask layer 329 (step S05). The etching of the first hard mask layer 329 may be performed using, for example, dry etching, wet etching, other suitable etching techniques, or any combination thereof.

[0044] refer to Figure 8 and Fig.15 , a process of etching the dielectric layer is performed (step S06), so that the regular through hole pattern 335 (see FIG. 1 ) formed in the first hard mask layer 329 is formed. Fig.14 ) Etch the fifth dielectric layer 327 and the fourth dielectric layer 321 (see Fig.14), and the third dielectric layer 315 is further etched through the super via pattern (i.e., superconducting via 343). As a result, regular vias 345 are formed in the fourth dielectric layer 321, and superconducting vias 343 are etched deeper in the interconnect structure. The etching process may be performed using, for example, anisotropic etching, other suitable techniques, or any combination thereof. In an illustrative embodiment, etching stops when the depth of the regular vias 345 reaches the middle of the fourth dielectric layer 321, and when the depth of the superconducting vias 343 reaches the lower portion of the third dielectric layer 315. During the subsequent trench formation process, the remaining thickness of the fourth dielectric layer 321 corresponding to the regular vias 345 in position and the remaining thickness of the third dielectric layer 315 corresponding to the superconducting vias 343 in position will be etched so as to reduce the time required for the etching process in this step. During the process of etching the dielectric layer to deepen the regular vias 345 and the superconducting vias 343, the second hard mask layer 331 may be removed (see Fig.14 ) and the first hard mask layer 329 (see Fig.14 ).

[0045] refer to Figure 8 and Fig.16 In the case where the metal hard mask layer 325 having the metal trench pattern formed therein is used as an etching mask, a trench forming process (step S07) is performed to remove the fifth dielectric layer 327 (see Fig.15 ), and etching the capping layer 323 and the fourth dielectric layer 321 to form trenches 347, 349, and 351 in the fourth dielectric layer 321. During the formation of the trenches 347, 349, and 351, the regular vias 345 and the superconducting vias 343 may be further deepened together to reach the etch stop layers 319 and 313, respectively, which are subsequently etched to expose the metal trench 317 and the metal plate 311. According to some embodiments, the removal of the fifth dielectric layer 327 and the etching of the capping layer 323 and the fourth dielectric layer 321 may be performed using, for example, anisotropic etching, other suitable techniques, or any combination thereof, but the present disclosure is not limited thereto.

[0046] Further references Fig.17, depositing a metal layer to fill the superconducting via 343, the regular via 345, and the trenches 347, 349, and 351, followed by a chemical mechanical planarization (CMP) process to remove the metal hard mask layer 325, the cap layer 323, and the excess portion of the metal layer, thereby forming a supermetal via 353 in the superconducting via 343, forming a regular metal via 355 in the regular via 345, and forming metal trenches 357, 359, and 361 in the trenches 347, 349, and 351, respectively (step S08). The supermetal via 353 extends between the metal trench 357 and the metal plate 311, and penetrates the third dielectric layer 315 of the intermediate interconnect layer from top to bottom. Therefore, the metal trench 357 is electrically connected to the metal trench 303 through the supermetal via 353, the metal plate 311, and the regular metal via 309. Regular metal vias 355 extend in fourth dielectric layer 321 between metal trench 359 and metal trench 317. According to some embodiments, deposition of the metal layer may include, for example, atomic layer deposition (ALD) to form a liner / barrier, chemical vapor deposition (CVD) to form a metal seed layer, and electrochemical plating (ECP) to grow a metal on the metal seed layer, but the present disclosure is not limited thereto, and other suitable deposition techniques and / or other suitable combinations of various deposition techniques may be used to form the metal layer in other embodiments.

[0047] Fig.18 FIG. 1 shows an interconnect structure including a supermetal via according to some embodiments, the supermetal via extending from the interconnect layer L to the interconnect layer L. x+n Metal groove M x+n Extend directly to the interconnect layer L x Metal plate M x , and penetrates the interconnect layer L x+1 To L x+n-1 . Metal sheet M x Through regular metal vias V x Electrically connected to the interconnect layer L x-1 Metal groove M x-1 .and Figure 1 Compared with the interconnect structure in Fig.18 The super metal via in the metal trench M x+n and metal groove M x-1 Provides a shorter conductive path between the two and provides fewer wide metal sections on the conductive path (e.g. Figure 1 The interconnect layer L x+1 To L x+n-1 metal trenches in the circuit) to achieve better resistor-capacitor delay.

[0048] Fig.19 FIG. 4 shows an interconnect structure including a plurality of supermetal vias stacked together according to some embodiments. In the illustrative embodiment, the plurality of interconnect layers Lx-1 To L x+n The interconnection layer L is formed on the substrate 200 in a given order from bottom to top. x-1 The interconnect layer L includes a metal trench 210 formed therein. x The interconnect layer L includes a dielectric layer 212, a liner 214 formed in the dielectric layer 212, a plurality of regular metal vias 215, and a first metal plate 220, wherein the regular metal vias 215 extend between the first metal plate 220 and the metal trench 210, and the liner 214 is disposed between the first metal plate 220 and the dielectric layer 212 and between the regular metal vias 215 and the dielectric layer 212. x+2 The first metal plate 225 includes a dielectric layer 227 and a second metal plate 230 formed in the dielectric layer 227. The first super metal via 225 extends between the second metal plate 230 and the first metal plate 220 and penetrates the interconnect layer L from top to bottom. x+1 The liner 224 is disposed between the second metal plate 230 and the dielectric layer 227, between the first super metal via 225 and the dielectric layer 227, and between the first super metal via 225 and the dielectric layer 222. The interconnect layer L x+n The dielectric layer 238 and the third metal plate 240 formed in the dielectric layer 238 are included. The second super metal via 235 extends between the third metal plate 240 and the second metal plate 230 and penetrates the interconnect layer L x+2 and L x+n . In other words, the second super-metal via 235 is connected to the second metal plate 230, is stacked above the first super-metal via 225 and is connected to the first super-metal via 225 through the second metal plate 230, and penetrates one or more dielectric layers above the second metal plate 230. Note that each of the first metal plate 220, the second metal plate 230, and the third metal plate 240 may be an independent component without being connected to any metal trench in the same interconnect layer, or connected to one or more metal trenches in the same interconnect layer, and the present disclosure is not limited thereto. According to some embodiments, one or more super-metal vias may be further stacked above the second super-metal via 235 by one or more additional metal plates (e.g., the third metal plate 240), and the present disclosure is not limited to the number of super-metal vias stacked together.

[0049] Fig. 20 is with Figure 21 to Figure 26 Flowchart that cooperates to illustrate steps for forming an interconnect structure including super-metal vias using a single damascene process in accordance with some embodiments.

[0050] exist Fig.21, a first interconnection layer is shown to include a first dielectric layer 401 and a metal trench 403 formed in the first dielectric layer 401; a second interconnection layer is disposed immediately above the first interconnection layer (where an etch stop layer 405 is interposed between the first interconnection layer and the second interconnection layer), and includes a second dielectric layer 407 and a plurality of regular metal vias 409 and a metal plate 411 formed in the second dielectric layer 407; and a third interconnection layer is disposed above the second interconnection layer (where an etch stop layer 413 is interposed between the second interconnection layer and the third interconnection layer), and includes a third dielectric layer 415 and a metal trench 417 formed in the third dielectric layer 415. The regular metal vias 409 extend between the metal plate 411 and the metal trench 403 in a vertical direction, and penetrate the etch stop layer 405, thereby electrically interconnecting the metal plate 411 with the metal trench 403.

[0051] refer to Fig. 20 and Fig. 22 , a capping layer 419, a metal hard mask layer 421, and a three-layer photoresist 423 are formed in a given order from bottom to top over the third dielectric layer 415 and the metal trench 417. The three-layer photoresist 423 includes a bottom layer 423A (e.g., a stripping photoresist layer), an intermediate layer 423B (e.g., a back anti-reflective coating), and a top layer 423C (e.g., a photosensitive layer). The three-layer photoresist 423 is formed with a super via pattern 425 (step S11). In the illustrative embodiment, a portion of the super via pattern 425 overlaps the metal plate 411 in the vertical direction and corresponds to a super metal via that is subsequently formed and connected to the metal plate 411.

[0052] refer to Fig. 20 and Fig.23 , after forming the super through hole pattern 425 (see Fig. 22 ) is used as an etching mask, the metal hard mask layer 421, the capping layer 419, the third dielectric layer 415 and the etching stop layer 413 are etched (step S12) to form a superconducting via 427 in the third dielectric layer 415, wherein the metal plate 411 is exposed in the superconducting via 427.

[0053] Further references Fig.24 , a metal layer is deposited to fill the superconducting via 427, thereby forming a supermetal via 429 in the superconducting via 427 (step S13). The supermetal via 429 is connected to the metal plate 411 and penetrates the third dielectric layer 415 of the third interconnect layer from top to bottom.

[0054] Further references Fig.25 , a CMP process (step S14) is performed to remove the metal hard mask layer 421, the capping layer 419 and the excess portion of the metal layer.

[0055] refer to Fig. 20and Fig.26 , a fourth interconnection layer is formed above the third interconnection layer (step S15). The fourth interconnection layer includes a fourth dielectric layer 433 and a regular metal via 435 and a metal trench 437 formed in the fourth dielectric layer 433. The regular metal via 435 extends between the metal trench 437 and the super metal via 429, so that the metal trench 437 is electrically connected to the metal trench 403 through the regular metal via 435, the super metal via 429, the metal plate 411 and the regular metal via 409.

[0056] According to some embodiments, an interconnect structure is provided, comprising: a substrate; a first dielectric layer disposed above the substrate; a second dielectric layer disposed above the first dielectric layer; a third dielectric layer disposed above the second dielectric layer; and a super via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connecting via. The connecting via interconnects the metal plate and the first metal trench. The super via penetrates the third dielectric layer and is connected to the metal plate. The super via is at least 1.5 times wider than the connecting via.

[0057] According to some embodiments, the metal plate has an overlapping portion overlapping the first metal trench in a vertical direction perpendicular to a surface of the substrate, and the connecting via extends from the overlapping portion of the metal plate to the first metal trench.

[0058] According to some embodiments, the first metal groove has a line portion extending in a straight line in an extension direction and a protruding portion extending laterally from the line portion. The overlapping portion of the metal plate overlaps with the protruding portion of the first metal groove, and the connecting via extends from the overlapping portion of the metal plate to the protruding portion of the first metal groove.

[0059] According to some embodiments, the metal plate has a center that is offset from the first metal groove in a vertical direction.

[0060] According to some embodiments, the super via completely stands on the metal plate.

[0061] According to some embodiments, the metal plate has a first length in a first lateral direction and a second length in a second lateral direction perpendicular to the first lateral direction, and each of the first length and the second length is in a range from 40nm to 150nm, and the bottom of the super via has a width in a range from 10nm to 60nm.

[0062] According to some embodiments, the first dielectric layer is further formed with a second metal trench, the second metal trench is adjacent to the first metal trench, and the bottom of the super via overlaps the second metal trench in a vertical direction perpendicular to the surface of the substrate.

[0063] According to some embodiments, the interconnect structure further includes another metal plate disposed over and connected to the supervia, another dielectric layer disposed over the another metal plate, and another supervia penetrating the another dielectric layer and connected to the another metal plate.

[0064] According to some embodiments, the super via has an aspect ratio ranging from 3-6.

[0065] According to some embodiments, an angle formed by a side surface of the super via and a top surface of the metal plate ranges from 75 degrees to 90 degrees.

[0066] According to some embodiments, the top of the supervia has a width in the range from 40 nm to 150 nm.

[0067] According to some embodiments, the bottom of the supervia has a width in the range from 10 nm to 60 nm.

[0068] According to some embodiments, an interconnect structure is provided, comprising: a substrate; a first metal trench disposed above the substrate; a metal plate disposed above and spaced apart from the first metal trench; a connecting via extending between the first metal trench and the metal plate; at least one dielectric layer disposed above the metal plate; and a super via penetrating the at least one dielectric layer and extending to the metal plate. The super via is at least 1.5 times wider than the connecting via.

[0069] According to some embodiments, the interconnect structure further includes a second metal trench adjacent to the first metal trench in a lateral direction parallel to the surface of the substrate. The metal plate overlaps the first metal trench and the second metal trench in a vertical direction perpendicular to the surface of the substrate.

[0070] According to some embodiments, a bottom of the super via overlaps with the second metal trench in the vertical direction.

[0071] According to some embodiments, the super via completely stands on the metal plate.

[0072] According to some embodiments, the metal plate has an overlapping portion overlapping the first metal trench in a vertical direction perpendicular to a surface of the substrate, and the connecting via extends from the overlapping portion of the metal plate to the first metal trench.

[0073] According to some embodiments, the first metal groove has a line portion extending in a straight line in an extension direction and a protruding portion extending laterally from the line portion. The overlapping portion of the metal plate overlaps with the protruding portion of the first metal groove, and the connecting via extends from the overlapping portion of the metal plate to the protruding portion of the first metal groove.

[0074] According to some embodiments, an interconnect structure is provided, including: a substrate; a plurality of dielectric layers stacked above the substrate; a super via penetrating at least one of the dielectric layers; a metal plate disposed in one of the dielectric layers; a connecting via disposed in the one of the dielectric layers; and a first metal trench disposed in another of the dielectric layers. The metal plate is connected to the bottom of the super via. The connecting via is connected to the bottom of the metal plate. The first metal trench is connected to the bottom of the connecting via. The super via is at least 1.5 times wider than the connecting via, and the bottom of the super via is wider than the first metal trench.

[0075] According to some embodiments, the interconnect structure further comprises a second metal trench disposed adjacent to the first metal trench in the other one of the dielectric layers. A bottom of the super via overlaps the second metal trench in a vertical direction perpendicular to the surface of the substrate.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An interconnect structure comprising: substrate; A first dielectric layer, disposed above the substrate and having a first metal trench formed therein; a second dielectric layer disposed above the first dielectric layer and formed with a metal plate and a connecting via, wherein the connecting via interconnects the metal plate and the first metal trench; a third dielectric layer disposed above the second dielectric layer; and a super via penetrating the third dielectric layer and connected to the metal plate; Wherein, the super through hole is at least 1.5 times wider than the connecting through hole.

2. The interconnect structure according to claim 1, wherein: The metal plate has an overlapping portion overlapping the first metal trench in a vertical direction perpendicular to a surface of the substrate, and the connection via extends from the overlapping portion of the metal plate to the first metal trench.

3. The interconnect structure according to claim 2, wherein: The first metal groove has a line portion extending in a straight line in an extending direction and a protruding portion extending laterally from the line portion; and The overlapping portion of the metal plate overlaps the protruding portion of the first metal groove, and the connecting through hole extends from the overlapping portion of the metal plate to the protruding portion of the first metal groove.

4. The interconnect structure according to claim 2, wherein: The metal plate has a center offset from the first metal groove in the vertical direction.

5. The interconnect structure according to claim 1, wherein: The super through hole is completely vertical on the metal plate.

6. The interconnect structure according to claim 5, wherein: The metal plate has a first length in a first lateral direction and a second length in a second lateral direction perpendicular to the first lateral direction, and each of the first length and the second length is in the range from 40nm to 150nm, and the bottom of the super through hole has a width in the range from 10nm to 60nm.

7. The interconnect structure according to claim 1, wherein: The first dielectric layer is further formed with a second metal trench, the second metal trench is adjacent to the first metal trench, and the bottom of the super via overlaps with the second metal trench in a vertical direction perpendicular to the surface of the substrate.

8. The interconnect structure of claim 1 , further comprising: another metal plate disposed above and connected to the super via; another dielectric layer disposed above the another metal plate; as well as Another super via penetrates the another dielectric layer and is connected to the another metal plate.

9. An interconnect structure comprising: substrate; A first metal trench is disposed above the substrate; a metal plate disposed above the first metal groove and spaced apart from the first metal groove; a connecting via extending between the first metal trench and the metal plate; at least one dielectric layer disposed above the metal plate; as well as a super via penetrating the at least one dielectric layer and extending to the metal plate; Wherein, the super through hole is at least 1.5 times wider than the connecting through hole.

10. An interconnect structure comprising: substrate; a plurality of dielectric layers stacked above the substrate; a super via penetrating at least one of the plurality of dielectric layers; a metal plate disposed in one of the plurality of dielectric layers and connected to a bottom of the super via; a connecting via disposed in said one of said plurality of dielectric layers and connected to a bottom of said metal plate; as well as a first metal trench disposed in another one of the plurality of dielectric layers and connected to a bottom of the connecting via; The super via is at least 1.5 times wider than the connecting via, and the bottom of the super via is wider than the first metal trench.

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