Test structure and test method for metal filling quality inspection

Abstract

The present application discloses a test structure and a test method for metal filling quality detection, the test structure includes a plurality of test units, the test unit includes a first metal layer, a second metal layer and a metal connection channel, wherein the first metal layer and the second metal layer are connected through the metal connection channel; the second metal layer is located above the first metal layer, the second metal layer and the metal connection channel are integrally formed through metal filling and the metal filling is performed by an electrochemical plating process; the perimeter of the second metal layer in different test units is different, and the quality of the metal filling in different test units is detected by testing the resistance value of the test unit. The present application realizes the simultaneous detection of multiple process windows with different metal filling qualities by improving the test structure, so that the optimal window when the electrochemical plating process is used for metal filling can be determined more conveniently.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a test structure and a test method for metal filling quality detection. Background Art

[0002] In advanced manufacturing processes, as the feature size of metal interconnects decreases, the metal filling process required to manufacture metal interconnects becomes increasingly difficult. Poor metal filling quality will lead to voids in the formed metal interconnects and then pits and other defects, which directly affect the quality of the chip. Currently, it is impossible to efficiently monitor and evaluate the metal filling quality of multiple process windows in the electrochemical plating (ECP) process with the help of existing test structures (testkeys), so it is also impossible to easily determine the optimal window for metal filling using the electrochemical plating process. Summary of the invention

[0003] In view of the above problems, the purpose of the present application is to provide a test structure and test method for metal filling quality detection. By improving the test structure, simultaneous detection of multiple process windows with different metal filling qualities can be achieved, so that the optimal window for metal filling using electrochemical plating process can be determined more conveniently.

[0004] According to a first aspect of the present invention, a test structure for metal filling quality detection is provided, the test structure comprising a plurality of test units, the test units comprising a first metal layer, a second metal layer and a metal connection channel, wherein:

[0005] The first metal layer and the second metal layer are connected via the metal connection channel;

[0006] The second metal layer is located above the first metal layer, and the second metal layer and the metal connection channel are integrally formed by metal filling, and the metal filling is performed by an electrochemical plating process;

[0007] The perimeters of the second metal layer in different test units are different, and the quality of the metal filling in different test units is detected by testing the resistance value of the test unit.

[0008] Optionally, the second metal layer includes a square area and four identical rectangular areas obtained by extending outwards from each edge of the square area;

[0009] The side length of the square area is a first length, and each side of the square area is extended outward by a second length to obtain the rectangular area. The sum of twice the second length and the first length is different in different test units.

[0010] Optionally, the first length is different and / or the second length is different in different test units.

[0011] Optionally, the metal connection channel is connected to the center of the square area.

[0012] Optionally, the areas of the first metal layers in different test units are the same and the thicknesses of the second metal layers are also the same;

[0013] The changing step length of the perimeter of the second metal layer in different test units is determined according to the area of ​​the first metal layer and the thickness of the second metal layer.

[0014] Optionally, there are multiple identical test units among the multiple test units, and the multiple identical test units are connected in series to form a test module.

[0015] Optionally, the test structure further includes: a first metal pin connected in series with the first test unit in the test module, and a second metal pin connected in series with the last test unit in the test module.

[0016] Optionally, the metal material filled during the metal filling process is copper.

[0017] According to a second aspect of the present invention, there is provided a testing method for metal filling quality detection, comprising:

[0018] Forming a test structure, wherein the test structure is any one of the test structures described in the first aspect;

[0019] A voltage is applied to the first metal layer and the second metal layer of the test unit included in the test structure to test the resistance value of the test unit, so as to detect the metal filling quality of the test unit according to the measured resistance value.

[0020] Optionally, the testing method further comprises: comparing the resistance values ​​measured by different testing units, so as to determine the window for metal filling by using the electrochemical plating process according to the comparison result.

[0021] The unexpected technical effects of this application are:

[0022] The test structure for metal filling quality detection provided by the embodiment of the present application includes a plurality of test units, wherein the test unit includes a first metal layer, a second metal layer and a metal connection channel, wherein the first metal layer and the second metal layer are connected through the metal connection channel; the second metal layer is located above the first metal layer, and the second metal layer and the metal connection channel are integrally formed by metal filling and the metal filling is performed by an electrochemical plating process; the perimeter of the second metal layer in different test units is different, and the metal filling quality in different test units is detected by testing the resistance value of the test unit. Since the metal filling quality of any two different test units is determined to be different based on the line edge density effect, the simultaneous detection of multiple process windows with different metal filling qualities is achieved, so that the optimal window when the electrochemical plating process is used for metal filling can be determined more conveniently.

[0023] Furthermore, the second metal layer includes a square area and four identical rectangular areas obtained by extending the edges of the square area outward, so that the area where the second metal layer is located can be used as a filling window during the metal filling process to release the internal stress of the filled metal through the four rectangular areas, so that voids are less likely to occur during the metal filling process. In the second metal layer, the side length of the square area is a first length, and the edges of the square area extend outward by a second length to obtain a rectangular area. The sum of twice the second length and the first length is different in different test units, thereby achieving different perimeters of the second metal layer in different test units.

[0024] Furthermore, there are multiple identical test units among the multiple test units, and multiple identical test units are connected in series to form a test module. Therefore, if there are voids in the metal connection channel during the metal filling process using the electrochemical plating process, the resistance value of the test module will change significantly. In addition, in the case where the resistance value of individual test units is affected by accidental factors other than the metal filling quality, it is possible to avoid accidental factors causing significant interference to the evaluation results of the metal filling quality. Therefore, the use of the test module is conducive to the detection accuracy of the metal filling quality of the test unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic cross-sectional view of a semiconductor device is shown;

[0027] Figure 2 A schematic cross-sectional view showing the formation of an interconnect structure in a manufacturing process of a semiconductor device;

[0028] Figure 3A schematic diagram showing electroplating a semiconductor structure using an electrochemical plating process;

[0029] Figure 4 A schematic diagram showing electroplating another semiconductor structure using an electrochemical plating process;

[0030] Figure 5 A schematic diagram showing electroplating results corresponding to two different line edge densities in the electroplating area;

[0031] Figure 6 A schematic top view of a test unit provided according to an embodiment of the present application is shown;

[0032] Figure 7 Schematic top views of two different test units provided according to an embodiment of the present application are shown;

[0033] Figure 8 A schematic top view of a test module provided according to an embodiment of the present application is shown;

[0034] Fig. 9 A flow chart of a testing method for metal filling quality detection provided according to another embodiment of the present application is shown.

[0035] Description of reference numerals: 100-semiconductor device; 101-semiconductor layer; 102-shallow trench structure; 103-source region; 104-drain region; 105-gate dielectric layer; 106-gate conductor; 107-interlayer dielectric layer; 108-wiring layer; 111-first connection channel; 112-second connection channel; 121-first wiring; 122-second wiring; 131-first connection hole; 132-second connection hole; 141-first wiring groove; 142-second wiring groove; 10-first semiconductor structure; 111-first connection channel; 112-second connection channel; 112-second wiring; 113-first connection hole; 114-second connection hole; 115-first wiring groove; 116-second wiring groove; 117-first connection channel; 118-second wiring groove; 119-first connection channel; 120-first connection channel; 121-first wiring; 122-second wiring; 131-first connection hole; 132-second connection hole; 141-first wiring groove; 142-second wiring groove; 10-first semiconductor structure; 110-first connection channel; 111-first connection channel; 112-second connection channel; 113-first connection channel; 114-second wiring groove; 115-first connection channel; 116-second wiring groove; 117-first connection channel; 118-second wiring groove; 119-first connection channel; 111-first connection channel; 112-second wiring; 113-first connection hole; 114-second connection hole; 115-first connection channel; 116-second wiring 1-first plate-like structure; 12-second plate-like structure; 13-first metal structure; 20-second semiconductor structure; 21-third plate-like structure; 22-fourth plate-like structure; 23-second metal structure; 210-test unit; 211-first metal layer; 212-second metal layer; 220-test unit; 221-first metal layer; 222-second metal layer; 230-test unit; 231-first metal layer; 232-second metal layer; 241-first metal pin; 242-second metal pin. DETAILED DESCRIPTION

[0036] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0037] This application may be presented in a variety of forms, some examples of which are described below.

[0038] like Figure 1 As shown, the semiconductor device 100 includes a semiconductor layer 101 and a shallow trench structure 102 located in the semiconductor layer 101. The semiconductor layer 101 can be composed of any one selected from a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor layer 101 is P-type doped; for a P-type MOSFET, the semiconductor layer 101 is N-type doped. The shallow trench structure 102 extends downward from the surface of the semiconductor layer 101 to form an isolation structure surrounding the active area of ​​the semiconductor device 100, which is used to separate the semiconductor device 100 from adjacent semiconductor devices. The shallow trench structure 102 can be composed of any one selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0039] Furthermore, the semiconductor device 100 includes a source region 103 and a drain region 104 located in the semiconductor layer 101, and a gate stack located above the semiconductor layer 101. The source region 103 and the drain region 104 are doped regions in the semiconductor layer 101. For example, for an N-type MOSFET, the source region 103 and the drain region 104 are N-type doped; for a P-type MOSFET, the source region 103 and the drain region 104 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 105 and a gate conductor 106, and the gate dielectric layer 105 is sandwiched between the semiconductor layer 101 and the gate conductor 106. The gate dielectric layer 105 is composed of, for example, silicon oxide, and the gate conductor 106 is composed of, for example, doped polysilicon. Metal silicide can also be grown on the surfaces of the source region 103, the drain region 104, and the gate conductor 106 to form a contact layer. As a contact layer, the metal silicide has the function of reducing the contact resistance. Since the contact layer is usually thin, Figure 1 Not specifically shown.

[0040] Further, the semiconductor device 100 includes an interlayer dielectric layer 107 located above the gate stack and the source region 103 and the drain region 104, a wiring layer 108 located above the interlayer dielectric layer 107, and an interconnection structure connected to the gate stack and the source region 103 and the drain region 104. The interlayer dielectric layer 107 is composed of, for example, silicon oxide, and is used to isolate the active region of the semiconductor device 100 from the wiring layer 108. The wiring layer 108 is composed of, for example, silicon nitride, and is used to isolate different wirings formed therein. The interconnection structure of the semiconductor device 100 includes a first connection channel 111 and a second connection channel 112 that penetrate the interlayer dielectric layer 107, and wirings located in the wiring layer 108. For example, the wirings in the wiring layer 108 include a first wiring 121 connected to the first connection channel 111 and a second wiring 122 connected to the second connection channel 112. The first connection channel 111 and the second connection channel 112 and the first wiring 121 and the second wiring 122 may be made of conductive materials, such as copper, aluminum, etc. Since the first connection channel 111 and the second connection channel 112 play the role of connecting the active area and the wiring, they are a typical metal interconnection line.

[0041] The manufacturing process of the semiconductor device 100 includes a front-end process and a back-end process, wherein the front-end process includes thin film deposition, ion implantation, and patterning, which are mainly used to form a source region 103, a drain region 104, and a gate stack of the semiconductor device 100; the back-end process includes thin film deposition and patterning, which are mainly used to form an interconnection structure of the semiconductor device 100, including forming a first connection channel 111 and a second connection channel 112, as well as a first wiring 121 and a second wiring 122 of the semiconductor device 100.

[0042] Figure 2 Schematic cross-sectional view showing the formation of an interconnect structure in the manufacturing process of a semiconductor device. Figure 2As shown, the wiring layer 108 is etched to form a first wiring groove 141 and a second wiring groove 142. A selective etchant can be used to etch a portion of the wiring layer 108 and the etching stops at the surface of the interlayer dielectric layer 107. Then, the interlayer dielectric layer 107 is etched to form a first connection hole 131 and a second connection hole 132. Similarly, a selective etchant can be used to etch a portion of the interlayer dielectric layer 107 and the etching stops at the surface of the source region 103, the drain region 104, and the gate conductor 106. At the same time, the wiring layer 108 is not etched, so that the formed first wiring groove 141 and the second wiring groove 142 are not damaged. After the first wiring groove 141 and the second wiring groove 142 and the first connection hole 131 and the second connection hole 132 are formed, metal is filled in the first wiring groove 141 and the second wiring groove 142 and the first connection hole 131 and the second connection hole 132 by using an electrochemical plating process, so that the first connection channel 111 and the second connection channel 112 and the first wiring 121 and the second wiring 122 are integrally formed. In this process, the first wiring groove 141 and the second wiring groove 142 are process windows for metal filling. It should be understood that the first wiring 121 and the second wiring 122 are formed after the first wiring groove 141 and the second wiring groove 142 are filled with metal, and the first connection channel 111 and the second connection channel 112 are formed after the first connection hole 131 and the second connection hole 132 are filled with metal.

[0043] As the characteristic size of the first connection hole 131 and the second connection hole 132 decreases, it becomes increasingly difficult to fill the first connection hole 131 and the second connection hole 132 with metal. Poor metal filling quality may result in voids in the first connection channel 111 and the second connection channel 112, thereby increasing the resistance of the first connection channel 111 and the second connection channel 112, thereby directly affecting the quality of the semiconductor device 100. The first wiring groove 141 and the second wiring groove 142 are process windows for metal filling, but currently it is impossible to efficiently monitor and evaluate the metal filling quality of various process windows in the electrochemical plating process with the help of existing test structures, and therefore it is also impossible to conveniently determine the optimal window for metal filling using the electrochemical plating process.

[0044] In view of this, an embodiment of the present application provides a test structure with a new shape based on the line edge density (LED) effect, the test structure including multiple test units, the test units including a first metal layer, a second metal layer and a metal connection channel, wherein the first metal layer and the second metal layer are connected through the metal connection channel and the second metal layer is located above the first metal layer, the second metal layer and the metal connection channel are integrally formed by metal filling and the metal filling is performed by an electrochemical plating process, the circumference of the second metal layer in different test units is different, and the quality of the metal filling in different test units is detected by testing the resistance value of the test unit.

[0045] In practice, the above test structure can be set in the dicing lanes of the chip, and the functional areas on the chip divided by the dicing lanes can be set as follows: Figure 1 A semiconductor device 100 is shown. In this case, the formation process of the test structure may include: providing a semiconductor layer 101, forming a source region 103 and a drain region 104 in the functional region of the semiconductor layer 101 and forming a gate stack above the functional region; growing a metal silicide on the surface of the source region 103 and the drain region 104 and the gate conductor 106 included in the gate stack to form a contact layer, and forming a first metal layer on the scribe line of the semiconductor layer 101; forming an interlayer dielectric layer 107 covering the semiconductor layer 101 and a wiring layer 108 covering the interlayer dielectric layer 107; etching the wiring layer 108 through a first mask to form a first The wiring groove 141 and the second wiring groove 142 are formed in the scribe line of the wiring layer 108 to form a test groove; the interlayer dielectric layer 107 is etched by the second mask to form the first connection hole 131 and the second connection hole 132 in the functional area of ​​the interlayer dielectric layer 107 and the test hole is formed in the scribe line of the interlayer dielectric layer 107; the surface of the wiring layer 108 is filled with a metal material (such as copper) by an electrochemical plating process to form the first wiring 121 and the second wiring 122 and the first connection channel 111 and the second connection channel 112 in the functional area, and form a second metal layer and a metal connection channel in the scribe line. It should be understood that the second metal layer is formed after the test groove is filled with metal material, and the metal connection channel test hole is formed after the metal material is filled. The metal filling process used in the first connection channel 111, the second connection channel 112 and the metal connection channel is different only in the filling window. If the metal filling quality is not good, there will be voids in the first connection channel 111, the second connection channel 112 and the metal connection channel, so that the resistance value when each is powered on increases.

[0046] Since the perimeter of the second metal layer in different test units is different, the above formation process can form multiple different test units through one wafer, so there is no need to use multiple wafers to design a multi-component separation experiment to detect the metal filling quality corresponding to multiple test units. Moreover, based on the line edge density effect, it can be known that there is a difference in the metal filling quality of any two different test units. Therefore, the detection of the metal filling quality of multiple test units can efficiently determine the metal filling quality of multiple process windows, thereby eliminating the need for a long experimental cycle to determine the optimal window for metal filling, that is, it can more conveniently determine the optimal window for metal filling using an electrochemical plating process.

[0047] It should be noted that the line edge density effect means that the greater the line edge density in the electroplating area, the more uniform the electric field and the slower the electroplating speed, so that the metal plated in the electrochemical plating process is more uniform, that is, it is less likely to have void defects and the metal filling quality is higher.

[0048] Figure 3 FIG. 1 is a schematic diagram of electroplating a semiconductor structure using an electrochemical plating process, wherein: Figure 3 Figure (a) shows a schematic diagram of the three-dimensional structure of the semiconductor structure. Figure 3 Figure (b) shows a cross-sectional schematic diagram of a semiconductor structure. Figure 3 As shown in FIG. 1 (a), the first semiconductor structure 10 includes a first plate-like structure 11 parallel to the xy plane and a second plate-like structure 12 parallel to the yz plane. The number of the second plate-like structures 12 is four and the four second plate-like structures 12 are arranged along the x-axis on the surface of the first plate-like structure 11. Figure 3 As shown in FIG. (b), the width of the second plate-like structure 12 is L, the height is H, the spacing between adjacent second plate-like structures 12 is 2L, the leftmost second plate-like structure 12 of the four second plate-like structures 12 is 2L away from the left edge of the first plate-like structure 11, and the rightmost second plate-like structure 12 is aligned with the right edge of the first plate-like structure 11. Figure 3 The first semiconductor structure 10 shown in FIG. 1 (a) is formed by an electrochemical plating process. Figure 3 As shown in FIG. (b) of FIG. 1 , during the formation of the first metal structure 13, metal needs to be electroplated on two surfaces of the second plate-like structure 12 parallel to the yz plane and one surface parallel to the xy plane, as well as on the surface of the first plate-like structure 11 where the second plate-like structure 12 is not arranged. In addition to the line edges along the y axis, these surfaces also have line edges parallel to the xz plane. Specifically, the size of the line edges parallel to the xz plane is as follows: Figure 3 As shown in Figure (b), there are a total of 8 Hs and 12 Ls (i.e. 4×(2L+L)).

[0049] Figure 4 FIG. 1 is a schematic diagram of electroplating another semiconductor structure using an electrochemical plating process, wherein: Figure 4 Figure (a) shows a schematic diagram of the three-dimensional structure of the semiconductor structure. Figure 4 Figure (b) shows a cross-sectional schematic diagram of a semiconductor structure. Figure 4 As shown in FIG. 1( a ), the second semiconductor structure 20 includes a third plate-like structure 21 parallel to the xy plane and a fourth plate-like structure 22 parallel to the yz plane. Figure 3 The first plate-like structures 11 have the same size, there are two fourth plate-like structures 22, and the two fourth plate-like structures 22 are arranged on the surface of the third plate-like structure 21 along the x-axis; Figure 4 As shown in FIG. 2( b ), the width of the fourth plate-like structure 22 is 2L, the height is H, the distance between the two fourth plate-like structures 22 is 4L, the left one of the two fourth plate-like structures 22 is 4L away from the left edge of the third plate-like structure 21, and the right one is aligned with the right edge of the third plate-like structure 21. Figure 4 The second semiconductor structure 20 shown in FIG. 1 (a) is formed by an electrochemical plating process. Figure 4 The second metal structure 23 shown in FIG. 2 (b) of FIG. 2 is formed by electroplating metal on two surfaces of the fourth plate-like structure 22 parallel to the yz plane and one surface parallel to the xy plane, as well as on the surface of the third plate-like structure 21 where the fourth plate-like structure 22 is not arranged. In addition to the line edges along the y axis, these surfaces also have line edges parallel to the xz plane. Specifically, the size of the line edges parallel to the xz plane is as follows: Figure 4 As shown in Figure (b), there are 4 Hs and 12 Ls (i.e. 2×(4L+2L)).

[0050] Will Figure 3 The first semiconductor structure 10 and Figure 4 Compared with the second semiconductor structure 20 shown in the figure, the main difference lies in the different line edge sizes in the electroplating plane parallel to the xz plane. Specifically, the line edge size of the first semiconductor structure 10 is 4H larger than that of the second semiconductor structure 20, that is, in the same electroplating area, the line edge density of the first semiconductor structure 10 is greater than the line edge density of the second semiconductor structure 20. In this way, the electroplating electric field of the first semiconductor structure 10 during the electrochemical plating process is more uniform and the electroplating speed is slower, so that the volume of the voids generated during the metal filling process is smaller and the metal filling quality is higher.

[0051] Figure 5 The figure shows the electroplating results corresponding to two different line edge densities in the electroplating area. The white area with an elliptical outline in the figure indicates an independent electroplating area and the black area in the white area indicates the void in the electroplating area. Figure 5 , (a) and (b) use white dashed boxes of the same size to frame the plating areas with voids. The inner part of the plating area in (a) is inscribed in the white dashed box, but the edges of the plating area in (b) are all on the inner side of the white dashed box. Therefore, the perimeter of the filling window of the plating area in (a) is larger than that of the plating area in (b). In the area framed by the white dashed boxes of the same size, the line edge density in (a) is larger than that in (b). Accordingly, the voids in the plating area in the white dashed box in (a) are larger than those in the plating area in the white dashed box in (b).

[0052] Figure 6 FIG. 1 is a schematic top view of a test unit provided in an embodiment of the present application. Figure 6 As shown, the test unit 210 includes a first metal layer 211 and a second metal layer 212, and the second metal layer 212 includes a square area Q 1 Q 2 Q 3 Q 4 and the square area Q 1 Q 2 Q 3 Q 4 The four identical rectangular areas obtained by extending the edges of 1 Q 2 P 2 P 1 , rectangular area Q 2 Q 3 P 4 P 3 , rectangular area Q 3 Q 4 P 6 P 5 and the rectangular area Q 4 Q 1 P 8 P 7 Since the four rectangular areas are in the square area Q 1 Q 2 Q 3 Q 4 Therefore, the area where the second metal layer 212 is located can be used as a filling window during the metal filling process to release the internal stress of the filled metal through the four rectangular areas, so that voids are less likely to occur during the metal filling process. Figure 6 Middle square area Q 1 Q 2 Q 3 Q 4 The central area O is framed by a white dotted line. 1 O 2 O 3 O 4It is connected to the metal connection channel, so that the internal stress of the metal filled in all directions during the metal filling process is relatively uniform. When the stress is released through the same rectangular area in four directions, there will be no stress accumulation caused by the stress difference between different directions, which is beneficial to further ensure that the metal filling process avoids the generation of voids.

[0053] Square area Q 1 Q 2 Q 3 Q 4 The side length is the first length A, and the square area is Q 1 Q 2 Q 3 Q 4 Each side of the second metal layer 212 is extended outward by a second length B to obtain a rectangular area. The sum of twice the second length B and the first length A in different test units is different. Since the perimeter of the second metal layer 212 is (4A+8B), the perimeter of the second metal layer 212 in different test units is different. In some examples, the size of the first length A in different test units can be adjusted to achieve different perimeters of the second metal layer 212 in different test units. For example, the first length A is reduced to obtain Figure 7 The test unit 220 shown in FIG. (a) is indicated by a dotted line frame in FIG. Figure 6 The rectangular area in the Figure 6 The square area Q in 1 Q 2 Q 3 Q 4 In some other examples, the size of the second length B in different test units can be adjusted to achieve different perimeters of the second metal layer 212 in different test units. For example, increasing the second length B to obtain Figure 7 The test unit 230 shown in FIG. (b) is also indicated by a dotted line frame in FIG. Figure 6 The rectangular area in the Figure 6 The square area Q in 1 Q 2 Q 3 Q 4 Of course, the perimeter of the second metal layer 212 in different test units can be different by adjusting the first length A and the second length B. In this example, the test structure may include Figure 6 The test unit 210 and Figure 7 The test unit 220 and the test unit 230 are shown, and these three test units are formed simultaneously during the formation of the test structure.

[0054] Furthermore, the areas of the first metal layers in different test units are the same and the thicknesses of the second metal layers are also the same, and the changing steps of the perimeters of the second metal layers in different test units are determined according to the areas of the first metal layers and the thicknesses of the second metal layers.

[0055] by Figure 6 and Figure 7 The multiple test units shown are used for illustration, the first metal layer 211 in the test unit 210, the first metal layer 221 in the test unit 220, and the first metal layer 231 in the test unit 230 have the same area, the second metal layer 212 in the test unit 210, the second metal layer 222 in the test unit 220, and the second metal layer 232 in the test unit 230 have the same thickness, and the metal connection channels in different test units also have the same size, but the circumferences of the second metal layers in different test units are different, thereby constructing different metal filling environments.

[0056] by Figure 6 The test unit shown is further explained, the parameter L that affects the metal filling quality ED It is expressed by the following formula (1), where H represents the thickness of the second metal layer 212 and S represents the area of ​​the first metal layer 211. Therefore, when the thickness H of the second metal layer 212 and the area S of the first metal layer 211 remain unchanged, the parameter L ED The parameter L is positively correlated with the perimeter (4A+8B) of the second metal layer 212, that is, the larger the perimeter (4A+8B) of the second metal layer 212 is, the larger the parameter L is. ED The larger the parameter L ED Indicates the line edge density, theoretically the parameter L ED The larger the length, the better the metal filling quality. Therefore, by adjusting the first length A and / or the second length B within a certain allowable range, a variety of metal filling environments with different metal filling qualities can be constructed.

[0057] Furthermore, from formula (1), we can know that the parameter L ED As the change rate of the perimeter (4A+8B) of the second metal layer 212 is twice the ratio H / S, the theoretical parameter L ED The larger the ratio H / S, the better the metal filling quality. Therefore, when the ratio H / S is large, a smaller circumference change step of the second metal layer 212 will result in a more obvious metal filling quality difference. The circumference change step of the second metal layer is determined according to the area of ​​the first metal layer and the thickness of the second metal layer. That is, the larger the ratio H / S, the smaller the circumference change step, thereby ensuring that the optimal window for metal filling using the electrochemical plating process can be determined based on the test structure.

[0058] L ED =[(4A+8B)×H×2+S] / S (1)

[0059] It should be noted that in practice, the metal filling quality is closely related to the parameter L ED There is not necessarily a linear positive correlation between them. Therefore, when the ratio H / S remains unchanged, the change step of the circumference of the second metal layer may not be constant. It can be calculated based on the experience of parameter L ED The metal filling quality changes with the parameter L under different values ED The rate of change of further adjusts the change step size of the second metal layer perimeter. In addition, in the parameter L ED In larger cases, the metal filling quality may also be affected by the parameter L ED It is affected by other factors, so it is necessary to detect the resistance values ​​of different test units through wafer acceptance test (WAT) to more accurately detect the metal filling quality of different test units, so as to more accurately determine the optimal window for metal filling using electrochemical plating process.

[0060] Furthermore, there are multiple identical test units among the multiple test units, and the multiple identical test units are connected in series to form a test module. It should be understood that the test unit includes a first metal layer and a second metal layer, and thus a test module connected in series is obtained by connecting one test unit to each of the first metal layer and the second metal layer. In this embodiment, the number of test modules in the test structure can be equal to the number of types of test units. Figure 6 The test unit 210 and Figure 7 In the case of three test units such as the test unit 220 and the test unit 230 shown, the test structure may include three test modules corresponding to the three test units. Testing the resistance value of the test module formed by connecting a plurality of identical test units in series can, on the one hand, make the resistance value change caused by the metal filling quality more obvious, and on the other hand, when the resistance value of individual test units is affected by accidental factors other than the metal filling quality, it can also avoid the accidental factors from causing obvious interference to the evaluation result of the metal filling quality, thereby facilitating the improvement of the accuracy of the metal filling quality detection of the test unit.

[0061] Figure 8 The following is a test module, which consists of Figure 6The test unit 210 shown is formed in series, and may also include a first metal pin 241 and a second metal pin 242, wherein the first metal pin 241 is connected in series with the first test unit in the test module, and the first test unit in the figure is connected to a test unit through the first metal layer, so the first metal pin 241 is connected to the second metal layer of the first test unit; the second metal pin 242 is connected in series with the last test unit in the test module, and the last test unit in the figure is connected to a test unit through the second metal layer, so the second metal pin 242 is connected to the first metal layer of the last test unit in the test module. When testing the resistance value of the test module, the first metal pin 241 and the second metal pin 242 are used to apply voltage.

[0062] Corresponding to the test structure provided in the above embodiments, another embodiment of the present application further provides a test method for metal filling quality detection. The test method adopts any one of the test structures provided in the above embodiments to detect the metal filling quality. Fig. 9 FIG. 1 is a flow chart of a test method provided in an embodiment of the present application. Fig. 9 Shown include:

[0063] Step S110, forming a test structure;

[0064] Step S120 , applying voltage to the first metal layer and the second metal layer of the test unit included in the test structure to test the resistance value of the test unit.

[0065] It should be noted that, during the formation of the test structure, the metal connection channel in the test unit and the metal interconnection line whose metal filling quality is to be tested are formed simultaneously. For example, in the application scenario of testing the metal filling quality of the semiconductor device 100, the execution process of step S110 adopts the formation process of the test structure described in the above embodiment.

[0066] Furthermore, the test method for metal filling quality detection provided in the embodiment of the present application may also include comparing the resistance values ​​measured by different test units, so as to determine the window for metal filling using the electrochemical plating process according to the comparison result. It should be noted that in practice, the metal filling window can be determined according to the comparison result by comprehensively considering factors such as metal filling quality and device volume, and therefore the perimeter of the second metal layer in the test unit with the smallest resistance value may not necessarily be used.

[0067] Since the embodiments of the present application are tested by forming the test structure provided in the above embodiments, it is possible to simultaneously detect a variety of process windows with different metal filling qualities, thereby being able to more conveniently determine the optimal window for metal filling using an electrochemical plating process.

[0068] Finally, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that technicians in the relevant technical field can make good use of the present application and the modified use based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A test structure for metal filling quality detection, comprising a plurality of test units, wherein the test units include a first metal layer, a second metal layer and a metal connection channel, wherein: The first metal layer and the second metal layer are connected via the metal connection channel; The second metal layer is located above the first metal layer, and the second metal layer and the metal connection channel are integrally formed by metal filling, and the metal filling is performed by an electrochemical plating process; The perimeters of the second metal layers in different test units are set to different values ​​based on the line edge density effect, the resistance value of the test unit is negatively correlated with the quality of the metal filling used, the quality of the metal filling in different test units is detected by testing the resistance value of the test unit, and the process parameters of the second metal layer in the test unit with the smallest resistance value are determined as the process window with the best measured metal filling quality; Among them, the second metal layer includes a square area and four identical rectangular areas obtained by extending the respective sides of the square area outward; the side length of the square area is a first length, and the respective sides of the square area are extended outward by a second length to obtain the rectangular area, and the sum of twice the second length and the first length is different in different test units.

2. The test structure according to claim 1, wherein: The first length and / or the second length are different in different test units.

3. The test structure according to claim 1, wherein: The metal connection channel is connected to the center of the square area.

4. The test structure according to claim 1, wherein: The areas of the first metal layers in different test units are the same and the thicknesses of the second metal layers are also the same; The changing step length of the perimeter of the second metal layer in different test units is determined according to the area of ​​the first metal layer and the thickness of the second metal layer.

5. The test structure according to claim 1, wherein: There are multiple identical test units among the multiple test units, and the multiple identical test units are connected in series to form a test module.

6. The test structure according to claim 5, further comprising: A first metal pin connected in series with the first test unit in the test module, and a second metal pin connected in series with the last test unit in the test module.

7. The test structure according to claim 1, wherein: During the metal filling process, the metal material filled is copper.

8. A test method for metal filling quality detection, comprising: forming a test structure, wherein the test structure is the test structure according to any one of claims 1 to 7; A voltage is applied to the first metal layer and the second metal layer of the test unit included in the test structure to test the resistance value of the test unit, so as to detect the metal filling quality of the test unit according to the measured resistance value, wherein the process parameters of the second metal layer in the test unit with the smallest resistance value are determined as the process window with the best measured metal filling quality.

9. The testing method according to claim 8, further comprising: The resistance values ​​measured by the different test units are compared to determine the process window for metal filling using the electrochemical plating process according to the comparison result.

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