Integrated circuit structure with internal spacer pad

Abstract

Integrated circuit structures with internal spacer pads, and methods of fabricating integrated circuit structures with internal spacer pads, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. The gate structure vertically surrounds the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer liner is between vertically adjacent horizontal nanowires in the stack of internal gate spacers and horizontal nanowires, and the internal spacer liner is between the internal gate spacers and the gate structure.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of integrated circuit structures and processing, and more particularly, to integrated circuit structures having internal spacer liners, and methods of fabricating integrated circuit structures having internal spacer liners. Background Art

[0002] Over the past several decades, the shrinking of features in integrated circuits has been the driving force behind the growing semiconductor industry. The shrinking to smaller and smaller features enables an increased density of functional units on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive for ever-larger capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0003] In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors have become more common as device sizes continue to shrink. In conventional processes, tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate manufacturing processes. On the other hand, when microelectronic device sizes are reduced to less than 10 nanometer (nm) nodes, maintaining mobility improvements and short channel control poses challenges in device manufacturing.

[0004] However, shrinking multi-gate and nanowire transistors is not without consequences. As the size of these basic building blocks of microelectronic circuit devices decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the photolithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a tradeoff between the minimum size (critical dimension) of a feature patterned in a semiconductor stack and the spacing between these components. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An angled cross-sectional view showing an integrated circuit structure with internal spacers is shown.

[0006] Figures 2A-2F Angled cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having internal spacers and internal spacer liner are illustrated in accordance with an embodiment of the present disclosure.

[0007] Figure 2G Angled cross-sectional views and corresponding cross-sectional views of a gate-all-around integrated circuit structure with an internal spacer and an internal spacer liner according to an embodiment of the present disclosure are shown.

[0008] Figure 3A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0009] Figures 4A-4H A plan view of a substrate processed using a double-sided device processing method according to some embodiments is shown.

[0010] Figures 5A-5H A cross-sectional view of a substrate processed using a double-sided device processing method according to some embodiments is shown.

[0011] Figure 6 A cross-sectional view taken through nanowires and fins for a non-endcap architecture is shown in accordance with an embodiment of the present disclosure.

[0012] Figure 7 A cross-sectional view taken through a nanowire and fin for a self-aligned gate end cap (SAGE) architecture is shown in accordance with an embodiment of the present disclosure.

[0013] Fig. 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0014] Figure 8B The embodiment according to the present disclosure is shown Fig. 8A A cross-sectional source or drain diagram of a nanowire-based integrated circuit structure taken along the a-a' axis.

[0015] Figure 8C The embodiment according to the present disclosure is shown Fig. 8A A cross-sectional channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0016] Fig. 9 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0017] Fig.10 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] Integrated circuit structures with internal spacer pads, and methods of manufacturing integrated circuit structures with internal spacer pads are described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0019] Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "posterior," and "side" describe the orientation and / or position of portions of a component within a consistent but arbitrary reference system, which is clear by reference to the text and related drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0020] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0021] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0022] The embodiments described below may be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes are illustrated using FEOL processing cases, such methods may also be applied to BEOL processing. Likewise, although exemplary processing schemes are illustrated using BEOL processing cases, such methods may also be applied to FEOL processing.

[0023] According to embodiments of the present disclosure, an amorphous silicon (aSi) internal spacer or dimple liner is described. One or more embodiments described herein relate to a full-all-around gate device and associated internal spacer or dimple liner. It should be understood that unless otherwise stated, references to nanowires herein may indicate nanowires or nanoribbons or even nanosheets (e.g., in a forksheet device).

[0024] To provide context, internal (or pit) spacer oxidation may occur in the presence of barrier spacers formed of silicon oxide. According to one or more embodiments of the present disclosure, methods of reducing pit spacer oxidation by changing barrier spacers from SiO to aSi are described. Embodiments may be implemented to improve performance, reduce defectivity, and provide a more robust process.

[0025] As a control example, Figure 1 An angled cross-sectional view showing an integrated circuit structure with internal spacers is shown.

[0026] refer to Figure 1, the integrated circuit structure 100 includes an integrated circuit structure supported face-down, for example, on a carrier 102, after a backside reveal process is performed to remove the substrate and form an exposed sub-fin. The starting structure 100 includes a planarized sub-fin 110 (e.g., protruding from a substrate bulk substrate before planarization), such as a silicon sub-fin previously protruding from a silicon substrate. The sub-fin 110 protrudes through a shallow trench isolation (STI) structure 126, such as a silicon oxide STI structure. A liner such as a silicon nitride liner can separate the sub-fin 110 from the STI structure 126. Each sub-fin 110 is above one or more stacks of corresponding nanowires 108, which may be above a corresponding insulator cap layer 124. A gate electrode 112 / 114 (such as a structure including a work function layer 114 and a conductive filler 112) is around the nanowire 108. The gate electrode 112 / 114 is separated from the nanowire 108 and the sub-fin 110 by a gate dielectric layer 116 (such as a high-k gate dielectric layer). The conductive trench contact structure 118 can be adjacent to the gate structure 112 / 114 / 116 and can be coupled to an overlying epitaxial source or drain structure (not shown). In one embodiment, as shown, adjacent conductive trench contact structures 118 and gate structures 112 / 114 / 116 are separated from each other by dielectric spacers 120 (such as silicon nitride spacers). Internal or pit spacers 122 are vertically included between the ends of the nanowires in each stack of nanowires 108. As shown, an opening exposing the dielectric spacer 120 can be formed from the back. The above features can be formed above a structure including a local conductive contact 106 in the patterned dielectric layer 104. It should be understood that the front BEOL metallization layer can also be manufactured before the back is exposed.

[0027] Internal spacer pads can be incorporated into structures with internal spacers. As an exemplary process flow, Figures 2A-2F Angled cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure having internal spacers and internal spacer liner are illustrated in accordance with an embodiment of the present disclosure.

[0028] refer to Figure 2A, the starting structure 200 includes sub-fins 204 and 206 protruding from the substrate 202, such as silicon sub-fins protruding from the silicon substrate. Depending on whether back access is ultimately to be achieved, the sub-fins 204 and 206 can be formed to different depths. A stack of horizontal nanowires 208 (such as horizontal silicon nanowires) is above the corresponding sub-fin in the sub-fin 204 or 206. Sacrificial intermediate materials 210 (such as silicon germanium) alternate with the nanowires 208 in the stack of nanowires 208. At this stage, the sacrificial intermediate material 210 has been laterally recessed relative to the nanowires 208 to produce a recessed portion that can be referred to as a pit. A dielectric cap layer 212 (such as a silicon nitride cap layer) may be included above the corresponding stack of horizontal nanowires 208. At this stage, a dummy gate structure is included above the corresponding stack in the stack of horizontal nanowires 208. The exemplary dummy gate structure includes a silicon oxide dummy gate dielectric 214 , a polysilicon gate placeholder 216 , a silicon nitride hard mask 218 , and a silicon nitride gate spacer 220 (which may be referred to as an extrinsic gate spacer). A trench 222 is between adjacent stacks of horizontal nanowires 208 .

[0029] refer to Figure 2B , the inner or pit spacer liner 224 is formed with Figure 2A The structure 200 is conformal, for example, within the pit above the dummy gate and between the nanowires 208. In an embodiment, the inner or pit spacer liner 224 is composed of an amorphous silicon liner. In one such embodiment, the amorphous silicon liner has a thickness in the range of 0.5-2 nanometers. In one embodiment, the amorphous silicon liner is undoped or has less than 1E15 atoms / cm 3 of doping concentration.

[0030] refer to Figure 2C , forming and Figure 2B The inner spacer-forming material 226 is formed of a conformal inner spacer such as silicon nitride (or silicon carbide, or silicon oxynitride, or carbon-doped silicon oxide, etc.). In an embodiment, the thickness of the inner spacer-forming material 226 is greater than the thickness of the inner or pit spacer liner 224. In an embodiment, the inner spacer-forming material 226 has a thickness in the range of 1-5 nanometers.

[0031] refer to Figure 2D , an anisotropic etch of the inner spacer-forming material 226 is performed to remove a majority of the exposed portions of the inner spacer-forming material 226. The etching process forms inner or pit spacers 226A and may leave remaining portions 226B at the bottom of the trenches, as shown.

[0032] refer to Figure 2E, an anisotropic etch of the inner or pit spacer liner 224 is performed to remove the exposed portion and leave the inner or pit spacer liner 224A. The inner or pit spacer liner 224A is interposed between the inner or pit spacer 226A and the nanowire 208, and between the inner or pit spacer 226A and the sacrificial material 210. In one embodiment, as shown, the remaining portion of the inner or pit spacer liner 224A is interposed between the remaining portion 226B of the inner spacer-forming material 226 and the bottom of the trench.

[0033] refer to Figure 2F , an epitaxial source or drain structure 228, such as an epitaxial silicon germanium or epitaxial silicon structure, is formed in the trench between the stacks of adjacent nanowires 208. In one embodiment, the epitaxial source or drain structure 228 is grown on the exposed ends of the stack of horizontal nanowires 208. In one embodiment, the epitaxial source or drain structure 228 is in contact with the inner or pit spacer liner 224A.

[0034] In order to highlight certain features, Figure 2G Angled cross-sectional views and corresponding cross-sectional views of a gate-all-around integrated circuit structure with an internal spacer and an internal spacer liner according to an embodiment of the present disclosure are shown.

[0035] refer to Figure 2G , structure 250 is Figure 2F 2. A cross section 260 is taken through the dashed line of structure 250 and additionally shows the intermediate shallow trench isolation structure 252. An inner or pit spacer liner 224A is shown between the inner or pit spacer 226A and the nanowire 208, and between the inner or pit spacer 226A and the sacrificial material 210. The outer gate spacer 220 wraps around the nanowire stack.

[0036] It should be understood that Figure 2F and Figure 2G Subsequent processing after the stage shown in can involve dummy gate structure removal, removal of sacrificial material 210 through the gate opening (nanowire release), formation of high-k gate dielectric and metal gate electrode (replacement gate), and then trench contact formation and back-end of line (BEOL) structure fabrication. With respect to the nanowire release and replacement gate processes, the resulting structure effectively includes a portion of the gate structure in place of the sacrificial material and vertically surrounding the nanowire (full-all-around gate).

[0037] It should be understood that, as used throughout the present disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon sub-fins, silicon nanowires, silicon nanoribbons, or silicon fins. As used throughout the text, a silicon layer or structure may be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that in practice, 100% pure Si may be difficult to form, and therefore, a very small percentage of carbon, germanium, or tin may be included. These impurities may be included as unavoidable impurities or components during Si deposition, or may "contaminate" Si when diffused during post-deposition processing. Therefore, the embodiments described herein involving silicon layers or structures may include silicon layers or structures containing relatively small amounts (e.g., "impurity" levels) of non-Si atoms or substances (such as Ge, C, or Sn). It should be understood that the silicon layer or structure described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0038] It should be understood that as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon germanium sub-fins, silicon germanium nanowires, silicon germanium nanoribbons, or silicon germanium fins. As used throughout, a silicon germanium layer or structure may be used to describe a silicon germanium material that is composed of a substantial portion of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In a specific embodiment, the silicon germanium layer or structure includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer or structure includes about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and therefore may include very small percentages of carbon or tin. These impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe when diffused during post-deposition processing. Therefore, the embodiments described herein involving silicon germanium layers or structures may include silicon germanium layers or structures containing relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon germanium layers or structures as described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0039] It should be understood that the above integrated circuit structure can be integrated with other integrated circuit structures exposed on the back side. Figure 2A-2G Other integrated circuit structures can be manufactured by the process described. As an example of a backside exposed device, Figure 3 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0040] refer to Figure 3 , the semiconductor structure or device 300 includes a non-planar active region (e.g., a solid fin structure including a protruding fin portion 304 and a sub-fin region 305) within a trench isolation region 306. In another embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (such as nanowires 304A and 304B) above the sub-fin region 305, as shown by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 300, the non-planar active region 304 is referred to below as the protruding fin portion. It should be understood that in one embodiment, there is no bulk substrate coupled to the sub-fin region 305.

[0041] The gate line 308 is disposed over the protruding portion 304 of the non-planar active area (including the surrounding nanowires 304A and 304B, if applicable), and over a portion of the trench isolation region 306. As shown, the gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, the gate line 308 may also include a dielectric cap layer 354. Also seen from this view are the gate contact 314 and the overlying gate contact via 316 and the overlying metal interconnect 360, all of which are disposed in an interlayer dielectric stack or layer 370. From Figure 3 It can also be seen from the perspective of FIG. 3 that, in one embodiment, the gate contact 314 is disposed over the trench isolation region 306 but not over the non-planar active region.

[0042] In an embodiment, the semiconductor structure or device 300 is a non-planar device, such as but not limited to a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 308 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0043] Also like Figure 3 As shown in , in an embodiment, an interface 380 exists between the protruding fin portion 304 and the sub-fin region 305. The interface 380 can be a transition region between the doped sub-fin region 305 and the lightly doped or undoped upper fin portion 304. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid-state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide. In another embodiment, the sub-fin region is a dielectric material formed by recessing the fin by wet or dry etching and filling the recessed cavity with a conformal or flowable dielectric.

[0044] Although not in Figure 3 , but it should be understood that the source or drain region of the protruding fin portion 304 or the source or drain region adjacent to the protruding fin portion 304 is on either side of the gate line 308, i.e., in and out of the page. In one embodiment, the source or drain region is a doped portion of the original material of the protruding fin portion 304. In another embodiment, the material of the protruding fin portion 304 is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form a discrete epitaxial bump (nub) or a non-discrete epitaxial structure. In either embodiment, the source or drain region may extend below the height of the dielectric layer of the trench isolation region 306, i.e., into the sub-fin region 305. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below the interface 380) suppresses source-to-drain leakage through that portion of the bulk semiconductor fin.

[0045] Reference again Figure 3 In an embodiment, the fins 304 / 305 (and possibly the nanowires 304A and 304B) are composed of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 93%. In another embodiment, the fins 304 / 305 are composed of III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, gallium indium arsenide, aluminum gallium arsenide, gallium indium phosphide, or a combination thereof. The trench isolation region 306 may be composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0046] The gate line 308 may be composed of a gate electrode stack including a gate dielectric layer 352 and a gate electrode layer 350. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a native oxide layer formed by the top layers of the substrate fin 304. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion, the lower portion being composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0047] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above the metal work function setting layer. The gate electrode layer can be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include but are not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In a further embodiment of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0048] The spacer associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating the permanent gate structure from an adjacent conductive contact (such as a self-aligned contact) or facilitating the isolation of the permanent gate structure from an adjacent conductive contact (such as a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0049] The gate contact 314 and the overlying gate contact via 316 may be made of a conductive material. In an embodiment, one or more of the contacts or vias are made of a metallic substance. The metallic substance may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0050] In an embodiment (although not shown), a contact pattern is formed that is substantially fully aligned with the existing gate pattern 308, while eliminating the use of a lithography step with a very tight registration budget. In one such embodiment, a self-aligned method enables the use of an essentially highly selective wet etch (e.g., relative to a conventionally implemented dry or plasma etch) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for critical lithography operations for generating contact patterns as otherwise used in conventional methods. In an embodiment, a trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, a trench contact grid is formed after gate grating patterning but before gate grating cutting.

[0051] In an embodiment, providing structure 300 involves manufacturing gate stack structure 308 by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, rather than from an earlier process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon, and the dummy gate is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon, and the dummy gate is removed using a wet etching process including the use of NH4OH or tetramethylammonium hydroxide aqueous solution. In one embodiment, the dummy gate is composed of silicon nitride, and the dummy gate is removed using a wet etching process including an aqueous phosphoric acid solution.

[0052] Reference again Figure 3 , the arrangement of semiconductor structure or device 300 places the gate contact above the isolation region. Such an arrangement may be viewed as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above the sub-fin 305) and in the same layer as the trench contact via.

[0053] It should be understood that it is not necessary to practice all aspects of the above process to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, before manufacturing the gate contact above the active portion of the gate stack, it is not necessary to form a dummy gate. The above-mentioned gate stack can actually be an initially formed permanent gate stack. In addition, the process described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for a logic unit or a memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, a dual-gate device connected by independent paths, a full-ring gate (GAA) device, a nanowire device, a nanobelt device, or a FIN-FET. One or more embodiments can be particularly useful for manufacturing semiconductor devices at a technology node below 10 nanometers (10nm).

[0054] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0055] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are the use of copper lines and structures, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers, including a conductive liner layer and a filling layer. Any suitable deposition process (such as electroplating, chemical vapor deposition or physical vapor deposition) may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as but not limited to Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or its alloy. Interconnects are sometimes also referred to as traces, wires, lines, metals or simply interconnects in the art.

[0056] In an embodiment, as also used throughout this specification, the hard mask material, cover layer or plug is composed of a dielectric material different from the interlayer dielectric material. In an embodiment, different hard mask, cover or plug materials may be used in different regions to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cover or plug layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cover or plug layers known in the art may be used. The hard mask, cover or plug layer may be formed by CVD, PVD or by other deposition methods.

[0057] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0058] On the other hand, the integrated circuit structures described herein can be manufactured using a backside exposure manufacturing method for a front side structure. In some exemplary embodiments, the exposure of the back side of a transistor or other device structure requires wafer-level backside processing. Compared to conventional TSV-type technologies, the exposure of the back side of the transistor as described herein can be performed at the density of the device unit, and even in a sub-region of the device. In addition, such exposure of the back side of the transistor can be performed to remove substantially all of the donor substrate on which the device layer is disposed during the front side device processing. Therefore, micron-deep TSVs become unnecessary, where the thickness of the semiconductor in the device unit after the back side of the transistor is exposed may be only tens or hundreds of nanometers.

[0059] The exposure techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer employed in front-side fabrication, exposed from the backside, and employed again in back-side fabrication. Processing both the front-side and exposed backside of device structures can address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0060] For example, a method for revealing the back side of a transistor may be used to remove at least a portion of the carrier layer and the intermediate layer of the donor-host substrate assembly, such as described below. Figures 4A-4Hand 5A-5H. The process flow begins with the input of a donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0061] In some embodiments, prior to the above steps, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. A cleaving or fracture process can be used to remove a large portion of the carrier layer as a bulk material, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case where the thickness of the carrier layer is 400-900 μm, 100-700 μm can be cleaved by implementing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted into the carrier layer to a uniform target depth of the desired fracture plane. After this cleaving process, the remaining thickness of the carrier layer in the donor-host substrate assembly can be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0062] Next, the exposure of the intermediate layer is detected. The detection is used to identify the point at which the back surface of the donor substrate has advanced to a point close to the device layer. Any known endpoint detection technology suitable for detecting the transition between the materials used for the carrier layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting changes in the optical absorption or emission of the back surface of the donor substrate during the execution of polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in the optical absorption or emission of byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproducts can be changed according to the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the substances in the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the treatment can be sampled by a quadrupole mass analyzer, and the changes in the mass of the substances can be related to the different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the friction between the back surface of the donor substrate and the polishing surface (in contact with the back surface of the donor substrate).

[0063] In the case where the removal process is selective for the carrier layer relative to the intermediate layer, the detection of the intermediate layer can be enhanced because the non-uniformity in the carrier removal process can be mitigated by the etch rate delta between the carrier layer and the intermediate layer. If the grinding, polishing and / or etching operation removes the intermediate layer at a rate sufficiently lower than the removal rate of the carrier layer, the detection can even be skipped. If no endpoint criteria are used, the grinding, polishing and / or etching operation of a predetermined fixed duration can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient to achieve selectivity in etching. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or greater.

[0064] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more constituent layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be uniformly removed by polishing. Alternatively, the thickness of the intermediate layer can be removed by a mask or blanket etching process. The process can use the same polishing or etching process used to thin the carrier, or it can be a different process with different process parameters. For example, in the case where the intermediate layer provides an etch stop for the carrier removal process, the latter operation can use a different polishing or etching process that is more conducive to the removal of the intermediate layer than the removal of the device layer. In the case of removing an intermediate layer thickness of less than a few hundred nanometers, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process for removing the carrier layer. The CMP process used can, for example, use a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intermediate layer (e.g., as electrical isolation between adjacent device regions).

[0065] For embodiments where the device layer is exposed by completely removing the intermediate layer, backside processing may be initiated on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region previously fabricated in the device layer, such as a source or drain region.

[0066] In some embodiments where wet and / or plasma etching is used to recess the back side of a carrier layer, an intermediate layer, or a device layer, such etching may be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the back side surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may be across a device cell (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back side device layer. Thus, the mask etching process may precede the etching of the corresponding mask device layer.

[0067] The above processing scheme can produce a donor-host substrate assembly including an IC device that exposes the back side of the intermediate layer, the back side of the device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer. Additional back side processing can then be performed on any of these exposed regions during downstream processing.

[0068] According to one or more embodiments of the present disclosure, in order to achieve backside access to partitioned source or drain contact structures, a double-sided device processing scheme can be practiced at the wafer level. In some exemplary embodiments, large formal substrate (e.g., 300 or 450 mm diameter) wafers can be processed. In an exemplary processing scheme, a donor substrate including a device layer is provided. In some embodiments, the device layer is a semiconductor material used by an IC device. As an example, in a transistor device such as a field effect transistor (FET), the channel semiconductor is formed by a semiconductor device layer. As another example, for an optical device such as a photodiode, a drift and / or gain semiconductor is formed by a device layer. The device layer can also be used in a passive structure with an IC device. For example, an optical waveguide can use a semiconductor patterned from a device layer.

[0069] In some embodiments, the donor substrate includes a stack of material layers. Such a material stack can facilitate the subsequent formation of an IC device stratum including a device layer but lacking other layers of the donor substrate. In an exemplary embodiment, the donor substrate includes a carrier layer separated from the device layer by one or more intermediate material layers. The carrier layer is used to provide mechanical support during the front processing of the device layer. The carrier can also provide a basis for crystallinity in the semiconductor device layer. (Multiple) intermediate layers can help remove the carrier layer and / or expose the back of the device layer.

[0070] The front manufacturing operation is then performed to form a device structure including one or more regions in the device layer. Any known front processing technology can be used to form any known IC device, and exemplary embodiments are further described in other parts of this article. The front side of the donor substrate is then bonded to the host substrate to form a device-host assembly. The host substrate is used to provide front mechanical support during the back side processing of the device layer. The host substrate may also require an integrated circuit device, and the IC device manufactured on the donor substrate is interconnected with the integrated circuit device. For such an embodiment, the bonding of the host substrate and the donor substrate may also require the formation of a 3D interconnect structure by hybrid (dielectric / metal) bonding. Any known host substrate and wafer-level bonding technology can be used.

[0071] The process flow continues, wherein the back side of the device structure layer is exposed by removing at least a portion of the carrier layer. In some further embodiments, any intermediate layer and / or portion of the front material deposited above the device layer may also be removed during the revealing operation. As described in the context of some exemplary embodiments elsewhere herein, (multiple) intermediate layers may facilitate highly uniform exposure of the back side of the device structure layer, for example, as one or more of the etching marks or etching stops used in the wafer-level backside revealing process. The device structure layer surface exposed from the back side is processed to form a double-sided device structure layer. The native material may then be replaced with one or more non-native materials, such as any of those materials of the donor substrate that are docked with the device region. For example, a portion of the semiconductor device layer or intermediate layer may be replaced with one or more other semiconductor, metal, or dielectric materials. In some further embodiments, a portion of the front material removed during the revealing operation may also be replaced. For example, a portion of a dielectric spacer, gate stack, or contact metallization formed during front device fabrication may be replaced with one or more other semiconductor, metal, or dielectric materials during backside reverse processing (deprocessing) / reprocessing of the front device. In other embodiments, a second device building layer or a metal interposer is bonded to the exposed backside.

[0072] The above process flow provides a device layer-host substrate assembly. The device layer-host assembly can then be further processed. For example, any known technology can be used to singulate and package the device layer-host substrate assembly. In the case where the host substrate is completely sacrificed, the packaging of the device layer-host substrate may require the separation of the host substrate from the device layer. In the case where the host substrate is not completely sacrificed (for example, in the case where the host substrate also includes a device layer), the device layer-host assembly output can be fed back as a host substrate input during subsequent iterations of the above process flow. Therefore, iterations of the above method can form wafer-level assemblies of any number of double-sided device layers, each layer having a thickness of only, for example, tens or hundreds of nanometers. In some embodiments, and as further described elsewhere herein, one or more device units within the device layer are electrically tested, for example as a yield control point in the manufacture of wafer-level assemblies of double-sided device layers. In some embodiments, electrical testing requires back-side device detection.

[0073] Figures 4A-4H A plan view of a substrate processed using a double-sided device processing method according to some embodiments is shown. Figures 5A-5H A cross-sectional view of a substrate processed using a double-sided device processing method according to some embodiments is shown.

[0074] like Figure 4A and Figure 5AAs shown, the donor substrate 401 includes a plurality of IC dies 411 in an arbitrary spatial arrangement above the front wafer surface. The front processing of the IC dies 411 can be performed after any technology for forming any device structure. In an exemplary embodiment, the die 411 includes one or more semiconductor regions within the device layer 415. The intermediate layer 410 separates the device layer 415 from the carrier layer 405. In an exemplary embodiment, the intermediate layer 410 is in direct contact with both the carrier layer 405 and the device layer 415. Alternatively, one or more spacer layers can be disposed between the intermediate layer 410 and the device layer 415 and / or the carrier layer 405. The donor substrate 401 may also include other layers, for example, disposed above the device layer 415 and / or below the carrier layer 405.

[0075] Device layer 415 may include one or more layers of any device material composition known to be suitable for a particular IC device (e.g., but not limited to, transistors, diodes, and resistors). In some exemplary embodiments, device layer 415 includes one or more Group IV (i.e., IUPAC Group 14) semiconductor material layers (e.g., Si, Ge, SiGe), Group III-V semiconductor material layers (e.g., GaAs, InGaAs, InAs, InP), or Group III-N semiconductor material layers (e.g., GaN, AlGaN, InGaN). Device layer 415 may also include one or more semiconductor transition metal dichalcogenides (TMD or TMDC) layers. In other embodiments, device layer 415 includes one or more graphene layers, or graphene material layers having semiconductor properties. In other embodiments, device layer 415 includes one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of transition metals (e.g., IUPAC Groups 4-10) or post-transition metals (e.g., IUPAC Groups 11-14). In a preferred embodiment, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxide may be a suboxide (AO), a monoxide (AO), a binary oxide (AO2), a ternary oxide (ABO3), and mixtures thereof. In other embodiments, the device layer 415 includes one or more layers of magnetic, ferromagnetic, or ferroelectric materials. For example, the device layer 415 may include one or more layers of any material known to be suitable for a tunnel junction device, such as, but not limited to, a magnetic tunnel junction (MTJ) device.

[0076] In some embodiments, device layer 415 is substantially single crystalline. Although single crystalline, there may still be a large number of crystal defects. In other embodiments, device layer 415 is amorphous or nanocrystalline. Device layer 415 can be of any thickness (e.g., Figure 5AIn some exemplary embodiments, device layer 415 has a thickness greater than the z-thickness of at least some of the semiconductor regions employed by die 411 because the functional semiconductor regions of die 411 built on and / or embedded in device layer 415 do not need to extend through the entire thickness of device layer 415. In some embodiments, the semiconductor regions of die 411 are disposed only at Figure 5A 410. The top side thickness of the device layer 415 is within the thickness of the top side of the device layer 415 distinguished by the dotted line 412. For example, the semiconductor region of the tube core 411 can have a z thickness of 200-300nm or less, while the device layer can have a z thickness of 700-1000nm or more. Therefore, a device layer thickness of about 600nm can separate the semiconductor region of the tube core 411 from the intermediate layer 410.

[0077] The carrier layer 405 may have the same material composition as the device layer 415, or may have a different material composition than the device layer 415. For embodiments where the carrier layer 405 and the device layer 415 have the same composition, the two layers may be identified by their position relative to the intermediate layer 410. In some embodiments where the device layer 415 is a crystalline Group IV, Group III-V, or Group III-N semiconductor, the carrier layer 405 is the same crystalline Group IV, Group III-V, or Group III-N semiconductor as the device layer 415. In alternative embodiments, where the device layer 415 is a crystalline Group IV, Group III-V, or Group III-N semiconductor, the carrier layer 405 is a different crystalline Group IV, Group III-V, or Group III-N semiconductor than the device layer 415. In other embodiments, the carrier layer 405 may include or be a material onto which the device layer 415 is transferred or grown. For example, the carrier layer may include one or more amorphous oxide layers (e.g., glass) or crystalline oxide layers (e.g., sapphire), a polymer sheet, or any material(s) constructed or laminated to a structural support known to be suitable as a carrier during IC device processing. The carrier layer 405 can be of any thickness depending on the properties of the carrier material and the diameter of the substrate (e.g. Figure 5A For example, in the case where the carrier layer 405 is a large format (eg, 300-450 mm) semiconductor substrate, the carrier layer thickness may be 700-1000 μm or more.

[0078] In some embodiments, one or more intermediate layers 410 are disposed between the carrier layer 405 and the device layer 415. In some exemplary embodiments, the intermediate layer 410 is compositionally different from the carrier layer 405 so that it can be used as a detectable marker during subsequent removal of the carrier layer 405. In some such embodiments, the intermediate layer 410 has a composition that will be etched at a much slower rate than the carrier layer 405 when exposed to an etchant for the carrier layer 405 (i.e., the intermediate layer 410 serves as an etch stop layer for the carrier layer etching process). In further embodiments, the intermediate layer 410 has a composition that is different from that of the device layer 415. The intermediate layer 410 can be, for example, a metal, a semiconductor, or a dielectric material.

[0079] In some exemplary embodiments in which at least one of the carrier layer 405 and the device layer 415 is a crystalline semiconductor, the intermediate layer 410 is also a crystalline semiconductor layer. The intermediate layer 410 may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415. Such embodiments may have the advantage of reduced donor substrate costs relative to alternative embodiments in which the intermediate layer 410 is a material that requires bonding (e.g., thermocompression bonding) of the intermediate layer 410 to the intermediate layer 410 and / or the carrier layer 405.

[0080] For embodiments where the intermediate layer 410 is a semiconductor, one or more of the primary semiconductor lattice element, alloy composition, or impurity concentration may vary between at least the carrier layer 405 and the intermediate layer 410. In some embodiments where at least the carrier layer 405 is a Group IV semiconductor, the intermediate layer 410 may also be a Group IV semiconductor, but with a different Group IV element or alloy and / or doped with an impurity substance at an impurity level different from that of the carrier layer 405. For example, the intermediate layer 410 may be a silicon-germanium alloy epitaxially grown on a silicon carrier. For such embodiments, the pseudomorphic intermediate layer may be heteroepitaxially grown to any thickness below the critical thickness. Alternatively, the intermediate layer 410 may be a relaxed buffer layer having a thickness greater than the critical thickness.

[0081] In other embodiments, where at least the carrier layer 405 is a III-V semiconductor, the intermediate layer 410 may also be a III-V semiconductor, but with a different III-V alloy and / or doped with impurity species at different impurity levels than the carrier layer 405. For example, the intermediate layer 410 may be an AlGaAs alloy epitaxially grown on a GaAs carrier. In some other embodiments where both the carrier layer 405 and the device layer 415 are crystalline semiconductors, the intermediate layer 410 is also a crystalline semiconductor layer, which may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415.

[0082] In embodiments where both the carrier layer 405 and the intermediate layer 410 have the same or different primary semiconductor lattice elements, the impurity dopant can differentiate between the carrier layer and the intermediate layer. For example, the intermediate layer 410 and the carrier layer 405 can both be silicon crystals, with the intermediate layer 410 lacking impurities present in the carrier layer 405, or being doped with impurities not present in the carrier layer 405, or being doped to different levels with impurities present in the carrier layer 405. Impurity differentiation can impart etch selectivity between the carrier and intermediate layers, or introduce only detectable species.

[0083] The intermediate layer 410 may be doped with electrically active impurities (i.e., to make it an n-type or p-type semiconductor) or undoped with electrically active impurities, as the impurities may provide any basis for detecting the intermediate layer 410 during subsequent carrier removal. Exemplary electrically active impurities of some semiconductor materials include group III elements (e.g., B), group IV elements (e.g., P). Any other element may be employed as the non-electrically active substance. The impurity dopant concentration within the intermediate layer 410 need only differ from the impurity dopant concentration of the carrier layer 405 by an amount sufficient for detection, which may be predetermined based on the detection technique and detector sensitivity.

[0084] As further described elsewhere herein, the intermediate layer 410 can have a different composition than the device layer 415. In some such embodiments, the intermediate layer 410 can have a bandgap that is different than the bandgap of the device layer 415. For example, the intermediate layer 410 can have a wider bandgap than the device layer 415.

[0085] In embodiments where the intermediate layer 410 comprises a dielectric material, the dielectric material may be an inorganic material (e.g., SiO, SiN, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane) or an organic material (polyimide, polynorbornene, benzocyclobutene). For some dielectric embodiments, the intermediate layer 410 may be formed as an embedded layer (e.g., by implanting oxygen into SiOx in the silicon device and / or carrier layer). Other embodiments of the dielectric intermediate layer may require bonding (e.g., thermocompression bonding) the carrier layer 405 to the device layer 415. For example, where the donor substrate 401 is a semiconductor on oxide (SOI) substrate, either or both of the carrier layer 405 and the device layer 415 may be oxidized and bonded together to form the SiO intermediate layer 410. Similar bonding techniques may be used for other inorganic or organic dielectric materials.

[0086] In some other embodiments, the intermediate layer 410 includes two or more materials spaced laterally within the layer. The two or more materials may include dielectrics and semiconductors, dielectrics and metals, semiconductors and metals, dielectrics and metals, two different dielectrics, two different semiconductors, or two different metals. In such an intermediate layer, a first material may surround an island of a second material extending through the thickness of the intermediate layer. For example, the intermediate layer may include a field isolation dielectric surrounding a semiconductor island extending through the thickness of the intermediate layer. The semiconductor may be epitaxially grown in the opening of the patterned dielectric, or a dielectric material may be deposited in the opening of the patterned semiconductor.

[0087] In some exemplary embodiments, semiconductor features (such as fins or mesas) are etched into the front surface of the semiconductor device layer. The trenches surrounding these features can be subsequently backfilled with an isolation dielectric, for example after any known shallow trench isolation (STI) process. One or more of the semiconductor features or the isolation dielectric can be used to terminate the back carrier removal process, for example as a back exposure etch stop. In some embodiments, the exposure of the trench isolation dielectric can stop, significantly delay the back carrier polishing, or induce a detectable signal for terminating the back carrier polishing. For example, when exposing the (bottom) surface of the trench isolation dielectric surrounding the semiconductor features including the device layer, CMP polishing of the carrier semiconductor using a slurry with a high selectivity that favors the removal of the carrier semiconductor (e.g., Si) rather than the removal of the isolation dielectric (e.g., SiO) may be significantly slowed. Because the device layer is disposed on the front side of the intermediate layer, the device layer does not need to be directly exposed to the back exposure process.

[0088] It is worth noting that for embodiments where the intermediate layer includes both semiconductor and dielectric, the intermediate layer thickness can be significantly greater than a critical thickness associated with the lattice mismatch of the intermediate layer and the carrier. Given that an intermediate layer having a thickness below the critical thickness may not be sufficient to accommodate the non-uniformity of the wafer-level backside exposure process, embodiments with a greater thickness can advantageously increase the backside exposure process window. Embodiments with pinhole dielectrics can otherwise facilitate subsequent separation of the carrier layer and the device layer as well as improve crystal quality within the device layer.

[0089] The semiconductor material within the intermediate layer including both semiconductor and dielectric may also be homoepitaxial.In some exemplary embodiments, the silicon epitaxial device layer is grown through a pinhole dielectric disposed over a silicon carrier layer.

[0090] Continue description Figure 4A and Figure 5A, the intermediate layer 410 may also be a metal. For such embodiments, the metal may be of any composition known to be suitable for bonding to the carrier layer 405 or the device layer 415. For example, either or both of the carrier layer 405 and the device layer 415 may be finished wtih a metal such as, but not limited to, Au or Pt, and subsequently bonded together, for example, to form an Au or Pt intermediate layer 410. Such a metal may also be part of an intermediate layer that also includes a patterned dielectric surrounding the metal features.

[0091] The intermediate layer 410 may have any thickness (eg, Figure 5A 410). The intermediate layer should be thick enough to ensure that the carrier removal operation can be reliably terminated before exposing the device area and / or device layer 415. Exemplary thicknesses of the intermediate layer 410 range from a few hundred nanometers to a few microns and can vary, for example, depending on the amount of carrier material to be removed, the uniformity of the carrier removal process, and the selectivity of the carrier removal process. For embodiments in which the intermediate layer has the same crystallinity and crystal orientation as the carrier layer 405, the carrier layer thickness can be reduced by the thickness of the intermediate layer 410. That is, the intermediate layer 410 can be the top portion of a 700-1000 μm thick Group IV crystalline semiconductor substrate that also serves as a carrier layer. In pseudomorphic heteroepitaxial embodiments, the intermediate layer thickness can be limited to a critical thickness. For heteroepitaxial intermediate layer embodiments employing aspect ratio trapping (ART) or another fully relaxed buffer architecture, the intermediate layer can have any thickness.

[0092] like Figure 4B and Figure 5B As further shown in the figure, the donor substrate 401 can be bonded to the host substrate 402 to form a donor-host substrate assembly 403. In some exemplary embodiments, the front surface of the donor substrate 401 is bonded to the surface of the host substrate 402, so that the device layer 415 is close to the host substrate 402 and the carrier layer 405 is away from the host substrate 402. The host substrate 402 can be any substrate known to be suitable for bonding to the device layer 415 and / or the front stack fabricated above the device layer 415. In some embodiments, the host substrate 402 includes one or more additional device building layers. For example, the host substrate 402 may also include one or more device layers (not shown). The host substrate 402 may include an integrated circuit device, and the IC device fabricated in the device layer of the host substrate 402 is interconnected with the integrated circuit device, in which case the bonding of the device layer 415 to the host substrate 402 may also require the formation of a 3D interconnect structure through wafer-level bonding.

[0093] although Figure 5BNot shown in detail, but there may be any number of front-side layers, such as interconnect metallization levels and interlayer dielectric (ILD) layers, between the device layer 415 and the host substrate 402. Any technique may be employed to bond the host substrate 402 and the donor substrate 401. In some exemplary embodiments further described elsewhere herein, the bonding of the donor substrate 401 to the host substrate 402 is performed by metal-metal, oxide-oxide, or hybrid (metal / oxide-metal / oxide) thermocompression bonding.

[0094] In the case where the host substrate 402 faces the device layer 415 on the side opposite to the carrier layer 405, at least a portion of the carrier layer 405 may be removed, such as Figure 4C and Figure 5C . With the entire carrier layer 405 removed, the donor-host substrate assembly 403 remains with a highly uniform thickness having a planar back surface and front surface. Alternatively, the carrier layer 405 may be masked and the intermediate layer 410 exposed only in unmasked sub-regions to form a non-planar back surface. Figure 4C and Figure 5C In the exemplary embodiment shown, the carrier layer 405 is removed from the entire back surface of the donor-host substrate assembly 403. The carrier layer 405 can be removed, for example, by cleaving, grinding and / or polishing (e.g., chemical mechanical polishing) and / or wet chemical etching and / or plasma etching through the thickness of the carrier layer to expose the intermediate layer 410. One or more operations can be used to remove the carrier layer 405. Advantageously, the removal operation(s) can be terminated based on an endpoint signal or duration sensitive to the exposure of the intermediate layer 410.

[0095] In other embodiments, for example, Figure 4D and Figure 5D As shown, the intermediate layer 410 is also at least partially etched to expose the back side of the device layer 415. At least a portion of the intermediate layer 410 can be removed after it serves as a carrier layer etch stop and / or a carrier layer etch endpoint trigger. With the entire intermediate layer 410 removed, the donor-host substrate assembly 403 maintains a highly uniform device layer thickness, wherein the planar back and front surfaces provided by the intermediate layer are much thinner than the carrier layer. Alternatively, the intermediate layer 410 can be masked and the device layer 415 exposed only in unmasked sub-regions, thereby forming a non-planar back surface. Figure 4D and Figure 5DIn the exemplary embodiment shown, the intermediate layer 410 is removed from the entire back surface of the donor-host substrate assembly 403. For example, the intermediate layer 410 can be removed by polishing (e.g., chemical mechanical polishing) and / or blanket wet chemical etching and / or blanket plasma etching through the thickness of the intermediate layer to expose the device layer 415. One or more operations can be used to remove the intermediate layer 410. Advantageously, the removal operation(s) can be terminated based on an endpoint signal or duration sensitive to the exposure of the device layer 415.

[0096] In some other embodiments, for example, Figure 4E and Figure 5E As shown, the device layer 415 is partially etched to expose the back side of the device structure previously formed during front side processing. At least a portion of the device layer 415 can be removed after it is used to fabricate one or more device semiconductor regions and / or it is used as an intermediate layer etch stop or endpoint trigger. With the device layer 415 thinned over the entire substrate area, the donor-host substrate assembly 403 maintains a highly consistent reduced thickness with flat rear and front surfaces. Alternatively, the device layer 415 can be masked and the device structure (e.g., device semiconductor region) selectively revealed only in unmasked sub-regions, thereby forming a non-planar back side surface. In Figure 4E and Figure 5E In the exemplary embodiment shown, the device layer 415 is thinned over the entire back surface of the donor-host substrate assembly 403. The device layer 415 can be thinned, for example, by polishing (e.g., chemical mechanical polishing) and / or wet chemical etching and / or plasma etching through the thickness of the device layer to expose one or more device semiconductor regions and / or one or more other device structures previously formed during front processing (e.g., front device terminal contact metallization, spacer dielectric, etc.). One or more operations can be used to thin the device layer 415. Advantageously, the device layer thinning can be terminated based on an endpoint signal or duration sensitive to the exposure of patterned features within the device layer 415. For example, in the case of front processing to form device isolation features (e.g., shallow trench isolation), the back thinning of the device layer 415 can be terminated when the isolation dielectric material is exposed.

[0097] The non-native material layer may be deposited over an intermediate layer within the device layer 415, a device layer, and / or a back surface of a particular device region, and / or over one or more other device structures (e.g., front device terminal contact metallization, spacer dielectric, etc.). One or more materials exposed (revealed) from the back side may be covered with a non-native material layer or replaced with such a material. In some embodiments, as Figure 4F and Fig. 5FAs shown, a non-native material layer 420 is deposited on the device layer 415. The non-native material layer 420 can be any material having a composition and / or microstructure different from the composition and / or microstructure of the material that is removed to reveal the back side of the device layer. For example, in the case where the intermediate layer 410 is removed to expose the device layer 415, the non-native material layer 420 can be another semiconductor with a composition or microstructure different from the composition or microstructure of the intermediate layer 410. In some such embodiments where the device layer 415 is a III-N semiconductor, the non-native material layer 420 can also be a III-N semiconductor of the same or different composition that is regrown on the exposed back side surface of the III-N device region. The material can be epitaxially regrown from the exposed III-N device region, for example, to have a better crystal quality than the crystal quality of the removed material, and / or induce strain in the device layer and / or device region within the device layer, and / or form a vertical (e.g., z-dimension) stack of device semiconductor regions suitable for stacking devices.

[0098] In some other embodiments where the device layer 415 is a III-V semiconductor, the non-native material layer 420 may also be a III-V semiconductor of the same or different composition regrown on the exposed back surface of the III-V device region. The material may be epitaxially regrown from the exposed III-V device region, for example, to have relatively better crystal quality than the removed material, and / or to induce strain in the device layer or a specific device region within the device layer, and / or to form a vertical stack of device semiconductor regions suitable for stacking devices.

[0099] In some other embodiments where the device layer 415 is a Group IV semiconductor, the non-native material layer 420 may also be a Group IV semiconductor of the same or different composition regrown on the exposed back surface of the Group IV device region. The material may be epitaxially regrown from the exposed Group IV device region, for example, to have relatively better crystal quality than the removed material, and / or to induce strain in the device region, and / or to form a stack of device semiconductor regions suitable for stacking devices.

[0100] In some other embodiments, the non-native material layer 420 is a dielectric material such as, but not limited to, SiO, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, benzocyclobutene, etc. Deposition of such a dielectric may be used to electrically isolate various device structures, such as semiconductor device regions, that may have been previously formed during front side processing of the donor substrate 401.

[0101] In some other embodiments, the non-native material layer 420 is a conductive material, such as any elemental metal or metal alloy known to be suitable for contacting one or more surfaces of a device region exposed from the back side. In some embodiments, the non-native material layer 420 is a metallization suitable for contacting a device region exposed from the back side, such as a transistor source or drain region. In embodiments, metal-to-metal contacts such as NixSiy, TixSiy, Ni:Si:Pt, TiSi, CoSi, etc. may be formed. Additionally, implants may be used to achieve robust contacts (e.g., P, Ge, B, etc.).

[0102] In some embodiments, the non-native material layer 420 is a material stack, such as a FET gate stack including both a gate dielectric layer and a gate electrode layer. As an example, the non-native material layer 420 can be a gate dielectric stack suitable for contacting a semiconductor device region (such as a transistor channel region) exposed from the back side. Any other material described as an option for the device layer 415 can also be deposited over the back side of the device layer 415 and / or formed over a device region within the device layer 415. For example, the non-native material layer 420 can be any of the above-mentioned oxide semiconductors, TMDCs, or tunneling materials, which can be deposited on the back side, for example, to incrementally manufacture vertically stacked device layers.

[0103] The backside wafer level processing can continue in any manner known to be suitable for frontside processing. For example, the non-native material layer 420 can be patterned into active device areas, device isolation areas, device contact metallizations, or device interconnects using any known photolithography and etching techniques. The backside wafer level processing can further fabricate one or more interconnect metallization levels that couple the terminals of different devices to the IC. In some embodiments further described elsewhere herein, backside processing can be employed to interconnect power buses to various device terminals within the IC.

[0104] In some embodiments, backside processing includes bonding to a secondary host substrate. Such bonding may employ any layer transfer process to bond a backside (e.g., non-native) material layer to another substrate. After such bonding, the previous host substrate may be removed as a sacrificial donor to re-expose the front side of the front stack and / or device layer. Such embodiments may enable iterative side-to-side lamination of device building layers with a first device layer serving as the core of the assembly. Figure 4G and Figure 5G In some of the embodiments shown, a secondary host substrate 440 bonded to the non-native material layer 420 provides at least mechanical support when the host substrate 402 is removed.

[0105] Any bonding, such as but not limited to thermocompression bonding, may be employed to bond the secondary host substrate 440 to the non-native material layer 420. In some embodiments, the surface layer of the secondary host substrate 440 and the non-native material layer 420 are both continuous dielectric layers (e.g., SiO) that are thermocompressively bonded. In some other embodiments, the surface layer of the secondary host substrate 440 and the non-native material layer 420 both include thermocompressively bonded metal layers (e.g., Au, Pt, etc.). In other embodiments, at least one of the surface layer of the patterned secondary host substrate 440 and the non-native material layer 420, including both a patterned metal surface (i.e., trace) and a surrounding dielectric (e.g., isolation), is thermocompressively bonded to form a hybrid (e.g., metal / oxide) bond. For such embodiments, the structural features in the secondary host substrate 440 and the patterned non-native material layer 420 are aligned (e.g., optically) during the bonding process. In some embodiments, the non-native material layer 420 includes one or more conductive back traces coupled to the terminals of the transistors fabricated in the device layer 415. The conductive backside traces may, for example, be bonded to metallization on the secondary host substrate 440 .

[0106] The bonding of the device layers can be performed from the front and / or back of the device layers before or after the front processing of the device layers has been completed. The back bonding process can be performed after the front fabrication of the device (e.g., transistor) is substantially complete. Alternatively, the back bonding process can be performed before the front fabrication of the device (e.g., transistor) is completed, in which case the front of the device layer can receive additional processing after the back bonding process. Figure 4H and Figure 5H As further shown in FIG. 4 , for example, front side processing includes removing host substrate 402 (as a second donor substrate) to re-expose the front side of device layer 415. At this point, donor-host substrate assembly 403 includes secondary host 440 bonded to device layer 415 via non-native material layer 420.

[0107] On the other hand, the above integrated circuit structure can be integrated with an integrated circuit structure exposed on the back side (such as an adjacent semiconductor structure or device separated by a self-aligned gate end cap (SAGE) structure). Specific embodiments may be directed to the integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, the nanowire / nanoribbon is integrated with multiple Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next-generation transistors with low power and high performance. An associated epitaxial source or drain region may be embedded (e.g., removing a portion of the nanowire and then performing source or drain (S / D) growth).

[0108] To provide further context, advantages of a self-aligned gate end cap (SAGE) architecture can include enabling higher layout density and, in particular, scaling of diffusion-to-diffusion spacing. To provide an illustrative comparison, Figure 6 A cross-sectional view taken through nanowires and fins for a non-endcap architecture is shown in accordance with an embodiment of the present disclosure. Figure 7 A cross-sectional view taken through a nanowire and fin for a self-aligned gate end cap (SAGE) architecture is shown in accordance with an embodiment of the present disclosure.

[0109] refer to Figure 6 , the integrated circuit structure 600 includes a substrate 602 having a fin 604 protruding therefrom by an amount 606 above an isolation structure 608 that laterally surrounds a lower portion of the fin 604. The upper portion of the fin may include a local isolation structure 622 and a growth enhancement layer 620, as shown. A corresponding nanowire 605 is above the fin 604. A gate structure may be formed above the integrated circuit structure 600 to fabricate a device. However, such a discontinuity in the gate structure may be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0110] refer to Figure 6 In an embodiment, after the gate is formed, the lower portion of structure 600 may be planarized and / or etched to level 634 to leave a back surface including the gate structure and the exposed bottom surface of the epitaxial source or drain structure. It should be understood that a back (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that planarization and / or etching may reach other levels, such as 630 or 632.

[0111] In contrast, reference Figure 7, the integrated circuit structure 750 includes a substrate 752 having a fin 754 protruding from it by a certain amount 756 above an isolation structure 758 that laterally surrounds the lower portion of the fin 754. The upper portion of the fin may include a local isolation structure 772 and a growth enhancement layer 770, as shown. The corresponding nanowire 755 is above the fin 754. An isolation SAGE wall 760 (which may include a hard mask thereon as shown) is included within the isolation structure 758 and between adjacent fin 754 / nanowire 755 pairs. The distance between the isolation SAGE wall 760 and the nearest fin 754 / nanowire 755 pair defines a gate end cap spacing 762. A gate structure may be formed above the integrated circuit structure 750, between the isolation SAGE walls to manufacture a device. The interruption in this gate structure is caused by the isolation SAGE wall. Since the isolation SAGE wall 760 is self-aligned, it can minimize the limitations from conventional methods to achieve a more aggressive diffusion to diffusion spacing. Furthermore, since the gate structure includes interruptions at all locations, the various gate structure portions can be layered connected by local interconnects formed above the isolation SAGE walls 670. In an embodiment, as shown, the isolation SAGE walls 760 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion.

[0112] refer to Figure 7 In an embodiment, after the gate is formed, the lower portion of structure 700 may be planarized and / or etched to level 784 to leave a back surface including the gate structure and the exposed bottom surface of the epitaxial source or drain structure. It should be understood that a back (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that planarization and / or etching may reach other levels, such as 780 or 782.

[0113] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to account for mask misalignment. Thus, embodiments may be implemented to achieve a reduction in transistor layout area. Embodiments described herein may involve the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0114] In an embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure can be composed of one or more materials suitable for ultimately electrically isolating portions of a permanent gate structure from one another or facilitating isolation of portions of a permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material such as hafnium oxide.

[0115] It should be understood that the above integrated circuit structures can be integrated with backside exposed integrated circuit structures (such as nanowire or nanoribbon based devices). Additionally or alternatively, a combination of Figure 2A-2G To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, Fig. 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 8B Shows Fig. 8A A cross-sectional source or drain diagram of a nanowire-based integrated circuit structure taken along the a-a' axis. Figure 8C Shows Fig. 8A A cross-sectional channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0116] refer to Fig. 8A , the integrated circuit structure 800 includes one or more vertically stacked nanowires (804 groups) above a substrate 802. In an embodiment, as shown, a local isolation structure 802C, a growth enhancement layer 802B, and a lower substrate portion 802A are included in the substrate 802, as shown. For illustrative purposes, in order to emphasize the nanowire portion, the optional fins below the bottommost nanowire and formed by the substrate 802 are not shown. The embodiments herein are directed to single-wire devices and multi-wire devices. As an example, a device based on three nanowires with nanowires 804A, 804B, and 804C is shown for illustrative purposes. For ease of description, nanowire 804A is used as an example, wherein the description focuses on one of the nanowires. It should be understood that in the case of describing the properties of a nanowire, an embodiment based on multiple nanowires may have the same or substantially the same properties for each of the nanowires.

[0117] Each of the nanowires 804 includes a channel region 806 in the nanowire. The channel region 806 has a length (L). Figure 8C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig. 8A and Figure 8C, the gate electrode stack 808 surrounds the entire perimeter (Pc) of each channel region 806. The gate electrode stack 808 includes a gate electrode and a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 808 without any intermediate materials, such as the substrate material below or the channel fabrication material above. Therefore, in an embodiment with multiple nanowires 804, the channel regions 806 of the nanowires are also discrete references relative to each other. Fig. 8A and Figure 8B , the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. The pair of non-discrete source or drain regions 810 / 812 are on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. In addition, the pair of non-discrete source or drain regions 810 / 812 abut the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment not shown, the pair of non-discrete source or drain regions 810 / 812 directly vertically abut the channel region 806 because epitaxial growth is on and between the portions of the nanowires that extend beyond the channel region 806, where the nanowire ends are shown within the source or drain structure. In another embodiment, as shown Fig. 8A As shown, the pair of non-discrete source or drain regions 810 / 812 indirectly vertically adjoin the channel region 806 because they are formed at the ends of the nanowires and not between the nanowires.

[0118] In an embodiment, as shown, the source or drain regions 810 / 812 are non-discrete in that there is not a separate and discrete source or drain region for each channel region 806 of the nanowire 804. Therefore, in an embodiment having multiple nanowires 804, the source or drain region 810 / 812 of the nanowire is a global or unified source or drain region, rather than being discrete for each nanowire. That is, the non-discrete source or drain region 810 / 812 is global in the sense that a single unified feature serves as the source or drain region for multiple (3 in this case) nanowires 804, and more specifically, for more than one discrete channel region 806. In one embodiment, from a cross-sectional perspective perpendicular to the length of the discrete channel region 806, each of the pair of non-discrete source or drain regions 810 / 812 is approximately rectangular in shape with a bottom tapered portion and a top vertex portion, such as Figure 8B However, in other embodiments, the source or drain region 810 / 812 of the nanowire is a relatively large but discrete non-vertically merged epitaxial structure, such as a nub.

[0119] According to an embodiment of the present disclosure, Fig. 8A and Figure 8BAs shown, the integrated circuit structure 800 also includes a pair of contacts 814, each contact 814 being on one of the pair of non-discrete source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds the corresponding non-discrete source or drain region 810 / 812 in a vertical sense. On the other hand, the entire perimeter of the non-discrete source or drain region 810 / 812 may not be in contact with the contact 814, and the contact 814 thus only partially surrounds the non-discrete source or drain region 810 / 812, as shown in FIG. Figure 8B In a comparative embodiment not shown, the entire perimeter of the non-discrete source or drain region 810 / 812 taken along the aa′ axis is surrounded by the contact 814 .

[0120] Reference again Fig. 8A In an embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As shown, outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810 / 812, thereby providing an "embedded" portion of the non-discrete source or drain regions 810 / 812 beneath the pair of spacers 816. As also shown, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend beneath the entire pair of spacers 816.

[0121] Substrate 802 may be composed of a material suitable for integrated circuit structure manufacturing. In one embodiment, substrate 802 includes a lower bulk substrate composed of a single crystal material, which may include but is not limited to silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer composed of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is on the lower bulk substrate. Therefore, structure 800 can be manufactured from a starting insulator-on-semiconductor substrate. Alternatively, structure 800 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the above-mentioned upper insulator layer. In another alternative embodiment, structure 800 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region, such as a nanowire, thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an omega-FET type structure.

[0122] In an embodiment, the nanowire 804 may be sized as a wire or ribbon, as described below, and may have square or rounded corners. In an embodiment, the nanowire 804 is composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowire is single crystalline. For example, for silicon nanowire 804, the single crystalline nanowire may be based on a (100) global orientation, for example, having a <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of nanowire 804 are nanometer-scale when viewed from a cross-sectional perspective. For example, in a particular embodiment, the smallest dimension of nanowire 804 is less than about 20 nanometers. In an embodiment, nanowire 804 is composed of strained material, particularly in channel region 806.

[0123] refer to Figure 8C , in an embodiment, each of the channel regions 806 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel regions 806 is approximately square, or if rounded, approximately circular. On the other hand, the width and height of the channel regions need not be the same, such as in the case of the nanoribbons described throughout.

[0124] Reference again Fig. 8A , Figure 8B and Figure 8C In an embodiment, the lower portion of structure 800 may be planarized and / or etched to level 899 to leave a back surface including an exposed bottom surface of the gate structure and the epitaxial source or drain structure. It should be understood that a back (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure.

[0125] In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate structure with corresponding one or more overlying nanowire structures, and an isolation structure between the finFET or tri-gate structure and the corresponding one or more overlying nanowire structures. In some embodiments, the finFET or tri-gate structure is retained. In other embodiments, the finFET or tri-gate structure may be ultimately removed in a substrate removal process.

[0126] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktops, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0127] Fig. 9 A computing device 900 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 900 houses a board 902. The board 902 may include a plurality of components, including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, the at least one communication chip 906 is also physically and electrically coupled to the board 902. In other implementations, the communication chip 906 is part of the processor 904.

[0128] Depending on its application, the computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0129] The communication chip 906 implements wireless communication for transmitting data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data via non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not include any wires, although in some embodiments they may not. The communication chip 906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. The computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 906 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0130] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures, such as integrated circuit structures constructed according to the implementation of the embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0131] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. The integrated circuit die of the communication chip 906 may include one or more structures, such as integrated circuit structures built according to implementations of embodiments of the present disclosure.

[0132] In further implementations, another component housed within computing device 900 may include an integrated circuit die that includes one or more structures, such as integrated circuit structures built according to implementations of embodiments of the present disclosure.

[0133] In various embodiments, the computing device 900 may be a laptop computer, a netbook, a notebook, an ultrabook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video camera. In other embodiments, the computing device 900 may be any other electronic device that processes data.

[0134] Fig.10 An interposer 1000 including one or more embodiments of the present disclosure is shown. Interposer 1000 is an intermediate substrate for bridging a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1000 is to extend connections to a wider spacing or to rewire connections to different connections. For example, interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that may then be coupled to a second substrate 1004. In some embodiments, the first substrate 1002 and the second substrate 1004 are attached to opposite sides of interposer 1000. In other embodiments, the first substrate 1002 and the second substrate 1004 are attached to the same side of interposer 1000. In further embodiments, three or more substrates are interconnected through interposer 1000.

[0135] Interposer 1000 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, interposer 1000 may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0136] The interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through silicon vias (TSVs) 1012. The interposer 1000 may also include embedded devices 1014, including passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 1000 or to manufacture components included in the interposer 1000.

[0137] Thus, embodiments of the present disclosure include integrated circuit structures having internal spacer liners, and methods of fabricating integrated circuit structures having internal spacer liners.

[0138] The above description of the illustrated implementations of the embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0139] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. On the contrary, the scope of the present disclosure is determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

[0140] Example embodiment 1: An integrated circuit structure includes a stack of horizontal nanowires. A gate structure vertically surrounds the stack of horizontal nanowires, and the stack of horizontal nanowires extends laterally beyond the gate structure. An internal gate spacer is between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer pad is between the internal gate spacer and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires, and the internal spacer pad is between the internal gate spacer and the gate structure.

[0141] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the inner spacer liner comprises amorphous silicon.

[0142] Example 3: The integrated circuit structure of Example 2, wherein the amorphous silicon has less than 1E15 atoms / cm 3 of dopant concentration.

[0143] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the inner spacer liner has a thickness in the range of 0.5-2 nanometers.

[0144] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3, or 4, wherein the internal gate spacer comprises silicon and nitrogen.

[0145] Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, or 5, wherein the internal gate spacer has a thickness in the range of 1-5 nanometers.

[0146] Example Embodiment 7: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5 or 6, further comprising an epitaxial source or drain structure at an end of the stack of horizontal nanowires, the epitaxial source or drain structure contacting the internal spacer liner.

[0147] Example Embodiment 8: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, or 7, further comprising a sub-fin structure below the stack of horizontal nanowires.

[0148] Example embodiment 9: An integrated circuit structure comprising a stack of horizontal nanowires, the stack of horizontal nanowires comprising silicon. A gate structure vertically surrounds the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. A layer comprising silicon and nitrogen is between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure. A layer comprising amorphous silicon is between the layer comprising silicon and nitrogen and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires, and the layer comprising amorphous silicon is between the layer comprising silicon and nitrogen and the gate structure. An epitaxial source or drain structure is at an end of the stack of horizontal nanowires, the epitaxial source or drain structure contacting the layer comprising amorphous silicon.

[0149] Example 10: The integrated circuit structure of Example 9, wherein the layer comprising amorphous silicon has less than 1E15 atoms / cm 3 The dopant concentration is 0.5-2 nm.

[0150] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a stack of horizontal nanowires. A gate structure vertically surrounds the stack of horizontal nanowires, and the stack of horizontal nanowires extends laterally beyond the gate structure. An internal gate spacer is between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer pad is between the internal gate spacer and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires, and the internal spacer pad is between the internal gate spacer and the gate structure.

[0151] Example Embodiment 12: The computing device of Example Embodiment 11, further comprising a memory coupled to the board.

[0152] Example Embodiment 13: The computing device of Example Embodiment 11 or 12, further comprising a communication chip coupled to the board.

[0153] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a camera coupled to the board.

[0154] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13, or 14, further comprising a battery coupled to the board.

[0155] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, further comprising a speaker coupled to the board.

[0156] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a compass coupled to the board.

[0157] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a GPS coupled to the board.

[0158] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a display coupled to the board.

[0159] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: A stack of horizontal nanowires; a gate structure, the gate structure vertically surrounding the stack of horizontal nanowires, the stack of horizontal nanowires laterally extending beyond the gate structure; an internal gate spacer between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure; as well as An internal spacer liner is interposed between the internal gate spacer and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires and between the internal gate spacer and the gate structure.

2. The integrated circuit structure according to claim 1, wherein: The inner spacer liner includes amorphous silicon.

3. The integrated circuit structure according to claim 2, wherein: The amorphous silicon has less than 1E15 atoms / cm 3 of dopant concentration.

4. The integrated circuit structure according to claim 1, 2 or 3, wherein: The inner spacer liner has a thickness in the range of 0.5-2 nanometers.

5. The integrated circuit structure according to claim 1, 2 or 3, wherein: The internal gate spacer includes silicon and nitrogen.

6. The integrated circuit structure according to claim 1, 2 or 3, wherein: The internal gate spacer has a thickness in the range of 1-5 nanometers.

7. The integrated circuit structure of claim 1, 2 or 3, further comprising an epitaxial source or drain structure at an end of the stack of horizontal nanowires, the epitaxial source or drain structure contacting the internal spacer liner.

8. The integrated circuit structure of claim 1, 2 or 3, further comprising a sub-fin structure below the stack of horizontal nanowires.

9. An integrated circuit structure comprising: a stack of horizontal nanowires, the stack of horizontal nanowires comprising silicon; a gate structure, the gate structure vertically surrounding the stack of horizontal nanowires, the stack of horizontal nanowires laterally extending beyond the gate structure; a layer comprising silicon and nitrogen between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure; a layer comprising amorphous silicon, the layer comprising amorphous silicon being between the layer comprising silicon and nitrogen and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires, and the layer comprising amorphous silicon being between the layer comprising silicon and nitrogen and the gate structure; as well as An epitaxial source or drain structure is at an end of the stack of horizontal nanowires, the epitaxial source or drain structure being in contact with the layer comprising amorphous silicon.

10. The integrated circuit structure according to claim 9, wherein: The layer comprising amorphous silicon has less than 1E15 atoms / cm 3 The dopant concentration is 0.5-2 nm.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: A stack of horizontal nanowires; a gate structure, the gate structure vertically surrounding the stack of horizontal nanowires, the stack of horizontal nanowires laterally extending beyond the gate structure; internal gate spacers between vertically adjacent horizontal nanowires in the stack of horizontal nanowires and laterally adjacent to the gate structure; and An internal spacer liner is interposed between the internal gate spacer and the vertically adjacent horizontal nanowires in the stack of horizontal nanowires and between the internal gate spacer and the gate structure.

12. The computing device of claim 11, further comprising: A memory is coupled to the board.

13. The computing device according to claim 11 or 12, further comprising: A communication chip is coupled to the board.

14. The computing device according to claim 11 or 12, further comprising: A camera is coupled to the board.

15. The computing device according to claim 11 or 12, further comprising: A battery is coupled to the board.

16. The computing device of claim 11 or 12, further comprising: A speaker is coupled to the board.

17. The computing device of claim 11 or 12, further comprising: A compass is coupled to the board.

18. The computing device of claim 11 or 12, further comprising: Coupled to the board's GPS.

19. The computing device of claim 11 or 12, further comprising: A display is coupled to the panel.

20. The computing device of claim 11 or 12, wherein: The component is a packaged integrated circuit die.

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