Integrated circuit structure with backside source or drain contact differential access

Abstract

Integrated circuit structures with backside source or drain contact differential access are described. In an example, an integrated circuit structure includes a first, second, and third plurality of horizontally stacked nanowires or fins and a first, second, and third gate stack. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fins and the third plurality of horizontally stacked nanowires or fins, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth is greater than the first depth.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication and in particular integrated circuit structures with backside source or drain contact differentiated access. Background Art

[0002] Over the past several decades, the reduction in size of features in integrated circuits has been the driving force behind the evolving semiconductor industry. The reduction in size to smaller and smaller features enables an increased density of functional units on the limited available area of ​​a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, suitable for preparing products with increased capacity. However, the drive for ever-larger capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0003] The variability of conventional and currently known fabrication processes may limit the possibility of further extending them into the 10 nm node or sub-10 nm node range. Therefore, fabricating functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into or replacement of current fabrication processes.

[0004] In the manufacture of integrated circuit devices, multi-gate transistors (such as tri-gate transistors) have become more prevalent as device dimensions continue to shrink. Tri-gate transistors are generally fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-throughput bulk silicon substrate infrastructure.

[0005] However, reducing the size of multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits is reduced and as the absolute number of basic building blocks produced in a given area increases, the constraints on the semiconductor processes used to produce these building blocks have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Illustrated are cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery according to embodiments of the present disclosure.

[0007] Figures 2 to 3 The illustrations are angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a backside source or drain contact access feature in accordance with an embodiment of the present disclosure.

[0008] Figures 4 to 9Illustrations are of angled, cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having differentiated backside source or drain contact access features in accordance with an embodiment of the present disclosure.

[0009] Fig. 10A Illustrated is a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

[0010] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated.

[0011] Fig.11A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0012] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated.

[0013] FIG. 12A to FIG. 12J Cross-sectional views illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0014] Fig.13 A computing device according to one implementation of the present disclosure is illustrated.

[0015] Fig.14 An interposer including one or more embodiments of the present disclosure is illustrated.

[0016] Fig.15 is an isometric view of a mobile computing platform employing an IC made according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0017] Fig.16 Illustrated is a cross-sectional view of a flip chip mounted die according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] An integrated circuit structure with differentiated access to backside source or drain contacts is described. In the following description, a large number of specific details (such as specific integration and material rules) are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other examples, well-known features (such as integrated circuit design layouts) are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Further, it will be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0019] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other implementations. Further, it is not intended to be bound by any express or implied theory presented in the preceding technical field, background, brief summary, or the following detailed description.

[0020] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0021] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0022] “Comprising”. This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0023] "Configured to." Various units or components may be described or claimed to be "configured to" perform one or more tasks. In such contexts, "configured to" is used to mean by indicating that the unit or component includes structure that performs the one or more tasks during operation. As such, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not turned on or active). Stating that a unit or circuit or component is "configured to" perform one or more tasks is expressly not intended to invoke 35 U.S.C. §112, paragraph 6, with respect to that unit or component.

[0024] "First," "second," etc. As used herein, these terms are used as labels for the nouns that follow them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0025] "Coupled"—The following description refers to elements or nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0026] In addition, certain terms may also be used in the following description for reference purposes only, and therefore are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of a portion of a component within a consistent but arbitrary frame of reference made clear by reference to the text describing the component in question and the associated drawings. Such terminology may include the terms specifically mentioned above, their derivatives, and terms of similar meaning.

[0027] "Inhibit" - As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely and utterly prevent a result, outcome, or future state. Additionally, "inhibit" may also refer to a reduction or lessening of an outcome, manifestation, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit an outcome or state, it need not completely prevent or eliminate the outcome or state.

[0028] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally encompasses everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0029] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Contacts (pads), interconnect wiring, vias, and dielectric structures are formed in the BEOL portion of the fabrication phase. For modern IC processing, more than 10 metal layers may be added in the BEOL.

[0030] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although the exemplary processing schemes may be illustrated using FEOL processing scenarios, such methods may also be applicable to BEOL processing. Likewise, although the exemplary processing schemes may be illustrated using BEOL processing scenarios, such methods may also be applicable to FEOL processing.

[0031] One or more embodiments are directed to forming self-aligned access features for backside source or drain contact structures (e.g., for backside epitaxial (epi) contacts). One or more embodiments are directed to self-aligned backside access features. One or more embodiments are directed to differentiated backside access features, where deeper features can ultimately be accessed while shallower features are not accessed and effectively become dummy features, which can be referred to as mirror images (such as titanium nitride (TiN)). One or more embodiments described herein are directed to all-around gate integrated circuit structures prepared using differentiated backside access features. It will be appreciated that, unless otherwise indicated, references herein to nanowires may indicate nanowires or nanoribbons or nanosheets or fork sheets. One or more embodiments described herein are directed to fin-based integrated circuit structures prepared using differentiated backside access features using a backside hard mask.

[0032] To provide context, low-resistance power delivery solutions are needed as shrinking semiconductor size continues to stress interconnects into increasingly compact spaces. Backside power delivery—a scheme in which the power delivery interconnect network connects directly to transistors from the backside of the wafer rather than sharing space with frontside routing—is a possible solution for future semiconductor technology generations.

[0033] Traditionally, power is delivered from the front side interconnect. At the standard cell level, power can be delivered just on top of the transistor or from the top and bottom cell boundaries. The power delivered from the top and bottom cell boundaries enables a relatively short standard cell height with a slightly higher power network resistance. However, the front side power network shares the interconnect stack with the signal routing, and reduces the signal routing track. In addition, for high-performance designs, the top and bottom cell boundary power metal wiring must be wide enough to reduce the power network resistance and improve performance. This usually causes the cell height to increase. According to one or more embodiments of the present disclosure, it is possible to deliver power from the back side of the wafer or substrate to solve area and performance problems. At the cell level, the wider metal 0 power at the top and bottom cell boundaries may no longer be needed, and the cell height can therefore be reduced. In addition, the power network resistance can be significantly reduced, resulting in performance improvements. At the block and chip levels, the front side signal routing track increases due to the removed power routing, and the power network resistance is significantly reduced due to very wide wiring, large vias, and reduced interconnect layers.

[0034] In earlier technologies, the power delivery network from bumps to transistors requires significant block resources. Such resource usage on the metal stack manifests itself in some process nodes as a standard cell architecture with layout version control or cell placement restrictions at the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows free-slip cell placement in a block without power delivery complexity and placement-related delay timing variations.

[0035] As an illustrative comparison, Figure 1 Illustrated are cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery according to embodiments of the present disclosure.

[0036] Reference Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0037] Refer again Figure 1, an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160 and a device contact 162, and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A, a conductive line 166A, and a metal bump 168A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168B. It will be appreciated that the backside power approach can also be implemented for structures including semiconductor fins.

[0038] To provide further context, a fundamental component of a backside power delivery network is an electrical functional feature that interfaces the source or drain contact of a transistor to the backside interconnect network. Therefore, there is a need for designs and methods for making interface features that are compatible with existing library cell design conventions and transistor contact processing flows.

[0039] Since backside power delivery has not yet been introduced in high volume manufacturing, there is currently no solution to adopt in high volume manufacturing. Approaches may ultimately include deep trench contacts (TCN), direct source-drain contacts from the backside, or replacement of gate contact tracks with backside power contacts. Depending on the proposed solution, the solution may suffer from high resistance contacts, negating the inherent value of backside power delivery co-optimization with front-end transistor processing, resulting in defects and performance risks and compromises.

[0040] In the first aspect, for comparison purposes, non-differentiated backside access features are described.

[0041] As an exemplary treatment scheme, Figures 2 to 3 Angled cross-sectional views showing various operations in a method of preparing an integrated circuit structure with backside source or drain contact access features in accordance with an embodiment of the present disclosure are illustrated. It will be appreciated that the described and illustrated embodiments may also be applicable to fin structures, replacing stacks of nanowires or nanoribbons or nanosheets or fork sheets.

[0042] Reference Figure 2, the starting structure 200 includes a plurality of horizontally stacked nanowires (or nanoribbons or nanosheets or forks, or alternatively, fins) 202, each of which is above a corresponding sub-fin 204 on a substrate 201, such as a silicon nanowire above a silicon sub-fin on a silicon substrate. A corresponding gate stack 206 (such as a stack including a metal gate electrode and a high-k gate dielectric layer) is above and around each of the plurality of horizontally stacked nanowires 202. Alternatively, at this stage, the gate stack 206 may be a dummy gate stack. A dielectric gate capping layer 207 (such as a silicon nitride capping) may be included on each gate stack 206. Dielectric sidewall spacers 208 (such as silicon nitride or carbon-doped silicon nitride spacers) are along the sides of each gate stack 206 and may be retained above each gate stack 206 by various processing operations (along with an optional cap layer). A shallow trench isolation structure 210 (such as a silicon oxide isolation structure) is adjacent to the sub-fin 204. The cavity 212 is located between the gate stacks in the locations where the source or drain structures will eventually be formed. The gate stack 206 can be used as a mask to etch trenches into the exposed portions of the fins (e.g., forming the nanowires of the fins), such as into the source and drain regions of the fins, forming the depicted structure with the cavity 212. In one embodiment, the etching extends at least partially into the sub-fin 204 or even completely through the sub-fin 204.

[0043] Reference Figure 3 , the etch extends under the source or drain locations for eventual backside contact formation. For example, the etch extends in the source or drain locations, and then first conductive source or drain contacts 214 (e.g., titanium nitride or tungsten placeholders or dummy structures) are formed in these locations, for example, by a deposition and etch-back process.

[0044] In preparation Figure 3 After the structure is formed, an epitaxial source or drain structure is formed, front side processing is completed, the structure is inverted, and a back side reveal is performed to expose the first conductive source or drain contact 214. The first conductive source or drain contacts 214 can be removed and permanent contacts (such as tungsten or cobalt contacts) are formed in their place for contacting the back side metallization.

[0045] In the second aspect, for comparison purposes, differentiated backside access features are described.

[0046] As an exemplary treatment scheme, Figures 4 to 9 Angled cross-sectional views showing various operations in a method of preparing an integrated circuit structure with differentiated backside source or drain contact access features in accordance with an embodiment of the present disclosure are illustrated. It will be appreciated that the described and illustrated embodiments may also be applicable to fin structures, replacing stacks of nanowires or nanoribbons or nanosheets or fork sheets.

[0047] Reference Figure 4 , the starting structure 400 includes a sub-fin structure 404 protruding from a substrate 402, such as a silicon sub-fin structure protruding from a silicon substrate. An isolation structure 406 (such as a silicon oxide or silicon dioxide shallow trench isolation structure) separates the sub-fin structures along the gate line direction. Fins 408 (such as fins of alternating stacks of silicon nanowires 410 and silicon germanium release layers 412) are located above corresponding sub-fin structures in the sub-fin structures 404. A channel capping layer 415 (such as a silicon nitride channel cap) is located above the fins 408. Dummy gate structures (such as polysilicon 416 and silicon nitride 418 dummy gate structures (and possibly, dummy gate oxide 414)) extend above the fins 408. Gate spacers 420 (such as silicon nitride gate spacers) are located above and along the sides of the dummy gate structures. At this stage, a protective cap layer 422 (such as a titanium cap) is on top of the gate spacer 420 as an artifact from an etching process used to etch the fin 408 in a location between the gate structures (e.g., for eventual source or drain formation). In an embodiment, the etching process extends deeper than the formed fin 408, and deep trenches 424 are etched into the sub-fin 404, as depicted.

[0048] Reference Figure 5 Using lithographic patterning and then continuing the etching process, select trenches in the deep trenches 424 are extended to form deeper trenches 426. The etching process may be referred to as a non-selective self-aligned etch because deep trenches are formed in all locations.

[0049] Reference Figure 6 , a contact placeholder material such as titanium nitride is formed in deep trench 424 and deeper trench 426, and etched back to form contact placeholder 430 and dummy contact placeholder 428. In an embodiment, contact placeholder 430 is ultimately accessed from the back side, while dummy contact placeholder 428 is not.

[0050] Reference Figure 7 , release layer 412 is recessed in the lateral direction relative to nanowire 410 to form recessed release layer 412A. Internal spacer material 432 (such as silicon nitride internal spacer material) is formed in the recess formed by recessed release layer 412A and on contact placeholder 430 and dummy contact placeholder 428 to form structure 700.

[0051] Reference Figure 8 , Figure 7The structure 700 is exposed to an epitaxial source or drain growth process, a replacement gate and nanowire release process, an inversion, and a backside reveal process. The resulting structure includes a frontside protective dielectric layer 802, a metal gate electrode 804, a high-k gate dielectric 806, a gate cap (such as silicon nitride) 808, an epitaxial source or drain structure (such as epitaxial silicon or epitaxial silicon germanium) 812 (which may be formed by patterning the internal spacer material 432 to form a placeholder cap 432A and an internal spacer 432B), a frontside trench contact 814, a dielectric sub-fin structure 816 (e.g., a replacement from a silicon sub-fin), and a dielectric gate cut insert 818. The contact placeholder 430 is backside revealed to form a planarized contact placeholder 430A. The dummy contact placeholder 428 is not revealed.

[0052] Reference Fig. 9 , the contact placeholders 430 and placeholder caps 432A are removed and replaced with permanent backside contacts 902, such as cobalt or tungsten contacts, to form structure 900. The permanent backside contacts 902 contact the corresponding source or drain structures 812A in the source or drain structures 812. The dummy contact placeholders 428 that are not selected for backside contact remain with the corresponding source or drain structures in the source or drain structures 812. In an embodiment, the permanent backside contacts 902 may ultimately be coupled to one or more backside metallization lines or layers.

[0053] Refer again Figures 4 to 9 (and especially with reference to the reverse Fig. 9), according to an embodiment of the present disclosure, the integrated circuit structure 900 includes a first plurality of horizontally stacked nanowires or fins 412, which are laterally spaced apart from a second plurality of horizontally stacked nanowires or fins 412, and the second plurality of horizontally stacked nanowires or fins 412 are laterally spaced apart from a third plurality of horizontally stacked nanowires or fins 412. A first gate stack 804 / 806 is above the first plurality of horizontally stacked nanowires or fins 412, a second gate stack 804 / 806 is above the second plurality of horizontally stacked nanowires or fins 412, and a third gate stack 804 / 806 is above the third plurality of horizontally stacked nanowires or fins 412. A first epitaxial source or drain structure 812 is between the first plurality of horizontally stacked nanowires or fins 412 and the second plurality of horizontally stacked nanowires or fins 412, and the first epitaxial source or drain structure 812 is above a first conductive material 428 having a first depth below the first epitaxial source or drain structure 812. The second epitaxial source or drain structure 812A is located between the second plurality of horizontally stacked nanowires or fins 412 and the third plurality of horizontally stacked nanowires or fins 412, and the second epitaxial source or drain structure 812A is located above a second conductive material 902 having a second depth below the second epitaxial source or drain structure 812A, and the second depth is greater than the first depth.

[0054] In an embodiment, the first conductive material and the second conductive material have different compositions. In an embodiment, the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

[0055] In an embodiment, a dielectric spacer cap is between the first epitaxial source or drain structure 812 and the first conductive material 428, as depicted. In an embodiment, the second conductive material 902 is in direct contact with the second epitaxial source or drain structure 812A, as depicted.

[0056] It will be appreciated that the differentiation methods described above may be detectable in the final product. Cross-sections may show unconnected or short contact "placeholders". It will be appreciated that even though the above figures show transistors based on all-around gates, embodiments may be applied to channels of any shape or material (fins, nanowires, nanoribbons, nanocombs / forks, etc.). It will be appreciated that even though the figures show a single layer of transistors, embodiments may be applied to multi-layer transistor architectures.

[0057] It will be appreciated that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon sub-fins, silicon nanowires, silicon nanoribbons, or silicon fins. As used throughout the text, a silicon layer or structure may be used to describe a silicon material composed of a very substantial amount of (if not all) silicon. However, it will be appreciated that, in practice, 100% pure Si may be difficult to form, and therefore may include a very small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during the deposition of Si, or may "contaminate" Si during diffusion during post-deposition processing. As such, the embodiments described herein for a silicon layer or structure may include a silicon layer or structure containing a relatively small amount (e.g., "impurity" level) of non-Si atoms or substances (such as Ge, C, or Sn). It will be appreciated that a silicon layer or structure as described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0058] It will be appreciated that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon germanium sub-fins, silicon germanium nanowires, silicon germanium nanoribbons, or silicon germanium fins. As used throughout, a silicon germanium layer or structure may be used to describe a silicon germanium material composed of a substantial portion of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon germanium layer or structure includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer or structure includes approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30 ). It will be appreciated that, in practice, 100% pure silicon germanium (generally referred to as SiGe) may be difficult to form, and therefore may include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during deposition of SiGe, or may "contaminate" SiGe when diffused during post-deposition processing. As such, embodiments described herein for silicon germanium layers or structures may include silicon germanium layers or structures that include relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (such as carbon or tin). It will be appreciated that the silicon germanium layers or structures described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0059] In another aspect, it will be appreciated that the backside source or drain contact differential access can be implemented using the frontside architecture. In one example, the backside source or drain contact differential access can be implemented using the contact (COAG) structure and processing over the active gate. It will also be appreciated that the following "color" hard mask COAG features can be applicable to the concept of the backside contact described above. One or more embodiments of the present disclosure are directed to the following semiconductor structure or device: it has one or more gate contact structures (e.g., as gate contact vias) disposed above the active portion of the gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure are directed to a method for preparing the following semiconductor structure or device: the semiconductor structure or device has one or more gate contact structures formed above the active portion of the gate electrode of the semiconductor structure or device. The method described herein can be used to reduce the standard cell area by enabling the formation of gate contacts over the active gate region. According to one or more embodiments, a tapered gate and trench contact is implemented to enable COAG preparation. The embodiment can be implemented to enable patterning with a tight pitch.

[0060] To provide further context for the importance of the COAG processing scheme, in a technology where space and layout constraints are somewhat relaxed compared to current generation space and layout constraints, contacts to the gate structure can be made by making contacts to the portion of the gate electrode that is disposed over the isolation region. As an example, Fig. 10A Illustrated is a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

[0061] Reference Fig. 10A, semiconductor structure or device 1000A includes a diffusion or active region 1004, which is disposed in substrate 1002 and within isolation region 1006. One or more gate lines (also referred to as multi-lines) such as gate lines 1008A, 1008B and 1008C are disposed above diffusion or active region 1004 and above a portion of isolation region 1006. Source or drain contacts (also referred to as trench contacts) such as contacts 1010A and 1010B are disposed above source and drain regions of semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contacts for trench contacts 1010A and 1010B, respectively. Separated gate contacts 1014 and overlying gate contact vias 1016 provide contacts for gate line 1008B. In contrast to the source trench contact 1010A or the drain trench contact 1010B, from a plan view perspective, the gate contact 1014 is disposed over the isolation region 1006, rather than over the diffusion or active region 1004. Furthermore, neither the gate contact 1014 nor the gate contact via 1016 is disposed between the source trench contact 1010A and the drain trench contact 1010B.

[0062] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is illustrated. Fig. 10B , semiconductor structure or device 1000B (eg, Fig. 10A 100A) includes a non-planar diffusion or active region 1004B (e.g., a fin structure) formed from substrate 1002 and within isolation region 1006. Gate line 1008B is disposed over non-planar diffusion or active region 1004B and over a portion of isolation region 1006. As shown, gate line 1008B includes gate electrode 1050 and gate dielectric layer 1052, along with a dielectric capping layer 1054. Also seen from this angle are gate contact 1014 and overlying gate contact via 1016, along with overlying metal interconnect 1060, all of which are disposed in an interlayer dielectric stack or layer 1070. From the perspective of FIG. Fig. 10B It is also seen from the perspective of FIG. 1 that the gate contact 1014 is disposed over the isolation region 1006 rather than over the non-planar diffusion or active region 1004B.

[0063] Refer again Fig. 10A and Fig. 10B, the arrangement of semiconductor structures or devices 1000A and 1000B respectively places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area will either require an extremely tight registration budget, or the gate size will have to be increased to provide sufficient space to lay out the gate contact. Further, historically, contacts to the gate above the diffusion region have been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the active area below. One or more embodiments described herein solve the above problems by providing a feasible method and resulting structure for preparing a contact structure that contacts a portion of a gate electrode formed above a diffusion or active area.

[0064] As an example, Fig.11A FIG. 1 is a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Fig.11A , semiconductor structure or device 1100A includes a diffusion or active region 1104, which is disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines such as gate lines 1108A, 1108B, and 1108C are disposed over the diffusion or active region 1104 and over a portion of the isolation region 1106. Source or drain trench contacts such as trench contacts 1110A and 1110B are disposed over the source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to trench contacts 1110A and 1110B, respectively. A gate contact via 1116 without an intermediate separated gate contact layer provides contact to gate line 1108B. Fig. 10A In contrast, from a plan view perspective, the gate contact 1116 is disposed over the diffusion or active region 1104 and between the source contact 1110A and the drain contact 1110B.

[0065] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is illustrated. Fig. 11B , semiconductor structure or device 1100B (eg, Fig.11A110A) includes a non-planar diffusion or active region 1104B (e.g., a fin structure) formed from a substrate 1102 and within an isolation region 1106. A gate line 1108B is disposed over the non-planar diffusion or active region 1104B and over a portion of the isolation region 1106. As shown, the gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152, along with a dielectric capping layer 1154. The gate contact via 1014 is also seen from this angle, along with the overlying metal interconnect 1160, both of which are disposed in an interlayer dielectric stack or layer 1170. From Fig. 11B It is also seen from the perspective that the gate contact via 1116 is disposed above the non-planar diffusion or active area 1104B.

[0066] Therefore, refer again to Fig.11A and Fig. 11B In an embodiment, the trench contact vias 1112A, 1112B and the gate contact via 1116 are formed in the same layer and are essentially coplanar. Fig. 10A and Fig. 10B In contrast, the contact for the gate line will additionally include an additional gate contact layer, which may, for example, run perpendicular to the corresponding gate line. Fig.11A and Fig. 11B In the (multiple) structures described in association, the preparation of structures 1100A and 1100B accordingly enables the contact to be laid out directly from the metal interconnect layer on the active gate portion without shorting to the adjacent source drain region. In an embodiment, such an arrangement provides a large area reduction in the circuit layout by eliminating the need to extend the transistor gate on the isolation to form a reliable contact. As used throughout the text, reference to the active portion of the gate refers to that portion of the gate line or structure that is disposed above the active or diffusion region of the substrate below (from a plan view angle). In an embodiment, reference to the non-active portion of the gate refers to that portion of the gate line or structure that is disposed above the isolation region of the substrate below (from a plan view angle).

[0067] In an embodiment, the semiconductor structure or device 1100 is a non-planar device (such as, but not limited to, a fin-FET or a tri-gate device). In such an embodiment, the corresponding semiconductor channel region is composed of or formed by a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 1108A and 1108B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made into a discrete three-dimensional body such as in a full-surround gate device. In one such embodiment, the gate electrode stacks of gate lines 1108A and 1108B each completely surround the channel region.

[0068] Generally, one or more embodiments are directed to methods for disposing gate contact vias directly on the gate of an active transistor and structures formed thereby. Such methods can eliminate the need to extend gate lines on isolation for contact purposes. Such methods can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from a gate line or structure. In an embodiment, the above features are eliminated by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric materials (e.g., trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric capping layer having different etching characteristics from the gate dielectric material capping layer used for trench contact alignment in a gate alignment contact process (GAP) process scheme (e.g., using a gate insulation layer (GILA)).

[0069] As an exemplary preparation scheme, the starting structure includes one or more gate stack structures disposed on a substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact (e.g., a contact for a diffusion region of a substrate or for an epitaxial region formed in a substrate) is separated from the gate stack structure by a dielectric spacer. An insulating capping layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact blocking region or "contact insert" that may be prepared from an interlayer dielectric material is included in the region where contact formation is to be blocked.

[0070] In an embodiment, the contact pattern is essentially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with extremely tight registration budgets. In one such embodiment, this method enables the use of inherently highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas phase isotropic etching (e.g., in contrast to classical dry or plasma etching)) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact insert lithography operation. In one such embodiment, the method enables the elimination of the need for lithography operations that are otherwise critical for generating contact patterns as used in other methods. This also allows perfect or near-perfect self-alignment with greater edge placement error tolerance. In an embodiment, the groove contact grid is not patterned separately, but instead is formed between multiple (gate) lines. For example, in one such embodiment, the groove contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0071] Further, the gate stack structure can be prepared by replacing the gate process. In such a scheme, the dummy gate material (such as polysilicon or silicon nitride column material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to being brought from an earlier process. In an embodiment, the dummy gate is removed by dry etching or wet etching. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0072] In an embodiment, one or more of the methods described herein inherently contemplates dummy and replacement gate processing in combination with dummy and replacement contact processing. In one such embodiment, the replacement contact processing is performed after the replacement gate processing to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure, such as after the gate dielectric layer is formed, is performed at a temperature above approximately 600 degrees Celsius. The annealing is performed prior to the formation of the permanent contacts.

[0073] Next, the trench contact may be recessed to provide a recessed trench contact having a height below the top surface of the adjacent spacer. An insulating capping layer (e.g., TILA) is then formed on the recessed trench contact. According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact is composed of a material having different etching characteristics than the insulating capping layer on the gate stack structure.

[0074] The trench contact can be recessed by a process that is selective to the materials of the spacer and the gate insulating capping layer. For example, in one embodiment, the trench contact is recessed by an etching process (such as a wet etching process or a dry etching process). The trench contact insulating capping layer can be formed by a process suitable for providing a conformal and sealing layer over the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating capping layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example, by chemical mechanical polishing (CMP), to provide the trench contact insulating capping layer material only over the recessed trench contact.

[0075] Regarding suitable material combinations for the gate or trench contact insulating capping layer, in one embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon oxide, and the other consists of silicon nitride. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon oxide, and the other consists of carbon-doped silicon nitride. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon oxide, and the other consists of silicon carbide. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon nitride, and the other consists of carbon-doped silicon nitride. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon nitride, and the other consists of silicon carbide. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of silicon nitride, and the other consists of silicon carbide. In another embodiment, one of a pair of gates for trench contact insulating capping materials consists of carbon-doped silicon nitride, and the other consists of silicon carbide.

[0076] In another aspect, a nanowire or nanoribbon structure is used to achieve differentiated access to back-side source or drain contacts. In a specific example, a nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process is described below. Additionally, in yet another aspect, due to patterning complexity, the reduction in back-end (BE) interconnect size may result in lower performance and higher manufacturing costs. The embodiments described herein can be implemented to enable front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wider interconnect spacing. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to enable robust functionality of reduced-size nanowire or nanoribbon transistors with low power and high performance.

[0077] One or more embodiments described herein are for directional bi-epitaxial (EPI) connections of nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is prepared by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0078] As an exemplary process flow for preparing another all-around gate device, FIG. 12A to FIG. 12J Cross-sectional views illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0079] Reference Fig. 12A, a method of making an integrated circuit structure includes forming a starting stack that includes alternating sacrificial layers 1204 and nanowires 1206 on top of fins 1202 (such as silicon fins). The nanowires 1206 may be referred to as a vertical arrangement of nanowires. A protective cap 1208 may be formed on top of the alternating sacrificial layers 1204 and nanowires 1206, as depicted. A relaxed buffer layer 1252 and a defect correction layer 1250 may be formed below the alternating sacrificial layers 1204 and nanowires 1206, also as depicted.

[0080] Reference Fig. 12B , a gate stack 1210 is formed above the vertical arrangement of horizontal nanowires 1206. The vertical arrangement of the horizontal nanowires 1206 is then released by removing portions of the sacrificial layer 1204 to provide a recessed sacrificial layer 1204' and a cavity 1212, as in Fig. 12C As depicted in .

[0081] You will understand that Fig. 12C The structure may be fabricated without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without the asymmetric contact processing), in an embodiment, the fabrication process involves using a processing scheme that provides a fully-around-gate integrated circuit structure having an epitaxial block (which may be a vertically discrete source or drain structure).

[0082] Reference Fig.12D , an upper gate spacer 1214 is formed at the sidewalls of the gate structure 1210. A cavity spacer 1216 is formed in the cavity 1212 below the upper gate spacer 1214. A deep trench contact etch is then optionally performed to form a trench 1218 and form a recessed nanowire 1206'. A patterned relaxed buffer layer 1252' and a patterned defect correction layer 1250' may also be present, as depicted.

[0083] Sacrificial material 1220 is then formed in trench 1218, as in Fig.12E In other processing schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0084] Reference Fig.12F , a first epitaxial source or drain structure (e.g., left-hand feature 1222) is formed at a first end of the vertical arrangement of horizontal nanowire 1206'. A second epitaxial source or drain structure (e.g., right-hand feature 1222) is formed at a second end of the vertical arrangement of horizontal nanowire 1206'. In an embodiment, as depicted, epitaxial source or drain structure 1222 is a vertically discrete source or drain structure and may be referred to as an epitaxial block.

[0085] An interlayer dielectric (ILD) material 1224 is then formed at each side of the gate electrode 1210 and the adjacent source or drain structure 1222, such as in Figure 12G As depicted in . Fig.12H , a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, as in Fig.12I The sacrificial material 1220 is then removed from one of the source drain locations (eg, the right hand side) to form trench 1232 , but is not removed from the other of the source drain locations to form trench 1230 .

[0086] Reference Fig.12J , forming a first conductive contact structure 1234 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 1222). Forming a second conductive contact structure 1236 coupled to the second epitaxial source or drain structure (e.g., right-hand feature 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In an embodiment, although in Fig.12J 1202, but the method further includes: forming an exposed surface of a second conductive contact structure 1236 at the bottom of the fin 1202. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples may include Ti, Ni, Co (for the former and W, Ru, Co (for the latter)).

[0087] In an embodiment, the second conductive contact structure 1236 is deeper along the fin 1202 than the first conductive contact structure 1234, as depicted. In one such embodiment, the first conductive contact structure 1234 is not along the fin 1202, as depicted. In another such embodiment not depicted, the first conductive contact structure 1234 is partially along the fin 1202.

[0088] In an embodiment, the second conductive contact structure 1236 is along the entire fin 1202. In an embodiment, although not depicted, the second conductive contact structure 1236 has an exposed surface at the bottom of the fin 1202 in case the bottom of the fin 1202 is exposed by the backside substrate removal process.

[0089] In another aspect, in order to enable access to two conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be prepared using the backside development of the front side structure preparation method. In some exemplary embodiments, the development of the back side of the transistor or other device structure requires wafer-level backside processing. In contrast to conventional TSV type technology, the development of the back side of the transistor described herein can be performed at the density of the device unit and even in a sub-area of ​​the device. Further, such development of the back side of the transistor can be performed to substantially remove all of the donor substrate on which the device layer is disposed during the front side device processing. As such, micron-deep TSVs become unnecessary in the case where the thickness of the semiconductor in the device unit may be only tens or hundreds of nanometers after the development of the back side of the transistor.

[0090] The visualization techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer employed in front-side fabrication, visualized from the backside, and employed again in back-side fabrication. Processing both the front side and the visualized back side of the device structure can address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0091] A method of transistor backside development can be employed to, for example, remove at least a portion of a carrier layer and an intermediate layer of a donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is etched by polishing (e.g., CMP) and / or etching using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be employed. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be employed. Likewise, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be employed.

[0092] In some embodiments, prior to the above, the carrier layer is split along a fracture plane substantially parallel to the intermediate layer. This splitting or fracture process can be used to remove a substantial portion of the carrier layer as a bulk mass, reducing the polishing or etching time required to remove the carrier layer. For example, in the case where the carrier layer is 400-900 μm in thickness, 100-700 μm can be split off by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted into the carrier layer at a uniform target depth at which the fracture plane is desired. After such a splitting process, the thickness of the carrier layer retained in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0093] Next, the exposure of the intermediate layer is detected. The detection is used to identify the time point at which the back surface of the donor substrate has advanced to the vicinity of the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in the light absorption or emission of the back surface of the donor substrate during the polishing or etching performed. In some other embodiments, the endpoint criteria are associated with changes in the light absorption or emission of the byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed as a function of the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the substance in the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the process can be sampled by a quadrupole mass analyzer, and the changes in the mass of the substance can be related to the different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0094] In the case where the removal process is selective to the carrier layer relative to the intermediate layer, detection of the intermediate layer can be enhanced because non-uniformities in the carrier removal process can be mitigated by the difference in etching rates between the carrier layer and the intermediate layer. If the grinding, polishing and / or etching operation removes the intermediate layer at a rate sufficiently lower than the rate at which the carrier layer is removed, detection can even be skipped. If an endpoint criterion is not adopted, then if the thickness of the intermediate layer is sufficient for the selectivity of the etching, the grinding, polishing and / or etching operation can be stopped on the intermediate layer material for a predetermined fixed duration. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or greater.

[0095] When exposing the intermediate layer, at least a portion of the intermediate layer may be removed. For example, one or more component layers of the intermediate layer may be removed. For example, the thickness of the intermediate layer may be uniformly removed by polishing. Alternatively, the thickness of the intermediate layer may be removed using a masking or blanket etching process. The process may employ the same polishing or etching process employed for thinning the carrier, or may be a different process with different process parameters. For example, in the case where the intermediate layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that facilitates the removal of the intermediate layer over the removal of the device layer. In the case where the thickness of the intermediate layer is to be removed to a value less than a few hundred nanometers, the removal process may be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than that employed for the removal of the carrier layer. For example, the CMP process employed may employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intermediate layer as electrical isolation between adjacent device regions, for example.

[0096] For embodiments in which the device layer is revealed by completely removing the intermediate layer, the backside processing can begin on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and the device region previously prepared in the device layer (such as a source or drain region).

[0097] In some embodiments where wet and / or plasma etching is used to recess the backside of a carrier layer, an intermediate layer, or a device layer, such etching may be a patterned etch that imparts significant non-planarity or topography into the backside surface of the device layer or an etch that is selective in the material. As further described below, the patterning may be within a device cell (i.e., "intra-cell" patterning) or may be across a device cell (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the backside device layer. Thus, the masked etching process may serve as the beginning of a correspondingly masked device layer etch.

[0098] The processing scheme described above can result in a donor-host substrate assembly including an IC device that reveals the backside of an intermediate layer, the backside of a device layer, and / or the backside of one or more semiconductor regions within a device layer, and / or the frontside metallization. Additional backside processing of any of these revealed regions can then be performed during downstream processing.

[0099] As described throughout this application, the substrate can be composed of a semiconductor material that can withstand manufacturing processing and in which charge can migrate. In an embodiment, the substrate is described herein as a bulk substrate, consisting of a crystalline silicon, silicon / germanium or germanium layer, doped with charge carriers (such as but not limited to phosphorus, arsenic, boron or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). The bulk substrate can alternatively be composed of III-V materials. In an embodiment, the bulk substrate is composed of III-V materials (such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenic, aluminum gallium arsenic, indium gallium phosphorus or a combination thereof). In one embodiment, the bulk substrate is composed of III-V materials, and the charge carrier dopant impurity atoms are atoms such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0100] As described throughout this application, the isolation region (such as a shallow trench isolation region or a sub-fin isolation region) can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a portion of the permanent gate structure from the underlying bulk substrate, or suitable for isolating an active region (such as an isolation fin active region) formed in the underlying bulk substrate. For example, in one embodiment, the isolation region is composed of one or more layers of a dielectric material (such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof).

[0101] As described throughout the present application, the gate line or gate structure may be composed of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of the following materials, such as but not limited to hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Further, a portion of the gate dielectric layer may include a layer of a native oxide formed by the top layers of the semiconductor substrate. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, the portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0102] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed on a metal work function setting layer. Depending on whether the transistor is to be a PMOS or NMOS transistor, the gate electrode layer can be composed of a P-type work function metal or an N-type work function metal. In some implementations, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for gate electrodes include but are not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may be composed of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including a sidewall portion substantially perpendicular to the top surface of the substrate. In a further implementation of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0103] As described throughout this application, spacers associated with gate lines or electrode stacks may be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from an adjacent conductive contact (such as a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0104] In an embodiment, as used throughout this description, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0105] In an embodiment, as used throughout this description, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are the use of copper lines and structures, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers including a conductive liner layer and a filling layer. Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form an interconnect. In an embodiment, the interconnect is composed of a conductive material (such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof). Interconnects are sometimes also referred to as traces, wiring, wires, metals, or simply interconnects in the art.

[0106] In an embodiment, as also used throughout this description, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide or both or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material comprises a metallic substance. For example, the hard mask or other overlying material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the specific implementation. The hard mask layer may be formed by CVD, PVD, or by other deposition methods.

[0107] In an embodiment, the lithographic operation is performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, as used throughout this description. Positive or negative resists may be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topographic mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topographic mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0108] In an embodiment, the method described herein may involve forming a contact pattern that is very well aligned with an existing gate pattern while eliminating the use of a lithography operation with an extremely tight registration budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., in contrast to a dry or plasma etch) to generate a contact opening. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact insert lithography operation. In one such embodiment, the method enables the elimination of the need for a lithography operation that is otherwise essential for generating a contact pattern as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but is instead formed between multiple (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0109] Further, the gate stack structure can be prepared by replacing the gate process. In such a scheme, the dummy gate material (such as polysilicon or silicon nitride column material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to being brought from an earlier process. In an embodiment, the dummy gate is removed by dry etching or wet etching. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0110] In an embodiment, one or more of the methods described herein essentially contemplates dummy and replacement gate processing in combination with dummy and replacement contact processing to obtain a structure. In one such embodiment, the replacement contact processing is performed after the replacement gate processing to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure, such as after the gate dielectric layer is formed, is performed at a temperature above approximately 600 degrees Celsius. The annealing is performed prior to the formation of the permanent contacts.

[0111] In some embodiments, the arrangement of the semiconductor structure or device places the gate contact above a portion of the gate line or places the gate stack above the isolation region. However, such an arrangement can be regarded as an inefficient use of the layout space. In another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active area. In general, before forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via (for example, in addition to forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via), one or more embodiments of the present disclosure include first using a trench contact process aligned with the gate. Such a process can be implemented to form a trench contact structure for semiconductor structure preparation (for example, for integrated circuit preparation). In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, other methods typically involve additional lithographic processing, in which the lithographic contact pattern is closely aligned with the existing gate pattern in combination with selective contact etching. For example, additional processing may include patterning of a multi-(gate) grid with separate patterning of contact features.

[0112] It will be appreciated that the pitch division process and patterning scheme may be implemented to enable the embodiments described herein, or may be included as part of the embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering, etc. The pitch division scheme may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. The pitch division process is then implemented as a technique for increasing line density.

[0113] In an embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a close-pitch grid structure. In one such embodiment, the close pitch is not directly achievable by the selected lithography. For example, a pattern based on the selected lithography can be first formed, but the pitch can be halved by patterning using a spacer mask, as known in the art. Even further, the original pitch can be quartered by a second round of spacer mask patterning. Therefore, the grid-like pattern described herein can have metal lines, ILD lines, or hard mask lines that are spaced apart at substantially uniform pitches and have substantially uniform widths. For example, in some embodiments, the pitch variation will be within ten percent, and the width variation will be within ten percent, and in some embodiments, the pitch variation will be within five percent, and the width variation will be within five percent. The pattern can be prepared by halving the pitch or quartering the pitch or other pitch division methods. In an embodiment, the grid is not necessarily a single pitch.

[0114] In an embodiment, the blanket film is patterned using lithography and etching processes, which may involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It will be appreciated that other pitch division methods may also be implemented. In any case, in an embodiment, a gridded layout may be prepared by a selected lithography method such as 193nm immersion lithography (193i). Pitch division may be implemented to increase the line density in the gridded layout to n times. A gridded layout formed using 193i lithography plus pitch division performed at 'n' times may be designated as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling may be extended to many generations with cost-effective pitch division.

[0115] It will also be appreciated that not all aspects of the processing described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a dummy gate is never formed before a gate contact is prepared over the active portion of the gate stack. The gate stack described above may actually be a permanent gate stack as initially formed. In addition, the processing described herein may be used to prepare one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, a FIN-FET, a nanowire, or a nanobelt. One or more embodiments may be particularly useful for preparing semiconductor devices at a 10 nanometer (10nm) technology node or a sub-10 nanometer (10nm) technology node.

[0116] Additional or intermediate operations for FEOL layer or structure preparation may include standard microelectronic preparation processes such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other actions associated with microelectronic component preparation. In addition, it will be appreciated that the processing operations described with respect to the foregoing process flows may be practiced in an alternate order, not every operation need be performed, or additional processing operations may be performed, or both.

[0117] The embodiments disclosed herein can be used to manufacture a variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic products, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0118] Fig.13A computing device 1300 is illustrated according to one implementation of the present disclosure. The computing device 1300 houses a board 1302. The board 1302 may include a number of components, including, but not limited to, a processor 1304 and at least one communication chip 1306. The processor 1304 is physically and electrically coupled to the board 1302. In some implementations, at least one communication chip 1306 is also physically and electrically coupled to the board 1302. In further implementations, the communication chip 1306 is part of the processor 1304.

[0119] Depending on its application, the computing device 1300 may include other components that may or may not be physically and electrically coupled to the board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, an encryption processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0120] The communication chip 1306 enables wireless communication for the transmission of data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 1306 may implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 1300 may include a plurality of communication chips 1306. For example, the first communication chip 1306 may be dedicated to shorter-range wireless communications (such as Wi-Fi and Bluetooth), and the second communication chip 1306 may be dedicated to longer-range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0121] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some implementations of the embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures constructed according to implementations of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers or memory to transform the electronic data (or both) into other electronic data that can be stored in registers or memory or both.

[0122] The communication chip 1306 also includes an integrated circuit die packaged within the communication chip 1306. According to another implementation of the present disclosure, the integrated circuit die of the communication chip is constructed according to the implementation of the present disclosure.

[0123] In further implementations, additional components housed within computing device 1300 may include integrated circuit dies constructed according to implementations of embodiments of the present disclosure.

[0124] In various embodiments, computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smart phone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.

[0125] Fig.14 The diagram includes an interposer 1400 of one or more embodiments of the present disclosure. Interposer 1400 is an intermediate substrate for bridging a first substrate 1402 to a second substrate 1404. First substrate 1402 may be, for example, an integrated circuit die. Second substrate 1404 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1400 is to extend connections to a wider spacing or to reroute connections to different connections. For example, interposer 1400 may couple an integrated circuit die to a ball grid array (BGA) 1406, which may then be coupled to a second substrate 1404. In some embodiments, first and second substrates 1402 / 1404 are attached to opposite sides of interposer 1400. In other embodiments, first and second substrates 1402 / 1404 are attached to the same side of interposer 1400. And in further embodiments, three or more substrates are interconnected by means of interposer 1400.

[0126] The interposer 1400 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further implementations, the interposer 1400 may be formed of alternating rigid or flexible materials that may include the same materials described above for use in semiconductor substrates such as silicon, germanium, and other III-V and IV materials.

[0127] Interposer 1400 may include metal interconnects 1408 and vias 1410, including but not limited to through silicon vias (TSVs) 1412. Interposer 1400 may further include embedded devices 1414, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices (such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices) may also be formed on interposer 1400. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used in preparing interposer 1400 or in preparing components included in interposer 1400.

[0128] Fig.15 is an isometric view of a mobile computing platform 1500 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0129] The mobile computing platform 1500 can be any portable device configured for one of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1500 can be any one of a tablet, a smart phone, a laptop computer, etc., and includes a display screen 1505 (which is a touch screen (capacitive, inductive, resistive, etc.) in an exemplary embodiment), a chip-level (SoC) or package-level integrated system 1510 and a battery 1513. As illustrated, the higher the level of integration in the system 1510 enabled by a higher transistor packing density, the larger the portion of the mobile computing platform 1500 that can be occupied by a battery 1513 or a non-volatile memory (such as a solid-state drive), or the larger the transistor gate count for the improved platform function. Similarly, the greater the carrier mobility of each transistor in the system 1510, the greater the function. As such, the techniques described herein can enable performance and form factor improvements in the mobile computing platform 1500.

[0130] The integrated system 1510 is further illustrated in an expanded view 1520. In an exemplary embodiment, the packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) prepared according to one or more processes described herein or including one or more features described herein. The packaged device 1577 is further coupled to the board 1560 along with one or more of the following: a power management integrated circuit (PMIC) 1515, an RF (wireless) integrated circuit (RFIC) 1525 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband, and the analog front end module further includes a power amplifier on the transmit path and a low noise amplifier on the receive path) and its controller 1511. Functionally, the PMIC 1515 performs battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to the battery 1513, and has an output that provides current supply to all other functional modules. As further illustrated, in an exemplary embodiment, RFIC 1525 has an output coupled to an antenna to provide implementation of any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to a packaging substrate of packaged device 1577, or within a single IC (SoC) coupled to a packaging substrate of packaged device 1577.

[0131] In another aspect, semiconductor packages are used to protect an integrated circuit (IC) chip or die and also provide the die with an electrical interface to external circuits. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support greater circuit density. Further, the demand for higher performance devices creates a need for improved semiconductor packages that enable a thin package profile and low overall warpage that is compatible with subsequent assembly processes.

[0132] In an embodiment, a wire bond to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the chip to a ceramic or organic package substrate. In particular, a C4 solder ball connection can be implemented to provide a flip chip interconnection between a semiconductor device and a substrate. Flip chip or controlled collapse chip connection (C4) is a type of installation for semiconductor devices (such as integrated circuit (IC) chips, MEMS or components) that utilizes solder bumps instead of wire bonds. Solder bumps are deposited on C4 pads located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is turned over with the active side facing down over the mounting area. Solder bumps are used to connect the semiconductor device directly to the substrate.

[0133] Fig.16 Illustrated is a cross-sectional view of a flip chip mounted die according to an embodiment of the present disclosure.

[0134] Reference Fig.16 , device 1600 includes a die 1602, such as an integrated circuit (IC), prepared according to one or more processes described herein or including one or more features described herein, according to an embodiment of the present disclosure. Die 1602 includes metallized pads 1604 thereon. A package substrate 1606 (such as a ceramic or organic substrate) includes connections 1608 thereon. Die 1602 and package substrate 1606 are electrically connected by solder balls 1610 coupled to metallized pads 1604 and connections 1608. An underfill material 1612 surrounds solder balls 1610.

[0135] Processing a flip chip can be similar to conventional IC preparation, with very few additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. Small solder dots are then deposited on each metallized pad. The chips are then cut from the wafer as usual. To attach the flip chip to the circuit, the chip is inverted to bring the solder dots down to the connectors on the underlying electronic device or circuit board. Typically an ultrasonic or alternative reflow process is used, and then the solder is re-melted to create an electrical connection. This also leaves a small space between the circuit of the chip and the mounting below. In most cases, an electrically insulating adhesive is then "bottom-filled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0136] In other embodiments, newer packaging and die-to-die interconnect methods (such as through silicon vias (TSVs) and silicon interposers) are implemented in accordance with embodiments of the present disclosure to prepare high-performance multi-chip modules (MCMs) and system-in-package (SiPs) that incorporate integrated circuits (ICs) prepared according to one or more of the processes described herein or that include one or more of the features described herein.

[0137] Thus, embodiments of the present disclosure include integrated circuit structures with differentiated access to backside source or drain contacts.

[0138] Although specific embodiments have been described above, even in the case where only a single embodiment is described for a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise specified, the examples of features provided in the present disclosure are intended to be illustrative rather than limiting. The description described above is intended to cover such substitutions, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of the present disclosure.

[0139] The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly) or any generalization thereof, whether or not it alleviates any or all of the problems raised herein. Accordingly, new claims may be formulated during the prosecution of the present application (or of an application claiming priority) to any such combination of features. In particular, features from dependent claims may be combined with features of the independent claims with reference to the appended claims, and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations listed in the appended claims.

[0140] The following examples relate to further embodiments. The various features of the different embodiments may be combined in various ways, with some features included and others excluded, to suit a variety of different applications.

[0141] Example embodiment 1: An integrated circuit structure comprising: a first plurality of horizontally stacked nanowires, which are laterally spaced apart from a second plurality of horizontally stacked nanowires, the second plurality of horizontally stacked nanowires being laterally spaced apart from a third plurality of horizontally stacked nanowires. A first gate stack is above the first plurality of horizontally stacked nanowires, a second gate stack is above the second plurality of horizontally stacked nanowires, and a third gate stack is above the third plurality of horizontally stacked nanowires. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure being above a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure being above a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth being greater than the first depth.

[0142] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the first conductive material and the second conductive material have different compositions.

[0143] Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

[0144] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2 or 3, further comprising a dielectric spacer cap between the first epitaxial source or drain structure and the first conductive material.

[0145] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the second conductive material is in direct contact with the second epitaxial source or drain structure.

[0146] Example embodiment 6: An integrated circuit structure comprising: a first fin, which is laterally spaced apart from a second fin, and the second fin is laterally spaced apart from a third fin. A first gate stack is above the first fin, a second gate stack is above the second fin, and a third gate stack is above the third fin. A first epitaxial source or drain structure is between the first fin and the second fin, and the first epitaxial source or drain structure is above a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second fin and the third fin, and the second epitaxial source or drain structure is above a second conductive material having a second depth below the second epitaxial source or drain structure, and the second depth is greater than the first depth.

[0147] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the first conductive material and the second conductive material have different compositions.

[0148] Example Embodiment 8: The integrated circuit structure of Example Embodiment 6 or 7, wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

[0149] Example Embodiment 9: The integrated circuit structure of Example Embodiment 6, 7 or 8 further comprising a dielectric spacer cap between the first epitaxial source or drain structure and the first conductive material.

[0150] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, 8 or 9, wherein the second conductive material is in direct contact with the second epitaxial source or drain structure.

[0151] Example embodiment 11: A computing device comprising: a board; and a component coupled to the board. The component comprises an integrated circuit structure comprising a first plurality of horizontally stacked nanowires or fins, which are laterally spaced apart from a second plurality of horizontally stacked nanowires or fins, the second plurality of horizontally stacked nanowires or fins being laterally spaced apart from a third plurality of horizontally stacked nanowires or fins. A first gate stack is above the first plurality of horizontally stacked nanowires or fins, a second gate stack is above the second plurality of horizontally stacked nanowires or fins, and a third gate stack is above the third plurality of horizontally stacked nanowires or fins. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the first epitaxial source or drain structure being above a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is located between the second plurality of horizontally stacked nanowires or fins and the third plurality of horizontally stacked nanowires or fins, and the second epitaxial source or drain structure is located above a second conductive material having a second depth below the second epitaxial source or drain structure, and the second depth is greater than the first depth.

[0152] Example Embodiment 12: The computing device of Example Embodiment 11, comprising the first plurality of horizontally stacked nanowires, the second plurality of horizontally stacked nanowires, and the third plurality of horizontally stacked nanowires.

[0153] Example Embodiment 13: The computing device as described in Example Embodiment 11, comprising the first fin, the second fin, and the third fin.

[0154] Example Embodiment 14: The computing device of Example Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0155] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0156] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, further comprising a battery coupled to the board.

[0157] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15 or 16, further comprising a camera coupled to the board.

[0158] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0159] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0160] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires laterally spaced apart from a third plurality of horizontally stacked nanowires; a first gate stack over the first plurality of horizontally stacked nanowires, a second gate stack over the second plurality of horizontally stacked nanowires, and a third gate stack over the third plurality of horizontally stacked nanowires; a first epitaxial source or drain structure between the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires, the first epitaxial source or drain structure being above a first conductive material having a first depth below the first epitaxial source or drain structure; and A second epitaxial source or drain structure is located between the second plurality of horizontally stacked nanowires and the third plurality of horizontally stacked nanowires, the second epitaxial source or drain structure being located above a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth being greater than the first depth.

2. The integrated circuit structure of claim 1, wherein the first conductive material and the second conductive material have different compositions.

3. The integrated circuit structure of claim 1 or 2, wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

4. The integrated circuit structure of claim 1 or 2, further comprising a dielectric spacer cap between the first epitaxial source or drain structure and the first conductive material.

5. The integrated circuit structure of claim 1 or 2, wherein the second conductive material is in direct contact with the second epitaxial source or drain structure.

6. An integrated circuit structure comprising: a first fin laterally spaced from a second fin, the second fin laterally spaced from a third fin; a first gate stack on the first fin, a second gate stack on the second fin, and a third gate stack on the third fin; a first epitaxial source or drain structure between the first fin and the second fin, the first epitaxial source or drain structure being above a first conductive material having a first depth below the first epitaxial source or drain structure; and A second epitaxial source or drain structure is located between the second fin and the third fin, and the second epitaxial source or drain structure is located above a second conductive material having a second depth below the second epitaxial source or drain structure, and the second depth is greater than the first depth.

7. The integrated circuit structure of claim 6, wherein the first conductive material and the second conductive material have different compositions.

8. The integrated circuit structure of claim 6 or 7, wherein the first conductive material comprises titanium and nitrogen, and the second conductive material comprises tungsten or cobalt.

9. The integrated circuit structure of claim 6 or 7, further comprising a dielectric spacer cap between the first epitaxial source or drain structure and the first conductive material.

10. The integrated circuit structure of claim 6 or 7, wherein the second conductive material is in direct contact with the second epitaxial source or drain structure.

11. A computing device comprising: plate; and an assembly coupled to the board, the assembly comprising an integrated circuit structure, the integrated circuit structure comprising: a first plurality of horizontally stacked nanowires or fins laterally spaced apart from a second plurality of horizontally stacked nanowires or fins laterally spaced apart from a third plurality of horizontally stacked nanowires or fins; a first gate stack on the first plurality of horizontally stacked nanowires or fins, a second gate stack on the second plurality of horizontally stacked nanowires or fins, and a third gate stack on the third plurality of horizontally stacked nanowires or fins; a first epitaxial source or drain structure between the first plurality of horizontally stacked nanowires or fins and the second plurality of horizontally stacked nanowires or fins, the first epitaxial source or drain structure being above a first conductive material having a first depth below the first epitaxial source or drain structure; and A second epitaxial source or drain structure is located between the second plurality of horizontally stacked nanowires or fins and the third plurality of horizontally stacked nanowires or fins, and the second epitaxial source or drain structure is located above a second conductive material having a second depth below the second epitaxial source or drain structure, and the second depth is greater than the first depth.

12. The computing device of claim 11, comprising the first plurality of horizontally stacked nanowires, the second plurality of horizontally stacked nanowires, and the third plurality of horizontally stacked nanowires. 13 . The computing device of claim 11 , comprising the first fin, the second fin, and the third fin.

14. The computing device of claim 11, 12, or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12, or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12, or 13, further comprising: A battery is coupled to the board.

17. The computing device of claim 11, 12, or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12, or 13, wherein the component is a packaged integrated circuit die.

20. The computing device of claim 11, 12, or 13, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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