Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a first channel separation structure and a second channel separation structure extending in a first direction and spaced apart from each other in a second direction; first gate structures spaced apart from each other in the first direction between the first channel separation structure and the second channel separation structure, in contact with the first channel separation structure and the second channel separation structure; a first channel pattern and a second channel pattern including a first sheet pattern and a second sheet pattern, respectively, the first and second sheet patterns being spaced apart from each other in the third direction, in contact with the corresponding first and second channel separation structures; a first source / drain pattern and a second source / drain pattern between the first channel separation structure and the second channel separation structure, the first source / drain pattern being in contact with the first channel pattern and the first channel separation structure, and the second source / drain pattern being in contact with the second channel pattern and the second channel separation structure; and a first gate separation structure between the first source / drain pattern and the second source / drain pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0084900 filed in the Korean Intellectual Property Office on June 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0004] As a scaling technology for increasing the density of integrated circuit devices, a concept of a multi-gate transistor has been proposed, in which a silicon body in the form of a fin or a nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0005] Multi-gate transistors can be easily scaled up and down by taking advantage of their three-dimensional (3D) channels. In addition, multi-gate transistors can improve the control of current without increasing the gate length. In addition, multi-gate transistors effectively mitigate the short channel effect (SCE), a phenomenon in which the potential of the channel region is affected by the drain voltage.

[0006] Meanwhile, as the pitch size of semiconductor devices decreases, it is necessary to study methods for reducing capacitance between contacts and ensuring electrical stability. Summary of the invention

[0007] Aspects of the present disclosure provide a semiconductor device capable of improving device performance and device integration.

[0008] Aspects of the present disclosure also provide a method for manufacturing a semiconductor device capable of improving device performance and device integration.

[0009] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0010] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a first channel separation structure extending in a first direction; a second channel separation structure spaced apart from the first channel separation structure in a second direction and extending in the first direction; a plurality of first gate structures spaced apart from each other in the first direction between the first channel separation structure and the second channel separation structure, the first gate structure being in contact with the first channel separation structure and the second channel separation structure, and comprising a first gate electrode and a first gate insulating film; a first channel pattern comprising a plurality of first sheet patterns spaced apart from each other in a third direction and in contact with the first channel separation structure; a second channel pattern comprising a plurality of second sheet patterns spaced apart from each other in the third direction and in contact with the second channel separation structure; a first source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the first channel pattern and the first channel separation structure; a second source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the second channel pattern and the second channel separation structure; and a first gate separation structure between the first source / drain pattern and the second source / drain pattern.

[0011] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a first channel separation structure extending in a first direction; a second channel separation structure spaced apart from the first channel separation structure in a second direction and extending in the first direction; a plurality of first gate structures spaced apart from each other in the first direction between the first channel separation structure and the second channel separation structure, the first gate structure being in contact with the first channel separation structure and the second channel separation structure and comprising a first gate electrode and a first gate insulating film; a gate capping pattern on the gate electrode and in contact with the first channel separation structure and the second channel separation structure; a gate spacer on a sidewall of the first gate structure; a first channel pattern comprising a plurality of first sheet patterns spaced apart from each other in a third direction , and in contact with the first channel separation structure; a second channel pattern, including a plurality of second sheet patterns, the plurality of second sheet patterns are spaced apart from each other in a third direction, and in contact with the second channel separation structure; a first source / drain pattern, between the first channel separation structure and the second channel separation structure and in contact with the first channel pattern; a second source / drain pattern, between the first channel separation structure and the second channel separation structure, and in contact with the second channel pattern and the first gate separation structure between the first source / drain pattern and the second source / drain pattern, wherein an upper surface of the first channel separation structure and an upper surface of the first gate separation structure are located on the same plane (i.e., coplanar), and an upper surface of the first channel separation structure and an upper surface of the gate capping pattern are located on the same plane (i.e., coplanar).

[0012] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a first lower pattern extending in a first direction; a second lower pattern extending in the first direction and spaced apart from the first lower pattern in a second direction; a field insulating film between the first lower pattern and the second lower pattern; a first channel separation structure on the first lower pattern and extending in the first direction, a portion of the first channel separation structure being in the first lower pattern; a second channel separation structure on the second lower pattern and extending in the first direction, a portion of the second channel separation structure being in the second lower pattern; a plurality of gate structures spaced apart from each other in the first direction between the first channel separation structure and the second channel separation structure and contacting the first channel separation structure and the second channel separation structure, the gate structure comprising a gate electrode and a gate insulating film; the first channel pattern, between the first channel separation structure and the gate structure, and including a plurality of first sheet patterns, the plurality of first sheet patterns are spaced apart from each other in a third direction and in contact with the first channel separation structure; a second channel pattern, between the second channel separation structure and the gate structure, and including a plurality of second sheet patterns, the plurality of second sheet patterns are spaced apart from each other in the third direction and in contact with the second channel separation structure; a first source / drain pattern, between the first channel separation structure and the second channel separation structure, and in contact with the first channel pattern; a second source / drain pattern, between the first channel separation structure and the second channel separation structure, and in contact with the second channel pattern; and a gate separation structure, between the first source / drain pattern and a second source / drain pattern facing the first source / drain pattern in the second direction, the gate separation structure being in contact with the field insulating film.

[0013] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first molded fin pattern and a second molded fin pattern extending in a first direction and spaced apart from each other in a second direction, the first molded fin pattern comprising a first lower pattern and a first pre-pattern structure, the second molded fin pattern comprising a second lower pattern and a second pre-pattern structure, and each of the first pre-pattern structure and the second pre-pattern structure comprising a pre-active pattern and a pre-sacrificial pattern alternately stacked with the pre-active pattern; forming a dummy gate electrode on the first molded fin pattern and the second molded fin pattern, the dummy gate electrode comprising an extending portion extending in the second direction, and a connecting portion extending in the first direction , an extension portion of the dummy gate electrode intersects the first molded fin pattern and the second molded fin pattern, and the connecting portion of the dummy gate electrode connects the extension portion of the dummy gate electrode between the first molded fin pattern and the second molded fin pattern; using the dummy gate electrode as a mask, a first pre-source / drain recess and a second pre-source / drain recess are formed in the first molded fin pattern and the second molded fin pattern, respectively; by forming a first channel separation structure extending in a first direction in the first pre-pattern structure, a first upper pattern structure is formed on the first lower pattern, the first channel separation structure divides the first pre-source / drain recess into two first source / drain recesses; by forming a first channel separation structure extending in the first direction in the second pre-pattern structure A two-channel separation structure is provided, wherein a second upper pattern structure is formed on the second lower pattern, the second channel separation structure divides the second pre-source / drain recess into two second source / drain recesses, and each of the first upper pattern structure and the second upper pattern structure includes an active pattern and a sacrificial pattern alternately stacked with the active pattern; a first source / drain pattern contacting the first upper pattern structure is formed in the first source / drain recess; a second source / drain pattern contacting the second upper pattern structure is formed in the second source / drain recess; a gate trench exposing the first upper pattern structure and the second upper pattern structure is formed by removing a dummy gate electrode, the gate trench including a gate trench extension extending along a second direction, and a gate trench connecting portion connecting the gate trench extension portion; forming a first sheet pattern in contact with the first source / drain pattern and the first channel separation structure by removing the exposed sacrificial pattern of the first upper pattern structure; forming a second sheet pattern in contact with the second source / drain pattern and the second channel separation structure by removing the exposed sacrificial pattern of the second upper pattern structure; forming a pre-gate electrode in the gate trench, the pre-gate electrode comprising a pre-gate electrode extension portion intersecting the first sheet pattern and the second sheet pattern, and a pre-gate electrode connecting portion connecting the pre-gate electrode extension portion; and forming a gate electrode by forming a gate separation structure, the gate separation structure separating the extension portions of the pre-gate electrode adjacent to each other in the first direction.

[0014] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first molded fin pattern and a second molded fin pattern extending in a first direction and spaced apart from each other in a second direction, the first molded fin pattern comprising a first lower pattern and a first pre-pattern structure, the second molded fin pattern comprising a second lower pattern and a second pre-pattern structure, and each of the first pre-pattern structure and the second pre-pattern structure comprising a pre-active pattern and a pre-sacrificial pattern alternately stacked with the pre-active pattern; forming a pre-sacrificial pattern alternately stacked with the first molded fin pattern on the first molded fin pattern and the second molded fin pattern; The method comprises the steps of: forming a plurality of dummy gate electrodes intersecting the first molded fin pattern and the second molded fin pattern and extending in a second direction; forming a gate separation structure between the first molded fin pattern and the second molded fin pattern, the gate separation structure connecting the dummy gate electrodes adjacent to each other in the first direction; using the dummy gate electrodes as masks, forming a first pre-source / drain recess and a second pre-source / drain recess in the first molded fin pattern and the second molded fin pattern, respectively; forming a first channel separation structure extending in the first direction in the first pre-pattern structure, forming a first upper pattern structure on the first lower pattern, the first channel separation structure The first pre-source / drain recess is divided into two first source / drain recesses by a separation structure; a second channel separation structure extending along a first direction is formed in the second pre-pattern structure, and a second upper pattern structure is formed on the second lower pattern, wherein the second channel separation structure divides the second pre-source / drain recess into two second source / drain recesses, and each of the first upper pattern structure and the second upper pattern structure includes an active pattern and a sacrificial pattern alternately stacked with the active pattern; a first source / drain pattern contacting the first upper pattern structure is formed in the first source / drain recess; and a second upper pattern structure is formed on the second source A second source / drain pattern in contact with a second upper pattern structure is formed in a source / drain recess; a gate trench exposing the first upper pattern structure and the second upper pattern structure is formed by removing a dummy gate electrode; a first sheet pattern in contact with the first source / drain pattern and the first channel separation structure is formed by removing an exposed sacrificial pattern of the first upper pattern structure; a second sheet pattern in contact with the second source / drain pattern and the second channel separation structure is formed by removing an exposed sacrificial pattern of the second upper pattern structure; and a gate electrode crossing the first sheet pattern and the second sheet pattern is formed in the gate trench.

[0015] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals (when used) designate corresponding elements throughout the several views, and in which:

[0017] Figure 1 is a layout (ie, plan) diagram of a semiconductor device according to some embodiments of the present invention;

[0018] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 Along Figure 1 A cross-sectional view taken along line AA, line BB, line CC, line DD, and line EE;

[0019] Figure 7 It is used to illustrate Figure 2 a diagram of the shape of the first sheet pattern;

[0020] Figures 8 to 12 yes Figure 1 The plan view of part P;

[0021] Figures 13 to 16 is a cross-sectional view or a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0022] Fig.17 and Fig.18 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0023] Fig.19 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 20 to Figure 22 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0025] Fig.23 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0026] Fig.24 and Fig.25 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0027] Fig.26 and Fig. 27 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figures 28 to 30 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0029] Fig.31 is a layout diagram of a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 32 to Figure 35 Along Fig.31A cross-sectional view taken along line AA, line BB, line CC, and line EE;

[0031] Fig.36 is a layout diagram of a semiconductor device according to some embodiments of the present disclosure;

[0032] Fig.37 and Fig.38 Along Fig.36 A cross-sectional view taken along line CC and line EE;

[0033] Figure 39 to Figure 41 yes Fig.36 The plane diagram of part Q;

[0034] Figures 42 to 67 is a layout diagram or a cross-sectional diagram illustrating an intermediate step of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0035] Figures 68 to 78 is a layout diagram or a cross-sectional diagram illustrating an intermediate step of an example method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0036] Figure 79 to Figure 83 are cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] It should be understood that the ordinal terms used herein, such as "first", "second", "third", etc., are used to describe various elements, components, regions, layers and / or parts for the purpose of distinguishing one element, component, region, layer or part from another element, component, region, layer or part, and are not intended to convey a specific order or relationship between one element, component, region, layer or part and another element, component, region, layer or part. Accordingly, without departing from the essence and scope of the present disclosure, the first element, component, region, layer or part described below may also be referred to as a second element, component, region, layer or part.

[0038] Transistors including nanowires or nanosheets are described as examples of semiconductor devices according to some embodiments of the present disclosure, but the present disclosure is not limited thereto. The technical principles described herein are also applicable to field effect transistors (FETs) based on two-dimensional (2D) materials and their heterostructures.

[0039] In addition, the semiconductor device according to some embodiments of the present disclosure may include a fin FET (FinFET), a tunnel FET, and a three-dimensional (3D) transistor including a channel region characterized by a fin-shaped pattern. In addition, the semiconductor device according to some embodiments of the present disclosure may include other types of transistors, such as a bipolar junction transistor, a lateral double diffused metal oxide semiconductor (LDMOS) transistor, etc.

[0040] The following will refer to Figures 1 to 12 Semiconductor devices according to some embodiments of the present disclosure are described.

[0041] Figure 1 is a layout (ie, plan) diagram of a semiconductor device according to some embodiments of the present invention. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 Along Figure 1 Cross-sectional views taken along lines AA, BB, CC, DD, and EE. Figure 7 It is conceptually depicted Figure 2 A perspective view of the shape of the first sheet pattern. Figures 8 to 12 yes Figure 1 A plan view of a region P of a semiconductor device is shown.

[0042] Figure 1 A semiconductor device according to some embodiments of the present disclosure is depicted, except for the first source / drain contact 180 ( Figure 2 )、Second source / drain contact 280( Figure 3 )、third source / drain contact 380( Figure 5 ), and the fourth source / drain contact 480 ( Figure 5 ). Figures 8 to 12 It may be a plan view taken at a level where the first source / drain contact 180 , the second source / drain contact 280 , the third source / drain contact 380 , and the fourth source / drain contact 480 are located.

[0043] Reference Figures 1 to 12 , the semiconductor device according to some embodiments of the present disclosure may include a first lower pattern BP1, a second lower pattern BP2, a first channel pattern CH1, a second channel pattern CH2, a third channel pattern CH3, a fourth channel pattern CH4, a first channel separation structure CCW1, a second channel separation structure CCW2, a plurality of first gate electrodes 120, a first source / drain pattern 150, a second source / drain pattern 250, a third source / drain pattern 350, a fourth source / drain pattern 450, and a first gate separation structure GCS1.

[0044] The first substrate 100 may have a first (upper) surface 100US and a second (lower) surface 100BS, respectively, which are opposite to each other in a third direction D3 perpendicular to the upper surface 100US of the substrate 100. The first gate electrode 120, the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, the fourth source / drain pattern 450, the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 may be disposed on the first surface 100US of the first substrate 100, and the first surface 100US of the first substrate 100 may be the upper surface of the first substrate 100. The second surface 100BS of the first substrate 100 opposite to the first surface 100US of the first substrate 100 may be the bottom surface of the first substrate 100.

[0045] The first substrate 100 may be formed of or include a semiconductor material. The first substrate 100 may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate 100 may include silicon germanium (SiGe), silicon Ge on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present invention is not limited thereto.

[0046] The first lower pattern BP1 may protrude (i.e., extend) from the first substrate 100 along the third direction D3. More specifically, the first lower pattern BP1 may extend upward (i.e., along the third direction D3) from the first surface 100US of the first substrate 100. The first lower pattern BP1 may extend along the first direction D1 parallel to the upper surface 100US of the substrate 100.

[0047] The second lower pattern BP2 may protrude from the first substrate 100 along the third direction D3. More specifically, the second lower pattern BP2 may extend upward (along the third direction D3) from the first surface 100US of the first substrate 100. The second lower pattern BP2 may extend along the first direction D1. The second lower pattern BP2 may be spaced apart from the first lower pattern BP1 in a second direction D2 that is parallel to the upper surface 100US of the substrate and intersects the first direction D1.

[0048] For example, the third direction D3 may correspond to a vertical direction of the first substrate 100. The first direction D1 and the second direction D2 may correspond to horizontal directions and be perpendicular to the third direction D3.

[0049] The first lower pattern BP1 and the second lower pattern BP2 may be separated by a fin trench FT extending in the first direction D1. For example, the first surface 100US of the first substrate 100 may correspond to the bottom surface of the fin trench FT. The first lower pattern BP1 may have a sidewall BP1_SW extending in the first direction D1, and the second lower pattern BP2 may have a sidewall BP2_SW extending in the first direction D1. The sidewall BP1_SW of the first lower pattern BP1 and the sidewall BP2_SW of the second lower pattern BP2 may be defined by the fin trench FT.

[0050] For example, the first lower pattern BP1 may be located in a p-type metal oxide semiconductor (PMOS) region, and the second lower pattern BP2 may be located in an n-type metal oxide semiconductor (NMOS) region.

[0051] Each of the first lower pattern BP1 and the second lower pattern BP2 may be formed by partially etching the first substrate 100, or may include an epitaxial layer grown from the first substrate 100. The first lower pattern BP1 and the second lower pattern BP2 may include an elemental semiconductor material, such as Si or germanium (Ge). The first lower pattern BP1 and the second lower pattern BP2 may also include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0052] The Group IV-IV compound semiconductor may be a binary or ternary compound containing at least two of carbon (C), Si, Ge, and tin (Sn), or a compound formed by doping the binary or ternary compound with a Group IV element.

[0053] Group III-V compound semiconductors may be binary, ternary or quaternary compounds formed by combining at least one Group III element such as aluminum Al, gallium (Ga) and indium (In) with a Group V element such as phosphorus (P), arsenic (As) or antimony (Sb).

[0054] The field insulating film 105 may be disposed on the first substrate 100. For example, the field insulating film 105 may be disposed on the first surface 100US of the first substrate 100. The field insulating film 105 may at least partially fill the fin trench FT, which separates the first lower pattern BP1 from the second lower pattern BP2. The term "fill" (or "filled with", "filled", etc.) that may be used herein is intended to broadly refer to completely filling a defined space (e.g., the fin trench FT) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have a void or other space throughout. The field insulating film 105 is not disposed on the upper surface BP1_US of the first lower pattern BP1 and the upper surface BP2_US of the second lower pattern BP2.

[0055] The field insulating film 105 may have an upper surface 105US and a bottom surface 105BS opposite to each other in the third direction D3 . The bottom surface 105BS of the field insulating film 105 may face the first substrate 100 .

[0056] For example, the field insulating film 105 may generally cover the sidewall BP1_SW of the first lower pattern BP1 and the sidewall BP2_SW of the second lower pattern BP2. The term "covering" (or "covering on" or other similar terms) as may be used herein is intended to broadly refer to a material, layer or structure on or above another material, layer or structure, but does not require that the material, layer or structure completely cover the other material, layer or structure. Accordingly, for example, a material or layer having an opening or hole therein may still be considered to cover another material or layer. In another example not explicitly shown, the field insulating film 105 may cover a portion of the sidewall BP1_SW of the first lower pattern BP1 and a portion of the sidewall BP2_SW of the second lower pattern BP2. In this example, portions of the first lower pattern BP1 and the second lower pattern BP2 may protrude beyond the upper surface 105US (i.e., extend upward) of the field insulating film 105 along the third direction D3.

[0057] The upper surface 105US of the field insulating film 105 is shown as being flat (i.e., planar), but the present disclosure is not limited thereto. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. The field insulating film 105 is shown as a single film, but the present disclosure is not limited thereto.

[0058] A plurality of first channel patterns CH1 may be disposed on the first lower pattern BP1. The first channel pattern CH1 may overlap the first lower pattern BP1 in the third direction D3. The term "overlap" (or "overlapping" or similar terms) as used herein is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., the third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The first channel patterns CH1 may be aligned with each other in the first direction D1.

[0059] A plurality of second channel patterns CH2 may be disposed on the second lower pattern BP2. The second channel pattern CH2 may overlap the second lower pattern BP2 in the third direction D3. The second channel patterns CH2 may be aligned with each other in the first direction D1.

[0060] A plurality of third channel patterns CH3 may be disposed on the first lower pattern BP1. The third channel pattern CH3 may overlap the first lower pattern BP1 in the third direction D3. The third channel patterns CH3 may be aligned with each other in the first direction D1. The third channel patterns CH3 may be disposed to correspond to the first channel patterns CH1. The third channel patterns CH3 and their corresponding first channel patterns CH1 may be spaced apart from each other in the second direction D2.

[0061] A plurality of fourth channel patterns CH4 may be disposed on the second lower pattern BP2. The fourth channel pattern CH4 may overlap the second lower pattern BP2 in the third direction D3. The fourth channel patterns CH4 may be aligned with each other in the first direction D1. The fourth channel patterns CH4 may be disposed to correspond to the second channel patterns CH2. The fourth channel patterns CH4 and their corresponding second channel patterns CH2 may be spaced apart from each other in the second direction D2.

[0062] For example, the first and third channel patterns CH1 and CH3 may be included in a PMOS channel region, and the second and fourth channel patterns CH2 and CH4 may be included in an NMOS channel region.

[0063] Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 may include a plurality of sheet patterns spaced apart from each other in the third direction D3. Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 is illustrated as including three sheet patterns, but the present disclosure is not limited thereto.

[0064] Each of the first channel patterns CH1 may include a plurality of first sheet patterns NS1. The first sheet patterns NS1 may be disposed on the upper surface BP1_US of the first lower pattern BP1. The first sheet patterns NS1 may be arranged on the first lower pattern BP1 along the third direction D3. The first sheet patterns NS1 may be spaced apart from each other in the third direction D3. Each of the first sheet patterns NS1 may have an upper surface NS1_US and a bottom surface NS1_BS that are opposite to each other in the third direction D3.

[0065] Each second channel pattern CH2 may include a plurality of second sheet patterns NS2. The second sheet patterns NS2 may be disposed on the upper surface BP2_US of the second lower pattern BP2. The second sheet patterns NS2 may be arranged on the second lower pattern BP2 along the third direction D3. The second sheet patterns NS2 may be spaced apart from each other in the third direction D3. Each second sheet pattern NS2 may have an upper surface NS2_US and a bottom surface NS2_BS that are opposite to each other in the third direction D3.

[0066] Each third channel pattern CH3 may include a plurality of third sheet patterns NS3. The third sheet patterns NS3 may be disposed on the upper surface BP1_US of the first lower pattern BP1. The third sheet patterns NS3 may be spaced apart from each other in the third direction D3. Each fourth channel pattern CH4 may include a plurality of fourth sheet patterns NS4. The plurality of fourth sheet patterns NS4 may be disposed on the upper surface BP2_US of the second lower pattern BP2. Each fourth sheet pattern NS4 may be spaced apart from each other in the third direction D3.

[0067] Each of the first sheet patterns NS1 may have first side walls NS1_SW1 opposite to each other in the first direction D1, and second side walls NS1_SW2 opposite to each other in the second direction D2. An upper surface NS1_US and a bottom surface NS1_BS of each of the first sheet patterns NS1 may be connected by the first side wall NS1_SW1 and the second side wall NS1_SW2 of the corresponding first sheet pattern NS1. The first side wall NS1_SW1 of each of the first sheet patterns NS1 may be connected to and in contact with its corresponding first source / drain pattern 150. The above description of the first sheet pattern NS1 may be directly applied to the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4.

[0068] The sheet patterns (NS1, NS2, NS3, and NS4) may include one of an elemental semiconductor material (e.g., Si or Ge), a group IV-IV compound semiconductor, and a group III-V compound semiconductor. The first sheet pattern NS1 and the third sheet pattern NS3 may include the same material as the first lower pattern BP1 or a material different from the first lower pattern BP1. The second sheet pattern NS2 and the fourth sheet pattern NS4 may include the same material as the second lower pattern BP2 or a material different from the second lower pattern BP2.

[0069] The first lower pattern BP1 and the second lower pattern BP2 may be silicon (Si) lower patterns including Si. The sheet patterns (NS1, NS2, NS3, and NS4) may be Si sheet patterns including Si.

[0070] The channel patterns ( CH1 , CH2 , CH3 , and CH4 ) will be described below, with particular attention paid to the first channel pattern CH1 and the second channel pattern CH2 as illustrative examples.

[0071] The first channel separation structure CCW1 may be disposed on the first lower pattern BP1. The first channel separation structure CCW1 may extend in the first direction D1. The first channel separation structure CCW1 may include a sidewall CCW1_SW extending in the first direction D1.

[0072] The first channel separation structure CCW1 separates the first channel pattern CH1 from the third channel pattern CH3. The first channel separation structure CCW1 may not separate the first lower pattern BP1. A portion of the first channel separation structure CCW1 may be partially disposed in the first lower pattern BP1. The first lower pattern BP1 may cover a portion of the sidewall CCW1_SW of the first channel separation structure CCW1.

[0073] The first channel separation structure CCW1 may be in contact with the first lower pattern BP1. The first channel pattern CH1 and the third channel pattern CH3 may be in contact with the first channel separation structure CCW1 (e.g., the sidewall CCW1_SW of the first channel separation structure CCW1). A plurality of first sheet patterns NS1 and a plurality of third sheet patterns NS3 may be in contact with the first channel separation structure CCW1. The first sheet pattern NS1 and the third sheet pattern NS3 may extend from the sidewall CCW1_SW of the first channel separation structure CCW1 along the second direction D2. For example, one second sidewall NS1_SW2 of each first sheet pattern NS1 may be in contact with one sidewall CCW1_SW of the first channel separation structure CCW1, and one second sidewall of each third sheet pattern NS3 may be in contact with the other sidewall CCW1_SW of the first channel separation structure CCW1.

[0074] Similarly, the second channel separation structure CCW2 may be disposed on the second lower pattern BP2. The second channel separation structure CCW2 may extend along the first direction D1. The second channel separation structure CCW2 may include a sidewall CCW2_SW extending along the first direction D1. The second channel separation structure CCW2 may be spaced apart from the first channel separation structure CCW1 in the second direction D2. The sidewall CCW2_SW of the second channel separation structure CCW2 may face the sidewall CCW1_SW of the first channel separation structure CCW1.

[0075] The second channel separation structure CCW2 separates the second channel pattern CH2 from the fourth channel pattern CH4. The second channel separation structure CCW2 may not separate the second lower pattern BP2. A portion of the second channel separation structure CCW2 may be disposed in the second lower pattern BP2. The second lower pattern BP2 may cover a portion of the sidewall CCW2_SW of the second channel separation structure CCW2.

[0076] The second channel separation structure CCW2 may be in contact with the second lower pattern BP2. The second channel pattern CH2 and the fourth channel pattern CH4 may be in contact with the second channel separation structure CCW2. A plurality of second sheet patterns NS2 and a plurality of fourth sheet patterns NS4 may be in contact with the second channel separation structure CCW2. The second sheet pattern NS2 and the fourth sheet pattern NS4 may protrude from the sidewall CCW2_SW of the second channel separation structure CCW2 along the second direction D2. For example, a second sidewall NS2_SW2 of each second sheet pattern NS2 may be in contact with a sidewall CCW2_SW of the second channel separation structure CCW2, and a second sidewall of each fourth sheet pattern NS4 may be in contact with the other sidewall CCW2_SW of the second channel separation structure CCW2.

[0077] The first and second channel patterns CH1 and CH2 may be disposed between the first and second channel separation structures CCW1 and CCW2 that are adjacent to each other in the second direction D2 .

[0078] The first trench separation structure CCW1 and the second trench separation structure CCW2 may include an insulating material. The first trench separation structure CCW1 and the second trench separation structure CCW2 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxycarbide (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO) and combinations thereof, but the present disclosure is not limited thereto. The first channel separation structure CCW1 and the second channel separation structure CCW2 are shown as a single film, but the present disclosure is not limited thereto. Since the first channel separation structure CCW1 and the second channel separation structure CCW2 are formed simultaneously, the first channel separation structure CCW1 and the second channel separation structure CCW2 may include the same material.

[0079] A height H11 from the bottom surface 105BS of the field insulating film 105 to the upper surface BP1_US of the first lower pattern BP1 is greater than a height H21 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first trench separation structure CCW1. With respect to the first surface 100US of the first substrate 100, the upper surface 105US of the field insulating film 105 may be higher than the lowermost portion of the first trench separation structure CCW1.

[0080] A plurality of first gate structures GS1 may be disposed on the first surface 100US of the first substrate 100. The first gate structures GS1 may extend along the second direction D2. The first gate structures GS1 may be adjacent to each other in the first direction D1.

[0081] The first gate structure GS1 may be disposed between the first and second channel separation structures CCW1 and CCW2 that are adjacent to each other in the second direction D2. The first gate structure GS1 may contact the first and second channel separation structures CCW1 and CCW2.

[0082] The first gate structure GS1 may be disposed on the first and second lower patterns BP1 and BP2. The first gate structure GS1 may cross the first and second lower patterns BP1 and BP2. The first gate structure GS1 may overlap portions of the first and second lower patterns BP1 and BP2 in the third direction D3.

[0083] The first gate structure GS1 may be in contact with the upper surface 105US of the field insulating film 105. The first gate structure GS1 may be in contact with upper surfaces BP1_US and BP2_US of the first and second lower patterns BP1 and BP2.

[0084] The first gate structure GS1 may include a first gate electrode 120 and a first gate insulating film 130. The first gate insulating film 130 of the first gate structure GS1 may contact the upper surface 105US of the field insulating film 105 and the upper surfaces BP1_US and BP2_US of the first and second lower patterns BP1 and BP2, respectively. The first gate insulating film 130 of the first gate structure GS1 may contact the sidewalls CCW1_SW of the first channel separation structure CCW1 and CCW2_SW of the second channel separation structure CCW2.

[0085] The first channel pattern CH1 may be disposed between the first gate structure GS1 and the first channel separation structure CCW1. The first sheet pattern NS1 may be disposed between the first gate structure GS1 and the first channel separation structure CCW1. Since the first sheet pattern NS1 contacts the first channel separation structure CCW1, the first gate structure GS1 may not surround the first sheet pattern NS1 in a cross-sectional view.

[0086] The second channel pattern CH2 may be disposed between the first gate structure GS1 and the second channel separation structure CCW2. The second sheet pattern NS2 may be disposed between the first gate structure GS1 and the second channel separation structure CCW2. Since the second sheet pattern NS2 contacts the second channel separation structure CCW2, the first gate structure GS1 may not surround the second sheet pattern NS2 in the cross-sectional view.

[0087] Each first gate structure GS1 may include a first inner gate structure INT_GS1. The first inner gate structure INT_GS1 may be disposed between the first lower pattern BP1 and the corresponding first sheet pattern NS1 adjacent to each other along the third direction D3 and between the corresponding first sheet patterns NS1. The first inner gate structure INT_GS1 may be disposed between the second lower pattern BP2 and the corresponding second sheet pattern NS2 adjacent to each other along the third direction D3 and between the corresponding second sheet patterns NS2.

[0088] The first inner gate structure INT_GS1 contacts an upper surface BP1_US of the first lower pattern BP1 and an upper surface NS1_US and a bottom surface NS1_BS of the corresponding first sheet pattern NS1. The first inner gate structure INT_GS1 may contact an upper surface BP2_US of the second lower pattern BP2 and an upper surface NS2_US and a bottom surface NS2_BS of the corresponding second sheet pattern NS2.

[0089] A plurality of first gate electrodes 120 may be disposed between the first channel separation structure CCW1 and the second channel separation structure CCW2, respectively. Since the first gate insulating film 130 is disposed between the first gate electrode 120 and the first channel separation structure CCW1 and between the first gate electrode 120 and the second channel separation structure CCW2, the first gate electrode 120 may not be in contact with the first channel separation structure CCW1 and the second channel separation structure CCW2. The term "contact" as may be used herein is intended to broadly refer to electrical and / or physical contact between two or more layers, structures, or other elements.

[0090] The first gate electrode 120 may be disposed on the first and second lower patterns BP1 and BP2. The first gate electrode 120 may overlap portions of the first and second lower patterns BP1 and BP2 in the third direction D3.

[0091] For example, the first gate electrode 120 may include a first connection gate electrode 120_1, a second connection gate electrode 120_2, and a third connection gate electrode 120_3 arranged along the first direction D1. The second connection gate electrode 120_2 may be disposed between the first connection gate electrode 120_1 and the third connection gate electrode 120_3.

[0092] The upper surface 120US of the first gate electrode 120 is Figure 2 and Figure 3 1. The upper surface 120US of the first gate electrode 120 is shown as a concave surface, but the present disclosure is not limited thereto. Alternatively, the upper surface 120US of the first gate electrode 120 may be flat.

[0093] The first gate electrode 120 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W) , aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) at least one and a combination thereof, but the present disclosure is not limited thereto. Here, the conductive metal oxide and the conductive metal oxynitride may cover the oxidized forms of the above materials, but the present disclosure is not limited thereto.

[0094] The first gate insulating film 130 may extend along the upper surface 105US of the field insulating film 105 and the upper surfaces BP1_US and BP2_US of the first lower pattern BP1 and the second lower pattern BP2. The first gate insulating film 130 may extend along a portion of the sidewall CCW1_SW of the first channel separation structure CCW1 and a portion of the sidewall CCW2_SW of the second channel separation structure CCW2. In a cross-sectional view, the first gate insulating film 130 may be disposed along a portion of the periphery (i.e., periphery) of the first sheet pattern NS1. The first gate insulating film 130 may be disposed along a portion of the periphery of the second sheet pattern NS2. The first gate electrode 120 is disposed on the first gate insulating film 130. The first gate insulating film 130 is disposed between the first gate electrode 120 and the first sheet pattern NS1 and between the first gate electrode 120 and the second sheet pattern NS2. The first gate insulating film 130 included in the second inner gate structure INS_GS1 may contact the first source / drain pattern 150 and the second source / drain pattern 250.

[0095] The first gate insulating film 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0096] The first gate insulating film 130 is shown as a single film, but the present disclosure is not limited thereto. Alternatively, the first gate insulating film 130 may include a stack of multiple films. The first gate insulating film 130 may include an interface layer disposed between the first channel pattern CH1 and the first gate electrode 120 and between the second channel pattern CH2 and the first gate electrode 120, and a high-k (i.e., high dielectric constant) insulating film. For example, the interface film may not be formed along the contour of the upper surface 105US of the field insulating film 105.

[0097] The semiconductor device according to some embodiments of the present disclosure may include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor.For example, each first gate insulating film 130 may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0098] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have a positive capacitance, the total capacitance of the two or more capacitors may be lower than the individual capacitance of each of the two or more capacitors. Conversely, if at least one of the two or more capacitors has a negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

[0099] If a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film can be increased. Accordingly, a transistor with a ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0100] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0101] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), silicon, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium, scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant may vary depending on the material type of the ferroelectric material film.

[0102] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include at least one of Gd, Si, Zr, Al, and Y, for example.

[0103] If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic percent (at%) to about 8 at% Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the sum of the amounts of Hf and Al to the amount of Al in the ferroelectric material film.

[0104] If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include about 2 at% to about 10 at% Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include about 2 at% to about 10 at% Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include about 1 at% to about 7 at% Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include about 50 at% to about 80 at% Zr.

[0105] The paraelectric material film may include paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and high-k metal oxide. The high-k metal oxide may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the present disclosure is not limited thereto.

[0106] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a different crystal structure from the hafnium oxide included in the paraelectric material film.

[0107] The ferroelectric material film may be thick enough to exhibit ferroelectric properties. The ferroelectric material film may have a thickness of, for example, about 0.5 nm to about 10 nm, but the present disclosure is not limited thereto. The critical thickness capable of exhibiting ferroelectric properties may vary depending on the type of ferroelectric material, and therefore, the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0108] For example, each first gate insulating film 130 may include a ferroelectric material film. In another example, each first gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. Each first gate insulating film 130 may have a structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0109] The first gate spacer 140 may be disposed on a sidewall of the first gate structure GS1. For example, the first gate spacer 140 may include a first portion extending along the second direction D2. According to the position of the first gate separation structure GCS1, the first gate spacer 140 may include a second portion extending along the first direction D1. The first portion of the first gate spacer 140 may be directly connected to the second portion of the first gate spacer 140. The first portion of the first gate spacer 140 may be disposed on a sidewall of the first gate structure GS1 extending along the second direction D2.

[0110] The first gate spacer 140 may not be disposed between the first lower patterns BP1 and their corresponding first sheet patterns NS1 adjacent to each other in the third direction D3 and between the corresponding first sheet patterns NS1. The first gate spacer 140 may not be disposed between the second lower patterns BP2 and their corresponding second sheet patterns NS2 adjacent to each other in the third direction D3 and between the corresponding second sheet patterns NS2.

[0111] Details about the shape of the first gate spacer 140 will be further described in a description section about the first gate separation structure GCS1.

[0112] The first gate spacer 140 may include, for example, SiN, SiON, SiO 2 , SiOCN, SiBN, SiOBN, SiOC, and combinations thereof. The first gate spacer 40 is shown as a single film, but the present disclosure is not limited thereto.

[0113] The first gate capping pattern 145 may be disposed on the first gate structure GS1 . The first gate capping pattern 145 may be disposed on the upper surface 120US of the first gate electrode 120 .

[0114] The first gate capping pattern 145 may be disposed on an upper surface of the first gate spacer 140. The first gate capping pattern 145 may cover the upper surface of the first gate spacer 140. Although not explicitly shown, in some embodiments, the first gate capping pattern 145 may be disposed between the first gate spacers 140. In this case, an upper surface 145US of the first gate capping pattern 145 may be disposed on the same plane as the upper surface of the first gate spacer 140 (i.e., coplanar).

[0115] The first gate capping pattern 145 may be disposed between the first channel separation structure CCW1 and the second channel separation structure CCW2 . The first gate capping pattern 145 may contact a sidewall CCW1_SW of the first channel separation structure CCW1 and a sidewall CCW2_SW of the second channel separation structure CCW2 .

[0116] The height from the bottom surface 105BS of the field insulating film 105 to the upper surface 145US of the first gate capping pattern 145 may be the same as the height "H21+H22" from the bottom surface 105BS of the field insulating film 105 to the upper surface CCW1_US of the first channel separation structure CCW1. For example, the upper surface 145US of the first gate capping pattern 145 may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1. For example, the upper surface 145US of the first gate capping pattern 145 may be disposed on the same plane as the upper surface CCW2_US of the second channel separation structure CCW2.

[0117] The first gate capping pattern 145 may include at least one of SiN, SiON, SiCN, SiOCN, and combinations thereof.

[0118] Although not explicitly shown, in some embodiments, the first gate capping pattern 145 may not be disposed on the first gate structure GS1. In this case, the height from the bottom surface 105BS of the field insulating film 105 to the upper surface of the first gate structure GS1 may be the same as the height from the bottom surface 105BS of the field insulating film 105 to the upper surface CCW1_US of the first channel separation structure CCW1 (i.e., H21+H22). The upper surface of the first gate structure GS1 may include the upper surface 120US of the first gate electrode 120.

[0119] The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 may be disposed on the side surface (ie, the sidewall) of the first gate electrode 120. The first source / drain pattern 150 may be connected to the first channel pattern CH1. The first source / drain pattern 150 may be in contact with the first channel pattern CH1. The first source / drain pattern 150 may be in contact with the first sheet pattern NS1. For example, the first source / drain pattern 150 may be in contact with the first inner gate structure INT_GS1.

[0120] The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be disposed on the side surface of the first gate electrode 120. The second source / drain pattern 250 may be connected to the second channel pattern CH2. The second source / drain pattern 250 may be in contact with the second channel pattern CH2. The second source / drain pattern 250 may be in contact with the second sheet pattern NS2. For example, the second source / drain pattern 250 may be in contact with the first inner gate structure INT_GS1.

[0121] The third source / drain pattern 350 may be disposed on the first lower pattern BP1. The first channel separation structure CCW1 may be disposed between the first source / drain pattern 150 and the third source / drain pattern 350. Although not specifically shown, the third source / drain pattern 350 may be connected to the third channel pattern CH3. The third source / drain pattern 350 may be in contact with the third channel pattern CH3.

[0122] The fourth source / drain pattern 450 may be disposed on the second lower pattern BP2. The second channel separation structure CCW2 may be disposed between the second source / drain pattern 250 and the fourth source / drain pattern 450. Although not specifically shown, the fourth source / drain pattern 450 may be connected to the fourth channel pattern CH4. The fourth source / drain pattern 450 may be in contact with the fourth channel pattern CH4.

[0123] The first source / drain pattern 150 and the second source / drain pattern 250 may be disposed between the first channel separation structure CCW1 and the second channel separation structure CCW2. The first source / drain pattern 150 and the second source / drain pattern 250 may be spaced apart from each other in the second direction D2.

[0124] The first source / drain pattern 150 may contact the first channel separation structure CCW1. For example, the first source / drain pattern 150 may contact the sidewall CCW1_SW of the first channel separation structure CCW1. The second source / drain pattern 250 may contact the second channel separation structure CCW2. For example, the second source / drain pattern 250 may contact the sidewall CCW2_SW of the second channel separation structure CCW2.

[0125] The first source / drain pattern 150 may be in contact with the first sheet pattern NS1 and the first lower pattern BP1. The second source / drain pattern 250 may be in contact with the second sheet pattern NS2 and the second lower pattern BP2.

[0126] The third source / drain pattern 350 may be in contact with the first channel separation structure CCW1 . The fourth source / drain pattern 450 may be in contact with the second channel separation structure CCW2 .

[0127] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be disposed on the first surface 100US of the first substrate 100. The first source / drain pattern 150 may be included in the source / drain of a transistor using the first sheet pattern NS1 as a channel region. The second source / drain pattern 250 may be included in the source / drain of a transistor using the second sheet pattern NS2 as a channel region. The third source / drain pattern 350 may be included in the source / drain of a transistor using the third sheet pattern NS3 as a channel region. The fourth source / drain pattern 450 may be included in the source / drain of a transistor using the fourth sheet pattern NS4 as a channel region.

[0128] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may include an epitaxial pattern. The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may include a semiconductor material.

[0129] The first source / drain pattern 150 and the third source / drain pattern 350 may include a p-type dopant. The p-type dopant may include at least one of boron (B) and gallium (Ga), but the present disclosure is not limited thereto. The second source / drain pattern 250 and the fourth source / drain pattern 450 may include an n-type dopant. The n-type dopant may include at least one of P, As, Sb, and bismuth (Bi), but the present disclosure is not limited thereto.

[0130] The source / drain etch stop film 185 may extend along the outer sidewalls of the first gate spacer 140, the sidewalls of the first source / drain pattern 150, the sidewalls of the second source / drain pattern 250, the sidewalls of the third source / drain pattern 350, and the sidewalls of the fourth source / drain pattern 450. The source / drain etch stop film 185 may extend along the upper surface 105US of the field insulating film 105.

[0131] Portions of the source / drain etch stop film 185 may extend along the sidewall CCW1_SW of the first channel separation structure CCW1 and the sidewall CCW2_SW of the second channel separation structure CCW2. The source / drain etch stop film 185 on the sidewall CCW1_SW of the first channel separation structure CCW1 and the sidewall CCW2_SW of the second channel separation structure CCW2 may be remaining portions that are not removed in the process of forming the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480.

[0132] The source / drain etch stop film 185 may not extend along the sidewalls of the first gate capping pattern 145. Although not explicitly shown, in some embodiments, the source / drain etch stop film 185 may extend along the sidewalls of the first gate capping pattern 145.

[0133] The source / drain etch stop film 185 may include, for example, at least one of SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0134] The upper interlayer insulating film 190 may be disposed on the first surface 100US of the first substrate 100. The upper interlayer insulating film 190 may be disposed on the source / drain etch stop film 185. The upper interlayer insulating film 190 may be disposed on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450.

[0135] The upper interlayer insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k (low dielectric constant) material. The low-k material may have a dielectric constant less than 3.9, which is the dielectric constant of silicon oxide.

[0136] The first gate separation structure GCS1 may be disposed on the first surface 100US of the first substrate 100 . The first gate separation structure GCS1 may be disposed on the field insulating film 105 . A portion of the first gate separation structure GCS1 may be disposed in the upper interlayer insulating film 190 .

[0137] The first gate separation structure GCS1 may be in contact with the field insulation film 105. A portion of the first gate separation structure GCS1 may be recessed in the field insulation film 105.

[0138] The first gate separation structure GCS1 may be disposed between the first channel separation structure CCW1 and the second channel separation structure CCW2. The first gate separation structure CGS1 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 250. For example, the first gate separation structure GCS1 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 250 facing the first source / drain pattern 150 along the second direction D2. For example, the first gate separation structure GCS1 may not contact the first source / drain pattern 150 and the second source / drain pattern 250.

[0139] The first gate separation structure GCS1 may be disposed between the first gate structures GS1 adjacent to each other along the first direction D1. The first gate separation structure GCS1 separates the first gate structures GS1. For example, the first gate separation structure GCS1 may separate the first gate structures GS1 adjacent to each other in the first direction D1.

[0140] The first gate separation structure GCS1 may be in contact with the first gate structure GS1. For example, the first gate separation structure GCS1 may be in contact with the first gate electrode 120 and the first gate insulating film 130.

[0141] Reference Figure 6 Each first gate separation structure GCS1 may include sidewalls opposite to each other in the first direction D1. The first gate insulating film 130 may not extend along the sidewalls of the first gate separation structure GCS1. The first gate insulating film 130 may not extend along the boundary between the first gate separation structure GCS1 and the first gate electrode 120.

[0142] Reference Figures 8 to 12 , the first gate electrode 120 may include a contact surface 120_CS in contact with the first gate separation structure GCS1. Figures 8 to 10 and Fig.12 , the contact surface 120_CS of the first gate electrode 120 may include a concave surface in a plan view. Fig.11 , the contact surface 120_CS of the first gate electrode 120 may appear as a straight line in a plan view.

[0143] Although not specifically shown, Fig. 9 , Fig.10 and Fig.12 The contact surface 120_CS of the first gate electrode 120 may appear as a straight line in a plan view.

[0144] The following will refer to Figures 8 to 12 A planar configuration between the first connection gate electrode 120_1 and the second connection gate electrode 120_2 and their corresponding first gate separation structure GCS1 is described. Figures 8 to 12 The contents described in the above description may also be respectively applied to the planar configuration between the second connection gate electrode 120_2 and the third connection gate electrode 120_3 and their corresponding first gate separation structure GCS1.

[0145] Reference Figures 8 to 12 , the first gate spacer 140 may extend along sidewalls of the first connection gate electrode 120_1 and the second connection gate electrode 120_2 .

[0146] Reference Figures 8 to 11 , the first gate spacer 140 on the sidewall of the first connection gate electrode 120_1 may be separated from the first gate spacer 140 on the sidewall of the second connection gate electrode 120_2 by the first gate separation structure GCS1.

[0147] Reference Fig.12 In the illustrated embodiment, the first gate spacers 140 on the sidewalls of the first connection gate electrode 120_1 are not separated from the first gate spacers 140 on the sidewalls of the second connection gate electrode 120_2 by the first gate separation structure GCS1.

[0148] Reference Figures 8 to 12, each of the first connection gate electrode 120_1 and the second connection gate electrode 120_2 may include a first gate electrode line portion 120L extending along the second direction D2.

[0149] Reference Figure 8 , Fig.11 and Fig.12 Each of the first gate electrode 120_1 and the second gate electrode 120_2 may further include a first gate electrode protrusion 120P extending from the first gate electrode line portion 120L in the first direction D1. The first gate electrode protrusions 120P of the first and second connection gate electrodes 120_1 and 120_2 may contact the first gate separation structure GCS1.

[0150] Reference Figure 8 and Fig.11 , a width W12 of the first gate electrode protrusion 120P of the first gate electrode structure GS1 in the second direction D2 may be smaller than a width W11 of the first gate separation structure GCS1 in the second direction D2.

[0151] Reference Fig.12 In some embodiments, the width W12 of the first gate electrode protrusion 120P of the first gate electrode structure GS1 in the second direction D2 may be the same as the width W11 of the first gate separation structure GCS1 in the second direction D2. Although not explicitly shown, if the first gate separation structure GCS1 removes part of the first gate spacer 40, the width W12 of the first gate electrode structure GS1 including the first gate electrode protrusion 120P in the second direction D2 may be smaller than the width W11 of the first gate separation structure GCS1 in the second direction D2.

[0152] Reference Fig. 9 , the second connection gate electrode 120_2 may include a first gate electrode line portion 120L and a first gate electrode protrusion 120P, and the first gate electrode protrusion 120P extends from the first gate electrode line portion 120L in the first direction D1. The first connection gate electrode 120_1 may include the first gate electrode line portion 120L but does not include the first gate electrode protrusion 120P. The first gate electrode protrusion 120P of the second connection gate electrode 120_2 and the first gate electrode line portion 120L of the first connection gate electrode 120_1 may contact the first gate separation structure GCS1.

[0153] Reference Fig.10 , each of the first connection gate electrode 120_1 and the second connection gate electrode 120_2 may not include the first gate electrode protrusion 120P.

[0154] For example, Figure 4 and Figure 5As shown, a height "H21+H22" from the bottom surface 105BS of the field insulating film 105 to the upper surface CCW1_US of the first channel separation structure CCW1 may be the same as a height "H31+H32" from the bottom surface 105BS of the field insulating film 105 to the upper surface GCS1_US of the first gate separation structure GCS1. For example, the upper surface GCS1_US of the first gate separation structure GCS1 may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1.

[0155] A height H22 of the first channel separation structure CCW1 in the third direction D3 may be different from a height H32 of the first gate separation structure GCS1 in the third direction D3 .

[0156] For example, a height H22 of the first channel separation structure CCW1 in the third direction D3 may be less than a height H32 of the first gate separation structure GCS1 in the third direction D3. A height H31 from the bottom surface 105BS of the field insulating film 105 to the lowest portion of the first gate separation structure GCS1 may be less than a height H21 from the bottom surface 105BS of the field insulating film 105 to the lowest portion of the first channel separation structure CCW1. A height H11 from the bottom surface 105BS of the field insulating film 105 to the upper surface BP1_US of the first lower pattern BP1 may be greater than a height H31 from the bottom surface 105BS of the field insulating film 105 to the lowest portion of the first gate separation structure GCS1. A height H12 from the bottom surface 105BS of the field insulating film 105 to the upper surface 105US of the field insulating film 105 may be greater than a height H31 from the bottom surface 105BS of the field insulating film 105 to the lowest portion of the first gate separation structure GCS1.

[0157] For example, a distance W21 between the first gate separation structure GCS1 and the first channel separation structure CCW1 in the second direction D2 may be the same as a distance W22 between the first gate separation structure GCS1 and the second channel separation structure CCW2 in the second direction D2. The distance W21 between the first gate separation structure GCS1 and the first channel separation structure CCW1 in the second direction D2 may be measured from an upper surface GCS1_US of the first gate separation structure GCS1 and an upper surface CCW1_US of the first channel separation structure CCW1.

[0158] The first gate separation structure GCS1 may include an insulating material. The first gate separation structure GCS1 may include SiN, SiON, SiO 2 , at least one of SiOCN, SiBN, SiOBN, SiOC, AlO, and combinations thereof. The first gate separation structure GCS1 is shown as a single film, but the present disclosure is not limited thereto.

[0159] The first source / drain contact 180 may be disposed on the first source / drain pattern 150. The first source / drain contact 180 is electrically connected to the first source / drain pattern 150. The first source / drain contact 180 is disposed between the first channel separation structure CCW1 and the first gate separation structure GCS1. The first source / drain contact 180 may be disposed on the upper interlayer insulating film 190. A portion of the source / drain etch stop film 185 may be disposed between the first source / drain contact 180 and the first channel separation structure CCW1.

[0160] The second source / drain contact 280 may be disposed on the second source / drain pattern 250. The second source / drain contact 280 is electrically connected to the second source / drain pattern 250. The second source / drain contact 280 is disposed between the second channel separation structure CCW2 and the first gate separation structure GCS1. The second source / drain contact 280 may be disposed on the upper interlayer insulating film 190. A portion of the source / drain etch stop film 185 may be disposed between the second source / drain contact 280 and the second channel separation structure CCW2.

[0161] The third source / drain contact 380 may be disposed on the third source / drain pattern 350. The third source / drain contact 380 is electrically connected to the third source / drain pattern 350. The fourth source / drain contact 480 may be disposed on the fourth source / drain pattern 450. The fourth source / drain contact 480 is electrically connected to the fourth source / drain pattern 450.

[0162] The first contact silicide film 155 may be disposed between the first source / drain contact 180 and the first source / drain pattern 150. The second contact silicide film 255 may be disposed between the second source / drain contact 280 and the second source / drain pattern 250. The third contact silicide film 355 may be disposed between the third source / drain contact 380 and the third source / drain pattern 350. The fourth contact silicide film 455 may be disposed between the fourth source / drain contact 480 and the fourth source / drain pattern 450.

[0163] Although not specifically shown, a gate contact on the first gate electrode 120 may be disposed in the first gate capping pattern 145 .

[0164] The first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 are shown as having a single conductive film structure, but the present disclosure is not limited thereto. Alternatively, each of the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 may have a multilayer conductive film structure consisting of a barrier film and a plug film. The first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first contact silicide film 155, the second contact silicide film 255, the third contact silicide film 355, and the fourth contact silicide film 455 may include a metal silicide material.

[0165] The 2D material may include a 2D allotrope or a 2D compound, such as graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide, but the present disclosure is not limited thereto. That is, various other 2D materials are also suitable for semiconductor devices according to some embodiments of the present disclosure.

[0166] Figures 13 to 16 is a cross-sectional view or a plan view of a semiconductor device according to some embodiments of the present disclosure. Figures 13 to 16 Examples of Figures 1 to 12 The differences in embodiments.

[0167] Specifically, Fig.13 and Fig.14 Along Figure 1 The device is shown in cross-sectional view taken along line DD and line EE. Fig.15 and Fig.16 yes Figure 1 A plan view of a region P of the device is shown.

[0168] Reference Figures 13 to 16 , the first gate electrode 120 may not contact the first gate separation structure GCS1.

[0169] Each first gate separation structure GCS1 may have first sidewalls opposite to each other in the first direction D1, and the first gate insulating films 130 may extend along the first sidewalls of their corresponding first gate separation structures GCS1. The first gate insulating films 130 may extend along the boundary between the first gate separation structure GCS1 and the first gate electrode 120.

[0170] Each of the first connection gate electrode 120_1 and the second connection gate electrode 120_2 may include only a first gate electrode line portion (eg, Fig.11 Each of the first connection gate electrode 120_1 and the second connection gate electrode 120_2 may not include a first gate electrode protrusion (eg, Fig.11 The sidewall of the first gate separation structure GCS1 facing the first gate structure GS1 may appear as a straight line in a plan view.

[0171] Reference Fig.15 The first gate structure GS1 may be in contact with the first gate separation structure GCS1. For example, the first gate insulating film 130 may be in contact with the first gate separation structure GCS1.

[0172] Reference Fig.16 , a portion of the first gate spacer 140 may be disposed between the first gate structure GS1 and the first connection gate structure 120_1 and the second connection gate structure 120_2. The first connection gate structure 120_1 and the second connection gate structure 120_2 may not contact the first gate separation structure GCS1. The first gate spacer 140 may include a first portion and a second portion. The first portion of the first gate spacer 140 overlaps the first gate separation structure GCS1 in the first direction D1. The second portion of the first gate spacer 140 does not overlap the first gate separation structure GCS1 in the first direction D1. The thickness of the second portion of the first gate spacer 140 in the first direction D1 may be greater than the thickness of the first portion of the first gate spacer 140 in the first direction D1.

[0173] Reference Fig.13 The field insulating film 105 may include a protrusion 105_PI. The protrusion 105_PI of the field insulating film 105 may extend in a third direction D3 perpendicular to the first substrate 100 and away from the first substrate 100. The protrusion 105_PI of the field insulating film 105 may be formed in the pre-source / drain recess ( Fig.73 The first gate spacer 140 extending in the first direction D1 along the first gate separation structure GCS1 may be disposed on the protrusion 105_PI of the field insulation film 105. The source / drain etch stop film 185 may cover the sidewall of the protrusion 105_PI of the field insulation film 105.

[0174] Fig.17 and Fig.18 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Fig.17 and Fig.18 Examples of Figures 1 to 12 The differences in embodiments.

[0175] Reference Fig.17 , a height of the first channel separation structure CCW1 may be the same as a height of the first gate separation structure GCS1.

[0176] A height H31 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first gate separation structure GCS1 may be the same as a height H21 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first channel separation structure CCW1.

[0177] Reference Fig.18 , a height of the first channel separation structure CCW1 may be greater than a height of the first gate separation structure GCS1.

[0178] A height H31 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first gate separation structure GCS1 may be greater than a height H21 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first channel separation structure CCW1 .

[0179] Fig.19 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Fig.19 Examples of Figures 13 to 16 The differences in embodiments.

[0180] Reference Fig.19 , the first gate separation structure GCS1 may be disposed on the protrusion 105_PI of the field insulating film 105 .

[0181] The first gate separation structure GCS1 may not be recessed in the field insulation film 105. The first gate spacer 140 extending in the first direction D1 along the first gate separation structure GCS1 may be disposed on the protrusion 105_PI of the field insulation film 105.

[0182] Figure 20 to Figure 22 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 20 to Figure 22 Examples of Figures 1 to 12 The differences in embodiments.

[0183] Reference Figure 20 to Figure 22 , the semiconductor device according to some embodiments of the present disclosure may further include a first lower insulating pattern BDI1 , a second lower insulating pattern BDI2 , a third lower insulating pattern BDI3 , and a fourth lower insulating pattern BDI4 .

[0184] The first lower insulating pattern BDI1 may be disposed between the first lower pattern BP1 and the first channel pattern CH1 along the third direction D3. The first lower insulating pattern BDI1 may contact the upper surface BP1_US of the first lower pattern BP1. The first lower insulating pattern BDI1 may extend in the first direction D1 along the upper surface BP1_US of the first lower pattern BP1.

[0185] The second lower insulating pattern BDI2 may be disposed between the second lower pattern BP2 and the second channel pattern CH2 along the third direction D3. The second lower insulating pattern BDI2 may contact the upper surface BP2_US of the second lower pattern BP2. The second lower insulating pattern BDI2 may extend in the first direction D1 along the upper surface BP2_US of the second lower pattern BP2.

[0186] The third lower insulating pattern BDI3 may be disposed between the first lower pattern BP1 and the third channel pattern CH3 along the third direction D3. The third lower insulating pattern BDI3 may contact the upper surface BP1_US of the first lower pattern BP1. The third lower insulating pattern BDI3 may extend in the first direction D1 along the upper surface BP1_US of the first lower pattern BP1.

[0187] The fourth lower insulating pattern BDI4 may be disposed between the second lower pattern BP2 and the fourth channel pattern CH4 along the third direction D3. The fourth lower insulating pattern BDI4 may contact the upper surface BP2_US of the second lower pattern BP2. The fourth lower insulating pattern BDI4 may extend in the first direction D1 along the upper surface BP2_US of the second lower pattern BP2.

[0188] The first lower insulating pattern BDI1 may be spaced apart from the third lower insulating pattern BDI3 in the second direction D2. The first channel separation structure CCW1 may separate the first lower insulating pattern BDI1 from the third lower insulating pattern BDI3.

[0189] The second lower insulating pattern BDI2 may be spaced apart from the fourth lower insulating pattern BDI4 in the second direction D2. The second channel separation structure CCW2 may separate the second lower insulating pattern BDI2 from the fourth lower insulating pattern BDI4.

[0190] The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may not extend along the upper surface 105US of the field insulating film 105. The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may not cover the upper surface 105US of the field insulating film 105.

[0191] The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may include, for example, at least one of SiN, SiON, SiCN, and SiOCN. Alternatively, the first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may include SiO 2 .

[0192] The first channel pattern CH1 may further include a first sheet pattern NS1 and a first dummy sheet pattern NSD1 disposed between the first lower insulating pattern BDI1 and the first sheet pattern NS1 along the third direction D3. The first dummy sheet pattern NSD1 may make contact with the first lower insulating pattern BDI1.

[0193] The second channel pattern CH2 may further include a second sheet pattern NS2 and a second dummy sheet pattern NSD2 disposed between the second lower insulating pattern BDI2 and the second sheet pattern NS2 along the third direction D3. The second dummy sheet pattern NSD2 may make contact with the second lower insulating pattern BDI2.

[0194] The third channel pattern CH3 may further include a third sheet pattern NS3 and a third dummy sheet pattern NSD3 disposed between the third lower insulating pattern BDI3 and the third sheet pattern NS3 along the third direction D3. The third dummy sheet pattern NSD3 may make contact with the third lower insulating pattern BDI3.

[0195] The fourth channel pattern CH4 may further include a fourth sheet pattern NS4 and a fourth dummy sheet pattern NSD4 disposed between the fourth lower insulating pattern BDI4 and the fourth sheet pattern NS4 along the third direction D3. The fourth dummy sheet pattern NSD4 may make contact with the fourth lower insulating pattern BDI4.

[0196] The thickness of the first dummy sheet pattern NSD1, the second dummy sheet pattern NSD2, the third dummy sheet pattern NSD3, and the fourth dummy sheet pattern NSD4 in the third direction D3 may be less than the thickness of the first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4 in the third direction D3. The first dummy sheet pattern NSD1, the second dummy sheet pattern NSD2, the third dummy sheet pattern NSD3, and the fourth dummy sheet pattern NSD4 may include the same material as the first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4, although the embodiment is not limited thereto.

[0197] The first lower insulating pattern BDI1 may have an upper surface and a bottom surface that are opposite to each other in the third direction D3. The bottom surface of the first lower insulating pattern BDI1 may be in contact with the upper surface BP1_US of the first lower pattern BP1. The upper surface of the first lower insulating pattern BDI1 may be higher than the upper surface 105US of the field insulating film 105 relative to the bottom surface 105BS of the field insulating film 105. The upper surface of the first lower insulating pattern BDI1 may protrude beyond the upper surface 105US of the field insulating film 105. Since the first dummy sheet pattern NSD1 is in contact with the upper surface of the first lower insulating pattern BDI1, the first gate insulating film 130 may not be in contact with the upper surface of the first lower insulating pattern BDI1.

[0198] The first source / drain pattern 150 may contact the first dummy sheet pattern NSD1 and the first sheet pattern NS1. The first source / drain pattern 150 may contact the first lower insulating pattern BDI1. The first source / drain pattern 150 may not contact the first lower pattern BP1.

[0199] The second source / drain pattern 250 may contact the second dummy sheet pattern NSD2 and the second sheet pattern NS2. The second source / drain pattern 250 may contact the second lower insulating pattern BDI2. The second source / drain pattern 250 may not contact the second lower pattern BP2.

[0200] The third source / drain pattern 350 may contact the third dummy sheet pattern NSD3 and the third sheet pattern NS3. The third source / drain pattern 350 may contact the third lower insulating pattern BDI3. The third source / drain pattern 350 may not contact the first lower pattern BP1.

[0201] The fourth source / drain pattern 450 may contact the fourth dummy sheet pattern NSD4 and the fourth sheet pattern NS4. The fourth source / drain pattern 450 may contact the fourth lower insulating pattern BDI4. The fourth source / drain pattern 450 may not contact the second lower pattern BP2.

[0202] Fig.23 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Fig.24 and Fig.25 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Fig.26 and Fig. 27 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 23 to Figure 27 Examples of Figure 20 to Figure 22 The differences in embodiments.

[0203] Reference Fig.23 , the first source / drain pattern 150 may penetrate (ie, extend to) the first lower insulating pattern BDI1.

[0204] The first source / drain pattern 150 may make contact with the first lower insulating pattern BDI1 and the first lower pattern BP1.

[0205] Since the first lower insulating patterns BDI1 are separated from each other by the first source / drain pattern 150, a plurality of first lower insulating patterns BDI1 may be disposed on the upper surface BP1_US of the first lower pattern BP1. The first lower insulating patterns BDI1 may be arranged along the first direction D1. The first lower insulating patterns BDI1 may be positioned to overlap the first gate structure GS1 in the third direction D3.

[0206] For example, the above description of the first source / drain pattern 150 and the first lower insulating pattern BDI1 may also be applied to the second source / drain pattern 250 and the second lower insulating pattern BDI2, the third source / drain pattern 350 and the third lower insulating pattern BDI3, and the fourth source / drain pattern 450 and the fourth lower insulating pattern BDI4. In another example, the above description of the first source / drain pattern 150 and the first lower insulating pattern BDI1 may also be applied to the third source / drain pattern 350 and the third lower insulating pattern BDI3, but not to the second source / drain pattern 250, the second lower insulating pattern BDI2, the fourth source / drain pattern 450 and the fourth lower insulating pattern BDI4.

[0207] Reference Fig.24 and Fig.25 , the first channel pattern CH1 does not include a dummy sheet pattern ( Fig. 20 and Fig.21 of "NSD1").

[0208] Since no dummy sheet pattern is disposed between the first lower insulating pattern BDI1 and the first sheet pattern NS1 group, the first gate insulating film 130 may contact the upper surface of the first lower insulating pattern BDI1.

[0209] Similarly, in this embodiment, the second channel pattern CH2 , the third channel pattern CH3 , and the fourth channel pattern CH4 do not include dummy sheet patterns.

[0210] Reference Fig.26 and Fig. 27 The semiconductor device according to some embodiments of the present disclosure may further include a sacrificial semiconductor pattern 160SC, a sacrificial pattern capping film 160IP, a rear source / drain contact 175 , and a rear wiring 290 .

[0211] The first lower pattern BP1 and the second lower pattern BP2 may be disposed on the second substrate 200. The second substrate 200 may have a first surface 200US and a second surface 200BS opposite to each other in the third direction D3, respectively. The first lower pattern BP1 and the second lower pattern BP2 may be disposed on the first surface 200US, which may be an upper surface of the second substrate 200.

[0212] The second substrate 200 may include an insulating material, such as at least one of silicon oxide and silicon nitride, and a combination thereof. Figures 2 to 6 The first substrate 100 is then formed through a deposition process.

[0213] The field insulating film 105 may be in contact with the second substrate 200 . A bottom surface 105BS of the field insulating film 105 faces the second substrate 200 .

[0214] The sacrificial semiconductor pattern 160SC may be disposed in the first lower pattern BP1 and the second lower pattern BP2. The sacrificial semiconductor pattern 160SC may be disposed between the second substrate 200 and the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. The sacrificial semiconductor pattern 160SC may overlap the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 in the third direction D3.

[0215] The sacrificial pattern capping film 160IP may be disposed between the first source / drain pattern 150 and the sacrificial semiconductor pattern 160SC and between the second source / drain pattern 250 and the sacrificial semiconductor pattern 160SC. The sacrificial pattern capping film 160IP may be disposed between the third source / drain pattern 350 and the sacrificial semiconductor pattern 160SC and between the fourth source / drain pattern 450 and the sacrificial semiconductor pattern 160SC.

[0216] The sacrificial semiconductor pattern 160SC may include a material having an etch selectivity with respect to the first and second lower patterns BP1 and BP2. In the case where the first and second lower patterns BP1 and BP2 are Si patterns, the sacrificial semiconductor pattern 160SC may include SiGe. The sacrificial pattern capping film 160IP may include an insulating material.

[0217] The rear wiring 290 may be disposed in the second substrate 200. The rear wiring 290 may include a line portion and a via portion. The line portion of the rear wiring 290 is shown as extending along the first direction D1, but the present disclosure is not limited thereto. The via portion of the rear wiring 290 may extend upward from the line portion of the rear wiring 290 along the third direction D3. Contrary to what is depicted, the rear wiring 290 may not include a via portion.

[0218] The rear source / drain contact 175 may be disposed between the first source / drain pattern 150 and the rear wiring 290. The rear source / drain contact 175 electrically connects the first source / drain contact 150 and the rear wiring 290.

[0219] The rear source / drain contacts 175 are shown connected to some of the first source / drain patterns 150 , but the present disclosure is not limited thereto. Although not explicitly shown, the rear source / drain contacts 175 may be connected to the second source / drain patterns 250 , the third source / drain patterns 350 , and the fourth source / drain patterns 450 .

[0220] A rear contact silicide film 156 may be disposed between the rear source / drain contact 175 and the first source / drain pattern 150 .

[0221] The rear source / drain contact 175 and the rear wiring 290 are shown as a single conductive film, but the present disclosure is not limited thereto. Although not explicitly shown, at least one of the rear source / drain contact 175 and the rear wiring 290 may have a multilayer conductive film structure including a barrier film and a filling film. The rear source / drain contact 175 and the rear wiring 290 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material.

[0222] Figures 28 to 30 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figures 28 to 30 Examples of Figures 1 to 12 The differences in embodiments.

[0223] Reference Fig.28 , the first gate separation structure GCS1 may contact the first source / drain pattern 150 and the second source / drain pattern 250 .

[0224] The source / drain etch stop film 185 may not be disposed on the field insulating film 105 between the first source / drain pattern 150 and the first gate separation structure GCS1. The source / drain etch stop film 185 may not be disposed between the second source / drain pattern 250 and the first gate separation structure GCS1.

[0225] Reference Fig.29 , a distance W21 between the first gate separation structure GCS1 and the first channel separation structure CCW1 in the second direction D2 may be greater than a distance W22 between the first gate separation structure GCS1 and the second channel separation structure CCW2 in the second direction D2.

[0226] The first gate separation structure GCS1 may not contact the first source / drain pattern 150. The first gate separation structure GCS1 may contact the second source / drain pattern 250.

[0227] Reference Fig.30 , the semiconductor device according to some embodiments of the present disclosure may further include an inner spacer 140IN disposed between the second source / drain pattern 250 and the first inner gate structure INT_GS1 .

[0228] The inner spacer 140IN may be disposed between the second lower pattern BP2 and its corresponding second sheet pattern NS2 adjacent to each other in the third direction D3 and between the corresponding second sheet patterns NS2 The first inner gate structure INT_GS1 may not contact the second source / drain pattern 250 .

[0229] The inner spacer 140IN may include, for example, SiN, SiON, SiO 2 , at least one of SiOCN, SiBN, SiOBN, SiOC and combinations thereof.

[0230] Fig.31 is a layout diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 32 to Figure 35 is along Fig.31 The device shown is a cross-sectional view taken along lines AA, BB, CC, and EE. Figure 31 to Figure 35 Examples of Figures 1 to 12 The differences in embodiments.

[0231] Reference Figure 31 to Figure 35 The semiconductor device according to some embodiments of the present disclosure may further include a second gate electrode 220 and a third gate electrode 320 respectively between the first gate electrodes 120 .

[0232] The second gate structure GS2 and the third gate structure GS3 may be disposed between the first gate structures GS1 adjacent to each other along the first direction D1. The second gate structure GS2 and the third gate structure GS3 may be aligned with each other in the second direction D2.

[0233] The second gate structure GS2 and the third gate structure GS3 may be spaced apart from each other in the second direction D2. The first gate separation structure GCS1 may separate the second gate structure GS2 from the third gate structure GS3. For example, the first gate structure GS1 may be separated by the first gate separation structure GCS1, thereby forming the second gate structure GS2 and the third gate structure GS3.

[0234] The second gate structure GS2 may be disposed between the first channel separation structure CCW1 and the first gate separation structure GCS1. The second gate structure GS2 may contact the first channel separation structure CCW1 and the first gate separation structure GCS1. The second gate structure GS2 may be disposed on the first lower pattern BP1.

[0235] The third gate structure GS3 may be disposed between the second channel separation structure CCW2 and the first gate separation structure GCS1. The third gate structure GS3 may contact the second channel separation structure CCW2 and the first gate separation structure GCS1. The third gate structure GS3 may be disposed on the second lower pattern BP2.

[0236] The second gate structure GS2 may contact the upper surface 105US of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. Some of the plurality of first channel patterns CH1 may be disposed between the second gate structure GS2 and the first channel separation structure CCW1.

[0237] The third gate structure GS3 may contact the upper surface 105US of the field insulating film 105 and the upper surface BP2_US of the second lower pattern BP2. Some of the plurality of second channel patterns CH2 may be disposed between the third gate structure GS3 and the second channel separation structure CCW2.

[0238] The second gate structure GS2 may include a second gate electrode 220 and a second gate insulating film 230. The third gate structure GS3 may include a third gate electrode 320 and a third gate insulating film 330.

[0239] The second gate structure GS2 may include a second inner gate structure INT_GS2. The second inner gate structure INT_GS2 may be disposed between the first lower pattern BP1 and the corresponding first sheet pattern NS1 adjacent to each other along the third direction D3 and between the corresponding first sheet patterns NS1. The third gate structure GS3 may include a third inner gate structure INT_GS3. The third inner gate structure INT_GS3 may be disposed between the second lower pattern BP2 and the corresponding second sheet pattern NS2 adjacent to each other along the third direction D3 and between the corresponding second sheet patterns NS2.

[0240] The second gate electrode 220 and the third gate electrode 320 may be disposed between the first channel separation structure CCW1 and the second channel separation structure CCW2 adjacent to each other in the second direction D2. The second gate electrode 220 and the third gate electrode 320 may be aligned in the second direction D2. The second gate electrode 220 and the third gate electrode 320 may be disposed between the first gate electrodes 120 adjacent to each other in the first direction D1. For example, the second gate electrode 220 and the third gate electrode 320 may be disposed between the first connection gate electrode 120_1 and the third connection gate electrode 120_3.

[0241] The second gate insulating film 230 may extend along the upper surface 105US of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1 (along the first direction D1 and / or the second direction D2). The second gate insulating film 230 may extend along a portion of the sidewall CCW1_SW of the first channel separation structure CCW1. The second gate insulating film 230 is disposed between the second gate electrode 220 and the first sheet pattern NS1.

[0242] The third gate insulating film 330 may extend along the upper surface 105US of the field insulating film 105 and the upper surface BP2_US of the second lower pattern BP2. The third gate insulating film 330 may extend along a portion of the sidewall CCW2_SW of the second channel separation structure CCW2. The third gate insulating film 330 is disposed between the third gate electrode 320 and the second sheet pattern NS2.

[0243] The second gate spacer 240 may be disposed on a sidewall of the second gate structure GS2. The third gate spacer 340 may be disposed on a sidewall of the third gate structure GS3.

[0244] The second gate capping pattern 245 may be disposed on the second gate structure GS2. The second gate capping pattern 245 may be disposed between the first channel separation structure CCW1 and the first gate separation structure GCS1. The second gate capping pattern 245 may contact the first channel separation structure CCW1 and the first gate separation structure GCS1.

[0245] The third gate capping pattern 345 may be disposed on the third gate structure GS3. The third gate capping pattern 345 may be disposed between the second channel separation structure CCW2 and the first gate separation structure GCS1. The third gate capping pattern 345 may contact the second channel separation structure CCW2 and the first gate separation structure GCS1.

[0246] The first gate separation structure GCS1 may contact the second gate structure GS2 and the third gate structure GS3 , respectively. The first gate separation structure GCS1 may contact the second gate electrode 220 and the second gate insulating film 230 . The first gate separation structure GCS1 may contact the third gate electrode 320 and the third gate insulating film 330 .

[0247] Fig.36 is a layout diagram of a semiconductor device according to some embodiments of the present disclosure. Fig.37 and Fig.38 is along Fig.36 A cross-sectional view of the device taken along lines CC and EE is shown. Figure 39 to Figure 41 yes Fig.36 FIG. 1 is a plan view of a region Q of the device shown in FIG. For convenience, the following description will be made of Figure 36 to Figure 41 Examples of Figures 1 to 12 The differences in embodiments.

[0248] Reference Figure 36 to Figure 41 The semiconductor device according to some embodiments of the present disclosure may further include a second gate separation structure GCS2 , a second gate electrode 220 , and a third gate electrode 320 .

[0249] The second gate structure GS2 including the second gate electrode 220 and the third gate structure GS3 including the third gate electrode 320 may be substantially the same as Figure 31 to Figure 35 The corresponding parts are the same and will be described below, focusing mainly on Figure 31 to Figure 35 The difference between the corresponding parts.

[0250] The second gate separation structure GCS2 may be disposed between the second gate structure GS2 and the third gate structure GS3. The second gate separation structure GCS2 may be disposed between the first gate separation structures GCS1 adjacent to each other along the first direction D1.

[0251] The second gate separation structure GCS2 separates the second gate structure GS2 from the third gate structure GS3. For example, the first gate structure GS1 may be separated in the first direction D1 by the second gate separation structure GCS2, thereby forming the second gate structure GS2 and the third gate structure GS3.

[0252] The second gate capping pattern 245 may be disposed between the first channel separation structure CCW1 and the second gate separation structure GCS2. The second gate capping pattern 245 may contact the first channel separation structure CCW1 and the second gate separation structure GCS2.

[0253] The third gate capping pattern 345 may be disposed between the second channel separation structure CCW2 and the second gate separation structure GCS2. The third gate capping pattern 345 may contact the second channel separation structure CCW2 and the second gate separation structure GCS2.

[0254] The second gate separation structure GCS2 may be in contact with the second gate structure GS2 and the third gate structure GS3. The second gate separation structure GCS2 may be in contact with the second gate electrode 220 and the second gate insulating film 230. The second gate separation structure GCS2 may be in contact with the third gate electrode 320 and the third gate insulating film 330. The second gate separation structure GCS2 may be in contact with the first gate separation structure GCS1, and the first gate separation structure GCS1 is disposed on both sides of the second gate separation structure GCS2 along the first direction D1.

[0255] The second gate separation structure GCS2 may include an insulating material. The second gate separation structure GCS2 may include, for example, SiN, SiON, SiO 2At least one of SiOCN, SiBN, SiOBN, SiOC, AlO, and combinations thereof. The second gate separation structure GCS2 is shown as a single film, but the present disclosure is not limited thereto.

[0256] A height "H21+H22" from the bottom surface 105BS of the field insulating film 105 to the upper surface CCW1_US of the first channel separation structure CCW1 in the third direction D3 may be the same as a height "H41+H42" from the bottom surface 105BS of the field insulating film 105 to the upper surface GCS2_US of the second gate separation structure GCS2. For example, the upper surface GCS2_US of the second gate separation structure GCS2 may be disposed on the same plane as the upper surface CCW1_US of the first channel separation structure CCW1.

[0257] A height H22 of the first channel separation structure CCW1 in the third direction D3 may be different from a height H42 of the second gate separation structure GCS2 in the third direction D3. A height H41 from the bottom surface 105BS of the field insulation film 105 to the lowermost portion of the second gate separation structure GCS2 in the third direction D3 may be different from a height H21 from the bottom surface 105BS of the field insulation film 105 to the lowermost portion of the second gate separation structure GCS2. Contrary to what is depicted, the height H22 of the first channel separation structure CCW1 may be the same as the height H42 of the second gate separation structure GCS2.

[0258] A height H32 of the first gate separation structure GCS1 in the third direction D3 may be different from a height H42 of the second gate separation structure GCS2 in the third direction D3. A height H41 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the second gate separation structure GCS2 may be different from a height H31 from the bottom surface 105BS of the field insulating film 105 to the lowermost portion of the first gate separation structure GCS1. Contrary to what is depicted, the height H32 of the first gate separation structure GCS1 may be the same as the height H42 of the second gate separation structure GCS2.

[0259] Reference Fig.39 The width W31 of the first gate separation structure GCS1 in the second direction D2 may be the same as the width W32 of the second gate separation structure GCS2 in the second direction D2. For example, the width W31 of the first gate separation structure GCS1 in the second direction D2 may be measured on the upper surface GCS1_US of the first gate separation structure GCS1.

[0260] A distance W33 between the first channel separation structure CCW1 and the second gate separation structure GCS2 in the second direction D2 may be the same as a distance W34 between the second channel separation structure CCW2 and the second gate separation structure GCS2 in the second direction D2.

[0261] Reference Fig.40 , the width W31 of the first gate separation structure GCS1 in the second direction D2 may be different from the width W32 of the second gate separation structure GCS2 in the second direction D2. For example, the width W31 of the first gate separation structure GCS1 in the second direction D2 may be greater than the width W32 of the second gate separation structure GCS2 in the second direction D2, but the present disclosure is not limited thereto.

[0262] Reference Fig.41 , a distance W33 between the first channel separation structure CCW1 and the second gate separation structure GCS2 in the second direction D2 may be different from a distance W34 between the second channel separation structure CCW2 and the second gate separation structure GCS2 in the second direction D2.

[0263] Figures 42 to 67 are layout diagrams or cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0264] Reference Figure 42 to Figure 44 , a first mold fin pattern FMS1 and a second mold fin pattern FMS2 may be formed on the first substrate 100 .

[0265] The first and second mold fin patterns FMS1 and FMS2 may extend in the first direction D1. The first and second mold fin patterns FMS1 and FMS2 may be spaced apart from each other in the second direction D2. The first and second mold fin patterns FMS1 and FMS2 may be defined by fin trenches FT extending in the first direction D1.

[0266] The first mold fin pattern FMS1 may include a first lower pattern BP1 and a first pre-pattern structure PFS1. The second mold fin pattern FMS2 may include a second lower pattern BP2 and a second pre-pattern structure PFS2. The first pre-pattern structure PFS1 is formed on the first lower pattern BP1. The second pre-pattern structure PFS2 is formed on the second lower pattern BP2.

[0267] Each of the first and second pre-pattern structures PFS1 and PFS2 may include a plurality of pre-sacrificial patterns SC_L and a plurality of pre-active patterns ACT_L alternately stacked with the pre-sacrificial patterns SC_L along the third direction D3. For example, the pre-active patterns ACT_L may include a silicon film, and the pre-sacrificial patterns SC_L may include a SiGe film.

[0268] A field insulating film 105 may be formed on the first substrate 100. The field insulating film 105 may partially fill the fin trench FT.

[0269] Reference Figures 45 to 48 , a dummy gate electrode 120DP may be formed on the first and second mold fin patterns FMS1 and FMS2 .

[0270] The dummy gate electrode 120DP may include an extension portion 120DP_L extending in the second direction D2, and a connection portion 120DP_E crossing the extension portion 120DP_L and extending in the first direction D1. In a plan view, the dummy gate electrode 120DP may be configured to have a mesh shape.

[0271] The extension portion 120DP_L of the dummy gate electrode 120DP may be formed on the first and second mold fin patterns FMS1 and FMS2 . The extension portion 120DP_L of the dummy gate electrode 120DP may cross the first and second mold fin patterns FMS1 and FMS2 .

[0272] The connection portion 120DP_E of the dummy gate electrode 120DP may connect each group of the extension portions 120DP_L adjacent to each other in the first direction D1. The connection portion 120DP_E of the dummy gate electrode 120DP may be formed between the first mold fin pattern FMS1 and the second mold fin pattern FMS2. The connection portion 120DP_E of the dummy gate electrode 120DP may be formed on the field insulating film 105.

[0273] A dummy gate insulating film 130P is formed between the dummy gate electrode 120DP and the first mold fin pattern FMS1 and between the dummy gate electrode 120DP and the second mold fin pattern FMS2. A dummy gate capping film 120HM is formed on the dummy gate electrode 120DP. The dummy gate capping film 120HM is formed along the upper surface of the dummy gate electrode 120DP.

[0274] The dummy gate insulating film 130P may include, for example, silicon oxide, but the present disclosure is not limited thereto. The dummy gate electrode 120DP may include, for example, polysilicon, but the present disclosure is not limited thereto. The dummy gate capping film 120HM may include, for example, silicon nitride, but the present disclosure is not limited thereto.

[0275] Reference Figures 49 to 51 , a dummy gate spacer 140P may be formed on a sidewall of the dummy gate electrode 120DP.

[0276] During the formation of the dummy gate spacer 140P, a first pre-source / drain recess 150R_P may be formed in the first mold fin pattern FMS1 using the dummy gate electrode 120DP as a mask.

[0277] Likewise, a second pre-source / drain recess 250R_P may be formed in the second mold fin pattern FMS2 using the dummy gate electrode 120DP as a mask. The first pre-source / drain recess 150R_P and the second pre-source / drain recess 250R_P may be formed simultaneously.

[0278] The first pre-source / drain recess 150R_P and the second pre-source / drain recess 250R_P may be formed between their corresponding groups of extensions 120DP_L adjacent to each other along the first direction D1. The first pre-source / drain recess 150R_P may be formed by removing at least a portion of the first pre-pattern structure PFS1. The second pre-source / drain recess 250R_P may be formed by removing at least a portion of the second pre-pattern structure PFS2.

[0279] Reference Figure 52 to Figure 55 , a sacrificial insulating film 50 may be formed on the first substrate 100 .

[0280] The sacrificial insulating film 50 may fill the first pre-source / drain recess 150R_P and the second pre-source / drain recess 250R_P. The sacrificial insulating film 50 may fill the space in the dummy gate electrode 120DP. The sacrificial insulating film 50 may be formed up to the upper surface of the dummy gate capping film 120HM.

[0281] Thereafter, a first channel separation structure CCW1 may be formed on the first lower pattern BP1. The first channel separation structure CCW1 may extend along the first direction D1. The first channel separation structure CCW1 may be formed in the first pre-pattern structure PFS1 and the sacrificial insulating film 50. The first channel separation structure CCW1 may separate the first pre-pattern structure PFS1 into two parts. Therefore, a first upper pattern structure UP1 and a third upper pattern structure UP3 may be formed on the first lower pattern BP1. Similarly, the first channel separation structure CCW1 may separate the first pre-source / drain recess 150R_P into two first source / drain recesses 150R.

[0282] A second channel separation structure CCW2 may be formed on the second lower pattern BP2. The second channel separation structure CCW2 may extend along the first direction D1. The second channel separation structure CCW2 may be formed in the second pre-pattern structure PFS2 and the sacrificial insulating film 50. The second channel separation structure CCW2 may separate the second pre-pattern structure PFS2 into two parts. Therefore, a second upper pattern structure UP2 and a fourth upper pattern structure UP4 may be formed on the second lower pattern BP2. Similarly, the second channel separation structure CCW2 may separate the second pre-source / drain recess 250R_P into two second source / drain recesses 250R. The first channel separation structure CCW1 and the second channel separation structure CCW2 may be formed simultaneously.

[0283] Each of the first, second, third, and fourth upper pattern structures UP1, UP2, UP3, and UP4 may include a plurality of sacrificial patterns SC_P and a plurality of active patterns ACT_P alternately stacked with the sacrificial patterns SC_P in the third direction D3.

[0284] The dummy gate spacers 140P may be separated by the first channel separation structure CCW1 and the second channel separation structure CCW2 . Thus, the first gate spacers 140 may be formed.

[0285] Reference Figure 52 to Figure 58 , remove the sacrificial insulating film 50.

[0286] Thus, the first source / drain recess 150R and the second source / drain recess 250R may be exposed. In other words, the first upper pattern structure UP1, the second upper pattern structure UP2, the third upper pattern structure UP3, and the fourth upper pattern structure UP4 may be exposed.

[0287] The first source / drain pattern 150 and the third source / drain pattern 350 may be formed in the first source / drain recess 150R. The first source / drain pattern 150 and the third source / drain pattern 350 may be formed on the first lower pattern BP1.

[0288] The first source / drain pattern 150 and the third source / drain pattern 350 may be separated by the first channel separation structure CCW1. The first source / drain pattern 150 and the third source / drain pattern 350 may be in contact with the first channel separation structure CCW1. The first source / drain pattern 150 may be in contact with the first upper pattern structure UP1. Although not specifically shown, the third source / drain pattern 350 may be in contact with the third upper pattern structure UP3.

[0289] The second source / drain pattern 250 and the fourth source / drain pattern 450 may be formed in the second source / drain recess 250R. The second source / drain pattern 250 and the fourth source / drain pattern 450 may be formed on the second lower pattern BP2.

[0290] The second source / drain pattern 250 and the fourth source / drain pattern 450 may be separated by the second channel separation structure CCW2. The second source / drain pattern 250 and the fourth source / drain pattern 450 may contact the second channel separation structure CCW2. The second source / drain pattern 250 may contact the second upper pattern structure UP2. Although not specifically shown, the fourth source / drain pattern 450 may contact the fourth upper pattern structure UP4.

[0291] Reference Figure 56 to Figure 58, the second source / drain pattern 250 , the third source / drain pattern 350 , and the fourth source / drain pattern 450 may contact the second upper pattern structure UP2 , the third upper pattern structure UP3 , and the fourth upper pattern structure UP4 , respectively.

[0292] After forming the first and third source / drain patterns 150 and 350, the second and fourth source / drain patterns 250 and 450 may be formed. Alternatively, after forming the second and fourth source / drain patterns 250 and 450, the first and third source / drain patterns 150 and 350 may be formed.

[0293] Thereafter, a source / drain etch stop film 185 and an upper interlayer insulating film 190 may be formed on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. During the formation of the source / drain etch stop film 185 and the upper interlayer insulating film 190, the dummy gate capping film 120HM may be removed. The dummy gate electrode 120DP may be exposed.

[0294] Reference Figure 59 to Figure 61 , the dummy gate electrode 120DP and the dummy gate insulating film 130P (see Fig.58 ) to form a gate trench 120t.

[0295] The gate trench 120t may expose the first, second, third, and fourth upper pattern structures UP1, UP2, UP3, and UP4. The gate trench 120t may include an extension portion 120t_L extending in the second direction D2, and a connection portion 120t_E crossing the extension portion 120t_L and extending in the first direction D1.

[0296] The extension 120t_L of the gate trench 120t may be formed at a position where the extension 120DP_L of the dummy gate electrode 120DP has been removed. The connection 120t_E of the gate trench 120t may be formed at a position where the connection 120DP_E of the dummy gate electrode 120DP has been removed. The gate trench 120t may have a mesh shape.

[0297] Reference Fig.62 and Fig.63 By removing the sacrificial pattern SC_P exposed by the gate trench 120 t of each first upper pattern structure UP1 , a first sheet pattern NS1 contacting the first channel separation structure CCW1 and the first source / drain pattern 150 may be formed.

[0298] By removing the sacrificial pattern SC_P of each second upper pattern structure UP2 exposed by the gate trench 120 t , a second sheet pattern NS2 contacting the second channel separation structure CCW2 and the second source / drain pattern 250 may be formed.

[0299] The third sheet pattern NS3 may be formed by removing the sacrificial pattern SC_P exposed by the gate trench 120 t of each third upper pattern structure UP3 , and the fourth sheet pattern NS4 may be formed by removing the sacrificial pattern SC_P exposed by the gate trench 120 t of each fourth upper pattern structure UP4 .

[0300] Reference Figure 62 to Figure 66 , a pre-gate structure including a pre-gate electrode 120PP and a first gate insulating film 130 may be formed in the gate trench 120t.

[0301] A first gate capping pattern 145 may be formed on the pre-gate electrode 120PP and the first gate insulating film 130. The pre-gate electrode 120PP may include an extension 120PL and a connection 120PE. The extension 120PL of the pre-gate electrode 120PP extends along the second direction D2. The extension 120PL of the pre-gate electrode 120PP may be formed in the extension 120t_L of the gate trench 120t. The extension 120PL of the pre-gate electrode 120PP may intersect the first sheet pattern NS1 and the second sheet pattern NS2.

[0302] The connection portion 120PE of the pre-gate electrode 120PP extends in the first direction D1. The connection portion 120PE of the pre-gate electrode 120PP may be formed in the connection portion 120t_E of the gate trench 120t. The connection portion 120PE of the pre-gate electrode 120PP connects each group of the extension portions 120PL of the pre-gate electrode 120PP adjacent to each other in the first direction D1.

[0303] Reference Figure 64 to Figure 67 , a first gate separation structure GCS1 may be formed between the extension portions 120PL of the pre-gate electrode 120PP that are adjacent to each other in the first direction D1.

[0304] The first gate separation structure GCS1 may separate the extension portions 120PL of the pre-gate electrodes 120PP adjacent to each other in the first direction D1. During the formation of the first gate separation structure GCS1, the connection portion 120PE of the pre-gate electrode 120PP may be removed.

[0305] At least a portion of the first gate insulating film 130 extending along the sidewall and the bottom surface of the connection portion 120PE of the pre-gate electrode 120PP may be removed. Thus, the first gate electrode 120 may be formed.

[0306] Although not specifically shown, the first gate separation structure GCS1 may separate at least one extension portion 120PL of the pre-gate electrode 120PP into two parts. In this case, the two parts may become Fig.34 The second gate electrode 220 and the third gate electrode 320 are formed.

[0307] Figures 68 to 78 is a layout diagram or cross-sectional diagram showing an intermediate step of an example method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Specifically, Fig.68 and Fig.69 Shown in Figure 42 to Figure 44 The steps to be performed after the step shown.

[0308] Reference Fig.68 and Fig.69 , a plurality of dummy gate electrodes 120DP may be formed on the first mold fin pattern FMS1 and the second mold fin pattern FMS2 .

[0309] The dummy gate electrode 120DP may extend in the second direction D2. The dummy gate electrodes 120DP are not connected to each other. The dummy gate electrode 120DP may have a linear shape. The dummy gate electrode 120DP may cross the first mold fin pattern FMS1 and the second mold fin pattern FMS2.

[0310] along Fig.68 The cross-sectional views taken along the lines AA and CC can be respectively Fig.46 and Fig.47 same.

[0311] Reference Fig.70 and Fig.71 , a first gate separation structure GCS1 may be formed on the field insulating film 105 .

[0312] The first gate separation structure GCS1 may be formed between the first mold fin pattern FMS1 and the second mold fin pattern FMS2 The first gate separation structure GCS1 connects a pair of dummy gate electrodes 120DP adjacent to each other in the first direction D1.

[0313] along Fig.70 The cross-sectional views taken along the lines AA and CC can be respectively Fig.46 and Fig.47 same.

[0314] Reference Fig.72 and Fig.73 , a dummy gate spacer 140P may be formed on a sidewall of the dummy gate electrode 120DP and a sidewall of the first gate separation structure GCS1.

[0315] During the formation of the dummy gate spacer 140P, the first pre-source / drain recess 150R_P and the second pre-source / drain recess 250R_P may be formed using the dummy gate electrode 120DP as a mask. The first pre-source / drain recess 150R_P may be formed in the first mold fin pattern FMS1. The second pre-source / drain recess 250R_P may be formed in the second mold fin pattern FMS2.

[0316] along Fig.72 The cross-sectional view taken along line AA can be compared with Fig.50 same.

[0317] Reference Fig.74 and Fig.75 , a first channel separation structure CCW1 may be formed on the first lower pattern BP1. A second channel separation structure CCW2 may be formed on the second lower pattern BP2.

[0318] During the formation of the first and second channel separation structures CCW1 and CCW2, the first, second, third, and fourth upper pattern structures UP1, UP2, UP3, and UP4 may be formed. Also, the first and second source / drain recesses 150R and 250R may be formed. The first gate spacer 140 may be formed.

[0319] You can refer to the above Figure 52 to Figure 55 The formation of the first and second trench separation structures CCW1 and CCW2 is performed in substantially the same manner as described.

[0320] Reference Figure 74 to Figure 76 , remove the sacrificial insulating film 50.

[0321] The first source / drain pattern 150 and the third source / drain pattern 350 may be formed in the first source / drain recess 150R. The second source / drain pattern 250 and the fourth source / drain pattern 450 may be formed in the second source / drain recess 250R.

[0322] Thereafter, a source / drain etch stop film 185 and an upper interlayer insulating film 190 may be formed on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. The dummy gate electrode 120DP may be exposed.

[0323] Fig.76 The steps described in can be compared with Figure 56 to Figure 58 The steps described are essentially the same.

[0324] Reference Figure 59 to Figure 63 as well as Figure 76 to Figure 78, the gate trench 120t may be formed by removing the dummy gate electrode 120DP and the dummy gate insulating film 130P.

[0325] The gate trench 120t may expose the first upper pattern structure UP1, the second upper pattern structure UP2, the third upper pattern structure UP3, and the fourth upper pattern structure UP4. The sacrificial pattern SC_P may be removed from each of the exposed first upper pattern structure UP1, the second upper pattern structure UP2, the third upper pattern structure UP3, and the fourth upper pattern structure UP4. Thus, the first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4 may be formed.

[0326] Thereafter, a first gate electrode 120 and a first gate insulating film 130 may be formed in the gate trench 120t. The first gate electrode 120 may cross the first sheet pattern NS1 and the second sheet pattern NS2.

[0327] Figure 79 to Figure 83 are cross-sectional views illustrating intermediate steps of an example method of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0328] Specifically, Fig.79 and Fig.80 Along Fig.42 A cross-sectional view taken along line AA and line CC, and Fig.81 , Fig.82 , Fig.83 Along Fig.45 Cross-sectional views taken along lines AA, CC and DD.

[0329] Reference Fig.79 and Fig.80 The first mold fin pattern FMS1 may include a lower buffer pattern BBF disposed between the first lower pattern BP1 and the first pre-pattern structure PFS1 along the third direction D3. The first pre-pattern structure PFS1 may further include a pre-dummy active pattern ACT_DL.

[0330] Similarly, the second mold fin pattern FMS2 may include a lower buffer pattern BBF disposed between the second lower pattern BP2 and the second pre-pattern structure PFS2 along the third direction D3 The second pre-pattern structure PFS2 may further include a pre-dummy active pattern ACT_DL.

[0331] Alternatively, contrary to what is depicted, in some embodiments, the first and second pre-pattern structures PFS1 and PFS2 may not include the pre-dummy active pattern ACT_DL.

[0332] For example, the pre-dummy active pattern ACT_DL may include a Si film. The lower buffer pattern BBF may include a material having an etch selectivity with respect to the pre-active pattern ACT_L and the pre-sacrificial pattern SC_L.

[0333] For example, the pre-sacrificial pattern SC_L may include a SiGe film doped with C, and the lower buffer pattern BBF may include a SiGe film. In another example, the pre-sacrificial pattern SC_L may include a SiGe film, and the lower buffer pattern BBF may include a SiGe film doped with C. The etching rate of the SiGe film may vary depending on whether the SiGe film is doped with C. That is, the pre-sacrificial pattern SC_L may have an etching selectivity relative to the lower buffer pattern BBF.

[0334] The etching selectivity of the lower buffer pattern BBF and the pre-active pattern ACT_L is not particularly limited. The material of the lower buffer pattern BBF is not limited to a specific type as long as it exhibits etching selectivity to the pre-active pattern ACT_L and the pre-sacrificial pattern SC_L.

[0335] Reference Figure 81 to Figure 83 , a dummy gate electrode 120DP may be formed on the first and second mold fin patterns FMS1 and FMS2 .

[0336] Thereafter, the lower buffer pattern BBF may be reset with a pre-lower insulating pattern BDID. Specifically, a space may be formed between the first lower pattern BP1 and the first pre-pattern structure PFS1 and between the second lower pattern BP2 and the second pre-pattern structure PFS2 by removing the lower buffer pattern BBF. Since the lower buffer pattern BBF has an etching selectivity with respect to the pre-sacrificial pattern SC_L and the lower buffer pattern BBF, the lower buffer pattern BBF may be selectively removed. The space between the first lower pattern BP1 and the first pre-pattern structure PFS1 and the space between the second lower pattern BP2 and the second pre-pattern structure PFS2 may be filled with an insulating material. Thus, a pre-lower insulating pattern BDI_D may be formed.

[0337] Afterwards, you can execute Figures 49 to 67 During the formation of the first and second trench separation structures CCW1 and CCW2, each of the pre-lower insulating patterns BDI_D may be separated into two parts.

[0338] Alternatively, you can Fig.79 and Fig.80 Follow the steps shown Figures 68 to 78 Steps shown.

[0339] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. A person skilled in the art of the present invention will be able to understand that the present invention can be implemented in other specific forms without changing the technical ideas or essential features of the present invention. Therefore, it should be understood that the above embodiments are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor device, comprising: A first trench separation structure extending along a first direction; a second trench separation structure spaced apart from the first trench separation structure in a second direction intersecting the first direction and extending along the first direction; a plurality of first gate structures spaced apart from each other in the first direction between the first trench separation structure and the second trench separation structure, the first gate structures respectively contacting the first trench separation structure and the second trench separation structure and comprising corresponding first gate electrodes and corresponding first gate insulating films; a first channel pattern including a corresponding plurality of first sheet patterns, the corresponding plurality of first sheet patterns being spaced apart from each other in a third direction perpendicular to the first direction and the second direction and contacting the first channel separation structure; a second channel pattern, comprising a corresponding plurality of second sheet-like patterns, the corresponding plurality of second sheet-like patterns being spaced apart from each other in the third direction and contacting the second channel separation structure; a first source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the first channel pattern and the first channel separation structure, respectively; a second source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the second channel pattern and the second channel separation structure, respectively; as well as The first gate separation structure is between the first source / drain pattern and the second source / drain pattern.

2. The semiconductor device according to claim 1, wherein An upper surface of the first trench separation structure is coplanar with an upper surface of the first gate separation structure.

3. The semiconductor device according to claim 2, wherein: A first height of the first trench separation structure is different from a second height of the first gate separation structure, and the first height and the second height are measured along the third direction relative to a bottom surface of the semiconductor device.

4. The semiconductor device according to claim 1, further comprising: a first lower pattern and a second lower pattern extending along the first direction and spaced apart from each other in the second direction, in, A portion of the first trench separation structure is in the first lower pattern, A portion of the second trench separation structure is in the second lower pattern, The first channel pattern is on the first lower pattern, and The second channel pattern is on the second lower pattern.

5. The semiconductor device according to claim 4, further comprising: A lower insulating pattern is located between the first lower pattern and the first channel pattern in the third direction and contacts an upper surface of the first lower pattern.

6. The semiconductor device according to claim 4, wherein: The first gate insulating film contacts upper surfaces of the first lower pattern and the second lower pattern.

7. The semiconductor device according to claim 1, wherein The first gate separation structure contacts the first gate electrode.

8. The semiconductor device according to claim 1, wherein The first gate separation structure is in contact with the first gate insulating film.

9. The semiconductor device according to claim 1, further comprising: The second gate structure and the third gate structure are located between two first gate structures adjacent to each other in the first direction in the first gate structure, and the second gate structure and the third gate structure are spaced apart from each other in the second direction, in, The second gate structure and the third gate structure include corresponding second gate electrodes and corresponding second gate insulating films, and The first gate separation structure separates the second gate structure from the third gate structure in the second direction.

10. The semiconductor device according to claim 1, further comprising: A second gate structure and a third gate structure are located between two first gate structures adjacent to each other in the first direction among the first gate structures, and the second gate structure and the third gate structure are spaced apart from each other in the second direction; as well as a second gate separation structure, between the second gate structure and the third gate structure, in, The second gate structure and the third gate structure include corresponding second gate electrodes and corresponding second gate insulating films, and The second gate separation structure contacts the first gate separation structure and the second gate structure and the third gate structure.

11. The semiconductor device according to claim 10, wherein: A first width of the first gate separation structure in the second direction is different from a second width of the second gate separation structure in the second direction.

12. The semiconductor device according to claim 1, further comprising: sacrificial semiconductor pattern and sacrificial pattern capping film, in, Each of the sacrificial semiconductor patterns overlaps with a corresponding one of the first source / drain patterns in the third direction, and The sacrificial pattern capping film is between the sacrificial semiconductor pattern and the first source / drain pattern.

13. A semiconductor device comprising: A first trench separation structure extending along a first direction; a second trench separation structure spaced apart from the first trench separation structure in a second direction intersecting the first direction and extending along the first direction; a plurality of first gate structures spaced apart from each other in the first direction between the first trench separation structure and the second trench separation structure, the first gate structures contacting the first trench separation structure and the second trench separation structure and including corresponding first gate electrodes and corresponding first gate insulating films; a gate capping pattern on the first gate electrode and in contact with the first trench separation structure and the second trench separation structure; Gate spacers, respectively on the side walls of the first gate structure; a first channel pattern including a corresponding plurality of first sheet patterns, the corresponding plurality of first sheet patterns being spaced apart from each other in a third direction perpendicular to the first direction and the second direction and contacting the first channel separation structure; a second channel pattern, comprising a corresponding plurality of second sheet-like patterns, the corresponding plurality of second sheet-like patterns being spaced apart from each other in the third direction and contacting the second channel separation structure; a first source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the first channel pattern respectively; second source / drain patterns between the first channel separation structure and the second channel separation structure and respectively contacting the second channel patterns; and a first gate separation structure, between the first source / drain pattern and the second source / drain pattern, in, The upper surface of the first trench separation structure is coplanar with the upper surface of the first gate separation structure, and An upper surface of the first trench separation structure is coplanar with an upper surface of the gate capping pattern.

14. The semiconductor device according to claim 13, wherein: The first gate separation structures are in contact with the first gate structures respectively.

15. The semiconductor device according to claim 13, wherein: A first height of the first trench separation structure relative to a bottom surface of the semiconductor device is different from a second height of the first gate separation structure relative to the bottom surface of the semiconductor device.

16. The semiconductor device according to claim 13, wherein: The first source / drain patterns are in contact with the first channel separation structures, respectively, and The second source / drain patterns are in contact with the second channel separation structures, respectively.

17. The semiconductor device according to claim 13, further comprising: The second gate structure and the third gate structure are located between two first gate structures adjacent to each other in the first direction in the first gate structure, and the second gate structure and the third gate structure are spaced apart from each other in the second direction, The first gate separation structure is in contact with the second gate structure and the third gate structure.

18. The semiconductor device according to claim 13, further comprising: A second gate structure and a third gate structure are located between two first gate structures adjacent to each other in the first direction among the first gate structures, and the second gate structure and the third gate structure are spaced apart from each other in the second direction; as well as a second gate separation structure, located between the second gate structure and the third gate structure in the second direction; The second gate separation structure is in contact with the first gate separation structure and the second gate structure and the third gate structure.

19. A semiconductor device comprising: a first lower pattern extending along a first direction; a second lower pattern extending along the first direction and spaced apart from the first lower pattern in a second direction crossing the first direction; a field insulating film between the first lower pattern and the second lower pattern; a first trench separation structure on the first lower pattern and extending along the first direction, a portion of the first trench separation structure being in the first lower pattern; a second trench separation structure on the second lower pattern and extending along the first direction, a portion of the second trench separation structure being in the second lower pattern; a plurality of gate structures spaced apart from each other in the first direction between the first trench separation structure and the second trench separation structure and contacting the first trench separation structure and the second trench separation structure, the gate structures comprising corresponding gate electrodes and corresponding gate insulating films; a first channel pattern between the first channel separation structure and the gate structure and including a corresponding plurality of first sheet patterns, the corresponding plurality of first sheet patterns being spaced apart from each other in a third direction perpendicular to the first direction and the second direction and contacting the first channel separation structure; a second channel pattern between the second channel separation structure and the gate structure and including a corresponding plurality of second sheet patterns, the corresponding plurality of second sheet patterns being spaced apart from each other in the third direction and contacting the second channel separation structure; a first source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the first channel pattern respectively; a second source / drain pattern between the first channel separation structure and the second channel separation structure and in contact with the second channel pattern respectively; as well as A gate separation structure is provided between the first source / drain pattern and a second source / drain pattern facing the first source / drain pattern in the second direction, the gate separation structure being in contact with the field insulating film.

20. The semiconductor device according to claim 19, wherein The field insulating film has an upper surface in contact with the gate structure and a bottom surface opposite to the upper surface in the third direction, and The upper surface of the field insulating film is higher than a lowermost portion of the first trench separation structure in the third direction relative to the bottom surface of the field insulating film.

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