A SiC power device with an embedded SBD to improve short-circuit resistance

Abstract

The present invention discloses a SiC power device with an embedded SBD that improves short-circuit resistance, including a metal drain, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a gate deep trench, a metal gate, a source shallow trench, an SBD metal, a P-type doped semiconductor shielding layer and a metal source. The metal gate is embedded at the top of the gate deep trench. The SBD metal, the source shallow trench and the P-type doped semiconductor shielding layer in the present invention can reduce the current density when the device is short-circuited, reduce the temperature of the device when it is short-circuited, avoid thermal breakdown of the device, and improve the short-circuit resistance of the device. In addition, the gate deep trench filled with a high-K dielectric in the present invention can modulate the potential distribution of the drift region to ensure low on-resistance and high reverse breakdown voltage, thereby taking into account the improvement of the on-resistance and short-circuit resistance of the device, and effectively reconciling the contradictory relationship between the two.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon carbide power devices, and in particular to a SiC power device with an embedded SBD for improving short-circuit resistance. Background Art

[0002] Silicon carbide (SiC) power devices are widely used in electric vehicles, renewable energy, industrial automation, power electronics, aerospace, portable electronic devices, power transmission, medical equipment and other scenarios due to their superior performance such as lower on-resistance and switching loss, better switching frequency and thermal management capabilities.

[0003] In recent years, integrating Schottky diodes (SBDs) into SiC power devices has become an important trend to improve device performance. With its extremely low forward voltage drop and fast reverse recovery characteristics, SBDs can significantly reduce switching losses and conduction losses. This integrated design not only optimizes power conversion efficiency, but also improves the system's thermal management capabilities and simplifies circuit design.

[0004] SiC power devices often work in high voltage and high current scenarios, and short-circuit stress is a key factor affecting their reliability. When a short circuit occurs, the following short-circuit hazards will occur, specifically:

[0005] 1. The device will instantly withstand a current several times higher than the rated value. This surge in current will cause the internal temperature of the device to rise rapidly, possibly exceeding its thermal limit and causing thermal failure.

[0006] 2. Short-circuit conditions exceeding the rated voltage will cause breakdown and damage the insulation layer.

[0007] 3. Excessive carrier injection may lead to unstable conduction characteristics of the device, thus affecting the overall performance.

[0008] 4. Thermal expansion mismatch may generate mechanical stress, leading to cracks or delamination at the material interface.

[0009] 5. It will accelerate the aging process of the device and shorten its service life.

[0010] Based on the above short-circuit hazards, SiC power devices usually introduce over-current and over-voltage protection measures such as fuses or varistors in the circuit in practical applications. However, although there are ways to deal with short circuits, improving the short-circuit resistance of the device itself is still the core element to ensure system reliability, performance and safety.

[0011] The traditional method of improving the short-circuit resistance of a device is to increase the on-resistance, thereby reducing the short-circuit current density of the device and avoiding circuit damage. Therefore, there is a contradictory relationship between improving the short-circuit resistance of the device and reducing the on-resistance. In order to optimize both at the same time, the present invention proposes a SiC power device with an embedded SBD that improves the short-circuit resistance. Summary of the invention

[0012] The technical problem to be solved by the present invention is to provide a SiC power device with an embedded SBD that improves the short-circuit resistance capability in view of the deficiencies of the above-mentioned prior art. The SiC power device with an embedded SBD that improves the short-circuit resistance capability takes into account both the power consumption and the short-circuit resistance capability of the device by using a stepped SBD metal in a shallow source trench and filling a high-K material in a deep gate trench.

[0013] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0014] A SiC power device with an embedded SBD for improving short-circuit resistance comprises a metal drain, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a gate deep trench, a metal gate, a source shallow trench, an SBD metal, a P-type doped semiconductor shielding layer and a metal source.

[0015] The metal drain, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source are arranged in sequence from bottom to top.

[0016] The gate deep trench and the source shallow trench are both vertically through-type arranged on both sides of the N-type doped semiconductor JFET region, and the bottoms of both extend into the N-type doped semiconductor epitaxial layer directly below; wherein, the depth of the gate deep trench is greater than the depth of the source shallow trench, and the gate deep trench is filled with a high-K dielectric, and the source shallow trench is filled with a metal source.

[0017] The metal gate is embedded in the top of the gate deep trench.

[0018] The SBD metal is stepped and embedded in the metal source, including an integrally arranged SBD horizontal portion and an SBD vertical portion; wherein the SBD vertical portion extends into the source shallow trench in a manner of being in contact with the side wall of the source shallow trench, and has an SBD gap with the bottom surface of the source shallow trench; the SBD horizontal portion is located at the bottom of the metal source, and the lower surface is in close contact with the upper surface of the N-type doped semiconductor JFET region.

[0019] The P-type doped semiconductor shielding layer is stepped, including a vertical shielding portion and a horizontal shielding portion; wherein the vertical shielding portion is arranged in an N-type doped semiconductor JFET region below the SBD vertical portion and coincides with the side wall of the source shallow trench; the horizontal shielding portion is arranged on the top of the N-type doped semiconductor epitaxial layer coincides with the bottom of the source shallow trench.

[0020] An interlayer insulating medium is arranged between the metal gate and the metal source.

[0021] It also includes a P-type doped semiconductor well; the P-type doped semiconductor well is arranged in the N-type doped semiconductor JFET region between the gate deep trench and the source shallow trench.

[0022] It also includes an N-type doped semiconductor source contact region and a P-type doped semiconductor ohmic contact region; the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are arranged side by side on the top of the N-type doped semiconductor JFET region just above the P-type doped semiconductor well.

[0023] The vertical depth of the metal gate exceeds the vertical depth of the P-type doped semiconductor well.

[0024] The length of the SBD transverse portion is not greater than 15% of the transverse width of the N-type doped semiconductor epitaxial layer, and the length of the SBD longitudinal portion is not greater than 150% of the longitudinal depth of the P-type doped semiconductor well.

[0025] The width of the source shallow trench is not less than 5% of the lateral width of the N-type doped semiconductor epitaxial layer and not greater than 20% of the lateral width of the N-type doped epitaxial layer; the depth of the source shallow trench is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not greater than 225% of the longitudinal depth of the P-type doped semiconductor well.

[0026] The SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well and not more than 75% of the longitudinal depth of the P-type doped semiconductor well.

[0027] The width of the gate deep trench is not less than 10% of the lateral width of the N-type doped semiconductor epitaxial layer and not greater than 20% of the lateral width of the N-type doped epitaxial layer; the depth of the gate deep trench is not less than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not greater than 80% of the longitudinal depth of the N-type doped epitaxial layer.

[0028] The doping concentration of the P-type doped semiconductor shielding layer is between 0.6×10 17 ~2×10 17 cm -3 between.

[0029] The present invention has the following beneficial effects: the arrangement of the stepped SBD metal, the source shallow trench and the P-type doped semiconductor shielding layer in the present invention can reduce the current density when the device is short-circuited, reduce the temperature of the device during the short-circuit process, avoid thermal breakdown of the device, and improve the short-circuit resistance of the SiC power device. In addition, the gate deep trench filled with a high-K dielectric in the present invention can modulate the potential distribution of the drift region to ensure low on-resistance and high reverse breakdown voltage, thereby taking into account the improvement of the on-resistance and short-circuit resistance of the SiC power device, and effectively reconciling the contradictory relationship between the two. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The schematic diagram shows the structure of a SiC power device with an embedded SBD for improving short-circuit resistance according to the present invention.

[0031] Figure 2 A schematic diagram of the structure of a conventional SiC power device with SBD (conventional device) is shown.

[0032] Figure 3 A comparison chart of the short-circuit withstand time of a conventional device and a device provided by an embodiment of the present invention is shown.

[0033] Figure 4 A comparison chart showing the temperature change over time of the SBD region of a conventional device and a device provided by an embodiment of the present invention when the gate is turned off after enduring a short-circuit stress of 5 ms.

[0034] Figure 5 The graph shows the relationship between the specific on-resistance of the device provided by the embodiment of the present invention and the depth of the gate deep trench.

[0035] Figure 6 The graph shows the relationship between the quality factor of the device provided by the embodiment of the present invention and the depth of the gate deep trench.

[0036] Figure 7 A schematic diagram of the structure after epitaxial growth of an N-type doped semiconductor epitaxial layer in step 1 is shown.

[0037] Figure 8 A schematic diagram of the structure after etching the gate deep trench and source shallow trench in step 2 is shown.

[0038] Fig. 9 A schematic diagram of the structure after the N-type doped semiconductor JFET region is prepared in step 3 is shown.

[0039] Fig.10 A schematic diagram of the structure after the P-type doped semiconductor well is prepared in step 4 is shown.

[0040] Fig.11 The schematic diagram of the structure after the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are prepared in step 5 is shown.

[0041] Fig.12 A schematic diagram of the structure after the preparation of the P-type doped semiconductor shielding layer in step 6 is shown.

[0042] Fig.13 A schematic diagram of the structure after the two trenches are filled in step 7 is shown.

[0043] Fig.14The schematic diagram of the structure after the etching of the gate embedding groove and the SBD embedding groove in step 8 is shown.

[0044] Fig.15 A schematic diagram of the structure after the metal gate and SBD metal are prepared in step 9 is shown.

[0045] Fig.16 The schematic diagram of the structure after the interlayer insulating medium is prepared in step 10 is shown.

[0046] Fig.17 The schematic diagram of the structure after the metal source and the metal drain are prepared in step 11 is shown.

[0047] Among them are:

[0048] 1. Metal drain; 2. N-type doped semiconductor substrate; 3. N-type doped semiconductor epitaxial layer; 4. N-type doped semiconductor JFET region; 5. P-type doped semiconductor well; 6. N-type doped semiconductor source contact region; 7. P-type doped semiconductor ohmic contact region; 8. Gate deep trench; 9. Metal gate; 10. Source shallow trench; 11. SBD metal; 12. P-type doped semiconductor shielding layer; 13. Metal source; 14. Interlayer insulating medium. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific preferred embodiments.

[0050] In the description of the present invention, it should be understood that the terms "left side", "right side", "upper part", "lower part" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second" and the like do not indicate the importance of the components, and therefore cannot be understood as limiting the present invention. The specific dimensions used in this embodiment are only for illustrating the technical solution, and do not limit the scope of protection of the present invention.

[0051] like Figure 1 As shown, a SiC power device with an embedded SBD for improving short-circuit resistance includes a metal drain 1, an N-type doped semiconductor substrate 2, an N-type doped semiconductor epitaxial layer 3, an N-type doped semiconductor JFET region 4, a P-type doped semiconductor well 5, an N-type doped semiconductor source contact region 6, a P-type doped semiconductor ohmic contact region 7, a gate deep trench 8, a metal gate 9, a source shallow trench 10, an SBD metal 11, a P-type doped semiconductor shielding layer 12, a metal source 13 and an interlayer insulating medium 14.

[0052] The metal drain, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source are arranged in sequence from bottom to top.

[0053] The gate deep trench and the source shallow trench are both vertically through-type arranged on both sides of the N-type doped semiconductor JFET region, and the P-type doped semiconductor well is arranged in the N-type doped semiconductor JFET region between the gate deep trench and the source shallow trench, wherein the P-type doped semiconductor well is completely surrounded by the N-type doped JFET region.

[0054] The bottoms of the above-mentioned gate deep trench and source shallow trench both extend into the N-type doped semiconductor epitaxial layer directly below; wherein the depth of the gate deep trench is greater than the depth of the source shallow trench, and further, the depth of the gate deep trench is not less than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not greater than 80% of the longitudinal depth of the N-type doped epitaxial layer; the width of the gate deep trench is not less than 10% of the lateral width of the N-type doped semiconductor epitaxial layer and not greater than 20% of the lateral width of the N-type doped epitaxial layer. In this embodiment, the width of the gate deep trench is preferably 1.2μm, and the depth is preferably 7μm.

[0055] The gate deep trench is filled with a high-K dielectric, preferably HfO2.

[0056] The metal source is filled in the above-mentioned source shallow trench, and the width of the source shallow trench is not less than 5% of the lateral width of the N-type doped semiconductor epitaxial layer and not more than 20% of the lateral width of the N-type doped epitaxial layer; the depth of the source shallow trench is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not more than 225% of the longitudinal depth of the P-type doped semiconductor well. In this embodiment, the width of the source shallow trench is preferably 0.4μm, and the depth is preferably 0.8μm.

[0057] The metal gate is embedded in the top of the gate deep trench, the vertical depth of the metal gate exceeds the vertical depth of the P-type doped semiconductor well, and the width of the metal gate is smaller than the width of the gate deep trench, so the metal gate does not contact the P-type doped semiconductor well.

[0058] The N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are arranged side by side on the top of the N-type doped semiconductor JFET region directly above the P-type doped semiconductor well. In this embodiment, the right side of the N-type doped semiconductor source contact region is closely connected to the left side of the P-type doped semiconductor ohmic contact region, and both are completely surrounded by the P-type doped semiconductor well 5.

[0059] The SBD metal is stepped and embedded in the metal source, that is, in direct contact with the metal source. In this embodiment, the SBD metal is preferably titanium metal.

[0060] The SBD metal includes an SBD transverse portion and an SBD longitudinal portion which are integrally arranged.

[0061] The above-mentioned SBD longitudinal portion extends into the source shallow trench in a manner that it fits the sidewall of the source shallow trench, and has a longitudinal SBD gap with the bottom surface of the source shallow trench. Furthermore, the length of the SBD longitudinal portion is not greater than 150% of the longitudinal depth of the P-type doped semiconductor well; the SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well, and not greater than 75% of the longitudinal depth of the P-type doped semiconductor well. In this embodiment, the length of the SBD longitudinal portion is preferably 0.4μm, and the SBD gap is 0.4μm.

[0062] The SBD lateral portion is located at the bottom of the metal source, that is, the lower surface of the SBD lateral portion is close to the upper surface of the N-type doped semiconductor JFET region, and the left side is aligned with the right boundary of the P-type doped semiconductor ohmic contact region. Further, the length of the SBD lateral portion is not greater than 15% of the lateral width of the N-type doped semiconductor epitaxial layer. In this embodiment, the length of the SBD lateral portion is preferably 1 μm.

[0063] The above-mentioned P-type doped semiconductor shielding layer is stepped, including a vertical shielding portion and a horizontal shielding portion; wherein the vertical shielding portion is arranged below the SBD vertical portion and in the N-type doped semiconductor JFET region that coincides with the sidewall of the source shallow trench; and the horizontal shielding portion is arranged on the top of the N-type doped semiconductor epitaxial layer that coincides with the bottom of the source shallow trench. Furthermore, the doping concentration of the P-type doped semiconductor shielding layer is preferably between 0.6×10 17 ~2×10 17 cm -3 In this embodiment, it is preferably 1×10 17 cm -3 .

[0064] The interlayer insulating dielectric is disposed between the metal gate and the metal source, preferably SiO2, for achieving electrical isolation.

[0065] How it works

[0066] like Figure 2 As shown, if traditional SiC power devices with SBDs (hereinafter referred to as traditional devices) want to improve their short-circuit resistance, they often need to increase the on-resistance of the device by reducing the doping concentration in the drift region of the device, thereby reducing the saturation current density when the device is short-circuited, and then reducing the temperature when the device is short-circuited, so as to improve the short-circuit resistance of the device. Increasing the on-resistance of the device will undoubtedly increase the power loss of the device during normal operation.

[0067] The SiC power device with embedded SBD for improving short-circuit resistance provided in this embodiment (hereinafter referred to as the device provided in this embodiment) opens a shallow source trench, adds a stepped SBD metal at the shallow source trench, and introduces a P-type doped semiconductor shielding layer at the bottom of the shallow source trench and the lower half of the sidewall. By giving play to the shielding effect of the P-type doped semiconductor well and the P-type doped semiconductor shielding layer on the short-circuit current, the saturation current density during short circuit is effectively reduced, and the design of the shallow source trench does not significantly increase the on-resistance of the device.

[0068] When a short circuit occurs, for SiC power devices with embedded SBDs, the leakage current is mainly the thermal electron emission current generated by the SBD. J SBD , the specific calculation formula is:

[0069]

[0070] In the formula, A is the Richardson constant, T is the temperature of the SBD region, q is the charge of the electron, is the barrier height, k is the thermal conductivity, is the barrier height change, C T is the tunneling coefficient, E M is the maximum electric field intensity in the SBD region.

[0071] It can be seen from the above formula that the thermal electron emission current generated by the SBD can be effectively reduced by reducing the temperature of the SBD region. The present invention adopts a stepped SBD metal, and effectively reduces the temperature of the device when it is short-circuited by using a P-type doped semiconductor shielding layer and a P-type doped semiconductor well to squeeze the SBD current flow path when short-circuited, thereby suppressing the thermal electron emission current and effectively improving the short-circuit resistance of the device.

[0072] like Figure 3 As shown, the gate-source voltage V gs = 15 V, drain-source voltage V ds = 400 V, TCAD short-circuit stress simulation is performed on the device provided in this embodiment and the traditional device respectively. It can be seen that:

[0073] A. For traditional devices

[0074] After enduring 4μs of short-circuit stress, the gate is turned off. As time goes by, the short-circuit current density of the device gradually decreases to 0.

[0075] After enduring 5μs of short-circuit stress, the short-circuit current density drops rapidly to a low level due to gate shutdown, but then begins to gradually increase as time goes on.

[0076] When the gate is turned off after enduring 8μs of short-circuit stress, the short-circuit current of the device rises rapidly until thermal damage occurs.

[0077] B. For the device provided in this embodiment

[0078] After withstanding the short-circuit stress for 7μs, the gate is turned off and the short-circuit current of the device gradually decreases to a lower level and remains stable.

[0079] After the gate is turned off after enduring 8μs of short-circuit stress, the device can no longer be turned off normally.

[0080] When the gate is turned off after being subjected to a short-circuit stress of 11μs, the short-circuit current of the device increases significantly over time.

[0081] Therefore, it can be considered that, compared with the short-circuit stress withstand time of 4 μs of the traditional device, the short-circuit stress withstand time of the device provided in this embodiment is improved to 7 μs.

[0082] Figure 4 The temperature simulation results of the SBD region of the device provided in this embodiment and the traditional device. After the gate is turned off after enduring a short-circuit stress of 5μs, the thermal electron emission current density in the SBD region of the traditional device gradually increases over time, causing the device temperature to rise, which in turn causes the thermal electron emission current density to further increase. Under the effect of temperature positive feedback, the device eventually fails thermally; while the temperature of the SBD region of the device provided in this embodiment gradually decreases over time.

[0083] Furthermore, the introduction of the gate deep trench filled with high-K dielectric in the present invention can effectively reduce the specific on-resistance of the device. R on，sp , but as the trench depth increases, the device specific on-resistance gradually increases, such as Figure 5 as shown; Figure 6 As shown, the device has a maximum quality factor.

[0084] A method for manufacturing a SiC power device with an embedded SBD for improving short-circuit resistance comprises the following steps.

[0085] Step 1, epitaxial growth of an N-type doped semiconductor epitaxial layer: epitaxial growth of an N-type doped semiconductor epitaxial layer 3 on an N-type doped semiconductor substrate 2 to form a Figure 7 The basic structure shown.

[0086] Step 2: Etching the deep gate trench and the shallow source trench: Figure 8As shown, a reactive ion etching process is used to etch the gate region and the source region to form two trenches, a gate deep trench and a source shallow trench, respectively. However, it should be noted that since the depths of the two trenches are different, different masks need to be used for the two etchings.

[0087] Step 3, prepare N-type doped semiconductor JFET region: Since the active region is 4H-SiC, nitride should be used as a mask for ion implantation. Considering the stress of nitride on SiC, first deposit 0.1μm thick oxide on the N-type doped semiconductor epitaxial layer 3, and then deposit 1μm thick nitride. Then use photoresist as a mask to etch away the nitride and oxide on the active region between the gate deep trench 8 and the source shallow trench 10, then etch away all the photoresist, perform N-type impurity ion implantation and high temperature annealing on the area without nitride protection to form an N-type doped semiconductor JFET region 4, and then completely etch away the remaining nitride and oxide, as shown in FIG. Fig. 9 shown.

[0088] Step 4, preparing a P-type doped semiconductor well: repeat the above-mentioned operation of depositing oxide and nitride, use the photoresist as a mask, etch away part of the nitride and oxide on the N-type doped semiconductor JFET region 4, then etch away all the photoresist, perform P-type impurity ion implantation and high temperature annealing on the area without nitride protection to form a P-type doped semiconductor well 5, and then completely etch away the remaining nitride and oxide, as shown in FIG. Fig.10 shown.

[0089] Step 5: Prepare N-type doped semiconductor source contact region and P-type doped semiconductor ohmic contact region

[0090] A. Preparation of N-type doped semiconductor source contact region

[0091] Repeat the above operation of depositing oxide and nitride, use the photoresist as a mask, etch away the nitride and oxide on the left side of the P-type doped semiconductor well 5, then etch away all the photoresist, perform high-dose N-type impurity ion implantation and high-temperature annealing on the area without nitride protection to form an N-type doped semiconductor source contact area 6, and then completely etch away the remaining nitride and oxide.

[0092] B. Preparation of P-type doped semiconductor ohmic contact region

[0093] Repeat the above-mentioned operation of depositing oxide and nitride, use the photoresist as a mask, etch away the nitride and oxide on the right side of the P-type doped semiconductor well 5, then etch away all the photoresist, perform high-dose P-type impurity ion implantation and high-temperature annealing on the area without nitride protection to form a P-type doped semiconductor ohmic contact area 7, and then completely etch away the remaining nitride and oxide, as shown in FIG. Fig.11 shown.

[0094] Step 6, preparing a P-type doped semiconductor shielding layer: repeat the above-mentioned operation of depositing oxide and nitride, use the photoresist as a mask, etch away the nitride and oxide on the source shallow trench 10, then etch away all the photoresist, perform P-type impurity ion implantation and high-temperature annealing on the source shallow trench 10 area without nitride protection to form a P-type doped semiconductor shielding layer 12, and then completely etch away the remaining nitride and oxide, as shown in FIG. Fig.12 shown.

[0095] Step 7: Groove filling: Fig.13 As shown, a magnetron sputtering deposition device is used to deposit HfO2 to fill the gate deep trench 8, and then a specific mask is used to deposit a metal source to the top of the source shallow trench 10. Considering the interface effect between HfO2 and SiC, a layer of SiO2 is prepared as a buffer layer before depositing HfO2.

[0096] Step 8: Etching the gate embedding groove and the SBD embedding groove

[0097] A. Etching the gate embedding groove: Use reactive ion etching to etch a shallow gate embedding groove on HfO2

[0098] B. Etching SBD embedded groove: Etch the metal source electrode deposited in step 7 to a set height to form an SBD embedded groove. Fig.14 shown.

[0099] Step 9, preparing metal gate and SBD metal: using different masks, depositing metal gate 9 and SBD metal 11 in the gate embedding groove and SBD embedding groove respectively, as shown in FIG. Fig.15 As shown, the SBD lateral portion of the SBD metal is deposited on the upper surface of the N-type doped semiconductor JFET region.

[0100] Step 10: Prepare interlayer insulating medium: Using photoresist as a mask, use chemical vapor deposition equipment to deposit SiO2 as interlayer insulating medium 14 on the metal gate 9. Fig.16 shown.

[0101] Step 11, preparing a metal source and a metal drain: depositing metal in the source region and the drain region and performing annealing treatment to form a metal source 13 and a metal drain 1. The final structure of the SiC power device with an embedded SBD and improved short-circuit resistance provided in this embodiment is as follows: Fig.17 shown.

[0102] The preferred embodiments of the present invention are described in detail above; however, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A SiC power device with an embedded SBD for improving short-circuit resistance, characterized in that: It includes a metal drain, an N-type doped semiconductor substrate, an N-type doped semiconductor epitaxial layer, an N-type doped semiconductor JFET region, a gate deep trench, a metal gate, a source shallow trench, an SBD metal, a P-type doped semiconductor shielding layer and a metal source; The metal drain, the N-type doped semiconductor substrate, the N-type doped semiconductor epitaxial layer, the N-type doped semiconductor JFET region and the metal source are arranged in sequence from bottom to top; The gate deep trench and the source shallow trench are both vertically through-type arranged on both sides of the N-type doped semiconductor JFET region, and the bottoms of both extend into the N-type doped semiconductor epitaxial layer directly below; wherein the depth of the gate deep trench is greater than the depth of the source shallow trench, and the gate deep trench is filled with a high-K dielectric, and the source shallow trench is filled with a metal source; The metal gate is embedded in the top of the gate deep trench; The SBD metal is stepped and embedded in the metal source, including an integrally arranged SBD horizontal portion and an SBD vertical portion; wherein the SBD vertical portion extends into the source shallow trench in a manner of being in contact with the sidewall of the source shallow trench, and has an SBD gap with the bottom surface of the source shallow trench; the SBD horizontal portion is located at the bottom of the metal source, and the lower surface is in close contact with the upper surface of the N-type doped semiconductor JFET region; The P-type doped semiconductor shielding layer is stepped, including a vertical shielding portion and a horizontal shielding portion; wherein the vertical shielding portion is arranged in an N-type doped semiconductor JFET region below the SBD vertical portion and coincides with the side wall of the source shallow trench; the horizontal shielding portion is arranged on the top of the N-type doped semiconductor epitaxial layer coincides with the bottom of the source shallow trench.

2. The SiC power device with an embedded SBD for improving short-circuit resistance according to claim 1, characterized in that: An interlayer insulating medium is arranged between the metal gate and the metal source.

3. The SiC power device with an embedded SBD for improving short-circuit resistance according to claim 1, characterized in that: It also includes a P-type doped semiconductor well; the P-type doped semiconductor well is arranged in the N-type doped semiconductor JFET region between the gate deep trench and the source shallow trench.

4. The SiC power device with an embedded SBD for improving short-circuit resistance according to claim 3, characterized in that: It also includes an N-type doped semiconductor source contact region and a P-type doped semiconductor ohmic contact region; the N-type doped semiconductor source contact region and the P-type doped semiconductor ohmic contact region are arranged side by side on the top of the N-type doped semiconductor JFET region just above the P-type doped semiconductor well.

5. The SiC power device with an embedded SBD for improving short-circuit withstand capability according to claim 3, characterized in that: The vertical depth of the metal gate exceeds the vertical depth of the P-type doped semiconductor well.

6. The SiC power device with embedded SBD for improving short-circuit resistance according to claim 3, characterized in that: The length of the SBD transverse portion is not greater than 15% of the transverse width of the N-type doped semiconductor epitaxial layer, and the length of the SBD longitudinal portion is not greater than 150% of the longitudinal depth of the P-type doped semiconductor well.

7. The SiC power device with an embedded SBD for improving short-circuit withstand capability according to claim 3, characterized in that: The width of the source shallow trench is not less than 5% of the lateral width of the N-type doped semiconductor epitaxial layer and not greater than 20% of the lateral width of the N-type doped epitaxial layer; the depth of the source shallow trench is not less than 30% of the longitudinal depth of the P-type doped semiconductor well and not greater than 225% of the longitudinal depth of the P-type doped semiconductor well.

8. The SiC power device with an embedded SBD for improving short-circuit withstand capability according to claim 3, characterized in that: The SBD gap is not less than 25% of the longitudinal depth of the P-type doped semiconductor well and not more than 75% of the longitudinal depth of the P-type doped semiconductor well.

9. The SiC power device with an embedded SBD for improving short-circuit withstand capability according to claim 1, characterized in that: The width of the gate deep trench is not less than 10% of the lateral width of the N-type doped semiconductor epitaxial layer and not greater than 20% of the lateral width of the N-type doped epitaxial layer; the depth of the gate deep trench is not less than 30% of the longitudinal depth of the N-type doped semiconductor epitaxial layer and not greater than 80% of the longitudinal depth of the N-type doped epitaxial layer.

10. The SiC power device with embedded SBD for improving short-circuit withstand capability according to claim 1, characterized in that: The doping concentration of the P-type doped semiconductor shielding layer is between 0.6×10 17 ~2×10 17 cm -3 between.

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