Power factor correction circuit control method, signal processing chip, device and medium

Abstract

The embodiment of the invention provides a power factor correction circuit control method, a signal processing chip, equipment and a medium, and the method comprises the steps: cutting off a pulse width modulation signal outputted to a power factor correction circuit when a protection signal of the power factor correction circuit is obtained; acquiring the states of the first switch tube and the second switch tube; according to the state of the first switching tube and the state of the second switching tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty ratio of a pulse width modulation signal corresponding to one of the first switching tube and the second switching tube is controlled; and the pulse width modulation signal output to the power factor correction circuit is recovered, so that the power factor correction circuit operates normally. Therefore, by controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit or controlling the duty ratio of the pulse width modulation signal, the situation that the energy storage capacity of the main phase circuit and the auxiliary phase circuit is not uniform, and consequently overcurrent protection is triggered all the time is prevented, and then the power factor correction circuit is protected.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit control, and in particular to a power factor correction circuit control method, a signal processing chip for power factor correction circuit control, an electronic device and a computer readable storage medium. Background Art

[0002] With the development of electronic technology, the percentage of high-order harmonic currents in the power grid is getting higher and higher, which will lead to a sharp decrease in the service life of electrical products and a lower and lower utilization rate of power supply. In order to solve this problem, most of the current methods to reduce harmonic currents are to add PFC (Power Factor Correction) circuits on the motherboard. However, in some cases, it is easy to trigger the overcurrent protection of the PFC circuit until it stops running, and in severe cases it may cause damage to electronic devices. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a power factor correction circuit control method, a signal processing chip for power factor correction circuit control, an electronic device and a computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a power factor correction circuit control method, the method is applied to a signal processing chip, the signal processing chip is connected to the power factor correction circuit; the power factor correction circuit includes: a main phase circuit and an auxiliary phase circuit; the main phase circuit includes a first switch tube; the auxiliary phase circuit includes a second switch tube, the method includes:

[0005] When a protection signal of the power factor correction circuit is obtained, cutting off the pulse width modulation signal output to the power factor correction circuit;

[0006] Acquire a state of the first switch tube and a state of the second switch tube;

[0007] According to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled;

[0008] The pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

[0009] Optionally, the signal processing chip includes an open-drain output pin; the power factor correction circuit includes a comparator; the open-drain output pin is connected to the comparator; when the protection signal of the power factor correction circuit is obtained, before the pulse width modulation signal output to the power factor correction circuit is cut off, the method includes:

[0010] Determine whether the digital signal output by the comparator obtained by the open-drain output pin changes from the first digital signal to the second digital signal;

[0011] When the open-drain output pin obtains the digital signal output by the comparator and changes from the first digital signal to the second digital signal, it is determined that the protection signal of the power factor correction circuit is obtained.

[0012] Optionally, the acquiring the state of the first switch tube and the state of the second switch tube includes:

[0013] determining the number of times the pulse width modulation signal output to the power factor correction circuit is cut off;

[0014] When the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is less than or equal to a preset number of times, the state of the first switch tube and the state of the second switch tube are obtained.

[0015] Optionally, controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or controlling the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, includes:

[0016] When the first switch tube is in the on state and the second switch tube is in the off state, the initial conduction sequence of the main phase circuit and the auxiliary phase circuit is swapped.

[0017] Optionally, controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or controlling the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, includes:

[0018] When the first switch tube is in a closed state and the second switch tube is in a conducting state, the duty cycle of the pulse width modulation signal corresponding to the second switch tube is adjusted to a preset value.

[0019] Optionally, the restoring the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit operates normally includes:

[0020] Detecting whether the protection signal of the power factor correction circuit disappears;

[0021] If the protection signal of the power factor correction circuit disappears, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

[0022] Optionally, if the protection signal of the power factor correction circuit disappears, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally, including:

[0023] If the protection signal of the power factor correction circuit disappears, determining the output period of the pulse width modulation signal output to the power factor correction circuit;

[0024] When entering the next output cycle, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

[0025] Optionally, the method further comprises:

[0026] When the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number, the power supply of the power factor correction circuit is restarted.

[0027] Optionally, the output period is determined based on a reference value of a current loop of the power factor correction circuit and a collected current signal of the power factor correction circuit.

[0028] The embodiment of the present invention discloses a signal processing chip controlled by a power factor correction circuit, wherein the signal processing chip is connected to the power factor correction circuit; the power factor correction circuit comprises: a main phase circuit and an auxiliary phase circuit; the main phase circuit comprises a first switch tube; the auxiliary phase circuit comprises a second switch tube, and the signal processing chip comprises:

[0029] A cutting module, used for cutting off the pulse width modulation signal output to the power factor correction circuit when a protection signal of the power factor correction circuit is obtained;

[0030] An acquisition module, used to acquire a state of the first switch tube and a state of the second switch tube;

[0031] a control module, configured to control a conduction sequence of the main phase circuit and the auxiliary phase circuit according to a state of the first switch tube and a state of the second switch tube, or to control a duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube;

[0032] The recovery module is used to recover the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit can operate normally.

[0033] Optionally, the signal processing chip includes an open-drain output pin; the power factor correction circuit includes a comparator; the open-drain output pin is connected to the comparator; the signal processing chip further includes:

[0034] A judging module, used for judging whether the digital signal output by the comparator obtained by the open-drain output pin changes from the first digital signal to the second digital signal;

[0035] A determination module is used to determine that a protection signal of the power factor correction circuit is obtained when the open-drain output pin obtains the digital signal output by the comparator and changes from the first digital signal to the second digital signal.

[0036] Optionally, the acquisition module includes:

[0037] A determination submodule, used to determine the number of times the pulse width modulation signal output to the power factor correction circuit is cut off;

[0038] The acquisition submodule is used to acquire the state of the first switch tube and the state of the second switch tube when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is less than or equal to a preset number of times.

[0039] Optionally, the control module includes:

[0040] The first control submodule is used to swap the initial conduction sequence of the main phase circuit and the auxiliary phase circuit when the first switch tube is in the on state and the second switch tube is in the off state.

[0041] Optionally, the control module includes:

[0042] The second control submodule is used to adjust the duty cycle of the pulse width modulation signal corresponding to the second switch tube to a preset value when the first switch tube is in an off state and the second switch tube is in an on state.

[0043] Optionally, the recovery module includes:

[0044] A detection submodule, used to detect whether the protection signal of the power factor correction circuit disappears;

[0045] The recovery submodule is used to restore the pulse width modulation signal output to the power factor correction circuit if the protection signal of the power factor correction circuit disappears, so that the power factor correction circuit can operate normally.

[0046] Optionally, the recovery submodule includes:

[0047] a determining unit, configured to determine an output period of a pulse width modulation signal output to the power factor correction circuit if the protection signal of the power factor correction circuit disappears;

[0048] The recovery unit is used to recover the pulse width modulation signal output to the power factor correction circuit when entering the next output cycle, so that the power factor correction circuit can operate normally.

[0049] Optionally, the signal processing chip further includes:

[0050] The restart module is used to restart the power supply of the power factor correction circuit when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number of times.

[0051] Optionally, the output period is determined based on a reference value of a current loop of the power factor correction circuit and a collected current signal of the power factor correction circuit.

[0052] The present invention also discloses an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the power factor correction circuit control method as described above when executing the computer program.

[0053] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the power factor correction circuit control method as described above are implemented.

[0054] The embodiments of the present invention include the following advantages:

[0055] In an embodiment of the present invention, when a protection signal of a power factor correction circuit is obtained, a pulse width modulation signal output to the power factor correction circuit is cut off, and then the state of the first switch tube and the state of the second switch tube are obtained, and then according to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled, and finally the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally, thereby preventing the main phase circuit and the auxiliary phase circuit from having uneven energy storage capacity, which causes the overcurrent protection to be triggered continuously, and thereby protecting the power factor correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a flow chart of the steps of a power factor correction circuit control method provided by an embodiment of the present invention;

[0057] Figure 2 is a schematic diagram of a power factor correction circuit provided by an embodiment of the present invention;

[0058] Figure 3 is a structural block diagram of a signal processing chip provided by an embodiment of the present invention;

[0059] Figure 4 is a schematic diagram of a pulse width modulation signal with different duty cycles provided by an embodiment of the present invention;

[0060] Figure 5 is a schematic diagram of a pulse width modulation signal provided by an embodiment of the present invention;

[0061] Figure 6 is a flowchart of another power factor correction circuit control method provided by an embodiment of the present invention;

[0062] Figure 7 It is a structural block diagram of another signal processing chip controlled by a power factor correction circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] In the related art, in some cases, the power factor correction circuit may easily trigger the overcurrent protection of the power factor correction circuit until it stops running, and in severe cases, it may also cause damage to electronic devices. In order to solve the above technical problems, the present invention discloses a power factor correction circuit control method. When the protection signal of the power factor correction circuit is obtained, the pulse width modulation signal output to the power factor correction circuit is cut off, and then the state of the first switch tube and the state of the second switch tube are obtained. Then, according to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled, and finally the pulse width modulation signal output to the power factor correction circuit is restored to make the power factor correction circuit run normally, thereby preventing the uneven energy storage capacity of the main phase circuit and the auxiliary phase circuit from causing the overcurrent protection to be triggered all the time by controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit, or controlling the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, thereby protecting the power factor correction circuit.

[0065] Reference Figure 1, shows a flow chart of the steps of a power factor correction circuit control method provided by an embodiment of the present invention, wherein the signal processing chip is connected to the power factor correction circuit; the power factor correction circuit comprises: a main phase circuit and an auxiliary phase circuit; the main phase circuit comprises a first switch tube; the auxiliary phase circuit comprises a second switch tube, and the method may specifically comprise the following steps:

[0066] Step 101, when a protection signal of the power factor correction circuit is obtained, the pulse width modulation signal output to the power factor correction circuit is cut off.

[0067] In an embodiment of the present invention, the signal processing chip may be connected to a power factor correction circuit, and the power factor correction circuit may include: a main phase circuit and an auxiliary phase circuit. The main phase circuit may include a first switch tube. The auxiliary phase circuit may include a second switch tube.

[0068] like Figure 2 As shown, a schematic diagram of a power factor correction circuit provided by an embodiment of the present invention is shown. Figure 3 , which shows a structural block diagram of a signal processing chip provided by an embodiment of the present invention. In the present invention, the signal processing chip in the present invention may be a DSP (Digital Signal Processor) chip. Figure 2 In the power factor correction circuit, L1 is the first inductor, G1 is the first switch tube, D1 is the first diode, the first inductor, the first switch tube and the first diode constitute the main phase circuit, L2 is the second inductor, G2 is the second switch tube, D2 is the second diode, the second inductor, the second switch tube and the second diode constitute the auxiliary phase circuit. Generally, the preset conduction sequence of the main phase circuit and the auxiliary phase circuit is that the main phase circuit is turned on first, and the auxiliary phase circuit is turned on later. AC is the alternating current voltage, DB is the rectifier bridge, and the alternating current voltage can be rectified by the rectifier bridge to obtain the direct current voltage Vac, and then the sampling signal Vac1 collected by the pin of the signal processing chip can be obtained after certain processing, for example, after being reduced by a certain multiple, to reach the sampling voltage range of the signal processing chip.

[0069] Vdc is the voltage on the bus capacitor C, and then after certain processing, the sampling signal Vdc1 collected by the pin of the signal processing chip is obtained. Ipfc is the voltage on the resistor R. After processing, the sampling signal Ipfc1 collected by the pin of the signal processing chip can be obtained. In the present invention, the sampling signal Ipfc1 is equivalent to the current signal on the resistor R. PWM1 is a pulse width modulation signal corresponding to the first switch tube, PWM2 is a pulse width modulation signal corresponding to the second switch tube, and the pulse width modulation signal is used to control the state of the switch tube. The pulse width modulation signal is provided by the signal processing chip.

[0070] Vn is the protection threshold set by the comparator U1, OC is the protection signal of the overcurrent of the power factor correction circuit, and OC is the open-drain output pin in the signal processing chip. When the voltage flowing through the resistor R is greater than Vn, the level received by the open-drain output pin of the signal processing chip will flip, for example, the high level becomes the low level, or the low level becomes the high level.

[0071] In the embodiment of the present invention, when the signal processing chip obtains the protection signal of the power factor correction circuit, it can cut off the pulse width modulation signal output by the power factor correction circuit, that is, cut off PWM1 and PWM2.

[0072] In an embodiment of the present invention, the signal processing chip may include an open-drain output pin; the power factor correction circuit may include a comparator; the open-drain output pin is connected to the comparator; when a protection signal of the power factor correction circuit is obtained, before the pulse width modulation signal output to the power factor correction circuit is cut off, it may include: judging whether the digital signal output by the comparator obtained by the open-drain output pin changes from a first digital signal to a second digital signal; when the digital signal output by the comparator obtained by the open-drain output pin changes from a first digital signal to a second digital signal, it is determined that the protection signal of the power factor correction circuit is obtained.

[0073] Specifically, the open-drain output pin of the signal processing chip can receive the digital signal output by the comparator in the power factor correction circuit, and determine whether the digital signal output by the comparator changes from the first digital signal to the second digital signal. In the present invention, when the first digital signal is high, the second digital signal is low, and when the first digital signal is low, the second digital signal is high. The specific signals of the first digital signal and the second digital signal can be set according to actual conditions. The present invention does not make specific limitations here. In order to better illustrate the embodiments, the subsequent embodiments of the present invention all take the high level changing to the low level as an example. When the digital signal output by the comparator obtained at the open-drain output pin changes from the first digital signal to the second digital signal, it can be determined that the protection signal of the power factor correction circuit has been obtained.

[0074] Step 102: Acquire the state of the first switch tube and the state of the second switch tube.

[0075] In an embodiment of the present invention, after the pulse width modulation signal output to the power factor correction circuit is cut off, the signal processing chip can obtain the state of the first switch tube and the state of the second switch tube. In the present invention, the state of the first switch tube and the state of the second switch tube can be the state before the protection signal is obtained, and the state of the first switch tube can be determined according to the pulse width modulation signal corresponding to the first switch tube before the protection signal is obtained, and the state of the second switch tube can be determined according to the pulse width modulation signal corresponding to the second switch tube before the protection signal is obtained.

[0076] In one embodiment, obtaining the state of the first switch tube and the state of the second switch tube may include: determining the number of times the pulse width modulation signal output to the power factor correction circuit is cut off; when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is less than or equal to a preset number, obtaining the state of the first switch tube and the state of the second switch tube.

[0077] Specifically, when the signal processing chip determines to cut off the pulse width modulation signal output to the power factor correction circuit, it can count the number of times the pulse width modulation signal output to the power factor correction circuit is cut off. When the number of times the pulse width modulation signal output to the power factor correction circuit is currently cut off is less than or equal to the preset number, the state of the first switch tube and the state of the second switch tube can be obtained. In the present invention, the preset number of times cannot be set too large, which may easily lead to insufficient protection of the power factor correction circuit. The preset number of times cannot be set too small, which may easily lead to the power factor correction circuit entering an unrecoverable state. Usually, the preset number of times can be set to 10 times. The specific number of times corresponding to the preset number of times in the present invention can be set according to actual conditions, and the present invention does not make specific limitations here.

[0078] In one embodiment, the power factor correction circuit control method of the present invention may further include: when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number, restarting the power supply of the power factor correction circuit.

[0079] For example, the preset number is 10 times. When the pulse width modulation signal output to the power factor correction circuit is cut off 11 times, the subsequent steps are not continued. The power supply of the power factor correction circuit can be cut off again and then restored for operation.

[0080] Step 103, according to the state of the first switch tube and the state of the second switch tube, control the conduction sequence of the main phase circuit and the auxiliary phase circuit, or control the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube.

[0081] In an embodiment of the present invention, after obtaining the state of the first switch tube and the state of the second switch tube, the signal processing chip can control the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or control the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube.

[0082] In one embodiment, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled according to the state of the first switch tube and the state of the second switch tube, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled, which may include: when the first switch tube is in the on state and the second switch tube is in the off state, the initial conduction sequence of the main phase circuit and the auxiliary phase circuit is swapped.

[0083] Specifically, when the state of the first switching tube obtained is the on state, and the state of the second switching tube obtained is the off state, the conduction sequence of the main phase circuit and the auxiliary phase circuit can be directly swapped to prevent the total conduction time of the first switching tube in the main phase circuit from being greater than the total conduction time of the second switching tube in the auxiliary phase circuit, thereby causing the energy storage of the first inductor to always be greater than the energy storage of the second inductor.

[0084] In one embodiment, according to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled, which may include: when the first switch tube is in the off state and the second switch tube is in the on state, adjusting the duty cycle of the pulse width modulation signal corresponding to the second switch tube to a preset value.

[0085] Specifically, when the state of the first switch tube obtained is the off state, and the state of the second switch tube obtained is the on state, the duty cycle of the pulse width modulation signal corresponding to the second switch tube can be reduced to balance the energy storage of the first inductor and the second inductor, so that it is subsequently constantly smaller than the first inductor. For example, the duty cycle of the pulse width modulation signal corresponding to the second switch tube can be constantly reduced by 5%. The percentage of the duty cycle constantly reduced in the present invention cannot be set too small, otherwise it may not achieve the effect of balancing the energy storage of the first inductor and the second inductor, and it cannot be too large, otherwise it may cause the energy storage of the first inductor to be greater than the energy storage of the second inductor. The percentage with constant reduction can be set according to actual needs, and the present invention does not make specific limitations here.

[0086] like Figure 4 As shown, a schematic diagram of a pulse width modulation signal with different duty cycles is shown. Figure 4 A schematic diagram of a pulse width modulation signal corresponding to a first switch tube with a duty cycle of 50% and a pulse width modulation signal corresponding to a second switch tube is shown in the figure, wherein PWM1 is the pulse width modulation signal corresponding to the first switch tube and PWM2 is the pulse width modulation signal corresponding to the second switch tube. A schematic diagram of a pulse width modulation signal corresponding to a first switch tube with a duty cycle of 33.3% and a pulse width modulation signal corresponding to the second switch tube is also shown. It should be noted that Figure 4The duty cycle of the pulse width modulation signal corresponding to the first switch tube is the same as the duty cycle of the pulse width modulation signal corresponding to the second switch tube.

[0087] Step 104, restoring the pulse width modulation signal output to the power factor correction circuit, so that the power factor correction circuit operates normally.

[0088] In an embodiment of the present invention, after the signal processing chip controls the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or controls the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, the pulse width modulation signal output to the power factor correction circuit can be restored to enable the power factor correction circuit to operate normally.

[0089] In one embodiment, restoring the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit operates normally may include: detecting whether the protection signal of the power factor correction circuit disappears; if the protection signal of the power factor correction circuit disappears, restoring the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit operates normally.

[0090] Specifically, after the signal processing chip controls the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or controls the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, it can detect whether the protection signal of the power factor correction circuit disappears. When the open-drain output pin obtains the digital signal output by the comparator and changes back to the first digital signal from the second digital signal, it can be determined that the protection signal of the power factor correction circuit has disappeared. Then the signal processing chip can restore the pulse width modulation signal output to the power factor correction circuit to enable the power factor correction circuit to operate normally.

[0091] In one embodiment, if the protection signal of the power factor correction circuit disappears, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally, including: if the protection signal of the power factor correction circuit disappears, determining the output cycle of the pulse width modulation signal output to the power factor correction circuit; when entering the next output cycle, restoring the pulse width modulation signal output to the power factor correction circuit to enable the power factor correction circuit to operate normally.

[0092] Specifically, if the protection signal of the power factor correction circuit disappears, the output period of the pulse width modulation signal output to the power factor correction circuit can be determined at this time. The output period in the present invention can be determined based on the reference value of the current loop of the power factor correction circuit and the current signal of the power factor correction circuit collected. The reference value of the current loop of the power factor correction circuit in the present invention can be calculated by the output of the voltage loop and the currently collected voltage signal Vac1. Generally, it is obtained by multiplying the output of the voltage loop and the currently collected voltage signal Vac1. Then, the actually collected current signal Ipfc1 and the reference value are input into the PID (Proportional-Integral-Derivative Controller) controller of the current loop. Finally, according to the signal output by the current loop, two pulse width modulation signals of equal size and constant opening time interval corresponding to the first switch tube and the pulse width modulation signal corresponding to the second switch tube are obtained through certain processing, that is, the output period of the pulse width modulation signal output to the power factor correction circuit is obtained, such as 20us. Figure 4 The pulse width modulation signal corresponding to the first switch tube in the circuit has the same output cycle as the pulse width modulation signal corresponding to the second switch tube. When entering the next output cycle, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

[0093] like Figure 5 As shown, a schematic diagram of a pulse width modulation signal provided by an embodiment of the present invention is shown, in which PWM1 is the pulse width modulation signal corresponding to the first switch tube, PWM2 is the pulse width modulation signal corresponding to the second switch tube, and each action started by the pulse width modulation signal corresponding to the first switch tube is a start signal for the later output of each pulse width modulation signal. The dotted line indicates that it needs to be turned on but is not turned on due to the existence of a protection signal.

[0094] like Figure 6As shown, a flow chart of the steps of another power factor correction circuit control method provided by an embodiment of the present invention is shown. The power factor correction circuit operates normally, and it is detected whether the power factor correction circuit outputs a protection signal due to overcurrent. If the protection signal output by the power factor correction circuit due to overcurrent is not detected, the power factor correction circuit operates normally. If the protection signal output by the power factor correction circuit due to overcurrent is detected, the pulse width modulation signal output to the power factor correction circuit is cut off, and the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is increased by one, and it is determined whether the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number. If it is greater than the preset number, the power factor correction circuit stops operating. If it is not greater than the preset number, the power factor correction circuit stops operating. A preset number of times is performed, then it is determined whether only the first switch tube is turned on before the protection signal is detected. If only the first switch tube is turned on, the conduction order of the main phase circuit and the auxiliary phase circuit is swapped, and then it is determined whether the protection signal disappears. If not only the first switch tube is turned on, then it is determined whether only the second switch tube is turned on before the protection signal is detected. If not only the second switch tube is turned on, then it is determined whether the protection signal disappears. If only the second switch tube is turned on, the duty cycle of the pulse width modulation signal corresponding to the second switch tube is reduced, and then it is determined whether the protection signal disappears. If the protection signal does not disappear, it is repeatedly determined whether the protection signal disappears. If the protection signal disappears, the pulse width modulation signal output to the power factor correction circuit is restored, and the power factor correction circuit operates normally.

[0095] In an embodiment of the present invention, when a protection signal of a power factor correction circuit is obtained, the pulse width modulation signal output to the power factor correction circuit is cut off; the state of the first switch tube and the state of the second switch tube are obtained; according to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled; the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally. Thus, by controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit, or controlling the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, it is prevented that the energy storage capacity of the main phase circuit and the auxiliary phase circuit is uneven, resulting in the overcurrent protection being triggered all the time, thereby protecting the power factor correction circuit.

[0096] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0097] Reference Figure 7 , shows a structural block diagram of a signal processing chip controlled by another power factor correction circuit provided by an embodiment of the present invention, wherein the signal processing chip is connected to the power factor correction circuit; the power factor correction circuit comprises: a main phase circuit and an auxiliary phase circuit; the main phase circuit comprises a first switch tube; the auxiliary phase circuit comprises a second switch tube, and the signal processing chip may specifically comprise the following modules:

[0098] A cutting module 701, used to cut off the pulse width modulation signal output to the power factor correction circuit when the protection signal of the power factor correction circuit is obtained;

[0099] An acquisition module 702 is used to acquire a state of the first switch tube and a state of the second switch tube;

[0100] A control module 703, configured to control a conduction sequence of the main phase circuit and the auxiliary phase circuit according to a state of the first switch tube and a state of the second switch tube, or to control a duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube;

[0101] The recovery module 704 is used to restore the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit can operate normally.

[0102] In one embodiment, the signal processing chip includes an open-drain output pin; the power factor correction circuit includes a comparator; the open-drain output pin is connected to the comparator; the signal processing chip further includes:

[0103] A judging module, used for judging whether the digital signal output by the comparator obtained by the open-drain output pin changes from the first digital signal to the second digital signal;

[0104] A determination module is used to determine that a protection signal of the power factor correction circuit is obtained when the open-drain output pin obtains the digital signal output by the comparator and changes from the first digital signal to the second digital signal.

[0105] In one embodiment, the acquisition module 702 includes:

[0106] A determination submodule, used to determine the number of times the pulse width modulation signal output to the power factor correction circuit is cut off;

[0107] The acquisition submodule is used to acquire the state of the first switch tube and the state of the second switch tube when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is less than or equal to a preset number of times.

[0108] In one embodiment, the control module 703 includes:

[0109] The first control submodule is used to swap the initial conduction sequence of the main phase circuit and the auxiliary phase circuit when the first switch tube is in the on state and the second switch tube is in the off state.

[0110] In one embodiment, the control module 703 includes:

[0111] The second control submodule is used to adjust the duty cycle of the pulse width modulation signal corresponding to the second switch tube to a preset value when the first switch tube is in an off state and the second switch tube is in an on state.

[0112] In one embodiment, the recovery module 704 includes:

[0113] A detection submodule, used to detect whether the protection signal of the power factor correction circuit disappears;

[0114] The recovery submodule is used to restore the pulse width modulation signal output to the power factor correction circuit if the protection signal of the power factor correction circuit disappears, so that the power factor correction circuit can operate normally.

[0115] In one embodiment, the recovery submodule includes:

[0116] a determining unit, configured to determine an output period of a pulse width modulation signal output to the power factor correction circuit if the protection signal of the power factor correction circuit disappears;

[0117] The recovery unit is used to recover the pulse width modulation signal output to the power factor correction circuit when entering the next output cycle, so that the power factor correction circuit can operate normally.

[0118] In one embodiment, the signal processing chip further includes:

[0119] The restart module is used to restart the power supply of the power factor correction circuit when the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number of times.

[0120] In one embodiment, the output period is determined based on a reference value of a current loop of the power factor correction circuit and a collected current signal of the power factor correction circuit.

[0121] In an embodiment of the present invention, a cut-off module is used to cut off the pulse width modulation signal output to the power factor correction circuit when the protection signal of the power factor correction circuit is obtained; an acquisition module is used to obtain the state of the first switch tube and the state of the second switch tube; a control module is used to control the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or to control the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube; a recovery module is used to restore the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit can operate normally. Thus, by controlling the conduction sequence of the main phase circuit and the auxiliary phase circuit, or controlling the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, it is prevented that the energy storage capacity of the main phase circuit and the auxiliary phase circuit is uneven, resulting in the overcurrent protection being triggered all the time, thereby protecting the power factor correction circuit.

[0122] As for the signal processing chip embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0123] An embodiment of the present invention further provides an electronic device, including:

[0124] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned power factor correction circuit control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0125] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned power factor correction circuit control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0126] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0127] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0128] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0129] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0130] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0131] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0132] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0133] The power factor correction circuit control method, a signal processing chip for power factor correction circuit control, an electronic device and a computer-readable storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A power factor correction circuit control method, characterized in that: The method is applied to a signal processing chip, the signal processing chip is connected to the power factor correction circuit; the power factor correction circuit comprises: a main phase circuit and an auxiliary phase circuit; the main phase circuit comprises a first switch tube; the auxiliary phase circuit comprises a second switch tube, and the method comprises: When a protection signal of the power factor correction circuit is obtained, cutting off the pulse width modulation signal output to the power factor correction circuit; Acquire a state of the first switch tube and a state of the second switch tube; According to the state of the first switch tube and the state of the second switch tube, the conduction sequence of the main phase circuit and the auxiliary phase circuit is controlled, or the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube is controlled; The pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

2. The power factor correction circuit control method according to claim 1, characterized in that: The signal processing chip includes an open-drain output pin; the power factor correction circuit includes a comparator; the open-drain output pin is connected to the comparator; when the protection signal of the power factor correction circuit is obtained, before the pulse width modulation signal output to the power factor correction circuit is cut off, the method includes: Determine whether the digital signal output by the comparator obtained by the open-drain output pin changes from the first digital signal to the second digital signal; When the open-drain output pin obtains the digital signal output by the comparator and changes from the first digital signal to the second digital signal, it is determined that the protection signal of the power factor correction circuit is obtained.

3. The power factor correction circuit control method according to claim 1, characterized in that: The acquiring the state of the first switch tube and the state of the second switch tube includes: determining the number of times the pulse width modulation signal output to the power factor correction circuit is cut off; When the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is less than or equal to a preset number of times, the state of the first switch tube and the state of the second switch tube are obtained.

4. The power factor correction circuit control method according to claim 1, characterized in that: The controlling of the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or the controlling of the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, comprises: When the first switch tube is in the on state and the second switch tube is in the off state, the initial conduction sequence of the main phase circuit and the auxiliary phase circuit is swapped.

5. The power factor correction circuit control method according to claim 1, characterized in that: The controlling of the conduction sequence of the main phase circuit and the auxiliary phase circuit according to the state of the first switch tube and the state of the second switch tube, or the controlling of the duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube, comprises: When the first switch tube is in a closed state and the second switch tube is in a conducting state, the duty cycle of the pulse width modulation signal corresponding to the second switch tube is adjusted to a preset value.

6. The power factor correction circuit control method according to claim 1, characterized in that: The method of restoring the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit operates normally includes: Detecting whether the protection signal of the power factor correction circuit disappears; If the protection signal of the power factor correction circuit disappears, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

7. The power factor correction circuit control method according to claim 6, characterized in that: If the protection signal of the power factor correction circuit disappears, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally, including: If the protection signal of the power factor correction circuit disappears, determining the output period of the pulse width modulation signal output to the power factor correction circuit; When entering the next output cycle, the pulse width modulation signal output to the power factor correction circuit is restored to enable the power factor correction circuit to operate normally.

8. The power factor correction circuit control method according to claim 3, characterized in that: The method further comprises: When the number of times the pulse width modulation signal output to the power factor correction circuit is cut off is greater than a preset number, the power supply of the power factor correction circuit is restarted.

9. The power factor correction circuit control method according to claim 7, characterized in that: The output period is determined according to a reference value of a current loop of the power factor correction circuit and a collected current signal of the power factor correction circuit.

10. A signal processing chip for power factor correction circuit control, characterized in that: The signal processing chip is connected to the power factor correction circuit; the power factor correction circuit includes: a main phase circuit and an auxiliary phase circuit; the main phase circuit includes a first switch tube; the auxiliary phase circuit includes a second switch tube, and the signal processing chip includes: A cutting module, used for cutting off the pulse width modulation signal output to the power factor correction circuit when a protection signal of the power factor correction circuit is obtained; An acquisition module, used to acquire a state of the first switch tube and a state of the second switch tube; a control module, configured to control a conduction sequence of the main phase circuit and the auxiliary phase circuit according to a state of the first switch tube and a state of the second switch tube, or to control a duty cycle of the pulse width modulation signal corresponding to one of the first switch tube and the second switch tube; The recovery module is used to recover the pulse width modulation signal output to the power factor correction circuit so that the power factor correction circuit can operate normally.

11. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the power factor correction circuit control method as described in any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the power factor correction circuit control method as described in any one of claims 1 to 9 are implemented.

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