Buck converter and control circuit and control method thereof

Abstract

The invention provides a buck converter and a control circuit and control method thereof, and the control circuit comprises a turn-off control unit which samples the output voltage of the buck converter to obtain a feedback signal, carries out the error amplification of the feedback signal and a first reference signal to obtain a compensation voltage, and generates a turn-off control signal according to the inductive current and the compensation voltage; the conduction control unit is used for generating a conduction control signal according to the first driving signal, the clock signal and the minimum turn-off time signal; and the driving unit is used for receiving the on control signal and the off control signal and generating a first driving signal to control the on or off of the first switching tube. According to the invention, on the basis of ensuring that the turn-off time of each switching period is not less than the minimum turn-off time, the switching power supply realizes constant-voltage output in a frequency reduction mode under the condition that the input voltage of the buck converter is close to the target voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to a buck converter and a control circuit and a control method thereof. Background Art

[0002] Switching power supply is a kind of power supply that uses modern power electronics technology to control the time ratio of the switch tube to be turned on and off to maintain a stable output voltage. Switching power supply is widely used in industrial automation control, military equipment, scientific research equipment, LED (Light Emitting Diode) lighting, industrial control equipment, communication equipment, power equipment, instrumentation, medical equipment and semiconductor refrigeration and heating. Among them, the buck converter has the characteristics of simple control and low cost, and is widely used in the power supply circuits of various electronic equipment.

[0003] In order to meet different application scenarios, buck converters with wide input range are widely used. However, in practical applications, due to the limitation of maximum duty cycle, when the input voltage is close to the target voltage, the output voltage may be lower than the target voltage. That is, due to the limitation of maximum duty cycle, buck converters cannot achieve a wider input voltage range.

[0004] In order to solve the above problems, the present disclosure provides a buck converter with a wide range of input voltage and a control circuit and a control method thereof. Summary of the invention

[0005] In view of the above problems, an object of the present disclosure is to provide a buck converter and a control circuit and a control method thereof, so as to realize a switching power supply with a wide input range.

[0006] According to a first aspect of the present disclosure, a control circuit of a buck converter is provided, comprising:

[0007] A shutdown control unit, sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference signal to obtain a compensation voltage, and generating a shutdown control signal according to the inductor current and the compensation voltage;

[0008] A conduction control unit, generating a conduction control signal according to the first drive signal, the clock signal, and the minimum off-time signal;

[0009] The driving unit receives the on-control signal and the off-control signal, generates a first driving signal, and controls the first switch tube to be on or off.

[0010] Optionally, the conduction control unit generates a conduction control signal according to the first drive signal, a clock signal, a minimum off-time signal and the off-control signal.

[0011] Optionally, the control circuit operates in a fixed frequency mode or a reduced frequency mode.

[0012] In the fixed frequency mode, the control circuit controls the first switch tube to be turned on based on the effective edge of the clock signal, and controls the first switch tube to be turned off when the inductor current reaches the compensation voltage;

[0013] In the frequency reduction mode, the pulse signal flips to a valid state when the valid edge of the clock signal arrives and is maintained in a valid state until the rising edge of the first drive signal arrives and the pulse signal is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to turn on according to the pulse signal in the maintained valid state, and the first switch tube is controlled to turn off when the inductor current reaches the compensation voltage.

[0014] Optionally, in fixed frequency mode,

[0015] The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0016] The conduction control signal generates a pulse of an effective state according to the off control signal of the invalid state, the pulse signal of the effective state and the minimum off time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on.

[0017] The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

[0018] Optionally, in frequency reduction mode, there are four stages:

[0019] Phase 1:

[0020] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0021] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0022] Phase 2:

[0023] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off. During the effective pulse of the shutdown control signal, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0024] The conduction control signal is kept in an invalid state according to the effective state shutdown control signal, the effective state pulse signal and the invalid state minimum shutdown time signal;

[0025] Phase 3:

[0026] After the first switch tube is turned off, the shutdown control signal returns to an invalid state, the first drive signal is in an invalid state, the minimum shutdown time signal is in an invalid state when the minimum shutdown time is not reached, and the pulse signal remains in a valid state.

[0027] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0028] Phase 4:

[0029] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state shutdown control signal, the valid state pulse signal and the valid state minimum off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to turn on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0030] Optionally, in frequency reduction mode, there are two stages:

[0031] Phase 1:

[0032] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0033] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0034] Phase 2:

[0035] After the turn-off time of the first switch tube reaches the minimum turn-off time, the minimum turn-off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state turn-off control signal, the valid state pulse signal and the valid state minimum turn-off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0036] Optionally, in fixed frequency mode,

[0037] The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0038] The conduction control signal generates a pulse of an effective state according to the pulse signal of the effective state and the minimum off-time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on.

[0039] The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

[0040] Optionally, in frequency reduction mode, there are three stages:

[0041] Phase 1:

[0042] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0043] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0044] Phase 2:

[0045] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0046] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0047] Phase 3:

[0048] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0049] Optionally, in frequency reduction mode, there are two stages:

[0050] Phase 1:

[0051] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0052] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0053] Phase 2:

[0054] After the off-time of the first switch tube reaches the minimum off-time, the minimum off-time signal flips to a valid state, and the on-control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off-time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0055] Optionally, a switching frequency of the first switch tube in the frequency reduction mode is lower than a switching frequency of the first switch tube in the fixed frequency mode.

[0056] Optionally, the frequency of the first driving signal in the frequency reduction mode is lower than the frequency of the clock signal.

[0057] Optionally, the effective edge of the first drive signal in the frequency reduction mode is synchronized or asynchronous with the effective edge of the clock signal, and the effective edge of the first drive signal in the fixed frequency mode is synchronized with the effective edge of the clock signal.

[0058] Optionally, in the fixed frequency mode, the off time of the first switch tube in one switching cycle is greater than or equal to the minimum off time, and in the reduced frequency mode, the off time of the first switch tube in one switching cycle is equal to the minimum off time.

[0059] Optionally, the conduction control unit generates a pulse signal of a valid state according to the effective edge of the clock signal, and resets the pulse signal after the first drive signal jumps to the valid state and lasts for a first time; the conduction control unit also generates the conduction control signal of the valid state according to the pulse signal of the valid state and the minimum off-time signal of the valid state, otherwise it generates the conduction control signal of the invalid state.

[0060] Optionally, the conduction control unit includes:

[0061] a monostable unit, outputting a delay signal that delays the first driving signal by the first time; a trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the pulse signal;

[0062] A first delay unit, wherein an input end of the first delay unit receives an inverted signal of the first driving signal, and an output end of the first delay unit outputs the minimum off-time signal; and

[0063] A first AND gate, wherein the first input end of the first AND gate is connected to the output end of the first delay unit to receive the minimum off-time signal, the second input end of the first AND gate is connected to the output end of the trigger to receive the pulse signal, and the output end of the first AND gate outputs the conduction control signal.

[0064] Optionally, the conduction control unit generates a pulse signal of a valid state according to the effective edge of the clock signal, and resets the pulse signal after the first drive signal jumps to the valid state and lasts for a first time; the conduction control unit also generates the conduction control signal of the valid state according to the pulse signal of the valid state, the minimum turn-off time signal of the valid state, and the turn-off control signal of the invalid state, otherwise it generates the conduction control signal of the invalid state.

[0065] Optionally, the conduction control unit includes:

[0066] a monostable unit, outputting a delay signal for delaying the first driving signal by the first time;

[0067] A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the pulse signal;

[0068] A first delay unit, wherein an input end of the first delay unit receives an inverted signal of the first drive signal, and an output end of the first delay unit outputs the minimum off-time signal;

[0069] a NOT gate, an input terminal of which receives the shutdown control signal; and

[0070] A second AND gate, wherein the first input terminal of the second AND gate is connected to the output terminal of the first delay unit to receive the minimum off-time signal, the second input terminal of the second AND gate is connected to the output terminal of the trigger to receive the pulse signal, the third input terminal of the second AND gate is connected to the output terminal of the NOT gate, and the output terminal of the second AND gate outputs the conduction control signal.

[0071] Optionally, the shutdown control unit generates the shutdown control signal in a valid state when the inductor current reaches the compensation voltage, and otherwise generates the shutdown control signal in an invalid state.

[0072] Optionally, the shutdown control unit includes:

[0073] A current sampling unit, sampling the inductor current to obtain a current sampling signal;

[0074] A voltage sampling unit, sampling the output voltage to obtain the feedback signal;

[0075] an operational amplifier, wherein a first input terminal of the operational amplifier receives the first reference signal, a second input terminal of the operational amplifier is connected to the voltage sampling unit to receive the feedback signal, and an output terminal of the operational amplifier outputs the compensation voltage;

[0076] A comparator, wherein a first input terminal of the comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the comparator receives the compensation voltage, and an output terminal of the comparator outputs the shutdown control signal.

[0077] Optionally, the driving unit generates a first driving signal of an invalid state according to an off control signal of a valid state and an on control signal of an invalid state, and generates a first driving signal of a valid state according to an on control signal of a valid state and an off control signal of an invalid state, and keeps the first driving signal at a previous level unchanged according to the on control signal of an invalid state and an off control signal of an invalid state.

[0078] Optionally, the driving unit comprises:

[0079] A latch, wherein the R end of the latch receives the shutdown control signal, the S end of the latch receives the conduction control signal, the first output end of the latch outputs the first drive signal, and the second output end of the latch outputs an inverted signal of the first drive signal.

[0080] Optionally, the shutdown control unit also receives a maximum on-time signal, and generates a shutdown control signal in a valid state when the inductor current reaches the compensation voltage or the on-time of the first switch tube reaches the maximum on-time, otherwise it generates a shutdown control signal in an invalid state.

[0081] Optionally, the shutdown control unit includes:

[0082] A current sampling unit, sampling the inductor current to obtain a current sampling signal;

[0083] A voltage sampling unit, sampling the output voltage to obtain the feedback signal;

[0084] an operational amplifier, wherein a first input terminal of the operational amplifier receives the first reference signal, a second input terminal of the operational amplifier is connected to the voltage sampling unit to receive the feedback signal, and an output terminal of the operational amplifier outputs the compensation voltage;

[0085] a comparator, wherein a first input terminal of the comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the comparator receives the compensation voltage, and an output terminal of the comparator outputs a comparison result between the current sampling signal and the compensation voltage; and

[0086] An OR gate, wherein a first input terminal of the OR gate is connected to an output terminal of the comparator, a second input terminal of the OR gate receives the maximum on-time signal, and an output terminal of the OR gate outputs the shutdown control signal.

[0087] Optionally, the minimum off-time of the first switch tube is smaller than the maximum on-time.

[0088] According to a second aspect of the present disclosure, there is provided a buck converter, comprising:

[0089] A first capacitor receives an input voltage;

[0090] The second capacitor outputs the output voltage;

[0091] inductance;

[0092] A control circuit as described above;

[0093] a first switch tube, wherein a first end of the first switch tube is connected to a first end of the first capacitor, a second end of the first switch tube is connected to a first end of the second capacitor via the inductor, and a control end of the first switch tube is connected to a control circuit to receive a first drive signal; and

[0094] A second switch tube, wherein the first end of the second switch tube is connected to the second end of the first switch tube and the inductor, the second end of the second switch tube is connected to the second end of the second capacitor and the second end of the first capacitor and is grounded, and the control end of the second switch tube is connected to the control circuit to receive an inverted signal of the first drive signal.

[0095] According to a third aspect of the present disclosure, a control method for a buck converter is provided, comprising:

[0096] Sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference signal to obtain a compensation voltage, and generating a shutdown control signal according to the inductor current and the compensation voltage;

[0097] A conduction control unit, generating a conduction control signal according to the first drive signal, the clock signal, and the minimum off-time signal;

[0098] A first driving signal is generated according to the on-control signal and the off-control signal to control the first switch tube to be on or off.

[0099] Optionally, it also includes:

[0100] A turn-on control signal is generated according to the first driving signal, the clock signal, the minimum turn-off time signal and the turn-off control signal.

[0101] Optionally, it also includes:

[0102] In the fixed frequency mode, the control circuit controls the first switch tube to be turned on based on the effective edge of the clock signal, and controls the first switch tube to be turned off when the inductor current reaches the compensation voltage;

[0103] In the frequency reduction mode, the pulse signal flips to a valid state when the valid edge of the clock signal arrives and is maintained in a valid state until the rising edge of the first drive signal arrives and the pulse signal is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to turn on according to the pulse signal in the maintained valid state, and the first switch tube is controlled to turn off when the inductor current reaches the compensation voltage.

[0104] Optionally, in fixed frequency mode,

[0105] The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0106] The conduction control signal generates a pulse of an effective state according to the off control signal of the invalid state, the pulse signal of the effective state and the minimum off time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on.

[0107] The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

[0108] Optionally, in frequency reduction mode, there are four stages:

[0109] Phase 1:

[0110] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0111] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0112] Phase 2:

[0113] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off. During the effective pulse of the shutdown control signal, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0114] The conduction control signal is kept in an invalid state according to the effective state shutdown control signal, the effective state pulse signal and the invalid state minimum shutdown time signal;

[0115] Phase 3:

[0116] After the first switch tube is turned off, the shutdown control signal returns to an invalid state, the first drive signal is in an invalid state, the minimum shutdown time signal is in an invalid state when the minimum shutdown time is not reached, and the pulse signal remains in a valid state.

[0117] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0118] Phase 4:

[0119] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state shutdown control signal, the valid state pulse signal and the valid state minimum off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to turn on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0120] Optionally, in frequency reduction mode, there are two stages:

[0121] Phase 1:

[0122] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0123] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0124] Phase 2:

[0125] After the turn-off time of the first switch tube reaches the minimum turn-off time, the minimum turn-off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state turn-off control signal, the valid state pulse signal and the valid state minimum turn-off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0126] Optionally, in fixed frequency mode,

[0127] The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0128] The conduction control signal generates a pulse of an effective state according to the pulse signal of the effective state and the minimum off-time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on.

[0129] The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

[0130] Optionally, in frequency reduction mode, there are three stages:

[0131] Phase 1:

[0132] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0133] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0134] Phase 2:

[0135] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0136] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0137] Phase 3:

[0138] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0139] Optionally, in frequency reduction mode, there are two stages:

[0140] Phase 1:

[0141] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0142] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0143] Phase 2:

[0144] After the off-time of the first switch tube reaches the minimum off-time, the minimum off-time signal flips to a valid state, and the on-control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off-time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0145] The buck converter and its control circuit and control method provided by the present disclosure determine whether the previous switching cycle is ended (this embodiment determines whether the first switch tube is in the off state and whether the off time is greater than or equal to the minimum off time according to the minimum off time signal and the first drive signal) through the conduction control unit at each edge of the clock signal to determine whether to turn on the first switch tube. On the basis of ensuring that the off time of each switching cycle is not less than the minimum off time, the frequency reduction control is used to achieve constant voltage output when the input voltage of the buck converter is close to the target voltage, thereby improving the stability and safety of the buck converter with a wide input range.

[0146] Furthermore, in the frequency reduction control mode of the present invention, the pulse signal is maintained to widen the pulse width, and then the conduction control signal is controlled by at least the pulse signal and the minimum off-time signal, so that after the off-time reaches the minimum off-time, the first switch tube is controlled to conduct according to the pulse signal in the maintained effective state, so that the switching frequency is reduced to achieve constant voltage output under high input.

[0147] The present disclosure also adds a limit on the maximum on-time, by outputting a shutdown control signal of a valid state when the on-time of the first switch tube reaches the maximum on-time according to the maximum on-time signal through the shutdown control unit, thereby limiting the minimum switching frequency and preventing the entry of audio. BRIEF DESCRIPTION OF THE DRAWINGS

[0148] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0149] Figure 1 A schematic diagram showing the structure of a buck converter provided by an embodiment of the present disclosure is shown;

[0150] Figure 2 A schematic diagram showing a control circuit of a buck converter provided by an embodiment of the present disclosure is shown;

[0151] Figure 3 A schematic diagram showing a control circuit of another buck converter provided by an embodiment of the present disclosure;

[0152] Figure 4A waveform diagram showing another control circuit of a buck converter provided by an embodiment of the present disclosure;

[0153] Figure 5 A schematic diagram showing another control circuit of a buck converter provided by an embodiment of the present disclosure is shown;

[0154] Figure 6 A flow chart of a control method for a buck converter provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0155] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0156] In practical applications, when the input voltage of the buck converter is close to the output voltage, after the maximum duty cycle is limited, the output voltage will decrease as the input voltage decreases. For example, the output voltage of the buck converter needs to be stabilized at the target voltage of 30V. For example, when the input voltage is 40V, the maximum duty cycle is required to make the output voltage reach the target voltage of 30V. For example, when the input voltage is about 35V (close to the target voltage), even if the maximum duty cycle is used, the output voltage is lower than the target voltage. That is, when the input voltage is close to the target voltage, the output voltage will decrease as the input voltage decreases due to the maximum duty cycle limit, and thus constant voltage output cannot be achieved.

[0157] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.

[0158] Figure 1 A schematic structural diagram of a buck converter provided in an embodiment of the present disclosure is shown. Figure 2 A schematic diagram of a control circuit of a buck converter provided by an embodiment of the present disclosure is shown. Figure 3 A schematic diagram of a control circuit of another buck converter provided by an embodiment of the present disclosure is shown. Figure 4 A waveform diagram of a control circuit of another buck converter provided in an embodiment of the present disclosure is shown.

[0159] like Figure 1 As shown, the buck converter includes a first switch tube Q1, a second switch tube Q2, a first capacitor C1, a second capacitor C2, an inductor Lm, and a control circuit 100.

[0160] The two ends of the first capacitor C1 receive the input voltage Vin, the first end of the first capacitor C1 is connected to the first end of the first switch tube Q1, and the second end of the first capacitor C1 is grounded. The second end of the first switch tube Q1 is connected to the first end of the inductor Lm, and the control end of the first switch tube Q1 is connected to the control circuit 100. The second end of the inductor Lm is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 is grounded, and the two ends of the second capacitor C2 output the output voltage Vout. The first end of the second switch tube Q2 is connected to the second end of the first switch tube Q1 and the first end of the inductor Lm, the second end of the second switch tube Q2 is grounded, and the control end of the second switch tube Q2 is connected to the control circuit 100.

[0161] The control circuit 100 receives the output voltage Vout, and is connected to the connection node of the first switch tube Q1 and the inductor Lm to receive the inductor current IL, and is used to provide a first drive signal VGH to the first switch tube Q1 to control the first switch tube Q1 to be turned on or off, and to provide a second drive signal VGL to the second switch tube Q2 to control the second switch tube Q2 to be turned on or off, thereby realizing the constant voltage output of the buck converter. Among them, the first drive signal VGH and the second drive signal VGL are mutually inverted signals. The control circuit 100 controls the first switch tube Q1 and the second switch tube Q2 to be turned on alternately to achieve constant voltage output through synchronous control.

[0162] Furthermore, in each switching cycle of the buck converter disclosed in the present invention, the control circuit 100 is used to control the first switch tube Q1 to be turned on and the second switch tube Q2 to be turned off, thereby causing the current IL of the inductor Lm to increase. When the inductor current IL reaches a preset value, the control circuit 100 controls the first switch tube Q1 to be turned off and the second switch tube Q2 to be turned on, and the buck converter enters the freewheeling stage. The buck converter achieves a constant output through the above control.

[0163] Furthermore, the output voltage Vout of the buck converter is Vin*Ton / (Ton+Toff), where Vin is the input voltage, Ton is the on-time of the first switch tube Q1, and Toff is the off-time of the first switch tube Q1. To ensure the circuit safety and stability of the buck converter, the off-time of the first switch tube Q1 should be limited by the minimum off-time. Under the constant frequency control mode, the value of Ton+Toff is constant, and when Toff is reduced to the minimum off-time, it cannot be reduced any further. To ensure constant voltage output, the range of the input voltage Vin of the buck converter will be limited. When the input voltage Vin is closer to the target voltage, the output voltage Vout will decrease as the input voltage Vin decreases, resulting in an inability to output constant voltage.

[0164] In order to solve the above problems, the control circuit 100 in the buck converter of the present application turns on and off the first switch tube Q1 through frequency reduction control on the basis of fixed frequency control, so that the buck converter can still maintain a constant voltage output when the input voltage is close to the target voltage.

[0165] It should be noted that the first end of the first switch tube Q1 and the second switch tube Q2 is, for example, a drain end of a transistor, the second end of the first switch tube Q1 and the second switch tube Q2 is, for example, a source end of a transistor, and the control end of the first switch tube Q1 and the second switch tube Q2 is, for example, a gate end of a transistor. In other embodiments, the first end of the first switch tube Q1 and the second switch tube Q2 may also be a source end of a transistor, and the second end of the first switch tube Q1 and the second switch tube Q2 may also be a drain end of a transistor.

[0166] like Figure 2 As shown, the control circuit 300 of the buck converter includes a turn-on control unit 310 , a turn-off control unit 120 and a driving unit 130 .

[0167] like Figure 3 As shown, the control circuit 100 of the buck converter includes a turn-on control unit 110 , a turn-off control unit 120 and a driving unit 130 .

[0168] The conduction control unit 110 generates a conduction control signal Vgs according to the first drive signal VGH, the clock signal CLK, the minimum off time signal Toffmin and the off control signal vgr. In other embodiments, the conduction control unit 310 generates a conduction control signal Vgs according to the first drive signal VGH, the clock signal CLK and the minimum off time signal Toffmin.

[0169] The shutdown control unit 120 samples the output voltage Vout of the buck converter to obtain a feedback signal Vfb, performs error amplification on the feedback signal Vfb and the first reference signal Vref1 to obtain a compensation voltage COMP, and generates a shutdown control signal Vgr according to the inductor current IL and the compensation voltage COMP. The driving unit 130 receives the on-control signal Vgs and the off-control signal Vgr, generates a first driving signal VGH, and controls the first switch tube Q1 to turn on or off.

[0170] The control circuit operates in a fixed frequency mode or a reduced frequency mode.

[0171] In the constant frequency mode, the control circuit controls the first switch tube Q1 to turn on based on the effective edge of the clock signal CLK, and controls the first switch tube Q1 to turn off when the inductor current IL reaches the compensation voltage COMP.

[0172] In the frequency reduction mode, the pulse signal Vgq flips to a valid state when the valid edge of the clock signal CLK arrives and is maintained in a valid state until the rising edge of the first drive signal VGH arrives and the pulse signal Vgq is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to be turned on according to the pulse signal Vgq in the maintained valid state, and the first switch tube is controlled to be turned off when the inductor current IL reaches the compensation voltage COMP.

[0173] For example, Figure 2 As shown:

[0174] In the fixed frequency mode, the first drive signal is in an invalid state, and the minimum off-time signal is in an effective state. When the effective edge of the clock signal arrives, the pulse signal flips to an effective state according to the effective edge of the clock signal, and the conduction control signal generates an effective pulse according to the pulse signal in the effective state and the minimum off-time signal in the effective state, thereby controlling the first drive signal to flip to an effective state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal. When the inductor current IL reaches the compensation voltage COMP, a turn-off control signal Vgr in an effective state is generated, and the first drive signal VGH becomes an invalid state to control the first switch tube Q1 to be turned off, and the turn-off control signal Vgr is reset to an invalid state.

[0175] In frequency reduction mode, there are three stages:

[0176] Phase 1:

[0177] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0178] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0179] Phase 2:

[0180] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0181] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0182] Phase 3:

[0183] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0184] Or in downclocking mode, there are two stages:

[0185] Phase 1:

[0186] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0187] The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state;

[0188] Phase 2:

[0189] After the off-time of the first switch tube reaches the minimum off-time, the minimum off-time signal flips to a valid state, and the on-control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off-time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0190] For example, Figure 3 As shown:

[0191] In fixed frequency mode,

[0192] The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0193] The conduction control signal generates a pulse of an effective state according to the off control signal of the invalid state, the pulse signal of the effective state and the minimum off time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on.

[0194] The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

[0195] In the frequency reduction mode, there are four stages:

[0196] Phase 1 (t7-t8):

[0197] When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0198] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0199] Phase 2 (t8-t9):

[0200] Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off. During the effective pulse of the shutdown control signal, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state.

[0201] The conduction control signal is kept in an invalid state according to the effective state shutdown control signal, the effective state pulse signal and the invalid state minimum shutdown time signal;

[0202] Phase 3 (t9-t10):

[0203] After the first switch tube is turned off, the shutdown control signal returns to an invalid state, the first drive signal is in an invalid state, the minimum shutdown time signal is in an invalid state when the minimum shutdown time is not reached, and the pulse signal remains in a valid state.

[0204] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0205] The fourth stage (after t10):

[0206] After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state shutdown control signal, the valid state pulse signal and the valid state minimum off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to turn on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0207] Or in downclocking mode, there are two stages:

[0208] Phase 1 (t5-t6):

[0209] The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal.

[0210] The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state;

[0211] The second stage (after t6):

[0212] After the turn-off time of the first switch tube reaches the minimum turn-off time, the minimum turn-off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state turn-off control signal, the valid state pulse signal and the valid state minimum turn-off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

[0213] Furthermore, the switching frequency of the first switch tube Q1 in the frequency reduction mode is lower than the switching frequency of the first switch tube Q1 in the fixed frequency mode.

[0214] Furthermore, the frequency of the first driving signal VGH in the frequency reduction mode is lower than the frequency of the clock signal CLK.

[0215] Furthermore, the effective edge of the first driving signal VGH in the frequency reduction mode is synchronized or asynchronous with the effective edge of the clock signal CLK, and the effective edge of the first driving signal VGH in the frequency fixed mode is synchronized with the effective edge of the clock signal CLK.

[0216] Furthermore, in the fixed frequency mode, the off time of the first switch tube Q1 in one switching cycle is greater than or equal to the minimum off time, and in the reduced frequency mode, the off time of the first switch tube Q1 in one switching cycle is equal to the minimum off time.

[0217] like Figure 2As shown, the conduction control unit 310 generates a pulse signal vgq in a valid state at the effective edge (exemplarily the rising edge) of the clock signal CLK, and resets the pulse signal Vgq after the first drive signal VGH jumps to the effective state and lasts for a first time. The conduction control unit 110 also generates a conduction control signal Vgs in a valid state according to the pulse signal Vgq in the effective state and the minimum off-time signal Toffmin in the effective state. Otherwise, a conduction control signal Vgs in an invalid state is generated. It should be noted that in the initial state, before the first effective edge of the clock signal CLK arrives, the first switch tube Q1 is in the off state, the first drive signal VGH is in an invalid state (exemplarily a low level), and when the first edge of the clock signal CLK arrives, the first drive signal VGH is in a valid state (exemplarily a high level), the conduction control signal Vgs is in an invalid state (exemplarily a low level), and the minimum off-time signal Toffmin is in a valid state (exemplarily a high level).

[0218] It should be noted that the minimum off-time signal Toffmin is a signal whose rising edge of the inverted signal VGL of the first driving signal is delayed by the minimum off-time.

[0219] Specifically, the conduction control unit 310 includes a monostable unit 111, a trigger D1, a first delay unit Delay1, and a first AND gate AND1. The monostable unit 111 receives the first drive signal VGH and outputs a delay signal of the first drive signal VGH delayed by a first time (for example, 10ns). The D terminal of the trigger D1 receives a power supply voltage VCC, the clock terminal CLK of the trigger D1 receives the clock signal CLK, the reset terminal RST of the trigger D1 is connected to the monostable unit 111 to receive the delay signal of the first drive signal VGH delayed by a first time, and the output terminal Q of the trigger D1 outputs a pulse signal Vgq. Among them, the trigger D1 is triggered at the effective edge (exemplarily the rising edge) of the clock signal CLK so that the output terminal Q follows the output of the D terminal, and resets the pulse signal Vgq output by the output terminal Q when the edge (exemplarily the rising edge) of the delay signal of the reset terminal RST arrives. The input end of the first delay unit Delay1 receives the inverted signal VGL of the first drive signal, and the output end of the first delay unit Delay1 outputs the minimum off-time signal Toffmin. The first delay unit Delay1 is used to delay the rising edge of the inverted signal VGL of the first drive signal VGH by the minimum off-time, and the delay of the falling edge of the inverted signal VGL of the first drive signal VGH can be ignored (the delay of the falling edge is used to generate the pulse width of the minimum off-time signal Toffmin). The first input end of the first AND gate AND1 is connected to the output end of the first delay unit Delay1, the second input end of the first AND gate AND1 is connected to the output end of the trigger D1 to receive the pulse signal Vgq, and the output end of the first AND gate AND1 outputs the conduction control signal Vgs.

[0220] like Figure 3 As shown, the conduction control unit 110 generates a pulse signal vgq in a valid state at the effective edge (exemplarily the rising edge) of the clock signal CLK, and resets the pulse signal Vgq after the first drive signal VGH jumps to the effective state and lasts for a first time. The conduction control unit 110 also generates a conduction control signal Vgs in a valid state according to the pulse signal Vgq in a valid state, the minimum off-time signal Toffmin in a valid state, and the off-control signal Vgr in an invalid state. Otherwise, a conduction control signal Vgs in an invalid state is generated. It should be noted that in the initial state, before the first effective edge of the clock signal CLK arrives, the first switch tube Q1 is in a turned-off state, the first drive signal VGH is in an invalid state (exemplarily a low level), and when the first edge of the clock signal CLK arrives, the first drive signal VGH is in a valid state (exemplarily a high level), the conduction control signal Vgs is in an invalid state (exemplarily a low level), and the minimum off-time signal Toffmin is in a valid state (exemplarily a high level).

[0221] It should be noted that the minimum off-time signal Toffmin is a signal whose rising edge of the inverted signal VGL of the first driving signal is delayed by the minimum off-time.

[0222] Specifically, the conduction control unit 110 includes a monostable unit 111, a trigger D1, a first delay unit Delay1, a NOT gate NOT2, and a second AND gate AND2. The monostable unit 111 receives a first drive signal VGH and outputs a delay signal of the first drive signal VGH delayed by a first time (for example, 10ns). The D terminal of the trigger D1 receives a power supply voltage VCC, the clock terminal CLK of the trigger D1 receives a clock signal CLK, the reset terminal RST of the trigger D1 is connected to the monostable unit 111 to receive a delay signal of the first drive signal VGH delayed by a first time, and the output terminal Q of the trigger D1 outputs a pulse signal Vgq. Among them, the trigger D1 is triggered at the effective edge (exemplarily the rising edge) of the clock signal CLK so that the output terminal Q follows the output of the D terminal, and resets the pulse signal Vgq output by the output terminal Q when the edge (exemplarily the rising edge) of the delay signal of the reset terminal RST arrives. The input end of the first delay unit Delay1 receives the inverted signal VGL of the first drive signal, and the output end of the first delay unit Delay1 outputs the minimum off-time signal Toffmin. Among them, the first delay unit Delay1 is used to delay the rising edge of the inverted signal VGL of the first drive signal VGH by the minimum off-time, and the delay of the falling edge of the inverted signal VGL of the first drive signal VGH can be ignored (the delay of the falling edge is used to generate the pulse width of the minimum off-time signal Toffmin). The input end of the NOT gate NOT2 receives the shutdown control signal Vgr. The first input end of the second AND gate AND2 is connected to the output end of the first delay unit Delay1, the second input end of the second AND gate AND2 is connected to the output end of the trigger D1 to receive the pulse signal Vgq, the third input end of the second AND gate AND2 is connected to the output end of the NOT gate NOT2, and the output end of the second AND gate AND2 outputs the conduction control signal Vgs.

[0223] Further, the shutdown control unit 120 generates a shutdown control signal Vgr in a valid state (exemplarily a high level) when the inductor current IL reaches the compensation voltage COMP, and otherwise generates a shutdown control signal Vgr in an invalid state (exemplarily a low level).

[0224] Specifically, the shutdown control unit 120 includes a current sampling unit 121, a voltage sampling unit 122, an operational amplifier OP1 and a comparator CMP1. The current sampling unit 121 is connected to the second end of the first switch tube Q1 of the buck converter and the first end of the inductor Lm to sample the inductor current IL and obtain a current sampling signal VIL. The current sampling unit 121, for example, includes a sampling resistor. The voltage sampling unit 122 samples the output voltage Vout of the buck converter and obtains a feedback signal Vfb. The voltage sampling unit 122, for example, includes a voltage divider network. The first input end (exemplarily the positive input end) of the operational amplifier OP1 receives the first reference signal Vref1, the second input end (exemplarily the reverse input end) of the operational amplifier OP1 receives the feedback signal Vfb, and the output end of the operational amplifier OP1 outputs a compensation voltage COMP. The compensation voltage COMP is, for example, a difference voltage between the first reference signal Vref1 and the feedback signal Vfb or an amplified value of the difference voltage. The first input terminal (exemplarily the positive input terminal) of the comparator CMP1 receives the current sampling signal VIL, the second input terminal (exemplarily the negative input terminal) of the comparator CMP1 receives the compensation voltage COMP, and the output terminal of the comparator CMP1 outputs the shutdown control signal Vgr.

[0225] The driving unit 130 is connected to the on-control unit 110 and the off-control unit 120, and generates a first driving signal VGH according to the on-control signal Vgs and the off-control signal Vgr to drive the first switch tube Q1 to be on or off. In addition, the driving unit 130 also generates a second driving signal VGL which is inverted with the first driving signal VGH to drive the second switch tube Q2 to be on or off.

[0226] Exemplarily, the driving unit 130 generates a first driving signal VGH in an invalid state (exemplarily at a low level) and a second driving signal VGL in an effective state (exemplarily at a high level) according to a turn-off control signal Vgr in an effective state (exemplarily at a high level) and a turn-on control signal Vgs in an ineffective state (exemplarily at a low level). And generates a second driving signal VGL in an invalid state (exemplarily at a low level) and a first driving signal VGH in an effective state (exemplarily at a high level) according to a turn-on control signal Vgs in an effective state (exemplarily at a high level) and a turn-off control signal Vgr in an ineffective state (exemplarily at a low level). And according to the turn-on control signal Vgs in an ineffective state (exemplarily at a low level) and the turn-off control signal Vgr in an ineffective state (exemplarily at a low level), the first driving signal VGH and the second driving signal VGL maintain the previous level state unchanged.

[0227] Specifically, the driving unit 130 includes a latch RS1. The R terminal of the latch RS1 is connected to the output terminal of the comparator CMP1 to receive the shutdown control signal Vgr, the S terminal of the latch RS1 is connected to the output terminal of the AND gate AND1 to receive the conduction control signal Vgs, the first output terminal Q of the latch RS1 outputs the first driving signal VGH, and the second output terminal of the latch RS1 outputs the first driving signal VGH. The second drive signal VGL is output. When one of the S terminal and the R terminal is at a low level, the first output terminal Q of the latch RS1 follows the S terminal output. The second output terminal Q of the latch RS1 follows the S terminal output. The level state is opposite to the level state of the first output terminal Q. When both the S terminal and the R terminal of the output terminal of the latch RS1 are at low level, the previous level state remains unchanged.

[0228] Combination Figure 4 , the three switching cycles of the buck converter are expanded.

[0229] The first switching cycle (t0-t2) operates in the constant frequency mode. When the input voltage Vin of the buck converter is high and has not reached the maximum duty cycle limit, the output voltage of the power conversion circuit can be kept constant by operating in the constant frequency mode.

[0230] At time t0, the inductor IL does not reach the compensation voltage COMP (indicating that the inductor current IL does not reach the preset value), and the shutdown control unit 110 outputs the shutdown control signal Vgr in an invalid state (exemplarily a low level). The conduction control unit 120 outputs a pulse signal Vgq in a valid state (exemplarily a high level), and then outputs a conduction control signal Vgs in a valid state (exemplarily a high level). Then, the S terminal of the latch RS1 is high level, the R terminal is low level, and the output terminal Q outputs a first drive signal VGH in a valid state (exemplarily a high level) and a second drive signal VGL in an invalid state (exemplarily a low level). The control circuit 100 controls the first switch tube Q1 to turn on and the second switch tube Q2 to turn off, and the inductor current IL rises linearly.

[0231] After the first time, the pulse signal Vgq is reset to an invalid state (exemplarily a low level), and the conduction control signal Vgs correspondingly jumps to an invalid state (exemplarily a low level). Then, the S terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0232] At time t1, the inductor IL reaches the compensation voltage COMP (indicating that the inductor current IL reaches the preset value), and the shutdown control unit 110 outputs the shutdown control signal Vgr in the valid state (exemplarily high level). The conduction control unit 120 outputs the pulse signal Vgq in the invalid state (exemplarily low level), and then outputs the conduction control signal Vgs in the invalid state (exemplarily low level). Then the S end of the latch RS1 is low level, the R end is high level, and the output end Q outputs the second drive signal VGL in the valid state (exemplarily high level) and the first drive signal VGH in the invalid state (exemplarily low level) to keep the first switch tube Q1 turned off. The control circuit 100 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on based on the frequency reduction method, and the inductor current IL decreases linearly.

[0233] After that, the inductor current IL decreases, and the shutdown control signal Vgr jumps to an invalid state (illustratively a low level). Then, the R terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged. It should be noted that the waveform of the shutdown control signal Vgr is for illustration only. In fact, the high-level pulse width of the shutdown control signal Vgr is very small and can be ignored.

[0234] In the switching cycle, the sum of the on time Ton1 and the off time Toff1 of the first switch tube Q1 is Ts1, wherein the off time Toff1 is greater than the minimum off time Tmin.

[0235] The second switching cycle (t2-t4) operates in the constant frequency mode. When the input voltage Vin of the buck converter decreases, it just reaches the maximum duty cycle limit. Working in the constant frequency mode can maintain the output voltage of the power conversion circuit constant.

[0236] At time t2, the inductor IL does not reach the compensation voltage COMP (indicating that the inductor current IL does not reach the preset value), and the shutdown control unit 110 outputs the shutdown control signal Vgr in an invalid state (exemplarily a low level). The conduction control unit 120 outputs a pulse signal Vgq in a valid state (exemplarily a high level), and then outputs a conduction control signal Vgs in a valid state (exemplarily a high level). Then, the S terminal of the latch RS1 is high level, the R terminal is low level, and the output terminal Q outputs a first drive signal VGH in a valid state (exemplarily a high level) and a second drive signal VGL in an invalid state (exemplarily a low level). The control circuit 100 controls the first switch tube Q1 to turn on and the second switch tube Q2 to turn off, and the inductor current IL rises linearly.

[0237] After the first time, the pulse signal Vgq is reset to an invalid state (exemplarily a low level), and the conduction control signal Vgs correspondingly jumps to an invalid state (exemplarily a low level). Then, the S terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0238] At time t3, the inductor IL reaches the compensation voltage COMP (indicating that the inductor current IL reaches the preset value), and the shutdown control unit 110 outputs the shutdown control signal Vgr in the valid state (exemplarily high level). The conduction control unit 120 outputs the pulse signal Vgq in the invalid state (exemplarily low level), and then outputs the conduction control signal Vgs in the invalid state (exemplarily low level). Then the S end of the latch RS1 is low level, the R end is high level, and the output end Q outputs the second drive signal VGL in the valid state (exemplarily high level) and the first drive signal VGH in the invalid state (exemplarily low level) to keep the first switch tube Q1 turned off. The control circuit 100 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on based on the frequency reduction method, and the inductor current IL decreases linearly.

[0239] After that, the inductor current IL decreases, and the shutdown control signal Vgr jumps to an invalid state (illustratively a low level). Then, the R terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged. It should be noted that the waveform of the shutdown control signal Vgr is for illustration only. In fact, the high-level pulse width of the shutdown control signal Vgr is very small and can be ignored.

[0240] In the switching cycle, the sum of the on time Ton2 and the off time Toff2 of the first switch tube Q1 is Ts1, wherein the off time Toff2 is equal to the minimum off time Tmin.

[0241] The third switching cycle (t4-t6) operates in the frequency reduction mode. When the input voltage Vin of the buck converter is close to the target voltage, due to the maximum duty cycle limitation, it operates in the frequency reduction mode to maintain the output voltage of the power conversion circuit constant.

[0242] At time t4, the inductor IL does not reach the compensation voltage COMP (indicating that the inductor current IL does not reach the preset value), and the shutdown control unit 110 outputs the shutdown control signal Vgr in an invalid state (exemplarily a low level). The conduction control unit 120 outputs a pulse signal Vgq in a valid state (exemplarily a high level), and then outputs a conduction control signal Vgs in a valid state (exemplarily a high level). Then, the S terminal of the latch RS1 is high level, the R terminal is low level, and the output terminal Q outputs a first drive signal VGH in a valid state (exemplarily a high level) and a second drive signal VGL in an invalid state (exemplarily a low level). The control circuit 100 controls the first switch tube Q1 to turn on and the second switch tube Q2 to turn off, and the inductor current IL rises linearly.

[0243] After the first time, the pulse signal Vgq is reset to an invalid state (exemplarily a low level), and the conduction control signal Vgs correspondingly jumps to an invalid state (exemplarily a low level). Then, the S terminal of the latch RS1 is at a low level, and the output of the latch RS1 remains unchanged.

[0244] At time t5, the inductor IL reaches the compensation voltage COMP (indicating that the inductor current IL reaches the preset value), and the shutdown control unit 110 outputs a shutdown control signal Vgr in a valid state (exemplarily a high level). The conduction control unit 120 outputs a pulse signal Vgq in a state (exemplarily a high level), but at this time the minimum off-time signal Toffmin is in a valid state, and then outputs a conduction control signal Vgs in an invalid state (exemplarily a low level). Then the S terminal of the latch RS1 is at a low level, the R terminal is at a high level, and the output terminal Q outputs a second drive signal VGL in a valid state (exemplarily a high level) and a first drive signal VGH in an invalid state (exemplarily a low level) to keep the first switch tube Q1 turned off. The control circuit 100 controls the first switch tube Q1 to turn off and the second switch tube Q2 to turn on based on the frequency reduction method, and the inductor current IL decreases linearly.

[0245] After that, it reaches t6 after the minimum off-time Tmin and enters the next switching cycle.

[0246] In this switching cycle, the sum of the on time Ton3 and the off time Toff3 of the first switch tube Q1 is Ts2, which is greater than Ts1, wherein the off time Toff3 is equal to the minimum off time Tmin. That is, in this switching cycle, the constant voltage output is achieved by extending the on time and maintaining the minimum off time.

[0247] Figure 5 A schematic diagram of another control circuit of a buck converter provided in an embodiment of the present disclosure is shown.

[0248] Compared with the control circuit 100, the control circuit 200 of the buck converter only changes the structure of the shutdown control unit. In addition, the shutdown control unit 220 in this embodiment can also replace the shutdown control unit 120 in the control circuit 300 to obtain a new control circuit.

[0249] The shutdown control unit 220 generates a compensation voltage COMP according to the feedback signal Vfb of the output voltage of the buck converter and the first reference signal Vref1 , and generates a shutdown control signal Vgr according to the maximum on-time signal Tonmax and a comparison result between the sampling current signal VIL and the compensation voltage COMP.

[0250] Exemplarily, the shutdown control unit 220 generates a shutdown control signal Vgr in a valid state (exemplarily a high level) when the inductor current IL reaches the compensation voltage COMP or the conduction time of the first switch tube Q1 reaches the maximum conduction time, otherwise it generates a shutdown control signal Vgr in an invalid state (exemplarily a low level).

[0251] Specifically, the shutdown control unit 220 further includes an OR gate OR1 based on the shutdown control unit 120. The first input terminal of the OR gate OR1 is connected to the output terminal of the comparator CMP1, the second input terminal of the OR gate OR1 receives the maximum on-time signal Tonmax, and the output terminal of the OR gate OR1 outputs the shutdown control signal Vgr. It should be noted that the maximum on-time signal Tonmax is, for example, a square wave signal whose pulse width is the maximum on-time and whose effective pulse is synchronized with the effective pulse of the on-control signal Vgs.

[0252] Further, the minimum off-time is smaller than the maximum on-time.

[0253] This embodiment increases the limit of the maximum on-time by outputting a shutdown control signal of a valid state when the on-time of the first switch tube reaches the maximum on-time according to the maximum on-time signal through the shutdown control unit, thereby limiting the minimum switching frequency and preventing the audio from entering.

[0254] Figure 5 A flow chart of a control method for a buck converter provided in an embodiment of the present disclosure is shown.

[0255] like Figure 5 As shown, the control method includes:

[0256] Step S100: sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and the first reference signal to obtain a compensation voltage, and generating a shutdown control signal according to the inductor current and the compensation voltage. The shutdown control unit generates the shutdown control signal in a valid state when the inductor current reaches the compensation voltage, otherwise generates the shutdown control signal in an invalid state.

[0257] In other embodiments, the shutdown control unit also receives a maximum on-time signal (Tonmax), and generates the shutdown control signal in a valid state when the inductor current reaches the compensation voltage or the on-time of the first switch tube reaches the maximum on-time, otherwise it generates the shutdown control signal in an invalid state.

[0258] Step S200: Generate a conduction control signal according to the first drive signal, the clock signal, and the minimum off-time signal. In an alternative embodiment, this step is: generate a conduction control signal according to the first drive signal, the clock signal, the minimum off-time signal, and the off-control signal. The conduction control unit generates a pulse signal of a valid state according to the effective edge of the clock signal, and resets the pulse signal after the first drive signal jumps to the valid state and lasts for a first time; the conduction control unit also generates the conduction control signal of a valid state according to the pulse signal of the valid state, the minimum off-time signal of the valid state, and the off-control signal of the invalid state, otherwise generates the conduction control signal of an invalid state.

[0259] Step S300: Generate a first drive signal to control the first switch tube to be turned on or off according to the on-control signal and the off-control signal. The first drive signal in the invalid state is generated according to the off-control signal in the valid state and the on-control signal in the invalid state, and the first drive signal in the valid state is generated according to the on-control signal in the valid state and the off-control signal in the invalid state, and the first drive signal in the valid state is maintained at the previous level state according to the on-control signal in the invalid state and the off-control signal in the invalid state.

[0260] Furthermore, it also includes:

[0261] In the fixed frequency mode, the control circuit controls the first switch tube to be turned on based on the effective edge of the clock signal, and controls the first switch tube to be turned off when the inductor current reaches the compensation voltage;

[0262] In the frequency reduction mode, the pulse signal flips to a valid state when the valid edge of the clock signal arrives and is maintained in a valid state until the rising edge of the first drive signal arrives and the pulse signal is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to turn on according to the pulse signal in the maintained valid state, and the first switch tube is controlled to turn off when the inductor current reaches the compensation voltage.

[0263] The buck converter and its control circuit and control method provided by the present disclosure determine whether the previous switching cycle is ended (this embodiment determines whether the first switch tube is in the off state and whether the off time is greater than or equal to the minimum on time according to the minimum off time signal and the first drive signal) through the conduction control unit at each edge of the clock signal to determine whether to turn on the first switch tube. On the basis of ensuring that the off time of each switching cycle is not less than the minimum off time, frequency reduction control is used to achieve constant voltage output when the input voltage of the buck converter is close to the target voltage, thereby improving the stability and safety of the buck converter with a wide input range.

[0264] Furthermore, in the frequency reduction control mode of the present invention, the pulse signal is maintained to widen the pulse width, and then the conduction control signal is controlled by at least the pulse signal and the minimum off-time signal, so that after the off-time reaches the minimum off-time, the first switch tube is controlled to conduct according to the pulse signal in the maintained effective state, so that the switching frequency is reduced to achieve constant voltage output under high input.

[0265] The present disclosure also adds a limit on the maximum on-time, by outputting a shutdown control signal of a valid state when the on-time of the first switch tube reaches the maximum on-time according to the maximum on-time signal through the shutdown control unit, thereby limiting the minimum switching frequency and preventing the entry of audio.

[0266] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a buck converter, wherein: include: A shutdown control unit, sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference signal to obtain a compensation voltage, and generating a shutdown control signal according to the inductor current and the compensation voltage; A conduction control unit, generating a conduction control signal according to the first drive signal, the clock signal, and the minimum off-time signal; The driving unit receives the on-control signal and the off-control signal, generates a first driving signal, and controls the first switch tube to be on or off.

2. The control circuit of the buck converter according to claim 1, wherein: The conduction control unit generates a conduction control signal according to the first drive signal, the clock signal, the minimum off-time signal and the off-control signal.

3. The control circuit of the buck converter according to claim 1 or 2, wherein: The control circuit operates in a fixed frequency mode or a reduced frequency mode. In the fixed frequency mode, the control circuit controls the first switch tube to be turned on based on the effective edge of the clock signal, and controls the first switch tube to be turned off when the inductor current reaches the compensation voltage; In the frequency reduction mode, the pulse signal flips to a valid state when the valid edge of the clock signal arrives and is maintained in a valid state until the rising edge of the first drive signal arrives and the pulse signal is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to turn on according to the pulse signal in the maintained valid state, and the first switch tube is controlled to turn off when the inductor current reaches the compensation voltage.

4. The control circuit of the buck converter according to claim 2, wherein: In fixed frequency mode, The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal generates a pulse of an effective state according to the off control signal of the invalid state, the pulse signal of the effective state and the minimum off time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on. The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

5. The control circuit of the buck converter according to claim 2, wherein: In the frequency reduction mode, there are four stages: Phase 1: When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 2: Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off. During the effective pulse of the shutdown control signal, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the effective state shutdown control signal, the effective state pulse signal and the invalid state minimum shutdown time signal; Phase 3: After the first switch tube is turned off, the shutdown control signal returns to an invalid state, the first drive signal is in an invalid state, the minimum shutdown time signal is in an invalid state when the minimum shutdown time is not reached, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 4: After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state shutdown control signal, the valid state pulse signal and the valid state minimum off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to turn on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

6. The control circuit of the buck converter according to claim 2, wherein: In the frequency reduction mode, there are two stages: Phase 1: The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 2: After the turn-off time of the first switch tube reaches the minimum turn-off time, the minimum turn-off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state turn-off control signal, the valid state pulse signal and the valid state minimum turn-off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

7. The control circuit of the buck converter according to claim 1, wherein: In fixed frequency mode, The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal generates a pulse of an effective state according to the pulse signal of the effective state and the minimum off-time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on. The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

8. The control circuit of the buck converter according to claim 1, wherein: In frequency reduction mode, there are three stages: Phase 1: When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 2: Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 3: After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

9. The control circuit of the buck converter according to claim 1, wherein: In the frequency reduction mode, there are two stages: Phase 1: The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 2: After the off-time of the first switch tube reaches the minimum off-time, the minimum off-time signal flips to a valid state, and the on-control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off-time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

10. The control circuit of the buck converter according to claim 3, wherein: The switching frequency of the first switch tube in the frequency reduction mode is lower than the switching frequency of the first switch tube in the fixed frequency mode.

11. The control circuit of the buck converter according to claim 3, wherein: The frequency of the first driving signal in the frequency reduction mode is lower than the frequency of the clock signal.

12. The control circuit of the buck converter according to claim 3, wherein: The effective edge of the first driving signal in the frequency reduction mode is synchronized or asynchronous with the effective edge of the clock signal, and the effective edge of the first driving signal in the fixed frequency mode is synchronized with the effective edge of the clock signal.

13. The control circuit of the buck converter according to claim 3, wherein: In the fixed frequency mode, the off time of the first switch tube in one switching cycle is greater than or equal to the minimum off time, and in the reduced frequency mode, the off time of the first switch tube in one switching cycle is equal to the minimum off time.

14. The control circuit of the buck converter according to claim 1, wherein: The conduction control unit generates a pulse signal in a valid state according to a valid edge of the clock signal, and resets the pulse signal after the first drive signal jumps to a valid state and lasts for a first time; The conduction control unit also generates the conduction control signal of the effective state according to the pulse signal of the effective state and the minimum off-time signal of the effective state, and otherwise generates the conduction control signal of the invalid state.

15. The control circuit of the buck converter according to claim 14, wherein: The conduction control unit comprises: a monostable unit, outputting a delay signal for delaying the first driving signal by the first time; A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the pulse signal; A first delay unit, wherein an input end of the first delay unit receives an inverted signal of the first driving signal, and an output end of the first delay unit outputs the minimum off-time signal; and A first AND gate, wherein the first input end of the first AND gate is connected to the output end of the first delay unit to receive the minimum off-time signal, the second input end of the first AND gate is connected to the output end of the trigger to receive the pulse signal, and the output end of the first AND gate outputs the conduction control signal.

16. The control circuit of the buck converter according to claim 2, wherein: The conduction control unit generates a pulse signal in a valid state according to a valid edge of the clock signal, and resets the pulse signal after the first drive signal jumps to a valid state and lasts for a first time; The conduction control unit also generates the conduction control signal of the effective state according to the pulse signal of the effective state, the minimum off-time signal of the effective state, and the off-control signal of the invalid state, and otherwise generates the conduction control signal of the invalid state.

17. The control circuit of the buck converter according to claim 16, wherein: The conduction control unit comprises: a monostable unit, outputting a delay signal for delaying the first driving signal by the first time; A trigger, wherein a D terminal of the trigger receives a power supply voltage, a clock terminal of the trigger receives the clock signal, a reset terminal of the trigger receives the delay signal, and an output terminal of the trigger outputs the pulse signal; A first delay unit, wherein an input end of the first delay unit receives an inverted signal of the first drive signal, and an output end of the first delay unit outputs the minimum off-time signal; a NOT gate, an input terminal of which receives the shutdown control signal; and A second AND gate, wherein the first input terminal of the second AND gate is connected to the output terminal of the first delay unit to receive the minimum off-time signal, the second input terminal of the second AND gate is connected to the output terminal of the trigger to receive the pulse signal, the third input terminal of the second AND gate is connected to the output terminal of the NOT gate, and the output terminal of the second AND gate outputs the conduction control signal.

18. The control circuit of the buck converter according to claim 1, wherein: The shutdown control unit generates the shutdown control signal in a valid state when the inductor current reaches the compensation voltage, and otherwise generates the shutdown control signal in an invalid state.

19. The control circuit of the buck converter according to claim 18, wherein: The shutdown control unit comprises: A current sampling unit, sampling the inductor current to obtain a current sampling signal; A voltage sampling unit, sampling the output voltage to obtain the feedback signal; an operational amplifier, wherein a first input terminal of the operational amplifier receives the first reference signal, a second input terminal of the operational amplifier is connected to the voltage sampling unit to receive the feedback signal, and an output terminal of the operational amplifier outputs the compensation voltage; A comparator, wherein a first input terminal of the comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the comparator receives the compensation voltage, and an output terminal of the comparator outputs the shutdown control signal.

20. The control circuit of the buck converter according to claim 1, wherein: The driving unit generates a first driving signal of an invalid state according to an off control signal of an effective state and an on control signal of an invalid state, generates a first driving signal of an effective state according to an on control signal of an effective state and an off control signal of an invalid state, and keeps a previous level state of the first driving signal unchanged according to an on control signal of an invalid state and an off control signal of an invalid state.

21. The control circuit of the buck converter according to claim 20, wherein: The driving unit comprises: A latch, wherein the R end of the latch receives the shutdown control signal, the S end of the latch receives the conduction control signal, the first output end of the latch outputs the first drive signal, and the second output end of the latch outputs an inverted signal of the first drive signal.

22. The control circuit of the buck converter according to claim 1, wherein: The shutdown control unit also receives a maximum on-time signal, and generates a shutdown control signal in a valid state when the inductor current reaches the compensation voltage or the on-time of the first switch tube reaches the maximum on-time, otherwise it generates a shutdown control signal in an invalid state.

23. The control circuit of the buck converter according to claim 22, wherein: The shutdown control unit comprises: A current sampling unit, sampling the inductor current to obtain a current sampling signal; A voltage sampling unit, sampling the output voltage to obtain the feedback signal; an operational amplifier, wherein a first input terminal of the operational amplifier receives the first reference signal, a second input terminal of the operational amplifier is connected to the voltage sampling unit to receive the feedback signal, and an output terminal of the operational amplifier outputs the compensation voltage; a comparator, wherein a first input terminal of the comparator is connected to the current sampling unit to receive the current sampling signal, a second input terminal of the comparator receives the compensation voltage, and an output terminal of the comparator outputs a comparison result between the current sampling signal and the compensation voltage; and An OR gate, wherein a first input terminal of the OR gate is connected to an output terminal of the comparator, a second input terminal of the OR gate receives the maximum on-time signal, and an output terminal of the OR gate outputs the shutdown control signal.

24. The control circuit of the buck converter according to claim 22, wherein: The minimum off time of the first switch tube is less than the maximum on time.

25. A buck converter, wherein: include: A first capacitor, receiving an input voltage; The second capacitor outputs the output voltage; inductance; A control circuit as described in any one of claims 1 to 24 above; a first switch tube, wherein a first end of the first switch tube is connected to a first end of the first capacitor, a second end of the first switch tube is connected to a first end of the second capacitor via the inductor, and a control end of the first switch tube is connected to a control circuit to receive a first drive signal; as well as A second switch tube, wherein the first end of the second switch tube is connected to the second end of the first switch tube and the inductor, the second end of the second switch tube is connected to the second end of the second capacitor and the second end of the first capacitor and is grounded, and the control end of the second switch tube is connected to the control circuit to receive an inverted signal of the first drive signal.

26. A control method for a buck converter, wherein: include: Sampling the output voltage of the buck converter to obtain a feedback signal, performing error amplification on the feedback signal and a first reference signal to obtain a compensation voltage, and generating a shutdown control signal according to the inductor current and the compensation voltage; A conduction control unit, generating a conduction control signal according to the first drive signal, the clock signal, and the minimum off-time signal; A first driving signal is generated according to the on-control signal and the off-control signal to control the first switch tube to be on or off.

27. The control method of the buck converter according to claim 26, wherein: Also includes: A turn-on control signal is generated according to the first driving signal, the clock signal, the minimum turn-off time signal and the turn-off control signal.

28. The control method of the buck converter according to claim 26, wherein: Also includes: In the fixed frequency mode, the control circuit controls the first switch tube to be turned on based on the effective edge of the clock signal, and controls the first switch tube to be turned off when the inductor current reaches the compensation voltage; In the frequency reduction mode, the pulse signal flips to a valid state when the valid edge of the clock signal arrives and is maintained in a valid state until the rising edge of the first drive signal arrives and the pulse signal is reset to an invalid state. After the off-time of the first switch tube reaches the minimum off-time, the first switch tube is controlled to turn on according to the pulse signal in the maintained valid state, and the first switch tube is controlled to turn off when the inductor current reaches the compensation voltage.

29. The control method of the buck converter according to claim 27, wherein: In fixed frequency mode, The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal generates a pulse of an effective state according to the off control signal of the invalid state, the pulse signal of the effective state and the minimum off time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on. The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

30. The control method of the buck converter according to claim 27, wherein: In the frequency reduction mode, there are four stages: Phase 1: When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 2: Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off. During the effective pulse of the shutdown control signal, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the effective state shutdown control signal, the effective state pulse signal and the invalid state minimum shutdown time signal; Phase 3: After the first switch tube is turned off, the shutdown control signal returns to an invalid state, the first drive signal is in an invalid state, the minimum shutdown time signal is in an invalid state when the minimum shutdown time is not reached, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 4: After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state shutdown control signal, the valid state pulse signal and the valid state minimum off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to turn on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

31. The control method of the buck converter according to claim 27, wherein: In the frequency reduction mode, there are two stages: Phase 1: The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the off control signal in the invalid state, the pulse signal in the valid state, and the minimum off time signal in the invalid state; Phase 2: After the turn-off time of the first switch tube reaches the minimum turn-off time, the minimum turn-off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the invalid state turn-off control signal, the valid state pulse signal and the valid state minimum turn-off time signal, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

32. The control method of the buck converter according to claim 26, wherein: In fixed frequency mode, The first driving signal is in an invalid state, the minimum off-time signal is in a valid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal generates a pulse of an effective state according to the pulse signal of the effective state and the minimum off-time signal of the effective state, thereby controlling the first driving signal to flip to the effective state to control the first switch tube to be turned on. The pulse signal is reset to an invalid state according to a rising edge of the first driving signal.

33. The control method of the buck converter according to claim 26, wherein: In frequency reduction mode, there are three stages: Phase 1: When the first driving signal is in a valid state, the first switch tube is in a conducting state, and the minimum off-time signal is in an invalid state, the effective edge of the clock signal arrives, and the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 2: Until the inductor current reaches the compensation voltage, the shutdown control signal generates a valid pulse to control the first switch tube to be turned off, the first drive signal is flipped to an invalid state, the minimum off-time signal is in an invalid state, and the pulse signal remains in a valid state. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 3: After the first switch tube is turned off and reaches the minimum off time, the minimum off time signal flips to a valid state, and the conduction control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

34. The control method of the buck converter according to claim 26, wherein: In the frequency reduction mode, there are two stages: Phase 1: The first driving signal is in an invalid state, the first switch tube is in an off state, the minimum off time signal is in an invalid state, and when the effective edge of the clock signal arrives, the pulse signal flips to a valid state according to the effective edge of the clock signal. The conduction control signal is kept in an invalid state according to the pulse signal in the valid state and the minimum off-time signal in the invalid state; Phase 2: After the off-time of the first switch tube reaches the minimum off-time, the minimum off-time signal flips to a valid state, and the on-control signal generates a valid pulse according to the pulse signal of the valid state and the minimum off-time signal of the valid state, thereby controlling the first drive signal to flip to a valid state to control the first switch tube to be turned on, and the pulse signal is reset to an invalid state according to the rising edge of the first drive signal.

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