Filter, preparation method thereof and electronic equipment

Abstract

The invention provides a filter, a preparation method thereof and electronic equipment, and belongs to the technical field of passive devices. The filter comprises a dielectric substrate, at least one capacitor and at least one inductor, wherein the at least one capacitor and the at least one inductor are integrated on the dielectric substrate; the filter further comprises a first buffer layer arranged on the dielectric substrate. The first buffer layer is made of an organic material; the first buffer layer is provided with a first accommodating part and a second accommodating part; the first containing part is filled with a first pole plate of the capacitor, the second containing part is filled with at least part of structure of the inductor, and the surface, away from the dielectric substrate, of the first pole plate of the capacitor and the surface, away from the dielectric substrate, of the structure, filled in the second containing part, of the inductor are flush with the surface, away from the dielectric substrate, of the first buffer layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of passive devices, and in particular relates to a filter and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of communication technology, the frequency used in mobile communications is getting higher and higher, from hundreds of megahertz in 2G technology to 3.5GHz and millimeter wave in 5G technology. The current market demand for the miniaturization of electronic products is getting higher and higher. At present, passive devices such as capacitors, inductors, and resistors account for about 70% of the area on the printed circuit board (PCB). Integrated passive devices (IPD) technology can reduce the area of ​​passive devices by more than 80%, and the market prospects are broad. Based on the different integrated substrates, integrated passive device technology can be divided into silicon-based, low-temperature co-fired ceramic (LTCC)-based, glass-based and other technical routes. As the main energy-consuming component in electronic products, the RF front end requires a significant reduction in device electromagnetic loss. Due to the advantages of glass-based materials in dielectric loss and cost, glass-based integrated passive devices have gradually become the mainstream route.

[0003] Glass-based IPDs directly stack single-sided or double-sided metal redistributed layer (RDL) lines on the glass surface. The metal RDL lines and glass materials have a difference of 3 to 7 times in thermal expansion coefficient and a difference of more than 10 to more than 300 times in thermal conductivity. The metal RDL lines are good conductors of heat and have a much larger thermal expansion coefficient than glass. When these two materials are directly interconnected, single-layer and multi-layer structures of different material layers (metal material layer, organic material layer, inorganic material layer) are stacked on top of them. During the process of structure manufacturing, flip-chip welding, and reliability testing, thermal stress will exist and be transferred to the interconnection surface of the metal RDL lines and glass, which will increase the risk of delamination and detachment of the metal RDL lines and the glass interconnection layer, and the reliability and performance of the device will decline or fail. Especially when multi-layer metal RDL lines and organic materials are stacked, the risk of delamination causing the reliability and performance of the device to decline or fail is higher. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a filter and a preparation method thereof, and an electronic device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a filter, comprising a dielectric substrate, at least one capacitor and at least one inductor integrated on the dielectric substrate; the filter also comprises a first buffer layer arranged on the dielectric substrate; the material of the first buffer layer is an organic material;

[0006] The first buffer layer has a first accommodating portion and a second accommodating portion; the first electrode plate of the capacitor is filled in the first accommodating portion, and at least a part of the structure of the inductor is filled in the second accommodating portion, and the first electrode plate of the capacitor is away from the surface of the dielectric substrate, and the structure of the inductor filled in the second accommodating portion is away from the surface of the dielectric substrate, and both are flush with the surface of the first buffer layer away from the dielectric substrate.

[0007] In some embodiments, the dielectric substrate includes a first surface and a second surface disposed opposite to each other along a thickness direction thereof, and a first connecting via penetrating along a thickness direction thereof; the first buffer layer is disposed on the first surface;

[0008] The inductor comprises a first conductive structure arranged on the first surface, a second conductive structure arranged on the second surface, and a first connecting electrode arranged in the first connecting via; the second conductive structure is electrically connected to the first conductive structure through the first connecting electrode to form a coil structure of the inductor;

[0009] The second accommodation portion penetrates the entire thickness of the first buffer layer, and the second conductive structure is filled in the second accommodation portion.

[0010] In some embodiments, the filter further comprises a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material;

[0011] The second buffer layer has a third accommodating portion, the third accommodating portion runs through the entire thickness of the second buffer layer, the first conductive structure is filled in the third accommodating portion, and a surface of the first conductive structure away from the dielectric substrate is flush with a surface of the second buffer layer away from the dielectric substrate.

[0012] In some embodiments, the first receiving portion penetrates a portion of the thickness of the first buffer layer.

[0013] In some embodiments, the dielectric substrate has a first slot partially penetrating along a thickness direction thereof, and the first slot defines the first accommodation portion.

[0014] In some embodiments, both the first accommodation portion and the second accommodation portion penetrate a portion of the thickness of the first buffer layer; and the coil structure of the inductor is filled in the second accommodation portion.

[0015] In some embodiments, the dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof;

[0016] The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

[0017] In some embodiments, the first buffer layer serves as the dielectric substrate.

[0018] In some embodiments, the organic material includes any one of polyimide, resin, and photoresist.

[0019] In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, comprising: providing a dielectric substrate, forming at least one capacitor and at least one inductor on the dielectric substrate, and further comprising forming a first buffer layer on the dielectric substrate; the step of forming the first buffer layer comprises:

[0020] Cleaning and drying the dielectric substrate;

[0021] forming a first film layer on the dielectric substrate; the first film layer covers the dielectric substrate;

[0022] The first film layer is patterned to form the first buffer layer; the first buffer layer has a first accommodating portion and a second accommodating portion, the first accommodating portion is configured to accommodate a first plate of a capacitor, and the second accommodating portion is configured to accommodate at least a partial structure of an inductor.

[0023] In some embodiments, both the first receiving portion and the second receiving portion penetrate a portion of the thickness of the first buffer layer, and the second receiving portion is configured to receive a coil structure of an inductor.

[0024] In some embodiments, the dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof;

[0025] The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

[0026] In some embodiments, the first film layer includes a first sub-film layer and a second sub-film layer which are sequentially formed in a direction away from the dielectric substrate.

[0027] In some embodiments, the step of forming at least one capacitor and at least one inductor on the dielectric substrate includes:

[0028] forming a first conductive film layer on a side of the first buffer layer away from the dielectric substrate; the first conductive film layer covers the first buffer layer;

[0029] The first conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a coil structure of the inductor; surfaces of the first electrode plate and the coil structure facing away from the dielectric substrate are flush with a surface of the first buffer layer facing away from the dielectric substrate.

[0030] In some embodiments, the dielectric substrate includes a first surface and a second surface disposed opposite to each other along a thickness direction thereof, and a first connecting via penetrating along a thickness direction thereof; the first buffer layer is disposed on the first surface;

[0031] The filter further comprises a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material;

[0032] The second buffer layer has a third accommodating portion, the third accommodating portion runs through the entire thickness of the second buffer layer, the third accommodating portion is configured to accommodate a first conductive structure of an inductor, and a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate;

[0033] The second receiving portion penetrates the entire thickness of the first buffer layer, and the second receiving portion is configured to receive a second conductive structure of an inductor.

[0034] In some embodiments, the first receiving portion penetrates a portion of the thickness of the first buffer layer.

[0035] In some embodiments, the dielectric substrate has a first slot partially penetrating along a thickness direction thereof, and the first slot defines the first accommodation portion.

[0036] In some embodiments, the step of forming at least one capacitor and at least one inductor on the dielectric substrate includes:

[0037] forming a first connection electrode of the inductor in the first connection via hole;

[0038] forming a second conductive film layer on a side of the second buffer layer away from the dielectric substrate;

[0039] The second conductive film layer is polished flat by CMP to form a first conductive structure of the inductor; a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate;

[0040] forming a third conductive film layer on a side of the first buffer layer away from the dielectric substrate;

[0041] The third conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a second conductive structure of the inductor; surfaces of the first electrode plate and the second conductive structure facing away from the dielectric substrate are both flush with a surface of the first buffer layer facing away from the dielectric substrate.

[0042] In a third aspect, an embodiment of the present disclosure further provides an electronic device, which includes the filter described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic structural diagram of an exemplary glass-based 3D IPD filter;

[0044] Figure 2 A schematic diagram of the structure of a filter provided in an embodiment of the present disclosure;

[0045] Figure 3 A schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0046] Figure 4 A schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0047] Figure 5 A schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0048] Figure 6 A schematic diagram of the structure of another filter provided in an embodiment of the present disclosure;

[0049] Figure 7a to Figure 7c A flow chart of a preparation process for forming a first buffer layer provided in an embodiment of the present disclosure;

[0050] Figure 8a to Figure 8c Another process flow chart of forming a first buffer layer provided in an embodiment of the present disclosure;

[0051] Figure 9a to Figure 9e Another process flow chart of forming a first buffer layer provided in an embodiment of the present disclosure;

[0052] Figure 10a to Figure 10d Another process flow chart of forming a first buffer layer provided in an embodiment of the present disclosure;

[0053] Fig.11 is a cross-sectional view of the first buffer layer in an embodiment of the present disclosure;

[0054] Figure 12a to Figure 12d A process flow chart of a filter manufacturing method provided by an embodiment of the present disclosure;

[0055] Figure 13a to Figure 13dA process flow chart of another filter manufacturing method provided by an embodiment of the present disclosure;

[0056] Figure 14a to Figure 14e A process flow chart of another filter manufacturing method provided by an embodiment of the present disclosure;

[0057] Figure 15a to Figure 15f A process flow chart of another filter manufacturing method provided by an embodiment of the present disclosure;

[0058] Figure 16a to Figure 16g A flow chart of a process for preparing another filter provided in an embodiment of the present disclosure.

[0059] The figures are marked as follows: 1. dielectric substrate; S1. first surface; S2. second surface; 21. first conductive structure; 22. second conductive structure; 23. first connecting electrode; 24. coil structure; 31. first electrode plate; 32. dielectric layer; 4. interlayer insulating layer; 5. protective layer; 6. first buffer layer; 61. first accommodating portion; 62. second accommodating portion; 7. second buffer layer; 71. third accommodating portion; 81. first slot; 82. second slot; 9. temporary carrier layer; 01. cutting path; 02. etching mask layer; 03. first film layer; 031. first sub-film layer; 032. second sub-film layer; 04. interface; 05. first conductive film layer; 06. second conductive film layer; 07. third conductive film layer. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0063] In the prior art, LC-type two-dimensional (2D) or three-dimensional (3D) IPD filters usually involve the stacking and overlapping of multiple layers of metal. The overlapping conditions of each layer of metal directly determine the performance and reliability of the device. Therefore, the more metal layers there are, the greater the process difficulty and the greater the risk of failure. Glass-based IPD is to directly stack single-sided or double-sided metal RDL lines on a glass substrate, and then make other stacked layers. The metal RDL lines referred to in the embodiments of the present disclosure refer to metal layers formed on one or both sides of a glass substrate. Figure 1 is a schematic diagram of the structure of an exemplary glass-based 3D IPD filter, as shown in Figure 1As shown, the filter includes a dielectric substrate 1, and at least one inductor and at least one capacitor integrated on the dielectric substrate 1. In the disclosed embodiment, the dielectric substrate 1 is a glass substrate, and the dielectric substrate 1 includes a first surface S1 and a second surface S2 arranged opposite to each other along its thickness direction, and a first connecting via hole penetrating along its thickness direction; the inductor includes a first conductive structure 21 arranged on the first surface S1, a second conductive structure 22 arranged on the second surface S2, and a first connecting electrode 23 arranged in the first connecting via hole; the second conductive structure 22 is electrically connected to the first conductive structure 21 through the first connecting electrode 23, and forms a coil structure 24 of the inductor; the capacitor includes a first electrode plate 31 arranged on the same layer as the second conductive structure 22, and a dielectric layer 32 arranged on the side of the first electrode plate 31 away from the dielectric substrate 1.

[0064] It should be noted that the "same-layer arrangement" in the embodiments of the present disclosure means that multiple structures are formed by the same material layer through a patterning process, so these structures are in the same layer in terms of stacking relationship; but this does not mean that the distances between these structures and the substrate must be the same. In the embodiments of the present disclosure, the "patterning process" refers to the steps of forming a structure with a specific pattern, which can be a photolithography process, which includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and stripping a photoresist; of course, the "patterning process" can also be other processes such as an imprinting process and an inkjet printing process.

[0065] Specifically, Figure 1 As shown, the filter also includes an interlayer insulating layer 4 arranged on the side of the second conductive structure 22 and the dielectric layer 32 away from the dielectric substrate 1, and a protective layer 5 arranged on the side of the first conductive structure 21 away from the dielectric substrate 1, and the interlayer insulating layer 4 has an opening exposing the second conductive structure 22 and the dielectric layer 32. The material of the interlayer insulating layer 4 can be an inorganic insulating material. For example, an inorganic insulating layer formed by silicon nitride (SiNx), or an inorganic insulating layer formed by silicon dioxide (SiO2), or a plurality of stacked composite film layers of SiNx inorganic insulating layers and SiO2 inorganic insulating layers. The metal RDL circuit in the filter is the first conductive structure 21, the second conductive structure 22 and the first electrode 31.

[0066] The inventors found that if Figure 1 The filter shown has the following problems:

[0067] 1) Poor reliability.

[0068] Due to the mismatch in thermal expansion coefficient and thermal conductivity between glass and metal materials, the combined effects of thermal shock and stress can easily lead to repeated expansion and contraction between the interconnect layer glass and the metal RDL line, causing material fatigue and delamination, shedding, high impedance, etc., which can lead to performance degradation or failure of the IPD.

[0069] Specifically, Figure 1 As shown, the first conductive structure 21 of the inductor, the second conductive structure 22 and the first plate 31 of the capacitor are directly connected to the glass substrate, wherein the second conductive structure 22 of the inductor and the first plate 31 of the capacitor facing away from the glass substrate will continue to stack single-layer and multi-layer structures of different material layers (metal material layer, organic material layer, inorganic material layer) in the future, and solder balls (Solder ball) or copper pillar bumps (Cu pillarbump) are made on the pads of the outermost metal RDL circuit, and they will be reflow soldered during the subsequent flip-chip soldering on the PCB substrate and reliability testing. Due to the large difference in thermal expansion coefficient and thermal conductivity between the metal RDL circuit and the glass, the metal RDL circuit is a good conductor of heat, and the thermal expansion coefficient is much larger than that of glass. When these two materials are directly interconnected, the heat is transmitted to the interconnection surface with the glass in a very short time through the metal RDL circuit, which generates a thermal shock to the interconnection layer, which is easy to cause repeated expansion and contraction between the interconnection layer glass and the metal RDL, resulting in material fatigue, and easy to cause the interconnection layer to be delaminated and fall off, thereby causing the performance of the IPD to degrade or fail. Especially when multi-layer metal RDL lines and organic materials are stacked, the multi-layer structure will generate greater stress and transfer it to the metal layer and glass interconnect interface, making delamination more likely to occur, which will reduce the reliability and performance of the device or increase the risk of failure.

[0070] 2) Device performance is unstable and has poor consistency.

[0071] The surface flatness and roughness of the layer where the second conductive structure 22 of the inductor and the first electrode 31 of the capacitor are located are difficult to control, which will lead to poor capacitance consistency, reduced and unstable device performance, and increased process manufacturing costs and control difficulties.

[0072] It should be noted that the disclosed embodiment only illustrates the first electrode 31 and the dielectric layer 32 of the capacitor. In fact, the capacitor also includes a second electrode arranged on the side of the dielectric layer 32 away from the dielectric substrate 1. The capacitor is a flat-plate capacitor structure, that is, a capacitor with a MIM (metal-insulator-metal) structure formed by two parallel metal electrodes and an insulating dielectric layer 32 in the middle. The capacitance is mainly determined by factors such as the overlapping area of ​​the metal electrodes, the metal flatness and the characteristics of the dielectric material. Although the capacitor structure is relatively simple, only by finely manufacturing each layer of material can the uniformity and accuracy of the integrated capacitor be effectively guaranteed. Specifically, the MIM structure capacitor is usually composed of three layers: an upper metal layer, a middle insulating layer and a lower metal layer. The upper metal layer and the lower metal layer are respectively connected to the external electrodes, and the current is conducted through the upper metal layer and the lower metal layer; the middle insulating layer separates the upper metal layer and the lower metal layer, that is, separates their electric potentials, thereby generating a capacitor circuit. As shown Figure 1As shown, the first plate 31 of the capacitor is the lower metal layer, the second plate not shown is the upper metal layer, the capacitor also includes a dielectric layer 32 (middle insulating layer) located between the first plate 31 and the second plate, and the capacitor is connected to the outside through a connecting structure.

[0073] The first electrode 31 serves as the lower metal layer of the capacitor. When forming the first electrode 31, a thick copper layer needs to be prepared. When the copper is thickened by copper electroplating, the copper surface has poor flatness and high roughness, which will lead to poor flatness of the dielectric layer 32, deteriorate the capacitor uniformity, and reduce and become unstable in device performance. To improve the capacitor uniformity, it is necessary to improve the flatness and roughness of the copper surface on the first electrode 31. Currently, chemical mechanical polishing (CMP) technology can be introduced to solve this problem. However, when using CMP, the electroplated thick copper layer on the first electrode 31 does not have an effective CMP cutoff layer, which will cause CMP to be unable to control the amount of copper grinding, and thus it is difficult to control the copper thickness after CMP. The separate production of the corresponding cutoff layer will increase the complexity of the process and the production cost. Therefore, it is difficult to use CMP for the following: Figure 1 Figure 2 shows the improvement in capacitor uniformity in the IPD filter.

[0074] In summary, if Figure 1 The IPD filter shown has poor reliability, unstable device performance and poor uniformity, while increasing the cost of process manufacturing and the difficulty of control.

[0075] In view of this, embodiments of the present disclosure provide a filter that substantially eliminates one or more of the problems caused by limitations and defects of the related art.

[0076] In the first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a filter, Figure 2 Schematic diagram of a filter structure provided in an embodiment of the present disclosure. Figure 2 As shown, the filter in the embodiment of the present disclosure includes a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1; the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62; the first plate 31 of the capacitor is filled in the first accommodating portion 61, and at least part of the structure of the inductor is filled in the second accommodating portion 62, and the surface of the first plate 31 of the capacitor facing away from the dielectric substrate 1, and the surface of the inductor filled in the second accommodating portion 62 facing away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0077] It should be noted that the three-dimensional integration of digital circuits (such as dynamic random access memory (DRAM), logic chips, etc.) currently generally adopts silicon substrates and through silicon via technology (TSV). In recent years, as people's demand for communication capacity and speed continues to increase, the communication frequency continues to increase. Due to high-frequency applications, the materials used for adapters or substrates must have low dielectric loss and low dielectric constant to reduce the RF power dissipation of the substrate and increase the self-resonance frequency. Since silicon is a semiconductor material, the carriers around TSV can move freely under the action of electric or magnetic fields, affecting adjacent circuits or signals and reducing the high-frequency performance of the chip. However, there is no free-moving charge inside the glass, the thermal expansion coefficient is adjustable, and the dielectric properties are excellent. Replacing silicon substrates with glass substrates and replacing TSVs with through glass via technology (TGV) can effectively avoid the high-frequency loss problem of TSV. In addition, due to the semiconductor properties of silicon, TSV also requires the production of electrical isolation layers, diffusion barrier layers, seed layers, and void-free copper filling in the through-holes. Not only is the process complex, but the parasitic capacitance is also significant, and it is often difficult to meet the performance requirements of three-dimensional integrated RF microsystems. TGV technology can eliminate the need for copper-filled barrier layers and oxide capping film layers, reduce the via capacitance between the copper-plated layer and the substrate, and reduce electromagnetic interference between the active and passive circuits of the vias. It can also significantly reduce process complexity and processing costs. The thinning and polishing process of glass is also relatively simple compared to silicon. Therefore, for the RF field, glass is a suitable material, and TGV is also an ideal three-dimensional integration solution.

[0078] Therefore, when describing the IPD filter in the embodiments of the present disclosure, the dielectric substrate 1 is described in detail using a glass substrate as an example, and will not be described in detail below. The 2D and 3D in the present disclosure refer to the inductor structure, and the capacitor in the filter is a 2D structure. The drawings in the embodiments of the present disclosure are only for illustration and are used to make it easier to understand the present invention. The specific specifications and parameters need to be designed and adjusted according to the specific product requirements.

[0079] Continue to refer to Figure 2Compared with the filter in the prior art, the filter in the embodiment of the present disclosure is provided with a first buffer layer 6, and the material of the first buffer layer 6 is an organic material. The first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62; the first plate 31 of the capacitor is filled in the first accommodating portion 61, and at least part of the structure of the inductor is filled in the second accommodating portion 62, and the surface of the first plate 31 of the capacitor away from the dielectric substrate 1, and the surface of the structure of the inductor filled in the second accommodating portion 62 away from the dielectric substrate 1, are flush with the surface of the first buffer layer 6 away from the dielectric substrate 1. The metal RDL circuit in the embodiment of the present disclosure is the first plate 31 of the capacitor filled in the first accommodating portion 61, and at least part of the structure of the inductor filled in the second accommodating portion 62. Such a configuration allows the first buffer layer 6 to buffer heat and stress, effectively solving the risk of delamination at the interface between the metal RDL line and the glass substrate interconnection layer due to heat and stress shock, and avoiding a decrease in device reliability and performance or failure. At the same time, the first buffer layer 6 in the disclosed embodiment can also serve as a stop layer for CMP planarization of the metal RDL line, thereby simplifying the process scheme for CMP planarization of the metal RDL line, reducing process difficulty and cost, and improving quality and efficiency.

[0080] In some embodiments, Figure 2 As shown, the dielectric substrate 1 includes a first surface S1 and a second surface S2 which are arranged opposite to each other along the thickness direction thereof, and a first connecting via hole which penetrates along the thickness direction thereof; a first buffer layer 6 is arranged on the first surface S1; the inductor includes a first conductive structure 21 arranged on the first surface S1, a second conductive structure 22 arranged on the second surface S2, and a first connecting electrode 23 arranged in the first connecting via hole; the second conductive structure 22 is electrically connected to the first conductive structure 21 through the first connecting electrode 23 to form the inductor; the second accommodating portion 62 penetrates the entire thickness of the first buffer layer 6, and the second conductive structure 22 is filled in the second accommodating portion 62.

[0081] Specifically, Figure 2As shown, the filter in the embodiment of the present disclosure is a glass-based 3D IPD filter, the first plate 31 of the capacitor is filled in the first accommodating portion 61, the second conductive structure 22 of the inductor is filled in the second accommodating portion 62, and the second accommodating portion 62 runs through the entire thickness of the first buffer layer 6. The surface of the first plate 31 of the capacitor away from the dielectric substrate 1 and the surface of the second conductive structure 22 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1. The metal RDL circuit in the embodiment of the present disclosure is the first plate 31 of the capacitor filled in the first accommodating portion 61 and the second conductive structure 22 of the inductor filled in the second accommodating portion 62. This arrangement allows the first buffer layer 6 to buffer heat and stress, effectively solve the risk of delamination at the interface between the metal RDL circuit and the glass substrate interconnection layer caused by heat and stress shock, and avoid the reliability and performance of the device from being reduced or failing; at the same time, the first buffer layer 6 in the embodiment of the present disclosure can also be used as a stop layer for CMP planarization of the metal RDL circuit, simplifying the process scheme of CMP planarization of the metal RDL circuit, reducing process difficulty and cost, and improving quality and efficiency.

[0082] In some embodiments, Figure 2 As shown, the filter in the embodiment of the present disclosure includes not only the first buffer layer 6, but also the second buffer layer 7 arranged on the second surface S2; the material of the second buffer layer 7 is an organic material; the second buffer layer 7 has a third accommodating portion 71; the third accommodating portion 71 runs through the entire thickness of the second buffer layer 7, the first conductive structure 21 is filled in the third accommodating portion 71, and the surface of the first conductive structure 21 away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 away from the dielectric substrate 1.

[0083] Specifically, Figure 2As shown, in the embodiment of the present disclosure, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the second buffer layer 7 has a third accommodating portion 71; the first plate 31 of the capacitor is filled in the first accommodating portion 61, the second conductive structure 22 of the inductor is filled in the second accommodating portion 62, and the first conductive structure 21 of the inductor is filled in the third accommodating portion 71, and the surface of the first plate 31 of the capacitor away from the dielectric substrate 1 and the surface of the second conductive structure 22 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1, and the surface of the first conductive structure 21 away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 away from the dielectric substrate 1. The metal RDL circuit in the embodiment of the present disclosure is the first plate 31 of the capacitor filled in the first accommodating portion 61, the second conductive structure 22 of the inductor filled in the second accommodating portion 62, and the first conductive structure 21 filled in the third accommodating portion 71. Such an arrangement allows the first buffer layer 6 and the second buffer layer 7 to buffer heat and stress, effectively solving the risk of delamination at the interface between the metal RDL line and the glass substrate interconnection layer due to heat and stress shock, and avoiding a decrease in device reliability and performance or failure. At the same time, the first buffer layer 6 and the second buffer layer 7 in the disclosed embodiment can also serve as a stop layer for CMP planarization of the metal RDL line, thereby simplifying the process scheme for CMP planarization of the metal RDL line, reducing process difficulty and cost, and improving quality and efficiency.

[0084] In some embodiments, Figure 2 As shown, the first receiving portion 61 penetrates part of the thickness of the first buffer layer 6. The dielectric substrate 1 of the filter in the embodiment of the present disclosure is a flat glass substrate, and the first receiving portion 61 penetrates part of the thickness of the first buffer layer 6 to accommodate the first electrode 31 of the capacitor.

[0085] In some embodiments, Figure 3 FIG. 1 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure, such as Figure 3As shown, the filter in the embodiment of the present disclosure is a glass-based 3D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the dielectric substrate 1 includes a first surface S1 and a second surface S2 arranged opposite to each other along its thickness direction, and a first connecting via hole penetrating along its thickness direction; the inductor includes a first conductive structure 21 arranged on the first surface S1, a second conductive structure 22 arranged on the second surface S2, and a first connecting electrode 23 arranged in the first connecting via hole; the second conductive structure 22 is electrically connected to the first conductive structure 21 through the first connecting electrode 23, and forms a coil structure of the inductor. The filter further comprises a first buffer layer 6 arranged on a first surface S1 of the dielectric substrate 1, and a second buffer layer 7 arranged on a second surface S2 of the dielectric substrate 1; the materials of the first buffer layer 6 and the second buffer layer 7 are both organic materials; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, the second buffer layer 7 has a third accommodating portion 71, the second accommodating portion 62 penetrates the entire thickness of the first buffer layer 6, and the third accommodating portion 71 penetrates the entire thickness of the second buffer layer 7; the first plate 31 of the capacitor is filled in the first accommodating portion 61, the second conductive structure 22 of the inductor is filled in the second accommodating portion 62, the first conductive structure 21 of the inductor is filled in the third accommodating portion 71, and the surface of the first plate 31 of the capacitor away from the dielectric substrate 1 and the surface of the second conductive structure 22 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1, and the surface of the first conductive structure 21 of the inductor away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 away from the dielectric substrate 1; the dielectric substrate 1 has a first slot 81 partially penetrated along the thickness direction thereof, and the first slot 81 defines the first accommodating portion 61.

[0086] The dielectric substrate 1 of the filter in the embodiment of the present disclosure is a grooved glass substrate, and the glass substrate is grooved to form a first groove 81 that partially penetrates along the thickness direction thereof, and when the first buffer layer 6 is formed on the glass substrate, the first groove 81 defines a first accommodation portion 61. In this way, the first buffer layer 6 does not need to be processed to form the first accommodation portion 61.

[0087] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure, such as Figure 4As shown, the filter in the embodiment of the present disclosure is a glass-based 2D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1, and the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6; the first electrode 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first electrode 31 of the capacitor away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0088] Specifically, Figure 4 As shown, the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6. The dielectric substrate 1 of the filter in the embodiment of the present disclosure is a flat glass substrate, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6 to accommodate the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor.

[0089] In some embodiments, Figure 5 FIG. 1 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure, such as Figure 5 As shown, the filter in the embodiment of the present disclosure is a glass-based 2D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1, and the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62; the dielectric substrate 1 has a first slot 81 and a second slot 82 partially penetrating along the thickness direction thereof; the first buffer layer 6 covers the dielectric substrate 1, and the first slot 81 defines the first accommodating portion 61, and the second slot 82 defines the second accommodating portion 62; the first electrode plate 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first electrode plate 31 of the capacitor away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0090] Specifically, Figure 5As shown, the dielectric substrate 1 of the filter in the embodiment of the present disclosure is a grooved glass substrate, and the glass substrate is grooved to form a first groove 81 and a second groove 82 that partially penetrate along the thickness direction thereof, and when the first buffer layer 6 is formed on the glass substrate, the first groove 81 defines a first accommodation portion 61, and the second groove 82 defines a second accommodation portion 62. In this way, the first buffer layer 6 may not be processed to form the first accommodation portion 61 and the second accommodation portion 62.

[0091] In some embodiments, Figure 6 FIG. 1 is a schematic diagram of the structure of another filter provided in an embodiment of the present disclosure, such as Figure 6 As shown, the filter in the embodiment of the present disclosure is a flexible 2D IPD filter, including a dielectric substrate 1, at least one capacitor and at least one inductor integrated on the dielectric substrate 1; the filter also includes a first buffer layer 6 arranged on the dielectric substrate 1, and the material of the first buffer layer 6 is an organic material; the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, and the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6; the first electrode plate 31 of the capacitor is filled in the first accommodating portion 61, and the coil structure 24 of the inductor is filled in the second accommodating portion 62, and the surface of the first electrode plate 31 of the capacitor away from the dielectric substrate 1 and the surface of the coil structure 24 of the inductor away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1; the first buffer layer 6 is used as the dielectric substrate 1.

[0092] Specifically, Figure 6 As shown, the first buffer layer 6 of the filter in the embodiment of the present disclosure is used as the dielectric substrate 1 to obtain a flexible 2D IPD filter.

[0093] In some embodiments, the organic material includes any one of polyimide, resin and photoresist. In the embodiments of the present disclosure, the organic material includes but is not limited to polyimide, resin and photoresist. Figure 2 and Figure 3 The first buffer layer 6 and the second buffer layer 7, and Figure 4 , Figure 5 and Figure 6The first buffer layer 6 in the structure can play the role of buffering heat and stress. For example, the organic material can be polyimide. The first buffer layer 6 and the second buffer layer 7 formed in this way can not only play the role of buffering heat and stress, but also alleviate the problems of delamination, shedding, and high RDL impedance caused by fatigue at the interface of the interconnection layer of the metal RDL line and the glass substrate, thereby improving the reliability of the IPD; in addition, the first buffer layer 6 and the second buffer layer 7 formed in this way can also be used as a cutoff layer for CMP planarization of the metal RDL line, which is conducive to improving the uniformity and stability of capacitance, thereby simplifying the process scheme of CMP planarization of the metal RDL line, reducing the process difficulty and large-scale production cost, and improving the device performance and quality.

[0094] In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, comprising: providing a dielectric substrate 1, forming at least one capacitor and at least one inductor on the dielectric substrate 1, and also comprising the step of forming a first buffer layer 6 on the dielectric substrate 1.

[0095] For ease of description and understanding, only the step of forming the first buffer layer 6 when preparing a glass-based 2D IPD filter is specifically described below.

[0096] Figure 7a to Figure 7c A preparation process flow chart of forming a first buffer layer 6 provided in an embodiment of the present disclosure is as follows: Figure 7a to Figure 7c As shown, the first buffer layer 6 prepared therefrom can be applied to Figure 4 In the glass-based 2D IPD filter shown in FIG. 1 , when forming the first buffer layer 6 , the preparation method thereof may include steps S11 to S13 , which are specifically as follows:

[0097] S11, cleaning and drying the dielectric substrate 1.

[0098] Specifically, Figure 7a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0099] Specifically, when cleaning the dielectric substrate 1 , it can be cleaned in sequence using deionized water (DI), a cleaning agent, isopropyl alcohol, etc. Each cleaning time is no less than 10 minutes.

[0100] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0101] S12 , forming a first film layer 03 on the dielectric substrate 1 .

[0102] Specifically, Figure 7bAs shown, when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0103] Specifically, an organic material may be coated on the dielectric substrate 1 to form the first film layer 03. The organic material includes but is not limited to polyimide, resin, and photoresist, as long as it can buffer heat and stress. For example, on the cleaned dielectric substrate 1, an organic material with a target thickness range of 2 to 20 um is coated by a spin coating process.

[0104] S13 , patterning the first film layer 03 to form a first buffer layer 6 .

[0105] Specifically, Figure 4 and Figure 7c As shown, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62 , the first accommodating portion 61 is configured to accommodate the first electrode plate 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor.

[0106] Specifically, the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor). The first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6. The first accommodating portion 61 and the second accommodating portion 62 are 1 to 15 um thick from the dielectric substrate 1 in a direction perpendicular to the dielectric substrate 1, i.e., 1 to 15 um of organic material is retained. Finally, the curing is performed to produce the required first buffer layer 6 having the first accommodating portion 61 and the second accommodating portion 62.

[0107] Further, such as Figure 7c As shown, the patterning process of the first film layer 03 can adopt Halftone photolithography technology to remove the organic material in the cutting line 01 and expose the dielectric substrate 1. Here, the organic material in the cutting line 01 is removed to separate adjacent devices and increase the warpage stress of the product.

[0108] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, when the product has a strong ability to resist the stress of the entire first buffer layer 6, it is not necessary to remove the organic material in the cutting street 01.

[0109] Figure 8a to Figure 8c Another process flow chart for forming the first buffer layer 6 provided in the embodiment of the present disclosure is as follows: Figure 8a to Figure 8c As shown, the first buffer layer 6 prepared therefrom can be applied to Figure 5In the glass-based 2D IPD filter shown in FIG. 1 , when forming the first buffer layer 6 , the preparation method thereof may include steps S21 to S23 , which are specifically as follows:

[0110] S21 , cleaning and drying the dielectric substrate 1 .

[0111] Specifically, Figure 8a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a grooved glass substrate. The dielectric substrate 1 has a first groove 81 and a second groove 82 that partially penetrate along the thickness direction thereof. The shape of the first groove 81 corresponds to the first electrode 31 of the capacitor, and the shape of the second groove 82 corresponds to the coil structure 24 of the inductor. The thickness of the glass substrate ranges from 0.1 to 0.4 mm, and the depth of the first groove 81 and the second groove 82 ranges from 3 to 30 um.

[0112] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0113] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0114] S22 , forming a first film layer 03 on the dielectric substrate 1 .

[0115] Specifically, Figure 8b As shown, when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0116] Specifically, an organic material may be coated on the dielectric substrate 1 to form the first film layer 03. The organic material includes but is not limited to polyimide, resin and photoresist, as long as it can buffer heat and stress. For example, an organic material with a target thickness of 1 to 25 um is coated on the cleaned dielectric substrate 1 by a spray coating process.

[0117] S23 , patterning the first film layer 03 to form a first buffer layer 6 .

[0118] Specifically, Figure 5 and Figure 8c As shown, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62, the first accommodating portion 61 is configured to accommodate the first electrode plate 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor. The first buffer layer 6 covers the dielectric substrate 1, and the first slot 81 defines the first accommodating portion 61, and the second slot 82 defines the second accommodating portion 62.

[0119] Specifically, the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). The first accommodating portion 61 and the second accommodating portion 62 are 1 to 20 um thick from the dielectric substrate 1 in a direction perpendicular to the dielectric substrate 1, i.e., 1 to 20 um of organic material is retained. Finally, the first buffer layer 6 having the first accommodating portion 61 and the second accommodating portion 62 is manufactured.

[0120] Further, such as Figure 8c As shown, the patterning process of the first film layer 03 can adopt Halftone photolithography technology to remove the organic material in the cutting line 01 and expose the dielectric substrate 1. Here, the organic material in the cutting line 01 is removed to separate adjacent devices and increase the warpage stress of the product.

[0121] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, when the product has a strong ability to resist the stress of the entire first buffer layer 6, it is not necessary to remove the organic material in the cutting street 01.

[0122] Figure 9a to Figure 9e Another process flow chart for forming the first buffer layer 6 provided in the embodiment of the present disclosure is as follows: Figure 9a to Figure 9e As shown, the first buffer layer 6 prepared therefrom can be applied to Figure 4 In the glass-based 2D IPD filter shown in FIG. 1 , when forming the first buffer layer 6 , the preparation method thereof may include steps S31 to S33 , which are specifically as follows:

[0123] S31, cleaning and drying the dielectric substrate 1.

[0124] Specifically, Figure 9a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0125] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0126] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0127] S32 , forming a first film layer 03 on the dielectric substrate 1 .

[0128] Specifically, Figure 9bAs shown, when the first film layer 03 is formed on the dielectric substrate 1 , the first film layer 03 covers the dielectric substrate 1 .

[0129] Specifically, an organic material may be coated on the dielectric substrate 1 to form the first film layer 03. The organic material includes but is not limited to polyimide, resin, and photoresist, as long as it can buffer heat and stress. For example, on the cleaned dielectric substrate 1, an organic material with a target thickness range of 2 to 20 um is coated by a spin coating process.

[0130] S33 , patterning the first film layer 03 to form a first buffer layer 6 .

[0131] Specifically, Figure 4 , Figure 9c-9e As shown, the first buffer layer 6 has a first accommodating portion 61 and a second accommodating portion 62 , the first accommodating portion 61 is configured to accommodate the first electrode plate 31 of the capacitor, and the second accommodating portion 62 is configured to accommodate the coil structure 24 of the inductor.

[0132] Further, such as Fig.9c As shown, the patterning process of the first film layer 03 can adopt Halftone photolithography technology to remove the organic material in the cutting path 01 and expose the dielectric substrate 1. Finally, the first film layer 03 with a thickness range of 1 to 15 um is produced by curing. Here, the organic material in the cutting path 01 is removed to space adjacent devices and increase the warpage stress of the product.

[0133] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, when the product has a strong ability to resist the stress of the entire first buffer layer 6, it is not necessary to remove the organic material in the cutting street 01.

[0134] Specifically, Figure 9d As shown, an etching mask layer 02 of the first film layer 03 is fabricated. A layer of photoresist with a thickness of 10-30 um is coated on the first film layer 03 by spin coating, and then photolithography is performed to expose the first film layer 03 corresponding to the metal RDL circuit that needs to be etched and thinned.

[0135] Specifically, Fig.9e As shown, the first film layer 03 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). A plasma stripper can be used to remove the first film layer 03 exposed after curing to a target groove depth range of 2 to 10 um, and then remove the photoresist (i.e., etching mask layer 02) to produce a first buffer layer 6 having a first accommodation portion 61 and a second accommodation portion 62.

[0136] The first accommodation portion 61 and the second accommodation portion 62 both penetrate a portion of the thickness of the first buffer layer 6 . The first accommodation portion 61 and the second accommodation portion 62 are 2 to 10 um away from the dielectric substrate 1 in a direction perpendicular to the dielectric substrate 1 .

[0137] Figure 10a to Figure 10d Another process flow chart for forming the first buffer layer 6 provided in the embodiment of the present disclosure is as follows: Figure 10a to Figure 10d As shown, the first buffer layer 6 prepared therefrom can be applied to Figure 4 In the glass-based 2D IPD filter shown in FIG. 1 , when forming the first buffer layer 6 , the preparation method thereof may include steps S41 to S43 , which are specifically as follows:

[0138] S41, cleaning and drying the dielectric substrate 1.

[0139] Specifically, Fig.10a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0140] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0141] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0142] S42 , forming a first film layer 03 on the dielectric substrate 1 ; the first film layer 03 comprises a first sub-film layer 031 and a second sub-film layer 032 which are sequentially formed in a direction away from the dielectric substrate 1 .

[0143] Specifically, Fig.10b As shown, when the first sub-film layer 031 is formed on the dielectric substrate 1 , the first sub-film layer 031 covers the dielectric substrate 1 .

[0144] Specifically, an organic material may be coated on the dielectric substrate 1 to form the first sub-film layer 031. The organic material includes but is not limited to polyimide, resin, and photoresist, as long as it can buffer heat and stress. For example, on the cleaned dielectric substrate 1, an organic material with a target thickness range of 2 to 10 um is coated by a spin coating process.

[0145] Further, such as Fig.10b As shown, the patterning process of the first sub-film layer 031 can adopt Halftone photolithography technology to remove the organic material in the cutting line 01 and expose the dielectric substrate 1. Here, the organic material in the cutting line 01 is removed to separate adjacent devices and increase the warpage stress of the product.

[0146] It should be noted that whether to remove the organic material in the cutting street 01 depends on the product's ability to resist the stress of the entire first buffer layer 6. For example, when the product has a strong ability to resist the stress of the entire first buffer layer 6, it is not necessary to remove the organic material in the cutting street 01.

[0147] S43 , patterning the first film layer 03 to form a first buffer layer 6 .

[0148] Specifically, Figure 4 , Fig.10c and Fig.10d As shown, a second sub-film layer 032 is formed on the side of the first sub-film layer 031 away from the dielectric substrate 1, and the second sub-film layer 032 is patterned to form a first buffer layer 6 corresponding to the metal RDL circuit (i.e., the first plate 31 of the capacitor and the coil structure 24 of the inductor). Photolithography (exposure and development) can be used to remove the organic material in the area corresponding to the metal RDL circuit and the cutting path 01, and then solidify and shape, and finally produce the required first buffer layer 6 with the first accommodating portion 61 and the second accommodating portion 62.

[0149] Specifically, the first accommodating portion 61 and the second accommodating portion 62 both penetrate part of the thickness of the first buffer layer 6 . The first accommodating portion 61 and the second accommodating portion 62 are 2 to 10 um thick from the dielectric substrate 1 in a direction perpendicular to the dielectric substrate 1 , that is, 2 to 10 um of organic material is retained.

[0150] In the embodiment of the present disclosure, the first buffer layer 6 is manufactured by a two-step coating process, that is, the thickness of the first sub-film layer 031 is actually the depth of the first accommodating portion 61 and the second accommodating portion 62 . Fig.11 is a cross-sectional view of the first buffer layer 6 in the embodiment of the present disclosure, as shown Fig.11 As shown, the first buffer layer 6 is sliced ​​to produce its cross-sectional view. From the cross-sectional view of the first buffer layer 6 obtained by scanning electron microscopy (SEM), it can be seen that there is an interface 04 between the buffer layers coated in two steps, that is, there is an interface 04 between the first sub-film layer 031 and the second sub-film layer 032.

[0151] It should be noted that the two-step coating method for the first buffer layer 6 can simplify the steps of forming the first receiving portion 61 and the second receiving portion 62, but the bonding strength is weaker than that of the one-step coating method. Whether one-step coating or two-step coating is used to prepare the first buffer layer 6 can be determined according to the actual needs of the product, and the present disclosure does not limit this.

[0152] It should be noted that when it is necessary to prepare the first buffer layer 6 of a glass-based 3D IPD filter, the steps are similar to the method for preparing the first buffer layer 6 of a glass-based 2D IPD filter mentioned above in the present invention. The main difference is that the second accommodating portion 62 runs through the entire thickness of the first buffer layer 6, which will not be repeated here in the present invention.

[0153] Figure 12a to Figure 12d A process flow chart of a filter manufacturing method provided by the present disclosure is shown in FIG. Figure 12a to Figure 12d As shown, in the preparation Figure 4 When the glass-based 2D IPD filter is shown, its preparation method may include steps S51 to S54, which are specifically as follows:

[0154] S51 , cleaning and drying the dielectric substrate 1 .

[0155] Specifically, Fig.12a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0156] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0157] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0158] S52 , forming a first buffer layer 6 .

[0159] Specifically, Figure 12b As shown, the step of forming the first buffer layer 6 on the dielectric substrate 1 may include any one of steps S11 to S13, steps S31 to S33, and steps S41 to S43, which is not limited in the present disclosure.

[0160] S53 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0161] Specifically, Fig.12c As shown, a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0162] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0163] S54 , grinding the first conductive film layer 05 flat by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor.

[0164] Specifically, Fig.12d As shown, the first conductive film layer 05 is polished by CMP to form the first plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0165] It should be noted that since the layer where the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor are located is very critical in the entire device, a high flatness requirement is imposed. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0166] Specifically, when the first conductive film layer 05 is polished by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the first buffer layer 6 away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surfaces of the first electrode plate 31 and the coil structure 24 away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0167] Figure 13a to Figure 13d A process flow chart of another filter manufacturing process provided by the embodiment of the present disclosure, such as Figure 13a to Figure 13d As shown, in the preparation Figure 5 When the glass-based 2D IPD filter is shown, its preparation method may include steps S61 to S64, which are specifically as follows:

[0168] S61 , cleaning and drying the dielectric substrate 1 .

[0169] Specifically, Fig.13a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a grooved glass substrate. The dielectric substrate 1 has a first groove 81 and a second groove 82 that partially penetrate along the thickness direction thereof. The shape of the first groove 81 corresponds to the first electrode 31 of the capacitor, and the shape of the second groove 82 corresponds to the coil structure 24 of the inductor. The thickness of the glass substrate ranges from 0.1 to 0.4 mm, and the depth of the first groove 81 and the second groove 82 ranges from 3 to 30 um.

[0170] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0171] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0172] S62 , forming a first buffer layer 6 .

[0173] Specifically, Fig.13b As shown, the step of forming the first buffer layer 6 on the dielectric substrate 1 may include steps S21 to S23, which will not be described in detail in the present disclosure.

[0174] S63 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0175] Specifically, Fig.13c As shown, a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0176] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0177] S64, grinding the first conductive film layer 05 flat by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor.

[0178] Specifically, Fig.13d As shown, the first conductive film layer 05 is polished by CMP to form the first plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0179] It should be noted that since the layer where the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor are located is very critical in the entire device, a high flatness requirement is imposed. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0180] Specifically, when the first conductive film layer 05 is polished by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the first buffer layer 6 away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surfaces of the first electrode plate 31 and the coil structure 24 away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0181] Figure 14a to Figure 14eA process flow chart of another filter manufacturing process provided by the embodiment of the present disclosure, such as Figure 14a to Figure 14e As shown, in the preparation Figure 6 When the flexible 2D IPD filter is shown, its preparation method may include steps S71 to S75, which are specifically as follows:

[0182] S71 , cleaning and drying the dielectric substrate 1 , and forming a temporary carrier layer 9 .

[0183] Specifically, Fig.14a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0184] Specifically, when cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, a cleaning agent, isopropyl alcohol, etc., wherein each cleaning time is not less than 10 minutes.

[0185] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0186] Specifically, a temporary carrier material is coated on the dielectric substrate 1 to form a temporary carrier layer 9. The thickness of the temporary carrier layer 9 is in the range of 5 to 20 um.

[0187] S72 , forming a first buffer layer 6 .

[0188] Specifically, Fig.14b As shown, the step of forming the first buffer layer 6 on the dielectric substrate 1 may include any one of steps S11 to S13, steps S31 to S33, and steps S41 to S43, which is not limited in the present disclosure.

[0189] S73 , forming a first conductive film layer 05 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0190] Specifically, Fig.14c As shown, a first conductive film layer 05 is formed on a side of the first buffer layer 6 facing away from the dielectric substrate 1 , and the first conductive film layer 05 covers the first buffer layer 6 .

[0191] Specifically, the first conductive film layer 05 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0192] S74 , grinding the first conductive film layer 05 flat by CMP to form the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor.

[0193] Specifically, Fig.14d As shown, the first conductive film layer 05 is polished by CMP to form the first plate 31 of the capacitor and the coil structure 24 of the inductor. The surfaces of the first plate 31 and the coil structure 24 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0194] It should be noted that since the layer where the first electrode plate 31 of the capacitor and the coil structure 24 of the inductor are located is very critical in the entire device, a high flatness requirement is imposed. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0195] Specifically, when the first conductive film layer 05 is polished by CMP, the metal Ti layer of the first conductive film layer 05 in contact with the first buffer layer 6 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the first buffer layer 6 away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surfaces of the first electrode plate 31 and the coil structure 24 away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0196] S75, removing the dielectric substrate 1.

[0197] Specifically, Fig.14e As shown, the dielectric substrate 1 is removed to obtain a flexible 2D IPD filter. After step S74, according to the device requirements, a single layer and a multi-layer structure of different material layers (metal material layer, organic material layer, inorganic material layer) are continuously stacked to complete the device manufacturing. Finally, the dielectric substrate 1 of the cut device is removed by destroying the temporary carrier layer 9 to obtain a flexible 2D IPD filter.

[0198] Figure 15a to Figure 15f A process flow chart of another filter manufacturing process provided by the embodiment of the present disclosure, such as Figure 15a to Figure 15f As shown, in the preparation Figure 2 When the glass-based 3D IPD filter is shown, its preparation method may include steps S81 to S86, which are specifically as follows:

[0199] S81 , cleaning and drying the dielectric substrate 1 , and forming a partial structure of the inductor and a second buffer layer 7 .

[0200] Specifically, Fig.15a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 includes a first surface S1 and a second surface S2 arranged opposite to each other along its thickness direction, and a first connecting via penetrating along its thickness direction. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0201] When cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, cleaning agent, isopropyl alcohol, etc. wherein each cleaning time is not less than 10 minutes.

[0202] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0203] Specifically, in the embodiment of the present disclosure, the laser induced etching method can be used to make the first connection via of the TGV, and the diameter of the first connection via can range from 50um to 80μm. The cross-sectional shape of the first connection via is different depending on the process technology used. For example, the cross-sectional shape of the first connection via can be cylindrical, hourglass-shaped, etc. Metallization filling is performed in the first connection via, and the metallization filling in the through hole is completed by sputtering and electroplating to form a first connection electrode 23 for connecting the upper and lower conductive structures of the inductor.

[0204] Specifically, a second buffer layer 7 is formed on the first surface S1 of the dielectric substrate 1. The material of the second buffer layer 7 is an organic material, and the second buffer layer 7 has a third accommodating portion 71, which runs through the entire thickness of the second buffer layer 7, and the third accommodating portion 71 is configured to accommodate the first conductive structure 21 of the inductor. The steps of forming the second buffer layer 7 on the first surface S1 of the dielectric substrate 1 can refer to steps S11 to S13, steps S31 to S33, and steps S41 to S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, when preparing the second buffer layer 7, the main difference from preparing a 2D IPD filter is that the third accommodating portion 71 runs through the entire thickness of the second buffer layer 7.

[0205] S82 , forming a second conductive film layer 06 on a side of the second buffer layer 7 facing away from the dielectric substrate 1 .

[0206] Specifically, Fig.15b As shown, a second conductive film layer 06 is formed on a side of the second buffer layer 7 facing away from the dielectric substrate 1 , and the second conductive film layer 06 covers the second buffer layer 7 .

[0207] Specifically, the second conductive film layer 06 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0208] S83 , grinding the second conductive film layer 06 flat by CMP to form a first conductive structure 21 of the inductor.

[0209] Specifically, Fig.15cAs shown, the second conductive film layer 06 is polished flat by CMP to form the first conductive structure 21 of the inductor. The surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1.

[0210] Specifically, when the second conductive film layer 06 is flattened by CMP, the metal Ti layer of the second conductive film layer 06 in contact with the second buffer layer 7 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the second buffer layer 7 away from the dielectric substrate 1, the metal Ti layer can be removed to make the surface of the first conductive structure 21 away from the dielectric substrate 1 flush with the surface of the second buffer layer 7 away from the dielectric substrate 1.

[0211] S84, forming a first buffer layer 6.

[0212] Specifically, Fig.15d As shown, the step of forming the first buffer layer 6 on the second surface S2 of the dielectric substrate 1 can refer to steps S11 to S13, steps S31 to S33, and steps S41 to S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, when preparing the first buffer layer 6, the main difference from preparing a 2D IPD filter is that the second accommodating portion 62 runs through the entire thickness of the first buffer layer 6, and the second accommodating portion 62 is configured to accommodate the second conductive structure 22 of the inductor. Regardless of whether it is a 3D IPD filter or a 2D IPD filter, when the dielectric substrate 1 does not have a slot, the first accommodating portion 61 runs through part of the thickness of the first buffer layer 6.

[0213] S85 , forming a third conductive film layer 07 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0214] Specifically, Fig.15e As shown, a third conductive film layer 07 is formed on a side of the first buffer layer 6 away from the dielectric substrate 1 , and the third conductive film layer 07 covers the first buffer layer 6 .

[0215] Specifically, the third conductive film layer 07 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0216] S86 , grinding the third conductive film layer 07 by CMP to form the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor.

[0217] Specifically, Fig.15fAs shown, the third conductive film layer 07 is polished by CMP to form the first plate 31 of the capacitor and the second conductive structure 22 of the inductor. The surfaces of the first plate 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0218] It should be noted that since the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor are located in a layer that is very critical in the entire device, a high flatness requirement is required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0219] Specifically, when the third conductive film layer 07 is polished by CMP, the metal Ti layer of the third conductive film layer 07 in contact with the first buffer layer 6 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the first buffer layer 6 away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surfaces of the first electrode plate 31 and the second conductive structure 22 away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0220] Figure 16a to Figure 16g A process flow chart of another filter manufacturing process provided by the embodiment of the present disclosure, such as Figure 16a to Figure 16g As shown, in the preparation Figure 3 When the glass-based 3D IPD filter is shown, its preparation method may include steps S91 to S97, which are specifically as follows:

[0221] S91, cleaning and drying the dielectric substrate 1, and forming a partial structure of the inductor.

[0222] Specifically, Fig.16a As shown, the dielectric substrate 1 is cleaned. The dielectric substrate 1 includes a first surface S1 and a second surface S2 arranged opposite to each other along its thickness direction, a first connecting via extending along its thickness direction, and a first slot 81 extending partially along its thickness direction. The dielectric substrate 1 is a glass substrate, and the thickness of the glass substrate ranges from 0.1 to 0.4 mm.

[0223] When cleaning the dielectric substrate 1, it can be cleaned in sequence by using DI, cleaning agent, isopropyl alcohol, etc. wherein each cleaning time is not less than 10 minutes.

[0224] After cleaning the dielectric substrate 1 , the dielectric substrate 1 is dried to ensure that no water marks remain on the surface of the dielectric substrate 1 .

[0225] Specifically, in the embodiment of the present disclosure, the laser induced etching method can be used to make the first connection via of the TGV, and the diameter of the first connection via can range from 50um to 80μm. The cross-sectional shape of the first connection via is different depending on the process technology used. For example, the cross-sectional shape of the first connection via can be cylindrical, hourglass-shaped, etc. Metallization filling is performed in the first connection via, and the metallization filling in the through hole is completed by sputtering and electroplating to form a first connection electrode 23 for connecting the upper and lower conductive structures of the inductor.

[0226] S92 , forming a second buffer layer 7 .

[0227] Specifically, Fig.16b As shown, a second buffer layer 7 is formed on the first surface S1 of the dielectric substrate 1. The material of the second buffer layer 7 is an organic material, and the second buffer layer 7 has a third accommodating portion 71, which runs through the entire thickness of the second buffer layer 7, and the third accommodating portion 71 is configured to accommodate the first conductive structure 21 of the inductor. The steps of forming the second buffer layer 7 on the first surface S1 of the dielectric substrate 1 can refer to steps S11 to S13, steps S31 to S33, and steps S41 to S43. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, when preparing the second buffer layer 7, the main difference from preparing a 2DIPD filter is that the third accommodating portion 71 runs through the entire thickness of the second buffer layer 7.

[0228] S93 , forming a second conductive film layer 06 on a side of the second buffer layer 7 facing away from the dielectric substrate 1 .

[0229] Specifically, Fig.16c As shown, a second conductive film layer 06 is formed on a side of the second buffer layer 7 facing away from the dielectric substrate 1 , and the second conductive film layer 06 covers the second buffer layer 7 .

[0230] Specifically, the second conductive film layer 06 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0231] S94 , grinding the second conductive film layer 06 flat by CMP to form a first conductive structure 21 of the inductor.

[0232] Specifically, Fig.16c As shown, the second conductive film layer 06 is polished flat by CMP to form the first conductive structure 21 of the inductor. The surface of the first conductive structure 21 facing away from the dielectric substrate 1 is flush with the surface of the second buffer layer 7 facing away from the dielectric substrate 1.

[0233] Specifically, when the second conductive film layer 06 is flattened by CMP, the metal Ti layer of the second conductive film layer 06 in contact with the second buffer layer 7 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the second buffer layer 7 away from the dielectric substrate 1, the metal Ti layer can be removed to make the surface of the first conductive structure 21 away from the dielectric substrate 1 flush with the surface of the second buffer layer 7 away from the dielectric substrate 1.

[0234] S95 , forming a first buffer layer 6 .

[0235] Specifically, Fig.16e As shown, the step of forming the first buffer layer 6 on the second surface S2 of the dielectric substrate 1 can refer to steps S21 to S23. Since the filter in the embodiment of the present disclosure is a 3D IPD filter, when preparing the first buffer layer 6, the main difference from preparing a 2D IPD filter is that the second accommodating portion 62 runs through the entire thickness of the first buffer layer 6, and the second accommodating portion 62 is configured to accommodate the second conductive structure 22 of the inductor. In addition, in the embodiment of the present disclosure, the dielectric substrate 1 has a slot, and the first slot 81 defines the first accommodating portion 61.

[0236] S96 , forming a third conductive film layer 07 on a side of the first buffer layer 6 facing away from the dielectric substrate 1 .

[0237] Specifically, Fig.16f As shown, a third conductive film layer 07 is formed on a side of the first buffer layer 6 away from the dielectric substrate 1 , and the third conductive film layer 07 covers the first buffer layer 6 .

[0238] Specifically, the third conductive film layer 07 is actually a titanium (Ti) / copper (Cu) metal seed layer and a thick copper layer formed on the side of the seed layer away from the dielectric substrate 1. The thickness of Ti is in the range of 20 to 200 nm, the thickness of Cu is in the range of 100 to 1000 nm, and the thick copper layer can be formed by electroplating copper to produce a copper layer with a thickness range of 2 to 10 um.

[0239] S97 , grinding the third conductive film layer 07 flat by CMP to form the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor.

[0240] Specifically, Figure 16g As shown, the third conductive film layer 07 is polished by CMP to form the first plate 31 of the capacitor and the second conductive structure 22 of the inductor. The surfaces of the first plate 31 and the second conductive structure 22 facing away from the dielectric substrate 1 are flush with the surface of the first buffer layer 6 facing away from the dielectric substrate 1.

[0241] It should be noted that since the first electrode plate 31 of the capacitor and the second conductive structure 22 of the inductor are located in a layer that is very critical in the entire device, a high flatness requirement is required. After the electroplating is completed, the excess electroplated copper is removed by CMP or grinding.

[0242] Specifically, when the third conductive film layer 07 is polished by CMP, the metal Ti layer of the third conductive film layer 07 in contact with the first buffer layer 6 can be used as a cutoff layer for the metal Cu layer. In this way, after removing the metal Cu layer on the side of the first buffer layer 6 away from the dielectric substrate 1, the metal Ti layer can be removed, so that the surfaces of the first electrode plate 31 and the second conductive structure 22 away from the dielectric substrate 1 are both flush with the surface of the first buffer layer 6 away from the dielectric substrate 1.

[0243] In a third aspect, an embodiment of the present disclosure further provides an electronic device, which includes the filter of any one of the above embodiments.

[0244] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A filter comprising a dielectric substrate, at least one capacitor and at least one inductor integrated on the dielectric substrate; characterized in that: The filter further comprises a first buffer layer disposed on the dielectric substrate; the material of the first buffer layer is an organic material; The first buffer layer has a first accommodating portion and a second accommodating portion; the first electrode plate of the capacitor is filled in the first accommodating portion, and at least a part of the structure of the inductor is filled in the second accommodating portion, and the first electrode plate of the capacitor is away from the surface of the dielectric substrate, and the structure of the inductor filled in the second accommodating portion is away from the surface of the dielectric substrate, and both are flush with the surface of the first buffer layer away from the dielectric substrate.

2. The filter according to claim 1, characterized in that The dielectric substrate comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof, and a first connecting via which penetrates along the thickness direction thereof; the first buffer layer is arranged on the first surface; The inductor comprises a first conductive structure arranged on the first surface, a second conductive structure arranged on the second surface, and a first connecting electrode arranged in the first connecting via; the second conductive structure is electrically connected to the first conductive structure through the first connecting electrode to form a coil structure of the inductor; The second accommodation portion penetrates the entire thickness of the first buffer layer, and the second conductive structure is filled in the second accommodation portion.

3. The filter according to claim 2, characterized in that It also includes a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material; The second buffer layer has a third accommodating portion, the third accommodating portion runs through the entire thickness of the second buffer layer, the first conductive structure is filled in the third accommodating portion, and a surface of the first conductive structure away from the dielectric substrate is flush with a surface of the second buffer layer away from the dielectric substrate.

4. The filter according to claim 3, characterized in that The first receiving portion penetrates a portion of the thickness of the first buffer layer.

5. The filter according to claim 3, characterized in that The dielectric substrate has a first slot partially penetrating along the thickness direction thereof, and the first slot defines the first accommodation portion.

6. The filter according to claim 1, characterized in that The first accommodating portion and the second accommodating portion both penetrate a portion of the thickness of the first buffer layer; and the coil structure of the inductor is filled in the second accommodating portion.

7. The filter according to claim 1, characterized in that The dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof; The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

8. The filter according to claim 6, characterized in that The first buffer layer serves as the dielectric substrate.

9. The filter according to any one of claims 1 to 8, characterized in that: The organic material includes any one of polyimide, resin and photoresist.

10. A method for preparing a filter, characterized in that: include: Providing a dielectric substrate, forming at least one capacitor and at least one inductor on the dielectric substrate, and further comprising the step of forming a first buffer layer on the dielectric substrate; The step of forming the first buffer layer comprises: Cleaning and drying the dielectric substrate; forming a first film layer on the dielectric substrate; the first film layer covers the dielectric substrate; The first film layer is patterned to form the first buffer layer; the first buffer layer has a first accommodating portion and a second accommodating portion, the first accommodating portion is configured to accommodate a first plate of a capacitor, and the second accommodating portion is configured to accommodate at least a partial structure of an inductor.

11. The method for preparing a filter according to claim 10, characterized in that: The first accommodation portion and the second accommodation portion both penetrate a portion of the thickness of the first buffer layer, and the second accommodation portion is configured to accommodate a coil structure of an inductor.

12. The method for preparing a filter according to claim 10, characterized in that: The dielectric substrate has a first slot and a second slot partially penetrating along the thickness direction thereof; The first buffer layer covers the dielectric substrate, and the first groove defines the first accommodating portion, and the second groove defines the second accommodating portion.

13. The method for preparing a filter according to claim 10, characterized in that: The first film layer includes a first sub-film layer and a second sub-film layer which are sequentially formed in a direction away from the dielectric substrate.

14. The method for preparing a filter according to claim 11 or 12, characterized in that: The step of forming at least one capacitor and at least one inductor on the dielectric substrate comprises: forming a first conductive film layer on a side of the first buffer layer away from the dielectric substrate; the first conductive film layer covers the first buffer layer; The first conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a coil structure of the inductor; surfaces of the first electrode plate and the coil structure facing away from the dielectric substrate are flush with a surface of the first buffer layer facing away from the dielectric substrate.

15. The method for preparing a filter according to claim 10, characterized in that: The dielectric substrate comprises a first surface and a second surface which are arranged opposite to each other along the thickness direction thereof, and a first connecting via which penetrates along the thickness direction thereof; the first buffer layer is arranged on the first surface; The filter further comprises a second buffer layer disposed on the second surface; the material of the second buffer layer is an organic material; A third accommodating portion is provided on the second buffer layer; the third accommodating portion penetrates the entire thickness of the second buffer layer, the third accommodating portion is configured to accommodate a first conductive structure of an inductor, and a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate; The second receiving portion penetrates the entire thickness of the first buffer layer, and the second receiving portion is configured to receive a second conductive structure of an inductor.

16. The method for preparing a filter according to claim 15, characterized in that: The first receiving portion penetrates a portion of the thickness of the first buffer layer.

17. The method for preparing a filter according to claim 15, characterized in that: The dielectric substrate has a first slot partially penetrating along the thickness direction thereof, and the first slot defines the first accommodation portion.

18. The method for preparing a filter according to claim 16 or 17, characterized in that: The step of forming at least one capacitor and at least one inductor on the dielectric substrate comprises: forming a first connection electrode of the inductor in the first connection via hole; forming a second conductive film layer on a side of the second buffer layer away from the dielectric substrate; The second conductive film layer is polished flat by CMP to form a first conductive structure of the inductor; a surface of the first conductive structure facing away from the dielectric substrate is flush with a surface of the second buffer layer facing away from the dielectric substrate; forming a third conductive film layer on a side of the first buffer layer away from the dielectric substrate; The third conductive film layer is polished by CMP to form a first electrode plate of the capacitor and a second conductive structure of the inductor; surfaces of the first electrode plate and the second conductive structure facing away from the dielectric substrate are both flush with a surface of the first buffer layer facing away from the dielectric substrate.

19. An electronic device, characterized in that: The filter comprises the filter according to any one of claims 1 to 9.

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