Gate drive circuit and method for optimal switching of semiconductor device

Abstract

A gate driving circuit and a method for optimal switching of a semiconductor device are provided. An adaptive gate drive circuit for an insulated gate bipolar transistor (IGBT)-based semiconductor switch provides a gate resistance device for reducing time delay and switching loss associated with an increase in switch junction temperature. A gate resistance device is disposed proximate to the switching junction and includes a negative temperature coefficient (NTC) thermistor and a linear gate resistor connected in parallel. Where the thermistor senses an increase in the junction temperature of the semiconductor switch, the gate resistance via the linear gate resistor is reduced to return the junction temperature to thermal equilibrium with a minimum delay, thereby enabling the semiconductor switch to switch faster and reduce associated switching losses.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit under 35 U.S.C. §119(e) of Indian Provisional Patent Application Serial No. 202311043329, filed on June 28, 2023. The Indian Provisional Patent Application is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to the field of integrated circuits, and in particular to adaptive gate drive circuits for semiconductor switching devices. Background Art

[0004] A power inverter for a semiconductor device can convert direct current (DC) into, for example, three-phase alternating current (AC), and provide alternating current as a gate drive voltage, switching quickly between an on (e.g., positive voltage) and off (e.g., non-positive voltage or zero / negative voltage) state controlled by a semiconductor switch (e.g., a metal oxide semiconductor field effect transistor MOSFET or an insulated gate bipolar transistor IGBT). The gate resistor determines how fast the semiconductor switches between the on and off states. Generally, the faster the switching, the lower the power loss associated with the switching. However, the faster the semiconductor switch switches, the greater the radiation emitted by the semiconductor switch. The International Special Committee on Radio Interference (CISPR) or equivalent standards provide maximum allowable radiation levels. Therefore, the gate resistor can be selected to adjust the power loss and enforce radiated emission limits. However, as more current flows through the semiconductor switch, the junction temperature will increase. If the gate resistance increases, the conduction switching loss will increase linearly. However, if the gate resistance remains constant, both the switching delay and the switching loss will increase as the junction temperature increases. Summary of the invention

[0005] In a first aspect, an adaptive gate drive circuit for supplying power to a semiconductor device is disclosed. In an embodiment, the adaptive gate drive circuit includes a semiconductor switch for supplying a gate drive voltage to the semiconductor device (e.g., based on a control signal from a control switch), the semiconductor switch having a radiated emission limit and a junction temperature, both of which must be maintained at an acceptable level. The gate drive voltage can be positive (corresponding to the "on" state of the semiconductor switch, associated with the on-switching time delay and the on-switching loss) or non-positive, i.e., zero or negative (corresponding to the "off" state of the semiconductor switch, associated with the off-switching time delay and the off-switching loss). The gate resistance device is connected in series between the semiconductor switch and the control switch and is thermally coupled to the semiconductor switch. The gate resistance device includes a negative temperature coefficient (NTC) resistor (e.g., a thermistor) and a linear gate resistor connected in parallel. The NTC thermistor senses the junction temperature of the semiconductor switch and, if the junction temperature reaches or exceeds a threshold level, reduces the turn-on (or turn-off) switching time or switching losses by reducing the gate resistance of the linear gate resistor, thereby keeping the junction temperature and / or radiated emission limits within acceptable levels.

[0006] In some implementations, the NTC thermistor reduces the gate resistance of the linear gate resistor until the junction temperature drops below a threshold level.

[0007] In some implementations, the NTC thermistor reduces the gate resistance of the linear gate resistor based on an inverse linear relationship to an increase in the sensed junction temperature.

[0008] In some implementations, the NTC thermistor increases the gate resistance of the linear gate resistor based on a decrease in the current load associated with the gate drive voltage.

[0009] In some implementations, an NTC thermistor increases the gate resistance of a linear gate resistor based on a reduced sensed junction temperature.

[0010] In some implementations, the linear gate resistor is associated with a minimum gate resistance based on a radiated emission limit of the semiconductor switch and a maximum gate resistance based on a power capability of the semiconductor switch.

[0011] In some embodiments, the semiconductor switch is an insulated gate bipolar transistor IGBT or a group thereof.

[0012] In some embodiments, the semiconductor device is a system on chip (SoC), and one or both of the semiconductor switch and the gate resistance device are surface mount devices (SMD).

[0013] In some implementations, reducing a conduction switching time (eg, in an on state) of a semiconductor switch includes reducing one or more of a conduction switching delay, a rise time, or a charging time.

[0014] In some implementations, reducing an off switching time of a semiconductor switch (eg, in an off state) includes reducing one or more of an off switching delay, a fall time, or a discharge time.

[0015] On the other hand, a method for optimal switching of a semiconductor device is disclosed. In an embodiment, the method includes connecting a gate resistance device in series between a control switch of the semiconductor device and a semiconductor switch (and thermally coupling the gate resistance device to the semiconductor switch), and the semiconductor switch provides a gate drive voltage to the semiconductor device in response to a control signal from the control switch. The semiconductor switch has a radiated emission limit and a junction temperature, both of which are to be maintained within an acceptable level (e.g., below a threshold level). The gate drive voltage corresponds to an on state (e.g., a positive voltage) or an off state (e.g., a non-positive voltage), the on state is associated with a turn-on switching time and switching losses, and the off state is associated with a turn-off switching time and switching losses. The gate resistance device includes a negative temperature coefficient (NTC) resistor (e.g., a thermistor) and a linear gate resistor connected in parallel. The method includes sensing the junction temperature of the semiconductor switch via an NTC thermistor. The method includes reducing the gate resistance of the linear gate resistor via the NTC thermistor (e.g., to reduce the junction temperature) when the sensed junction temperature reaches or exceeds a threshold level.

[0016] In some implementations, the method includes reducing a gate resistance of the linear gate resistor based on an inverse linear relationship with increasing junction temperature.

[0017] In some embodiments, the method includes reducing the gate resistance of the linear gate resistor until the junction temperature decreases below a threshold level.

[0018] In some implementations, the method includes increasing a gate resistance based on a decrease in a current load associated with a gate drive voltage.

[0019] In some embodiments, the method includes increasing the gate resistance based on the reduced junction temperature.

[0020] In some implementations, the linear gate resistor is associated with a minimum gate resistance based on a radiated emission limit of the semiconductor switch and a maximum gate resistance based on a power capability of the semiconductor switch.

[0021] In some embodiments, the semiconductor switch is an insulated gate bipolar transistor IGBT or a group thereof.

[0022] In some embodiments, the semiconductor device is a system on chip (SoC), and one or both of the semiconductor switch and the gate resistance device are surface mount devices (SMD).

[0023] In some implementations, reducing a conduction switching time (eg, in an on state) of a semiconductor switch includes reducing one or more of a conduction switching delay, a rise time, or a charging time.

[0024] In some implementations, reducing an off switching time of a semiconductor switch (eg, in an off state) includes reducing one or more of an off switching delay, a fall time, or a discharge time.

[0025] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative only and are not necessarily restrictive of the present disclosure. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate the subject matter of the present disclosure. Figure 1 It is used to illustrate the principle of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The detailed description is described with reference to the accompanying drawings. The use of the same reference numerals at different instances in the description and drawings may indicate similar or identical items. Various embodiments or examples ("examples") of the present disclosure are disclosed in the following detailed description and drawings. The drawings are not necessarily drawn to scale. In general, unless otherwise provided in the claims, the operations of the disclosed processes may be performed in any order. In the drawings:

[0027] Figure 1 is a block diagram of a conventional gate drive circuit for a semiconductor device;

[0028] Figure 2A and Figure 2B With the passage Figure 1 A graphical representation of the increased switching losses with increased current and gate resistance for a conventional gate drive circuit;

[0029] Figure 3 It follows Figure 1 A tabular representation of the increased switching loss and switching time as the junction temperature across the semiconductor switch of a conventional gate drive circuit increases;

[0030] Figure 4 is a block diagram illustrating a gate drive circuit incorporating a negative temperature coefficient (NTC) gate resistor device according to an example embodiment of the present disclosure;

[0031] Figure 5A yes Figure 4 A graphical illustration of the gate resistance of various components of an NTC gate resistance device as a function of temperature;

[0032] Figure 5B yes Figure 4 A graphical illustration of the total gate resistance of an NTC gate resistance device as a function of temperature;

[0033] Figure 6 The following are the graphic descriptions: Figure 1 The turn-on and turn-off switching times of conventional gate drive circuits at nominal junction temperature; Figure 1 The turn-on and turn-off switching times of a conventional gate drive circuit at an elevated junction temperature; and Figure 4 The turn-on and turn-off switching times of the gate drive circuit at elevated junction temperatures;

[0034] and FIG. 7A to FIG. 7C is a process flow diagram illustrating a method for optimal switching of a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Before describing one or more embodiments of the present disclosure in detail, it should be understood that the embodiments are not limited to the details of the construction and arrangement of the parts or steps or methods described in the following description or shown in the accompanying drawings in their application. In the detailed description of the following embodiments, many specific details may be described in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art who benefit from the present disclosure that the embodiments disclosed herein may be practiced without some of these specific details. In other cases, well-known features may not be described in detail to avoid unnecessarily complicating the present disclosure.

[0036] As used herein, a letter following a reference number is intended to reference an embodiment of a feature or element that may be similar, but not necessarily identical, to a previously described element or feature having the same reference number (e.g., 1, 1a, 1b). Such shorthand notation is used only for convenience and should not be construed as limiting the present disclosure in any way unless expressly stated to the contrary.

[0037] In addition, unless expressly stated to the contrary, "or" refers to an inclusive or rather than an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0038] In addition, "a" or "an" may be used to describe elements and components of the embodiments disclosed herein. This is done only for convenience and "a" and "an" are intended to include "one" or "at least one", and the singular also includes the plural, unless it is obvious that it is otherwise indicated.

[0039] Finally, as used herein, any reference to "one embodiment" or "some embodiments" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment disclosed herein. The appearance of the phrase "in some embodiments" in various places in the specification is not necessarily all referring to the same embodiment, and an embodiment may include one or more features explicitly described or inherently present herein, or any combination or sub-combination of two or more such features, as well as any other features not necessarily explicitly described or inherently present in the present disclosure.

[0040] Broadly speaking, embodiments of the inventive concepts disclosed herein relate to systems and methods for operating semiconductor devices at optimal efficiency via an adaptive gate drive circuit including a negative temperature coefficient (NTC) gate resistor (“thermistor”). For example, in a conventional gate drive circuit, an NTC gate resistor or thermistor (e.g., whose resistance may decrease as temperature increases) may infer the junction temperature of a semiconductor switch (e.g., a metal oxide semiconductor field effect transistor MOSFET, an insulated gate bipolar transistor IGBT, other similar transistor or switch device) based on a sensed temperature of a heat sink or substrate (which itself may be based on heat transferred from the semiconductor switch and may therefore be associated with a finite delay). A circuit controller may then reduce voltage, current, and / or switching frequency in response to the rising junction temperature. However, an adaptive gate drive circuit according to an example embodiment of the inventive concepts disclosed herein may place the NTC gate resistor closer to the actual junction of the semiconductor switch, thereby eliminating the need to periodically monitor the heat sink temperature and associated delays. The semiconductor switch is able to perform faster on / off switching while reducing switching losses and maintaining radiated emission limits at higher junction temperatures. The thermal time constant of the system can be increased and the intelligence transferred from the microprocessor-based controller to the gate drive circuit.

[0041] Now refer to Figure 1 , shows a conventional gate drive circuit 100 for a semiconductor device. An on / off control signal 102 (eg, respectively, and a positive or non-positive (eg, zero or negative) gate drive voltage 104 (eg, V CE =600V, V CE=±15V) is associated) and amplified by a totem pole circuit of transistors Q1, Q2 and resistor R1. Transistors (e.g., semiconductor switches) Q3, Q4 form one arm of a three-phase half-bridge inverter and control on / off switching based on a control signal. In an embodiment, transistors Q3 and Q4 are insulated gate bipolar transistors IGBT. Resistors R3, R5 and capacitors C3, C4 form a circuit for providing current when Q4 is in an on / on state; in addition, when Q4 is in an off / off state, resistor R2 is connected in parallel with R3 (e.g., together with C4, R5). In the on state, Q4 can be switched slower or faster by changing the resistance of R3, R5 and the capacitance of C4.

[0042] In an embodiment, the on and off switching times (eg, for the on and off states, respectively) each have three main components. For example, the on switching time may include a rise time t r , switching delay t d(on) and charging time (e.g., for charging gate capacitors C3, C4). Similarly, the turn-off switching time may include the fall time t f , switching delay t d(off) and discharge time (e.g., for discharging the gate capacitance from C4). Ideally, Q4 should be turned on / off as quickly as possible to reduce the power losses associated with switching. With respect to Q4, the power losses include switching losses and conduction losses:

[0043]

[0044] However, as Q4 switches faster, the emissions radiated by the semiconductor switch increase. As mentioned above, CISPR or equivalent standards provide an upper limit on acceptable radiated emission levels. Therefore, the selection of gate resistor R5 can be an engineering compromise to adjust power losses and maintain radiated emission limits.

[0045] Reference Figure 2A and Figure 2B , shows a typical half-bridge semiconductor switch (e.g. Figure 1 For example, Figure 2A As shown, the gate resistor R5 is the gate resistor R G When the conduction switching loss E remains constant, on and turn-off switching loss E off (measured in millijoules) is usually the current flowing through a semiconductor switch (e.g., the collector current I C , emitter current I E ), as the junction temperature T j It increases evenly from 125°C to 150°C.

[0046] like Figure 2B As shown, with the gate resistor R G (e.g., internal or external) increases, the conduction switching loss E on Increase linearly.

[0047] Still refer to Figure 3 , shows a typical half-bridge semiconductor switch (Q3, Q4; Figure 1 ) switching time components. For example, due to the collector current load I C , Gate drive voltage V CE 、V GE and gate resistor R G(on) , R G(off) Keep constant and the junction temperature T j From the nominal 25℃ to 125℃ and 150℃, the switching delay t d(on) and t d(off) As the temperature increases, the rise time t r and the fall time t f Also increases. Similarly, as mentioned above Figure 2B As mentioned above, the switching loss E on 、E off Also with increasing temperature.

[0048] As above Figure 2B As shown, the conduction switching loss E on With gate resistor R G(on) This may cause the junction temperature T j rise, which in turn may increase the switching time delay, thereby slowing down the operation of the semiconductor device. In addition, the junction temperature T j may rise high enough to cause a malfunction in the gate drive circuit 100 .

[0049] Now refer to Figure 4 , an adaptive gate drive circuit 400 is shown. The adaptive gate drive circuit 400 can be controlled by semiconductor switches 404, 406 (eg, IGBTs Q3 and Q4, respectively) to supply power to connected semiconductor devices (not shown) via a DC bus 402.

[0050] Broadly speaking, the adaptive gate drive circuit 400 enables the connected semiconductor switch Q4 (406) to operate more efficiently and switch faster, while regulating switching losses and keeping both junction temperature and radiated emissions at acceptable levels. In embodiments, the characteristics attributed to the Q4 IGBT 406 may be similarly applied to the Q3 IGBT 404, which may have its own dedicated adaptive gate drive circuit 400a, which may be implemented and function similarly to the adaptive gate drive circuit 400 dedicated to the Q4 IGBT. For example, all references below to the adaptive gate drive circuit 400, its components, and the semiconductor switch 406 (e.g., IGBT Q4) may be similarly applied to the adaptive gate drive circuit 400a and the semiconductor switch 404 (e.g., IGBT Q3).

[0051] In an embodiment, the adaptive gate drive circuit 400 may include a gate resistance device 408 disposed near the semiconductor switch 406. For example, the gate resistance device 408 may include a negative temperature coefficient NTC thermistor 410 configured to monitor the junction temperature of the semiconductor switch 406, which is connected in parallel with a linear gate resistor 412. In some embodiments, the gate resistance device 408 may be disposed near a semiconductor device (not shown) to monitor its chip temperature. In some embodiments, the semiconductor device and / or the adaptive gate drive circuit 400 is a system-on-chip SoC device or a surface mount device SMD. For example, placing the gate resistance device 408 near the semiconductor switch 406 and / or the semiconductor device enables appropriate temperature coupling of the NTC thermistor 410, and enables the gate resistance device to adjust the gate resistance in response to changes in the junction temperature (e.g., chip temperature) with minimal delay.

[0052] In an embodiment, the NTC thermistor 410 and the gate resistor 412 are configured to adjust the resistance based on the junction temperature sensed by the NTC thermistor. For example, as the current flowing through the semiconductor switch 406 increases (eg, the collector current I C , emitter current I E ), switching losses increase and thus junction temperature increases, the gate resistance device 408 can reduce the gate resistance. The reduced gate resistance enables the semiconductor switch 406 to switch faster (eg, reduced switching delay).

[0053] In an embodiment, if the current load through the semiconductor switch 406 is reduced, the conduction losses can also be reduced and the junction temperature can drop. Therefore, the gate resistance device 408 can respond to the lower junction temperature by increasing the gate resistance to operate the semiconductor switch 406 at normal switching loss levels. Broadly speaking, optimizing the semiconductor switch 406 and its cooling system enables the thermal time constant of the semiconductor switch and the cooling system to be significantly increased.

[0054] In an embodiment, the gate resistance R of the gate resistance device 408 is G(on) , R G(off) The resistance level may be adjusted between a minimum resistance level and a maximum resistance level. For example, the minimum resistance may be determined by the maximum acceptable radiated emission levels when turned on and off. Similarly, the maximum resistance level may be determined based on the thermal or power capacity of the semiconductor switch 406 (e.g., and any available cooling system or heat sink).

[0055] In the implementation mode, still refer to Figure 5A and Figure 5B , diagrams 500 and 502 show various components of the gate resistance device 408 of the adaptive gate drive circuit 400 and 400a ( Figure 4 ; For example, the resistance (R; kΩ(500), Ω(504)) of the NTC thermistor 410, gate resistor 412) as a function of the junction temperature (°C), rather than the resistance of the overall composite gate resistor device (e.g., where the NTC thermistor and gate resistor are connected in parallel).

[0056] In an embodiment, the gate resistance device 408 may include a gate resistor 412 connected in parallel with the NTC thermistor 410 to ensure that the gate resistance device is configured to reduce the total gate resistance in inverse linear proportion to the increase in junction temperature. For example, the resistance curve 504 of the NTC thermistor 410 as a function of junction temperature may generally be inverse, but non-linear in nature. However, by connecting the NTC thermistor 410 in parallel with the gate resistor 412 having a linear resistance curve 506, the resistance curve 508 of the composite gate resistance device 408 may closely approximate an inverse linear relationship with junction temperature (e.g., Figure 5B best shown).

[0057] Now refer to Figure 6 , a diagram 600 shows a conventional semiconductor switch IGBT (Q4, Figure 1 ) of the typical on-switching time 602 and off-switching time 604. In an embodiment, the collector voltage V CThe on switching time 602 and the off switching time 604 are shown as a function of time (eg, in nanoseconds (ns)) at a nominal 25°C junction temperature. As described above, the on switching time 602 includes a rise time t r , switching delay t d(on) and charging time (eg, for charging the internal / external gate capacitor). Similarly, the turn-off switching time 604 includes the fall time t f , switching delay t d(off) and discharge time.

[0058] Graph 600a shows typical on-switching times 606 and off-switching times 608 of a conventional semiconductor switch Q4 at an elevated junction temperature of 125° C. As described above, longer on-switching times 606 and off-switching times 608 (due to, for example, one or more of longer rise / fall times, longer switching delays, longer charge / discharge times) increase switching losses, which in turn increases junction temperature and chip temperature, which in turn can cause a thermal runaway condition.

[0059] Graph 600b shows semiconductor switches Q3, Q4 (404, 406; Figure 4 ) and adaptive gate drive circuit (400, 400a; Figure 4 ) OFF switching time 610 and ON switching time 612 at an elevated junction temperature of 125° C. In an embodiment, incorporating the gate resistor device 408 through the adaptive gate drive circuit 400, 400a can reduce switching delays and charge / discharge times, thereby reducing overall switching losses even at elevated junction temperatures while keeping radiated emissions from the semiconductor switches 404, 406 within acceptable limits.

[0060] Now refer to Fig. 7A The operating method 700 may be implemented by the adaptive gate drive circuit 400 , 400 a and may include the following steps.

[0061] At step 702, a gate resistance device is connected in series between each semiconductor switch (e.g., an insulated gate bipolar transistor IGBT) of the semiconductor device and a control switch of the semiconductor device. For example, each gate resistance device includes a negative temperature coefficient NTC thermistor (placed near the IGBT junction) and a linear gate resistor connected in parallel. In an embodiment, the semiconductor switch supplies a gate drive voltage to the semiconductor device (e.g., in response to a control signal received from the control switch). In addition, the semiconductor switch is associated with a radiated emission limit (corresponding to a minimum gate resistance of the linear gate resistor), a junction temperature, and / or a power capacity (corresponding to a maximum gate resistance of the linear gate resistor). In addition, the gate drive voltage corresponds to one of an on state (e.g., associated with an on switching time and an on switching loss) or an off state (e.g., associated with an off switching time and an off switching loss). For example, the on switching time may include a turn-on delay, a rise time, and / or a charging time associated with the on state. Similarly, the off switching time includes a turn-off delay, a fall time, and / or a discharge time associated with the off state. In some embodiments, the semiconductor device is a system on chip (SoC) and one or more of the semiconductor switch or gate resistance devices are surface mount devices.

[0062] At step 704 , the NTC thermistor senses a junction temperature associated with a switching operation (eg, on / off switching) of a semiconductor switch.

[0063] At step 706, the NTC reduces the gate resistance of the linear resistor in the event that the junction temperature reaches or exceeds the threshold temperature. In some embodiments, the NTC reduces the gate resistance until the junction temperature drops back below the threshold level, thereby enabling fast on / off switching of the semiconductor switch with minimal delay and / or minimal conduction losses. In some embodiments, the NTC thermistor reduces the gate resistance of the linear gate resistor based on an inverse linear relationship to an increase in the sensed junction temperature.

[0064] Also refer to Figure 7B , the method 700 may include an additional step 708. At step 708, the NTC thermistor responds to the decrease in junction temperature by increasing the gate resistance of the linear gate resistor to enable the semiconductor switch to continue to operate at normal switching loss levels.

[0065] Also refer to Figure 7C , the method 700 may include an additional step 710. At step 710, the NTC thermistor responds to a decrease in current load by increasing a gate resistance of the linear gate resistor based on the gate drive voltage.

[0066] in conclusion

[0067] It is contemplated that this system may have many advantages. For example, the system may provide the end user with the ability to customize the user interface and the final view of the user interface containing the desired data in near real time. Similarly, the system will significantly reduce the cycle time for incorporating and finalizing end user requirements and desired features.

[0068] Those skilled in the art will recognize that the prior art has advanced to the point where there is little distinction between hardware and software implementations of various aspects of the system; the use of hardware or software is often (but not always, as the choice between hardware and software can become important in certain circumstances) a design choice that represents a cost-efficiency tradeoff. Those skilled in the art will understand that there are a variety of tools (e.g., hardware, software, and / or firmware) that can implement the processes and / or systems and / or other techniques described herein, and that the preferred tool will vary with the circumstances in which the processes and / or systems and / or other techniques are employed. For example, if the implementer determines that speed and accuracy are most important, the implementer may choose a tool that is primarily hardware and / or firmware; alternatively, if flexibility is most important, the implementer may choose an implementation that is primarily software; or, again alternatively, the implementer may choose some combination of hardware, software, and / or firmware. Thus, there are several possible tools by which the processes and / or devices and / or other techniques described herein can be implemented, none of which is inherently superior to other tools, as any tool to be used is a choice that depends on the circumstances in which the tool will be deployed and the implementer's specific concerns (e.g., speed, flexibility, or predictability), any of which may vary. Those skilled in the art will recognize that the optical aspects of an implementation will typically employ optically oriented hardware, software, and / or firmware.

[0069] The foregoing specific embodiments have been described through the use of block diagrams, flow charts and / or examples to illustrate various embodiments of the device and / or processing. The block diagrams, flow charts and / or examples within this scope include one or more functions and / or operations, and those skilled in the art will understand that each function and / or operation within such block diagrams, flow charts or examples can be implemented individually and / or collectively by a wide range of hardware, software, firmware or any combination thereof. In an embodiment, several parts of the subject matter described herein can be implemented via an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP) or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein can be implemented in whole or in part equivalently in an integrated circuit, implemented as one or more computer programs running on one or more computers (e.g., implemented as one or more programs running on one or more computer systems), implemented as one or more programs running on one or more processors (e.g., implemented as one or more programs running on one or more microprocessors), implemented as firmware or actually implemented as any combination thereof, and according to the present disclosure, designing circuit systems and / or writing codes for software and / or firmware will be completely within the technical scope of those skilled in the art. In addition, those skilled in the art will appreciate that the mechanisms of the subject matter described herein can be distributed as a program product in a variety of forms, and that the illustrative embodiments of the subject matter described herein apply regardless of the specific type of signal-bearing medium used to actually perform the distribution. Examples of signal-bearing media include, but are not limited to, the following: recordable type media, such as floppy disks, hard drives, compact disks (CDs), digital video disks (DVDs), digital tapes, computer memories, etc.; and transmission-type media, such as digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0070] In a general sense, those skilled in the art will recognize that the various aspects described herein that may be implemented, individually and / or collectively, by a wide range of hardware, software, firmware, or any combination thereof may be viewed as including various types of "circuitry." Thus, as used herein, "circuitry" includes, but is not limited to, circuitry having at least one discrete circuit, circuitry having at least one integrated circuit, circuitry having at least one application-specific integrated circuit, circuitry forming a general-purpose computing device configured by a computer program (e.g., a general-purpose computer configured by a computer program that at least partially performs the processes and / or devices described herein, or a microprocessor configured by a computer program that at least partially performs the processes and / or devices described herein), circuitry forming a memory device (e.g., in the form of random access memory), and / or circuitry forming a communication device (e.g., a modem, a communication switch, or an optoelectronic device). Those skilled in the art will recognize that the subject matter described herein may be implemented in an analog or digital manner, or some combination thereof.

[0071] Those skilled in the art will recognize that it is common in the art to describe devices and / or processes in the manner set forth herein, and thereafter to integrate such described devices and / or processes into data processing systems using engineering practices. That is, at least a portion of the devices and / or processes described herein can be integrated into data processing systems via a reasonable amount of experimentation. Personnel with the skill of the art will recognize that a typical data processing system typically includes one or more of the following: a system unit housing, a video display device, a memory such as volatile and non-volatile memory, a processor such as a microprocessor and a digital signal processor, a computing entity such as an operating system, a driver, a graphical user interface, and an application, one or more interactive devices such as a touch pad or screen, and / or a control system including a feedback loop and a control motor (e.g., feedback for sensing position and / or velocity; a control motor for moving and / or adjusting components and / or quantities). A typical data processing system can be implemented using any suitable commercially available components, such as those typically found in data computing / communication and / or network computing / communication systems.

[0072] The subject matter described herein sometimes illustrates different components included in or connected to different other components.It should be understood that the architecture depicted in this way is only exemplary, and many other architectures that realize the same function can actually be implemented.In the sense of conception, the arrangement of any components that realize the same function is effectively "associated" to achieve the desired function.Therefore, any two components that are combined to realize a specific function in this article can be regarded as "associated" with each other to achieve the desired function, regardless of the architecture or intermediate components.Similarly, any two components so associated can also be regarded as "operably connected" or "operably coupled" to achieve the desired function, and any two components that can be so associated can also be regarded as "operably coupled" to achieve the desired function.Specific examples that can be operably coupled include but are not limited to physically matchable and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0073] Although particular aspects of the subject matter described herein have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made based on the teachings herein without departing from the subject matter described herein and its broader aspects, and therefore, the appended claims cover within their scope all such changes and modifications within the true spirit and scope of the subject matter described herein. In addition, it should be understood that the invention is defined by the appended claims.

Claims

1. A gate drive circuit for a semiconductor device, comprising: at least one semiconductor switch configured to supply a gate drive voltage to the semiconductor device in response to a control signal received from a control switch, the at least one semiconductor switch being associated with: Radiated emission limits; as well as Junction temperature; Wherein, the gate drive voltage is one of the following: a positive voltage corresponding to an on-state associated with at least one of an on-switching time or an on-switching loss; as well as a non-positive voltage corresponding to an off state, the off state being associated with at least one of an off switching time or an off switching loss; as well as a gate resistance device connected in series between the control switch and the at least one semiconductor switch, the gate resistance device being thermally coupled to the at least one semiconductor switch, the gate resistance device comprising a negative temperature coefficient thermistor and a linear gate resistor connected in parallel; Wherein, the negative temperature coefficient thermistor is configured as: sensing a junction temperature associated with at least one of the on-state or the off-state; as well as In the event that the junction temperature reaches or exceeds a threshold level, one or more of an associated on switching time or an off switching time or an associated on switching loss or an off switching loss is reduced by reducing the gate resistance of the linear gate resistor.

2. The gate drive circuit according to claim 1, wherein: The negative temperature coefficient thermistor is configured to reduce the gate resistance until the junction temperature decreases below the threshold level.

3. The gate driving circuit according to claim 1, wherein: The negative temperature coefficient thermistor is configured to decrease the gate resistance based on an inverse linear relationship to an increase in the sensed junction temperature.

4. The gate driving circuit according to claim 1, wherein: The negative temperature coefficient thermistor is configured to increase the gate resistance based on a reduced current load associated with the gate drive voltage.

5. The gate driving circuit according to claim 1, wherein: The negative temperature coefficient thermistor is configured to increase the gate resistance based on a sensed decrease in junction temperature.

6. The gate driving circuit according to claim 1, wherein: The linear gate resistor is associated with: The minimum gate resistance corresponding to the stated radiated emission limit; as well as Maximum gate resistance based on the power capability of the semiconductor switch.

7. The gate driving circuit according to claim 1, wherein: The at least one semiconductor switch comprises at least one insulated gate bipolar transistor IGBT.

8. The gate driving circuit according to claim 1, wherein: The semiconductor device is a system on chip SoC; and The at least one semiconductor switch and the gate resistance device include at least one surface mounted device (SMD).

9. The gate driving circuit according to claim 1, wherein: The conduction switching time includes at least one of the following: a turn-on delay associated with the turn-on state; a rise time associated with the on-state; or A charging time associated with the on-state.

10. The gate driving circuit according to claim 1, wherein: The off switching time includes at least one of the following: a shutdown delay associated with the shutdown state; a fall time associated with the off state; and A discharge time associated with the off state.

11. A method for optimal switching of a semiconductor device, the method comprising: connecting a gate resistance device in series between a semiconductor switch of a semiconductor device and a control switch of the semiconductor device, the semiconductor switch being configured to supply a gate drive voltage to the semiconductor device in response to a control signal received from the control switch, the semiconductor switch being associated with a radiated emission limit and a junction temperature, the gate drive voltage corresponding to at least one of an on-state or an off-state, the on-state being associated with an on-switching time and an on-switching loss, the off-state being associated with an off-switching time and an off-switching loss; and The gate resistance device is thermally coupled to the semiconductor switch and includes a negative temperature coefficient thermistor and a linear gate resistor connected in parallel; sensing a junction temperature associated with at least one of the on-state or the off-state via the negative temperature coefficient thermistor; as well as In the event that the junction temperature reaches or exceeds a threshold level, the gate resistance of the linear gate resistor is reduced via the negative temperature coefficient thermistor.

12. The method according to claim 11, wherein: In the event that the junction temperature reaches or exceeds a threshold level, reducing the gate resistance of the linear gate resistor via the negative temperature coefficient thermistor, comprising: The gate resistance is reduced based on an inverse linear relationship to an increase in the sensed junction temperature.

13. The method according to claim 11, wherein: In the event that the junction temperature reaches or exceeds a threshold level, reducing the gate resistance of the linear gate resistor via the negative temperature coefficient thermistor, comprising: In the event that the junction temperature reaches or exceeds a threshold level, the gate resistance is reduced until the junction temperature decreases below the threshold level.

14. The method according to claim 11, further comprising: The gate resistance is increased via the negative temperature coefficient thermistor based on a reduced current load associated with the gate drive voltage.

15. The method according to claim 11, further comprising: The gate resistance is increased via the negative temperature coefficient thermistor based on a sensed decrease in junction temperature.

16. The method according to claim 11, wherein: The linear gate resistor is associated with: The minimum gate resistance corresponding to the stated radiated emission limit; as well as Maximum gate resistance based on the power capability of the semiconductor switch.

17. The method according to claim 11, wherein: The semiconductor switch is an insulated gate bipolar transistor IGBT.

18. The method of claim 11, wherein: The semiconductor device is a system on chip SoC; and The semiconductor switch and the gate resistance device include at least one surface mount device (SMD).

19. The method according to claim 11, wherein: The conduction switching time includes at least one of the following: a turn-on delay associated with the turn-on state; a rise time associated with the on-state; or A charging time associated with the on-state.

20. The method according to claim 11, wherein: The off switching time includes at least one of the following: a shutdown delay associated with the shutdown state; a fall time associated with the off state; or A discharge time associated with the off state.

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