Time-interleaved analog-to-digital converter and signal conversion method

Abstract

The invention relates to a time-interleaved analog-to-digital converter and a signal conversion method. The time-interleaved analog-to-digital converter includes a plurality of channel circuitry, an output circuit, and a correction circuitry. The plurality of channel circuitry is configured to sample an input signal to generate a plurality of first digital codes according to the input signal. The output circuit is used for outputting a second digital code according to the first digital code. The correction circuit system is used for adjusting a sampling sequence of the channel circuit system to the input signal according to the second digital code in an initial period, and controlling the channel circuit system to sample the input signal according to the adjusted sampling sequence in an analog-digital conversion period.

Description

Technical Field

[0001] The present disclosure relates to an analog-to-digital converter, and more particularly to a time-interleaved analog-to-digital converter capable of adjusting a sampling sequence and a signal conversion method. Background Art

[0002] In an existing time-interleaved analog to digital converter, multiple channels sample input signals in a fixed sampling order. However, in actual applications, the phases of multiple clock signals that control the sampling order may be skewed, resulting in an inaccurate sampling order. Therefore, an additional phase error correction circuit is required to correct the clock signals, resulting in an increase in circuit area and power consumption. On the other hand, when the number of channels increases, the mismatch caused by process variations and other reasons in the actual circuit will also increase, making the originally preset fixed sampling order may not be suitable for the actual circuit. Under this condition, if sampling is still performed in the original fixed sampling order, the performance of the time-interleaved analog to digital converter will be reduced. Summary of the invention

[0003] In some implementations, one of the purposes of the present disclosure is (but not limited to) to provide a time-interleaved analog-to-digital converter and a signal conversion method capable of adjusting the sampling order, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, a time-interleaved analog-to-digital converter includes a plurality of channel circuit systems, an output circuit, and a correction circuit system. The plurality of channel circuit systems are used to sample an input signal to generate a plurality of first digital codes according to the input signal. The output circuit is used to output a second digital code according to the first digital codes. The correction circuit system is used to adjust a sampling order of the input signal by the channel circuit systems according to the second digital code during an initial period, and control the channel circuit systems to sample the input signal in the adjusted sampling order during an analog-to-digital conversion period.

[0005] In some embodiments, the signal conversion method includes the following operations: sampling an input signal through multiple channel circuit systems and generating multiple first digital codes based on the sampled input signal; outputting a second digital code based on the first digital codes; and adjusting a sampling order of the input signal by the channel circuit systems according to the second digital code during an initial period, and controlling the channel circuit systems to sample the input signal in the adjusted sampling order during an analog-to-digital conversion period.

[0006] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a time-interleaved analog-to-digital converter according to some embodiments of the present disclosure;

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1 A flowchart of a plurality of operations performed by a correction circuit system;

[0009] Figure 3 A schematic diagram of a time-interleaved analog-to-digital converter according to some embodiments of the present disclosure;

[0010] Figure 4 According to some embodiments of the present disclosure Figure 1 A flowchart of a plurality of operations performed by a correction circuit system;

[0011] Figure 5A According to some embodiments of the present disclosure Figure 3 Schematic diagram of the sampling circuit in;

[0012] Figure 5B According to some embodiments of the present disclosure Figure 3 A schematic diagram of a sampling circuit in; and

[0013] Figure 6 The present invention is a flowchart of a signal conversion method according to some embodiments of the present disclosure.

[0014] Explanation of symbols

[0015] 100,300: Time-interleaved analog-to-digital converter

[0016] 110[1],310[1],320[1],320[2]:Sampling circuit

[0017] 120[1],330[1],330[2]: Analog-to-digital converter circuit

[0018] 130: Output circuit

[0019] 140: Correction circuit system

[0020] 142: Control logic circuit

[0021] 144: Clock generator circuit

[0022] 146: Clock multiplexer circuit

[0023] 148: Frequency divider circuit

[0024] 510: Switch

[0025] 520: Capacitor

[0026] 600: Signal conversion method

[0027] CH1~CH4: Channel circuit system

[0028] CK1[1]~CK1[4], CK2[1]~CK2[4]: clock signal

[0029] CK3[1-1],CK3[1-2],CK3[2-1],CK3[2-2]: clock signals

[0030] CK3[3-1],CK3[3-2],CK3[4-1],CK3[4-2]: clock signals

[0031] D1[1]~D1[4],D1[1-1],D1[1-2],D1[2-1],D1[2-2],D1[3-1],D1[3-2]: digital code

[0032] D1[4-1],D1[4-2],D2: digital code

[0033] S1, S2: Signal

[0034] S210,S220,S230,S240,S250,S260,S270: Operation

[0035] S410,S415,S420,S430,S435,S440,S450,S460,S470: Operation

[0036] S610, S620, S630: Operation

[0037] SC: Control signal

[0038] SIN: Input signal DETAILED DESCRIPTION

[0039] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the content of this disclosure are only illustrative and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0040] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuitry" may be a system formed by at least one circuit, and the term "circuit" may be a device that is connected in a certain manner by at least one transistor and / or at least one active and passive element to process signals.

[0041] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this article, the words first, second, third, etc. are used to describe and distinguish each element. Therefore, the first element in this article can also be called the second element without departing from the original intention of the present disclosure. For ease of understanding, similar elements in the various drawings will be designated with the same reference numerals.

[0042] Figure 1 FIG. 1 is a schematic diagram of a time-interleaved analog-to-digital converter 100 according to some embodiments of the present disclosure. The time-interleaved analog-to-digital converter 100 includes a plurality of channel circuit systems CH1 - CH4 , an output circuit 130 and a calibration circuit system 140 .

[0043] A plurality of channel circuit systems CH1 to CH4 are used to sample an input signal SIN to generate a plurality of digital codes D1[1] to D1[4] according to the input signal SIN. For example, the plurality of channel circuit systems CH1 to CH4 may be turned on according to a plurality of clock signals CK1[1] to CK1[4] to sequentially sample the input signal SIN to generate a plurality of digital codes D1[1] to D1[4]. In this example, each of the plurality of channel circuit systems CH1 to CH4 includes a sampling circuit and an analog-to-digital converter circuit. Taking the channel circuit system CH1 as an example, the channel circuit system CH1 includes a sampling circuit 110[1] and an analog-to-digital converter circuit 120[1]. The sampling circuit 110[1] is turned on according to a corresponding clock signal CK1[1] among the plurality of clock signals CK1[1] to CK1[4] to sample the input signal SIN to generate a signal S1. In some embodiments, the sampling circuit 110[1] may include a switch (not shown) and a capacitor (not shown). The switch is turned on according to the clock signal CK1[1] to transmit the input signal SIN to the capacitor, and the capacitor can sample the input signal SIN to generate a signal S1. The analog-to-digital converter circuit 120[1] can convert the signal S1 into a corresponding digital code D1[1] among a plurality of digital codes D1[1] to D1[4]. In different embodiments, the analog-to-digital converter circuit 120[1] can be, but not limited to, a flash analog-to-digital converter circuit, a successive approximation register analog-to-digital converter circuit, a pipeline analog-to-digital converter circuit, etc., but the present disclosure is not limited thereto. Various types of analog-to-digital converter circuits are all within the scope of the present disclosure.

[0044] Each of the multiple channel circuit systems CH1-CH4 may have the same circuit configuration. Similarly, the configuration between the multiple channel circuit systems CH2-CH4, the multiple clock signals CK1[2]-CK1[4] and the multiple digital codes D1[2]-D1[4] can be understood.

[0045] The output circuit 130 is coupled to a plurality of channel circuit systems CH1-CH4 to receive a plurality of digital codes D1[1]-D1[4]. The output circuit 130 may output a digital code D2 according to the plurality of digital codes D1[1]-D1[4]. In some embodiments, the output circuit 130 may be a parallel-to-serial converter circuit that may convert parallel data (e.g., a plurality of digital codes D1[1]-D1[4]) into serial data (e.g., digital code D2). In some embodiments, the output circuit 130 may be a multiplexer circuit.

[0046] The calibration circuit system 140 is used to adjust the sampling order of the input signal SIN by the plurality of channel circuit systems CH1-CH4 according to the digital code D2 during an initial period (e.g., a period after the time-interleaved analog-to-digital converter 100 is powered on for the first time), and control the plurality of channel circuit systems CH1-CH4 to sample the input signal SIN in the adjusted sampling order during an analog-to-digital conversion period (e.g., a period when the conversion of the valid input signal SIN starts after the sampling order is adjusted). For example, the calibration circuit system 140 may output the plurality of clock signals CK2[1]-CK2[4] in different orders as the plurality of clock signals CK1[1]-CK1[4] during the initial period, wherein the phases of the plurality of clock signals CK2[1]-CK2[4] differ in sequence by a fixed value. For example, the phases of the plurality of clock signals CK2[1]-CK2[4] may be approximately 0 degrees, 90 degrees, 180 degrees, and 270 degrees in sequence. The calibration circuit system 140 can determine a performance indicator related to the time-interleaved analog-to-digital converter 100 according to the digital code D2 obtained during the initial period, so as to determine whether to use a specific sequence to output the multiple clock signals CK2[1]-CK2[4] as multiple clock signals CK1[1]-CK1[4], thereby determining the sampling sequence of the multiple channel circuit systems CH1-CH4. The detailed operation here will be referred to later. Figure 2 illustrate.

[0047] In some embodiments, the calibration circuit system 140 includes a control logic circuit 142, a clock generator circuit 144, and a clock multiplexer circuit 146. The control logic circuit 142 may execute the following Figure 2 In some embodiments, the control logic circuit 142 may be a signal processing circuit with computing capability, which may be used to perform the operation of Figure 2 In some embodiments, the correction circuit system 140 may include one or more storage circuits (for example, but not limited to, registers) that can be used to temporarily store the aforementioned performance indicators and the values ​​of the control signal SC. The clock generator circuit 144 can generate a plurality of clock signals CK2[1]-CK2[4]. In some embodiments, the clock generator circuit 144 can operate in conjunction with a skew correction circuit to correct the phase errors of the plurality of clock signals CK2[1]-CK2[4]. The clock multiplexer circuit 146 outputs the plurality of clock signals CK2[1]-CK2[4] in different sequences as a plurality of clock signals CK1[1]-CK1[4] according to the control signal SC, thereby adjusting the sampling sequence of the channel circuit systems CH1-CH4 for the input signal SIN. In some embodiments, the plurality of clock signals CK2[1]-CK2[4] can also be generated by other clock generator circuits in the system.

[0048] It should be understood that Figure 1 The number of circuits shown is only an example, and the present disclosure is not limited thereto. In different embodiments, the time-interleaved analog-to-digital converter 100 may include more channel circuit systems. Figure 1 The present invention is limited to the embodiments of the present invention.

[0049] Figure 2 According to some embodiments of the present disclosure Figure 1 Flowchart of multiple operations performed by the correction circuit system 140. In some embodiments, Figure 2 The multiple operations in may be performed during the aforementioned initial period, but the present disclosure is not limited thereto. In some embodiments, Figure 2 Multiple operations in Figure 1 The correction circuit system 140 is performed by multiple circuits in the correction circuit system 140.

[0050] In operation S210, a control signal SC is output to control the clock multiplexer circuit 146 to output the plurality of clock signals CK2[1]-CK2[4] in a first sequence as a plurality of clock signals CK1[1]-CK1[4]. In operation S220, a first performance indicator is determined according to a digital code D2 corresponding to the first sequence.

[0051] For example, during the initial period, the control logic circuit 142 may output a control signal SC to control the clock multiplexer circuit 146 to output the plurality of clock signals CK2[1]-CK2[4] in a first sequence as a plurality of clock signals CK1[1]-CK1[4]. In the first sequence, the plurality of clock signals CK2[1], CK2[2], CK2[3] and CK2[4] are respectively output as a plurality of clock signals CK1[1], CK1[2], CK1[3] and CK1[4]. During the initial period, the control logic circuit 142 may also switch the input signal SIN to a test signal. Under this condition, the phases of the plurality of clock signals CK1[1]-CK1[4] may be 0 degrees, 90 degrees, 180 degrees and 270 degrees in sequence, so that the plurality of channel circuit systems CH1-CH4 may be turned on in sequence to sample the input signal SIN, thereby generating a corresponding digital code D2. In other words, the sampling order of the input signal SIN by the plurality of channel circuit systems CH1 - CH4 is adjusted to the first order. Thus, the control logic circuit 142 can determine the performance indicator corresponding to the first order according to the digital code D2.

[0052] In some embodiments, the aforementioned performance indicator includes at least one of the effective number of bits (ENOB), spurious free dynamic range (SFDR), signal to noise ratio (SNR), or skew error. The aforementioned performance indicator can be used to indicate the resolution of the digital code D2 or the overall performance of the time-interleaved analog-to-digital converter 100. The aforementioned multiple performance indicators are well known to those skilled in the art, so they are not further described in detail here. The aforementioned multiple performance indicators are only used for example, and the present disclosure is not limited thereto. Various performance indicators that can indicate the resolution of the digital code D2 or indicate the performance of the time-interleaved analog-to-digital converter 100 are all within the scope of the present disclosure.

[0053] Continue to refer to Figure 2 In operation S230, the control signal SC is switched to control the clock multiplexer circuit 146 to output the plurality of clock signals CK2[1]-CK2[4] in a second order as a plurality of clock signals CK1[1]-CK1[4]. In operation S240, a second performance indicator corresponding to the second order is determined according to the digital code D2. In operation S250, operations S230 and S240 are repeatedly performed to obtain a plurality of performance indicators corresponding to different orders. In operation S260, an optimal performance indicator is determined according to the plurality of performance indicators previously obtained. In operation S270, a sequence corresponding to the optimal performance indicator is selected from the plurality of sequences.

[0054] For example, after obtaining the first performance indicator, the control logic circuit 142 may switch the control signal SC so that the clock multiplexer circuit 146 outputs the plurality of clock signals CK2[1]-CK2[4] in a second sequence as a plurality of clock signals CK1[1]-CK1[4]. For example, in the second sequence, the plurality of clock signals CK2[2], CK2[3], CK2[4] and CK2[1] are respectively output as a plurality of clock signals CK1[1], CK1[2], CK1[3] and CK1[4]. Under this condition, the phases of the plurality of clock signals CK1[1]-CK1[4] may be 90 degrees, 180 degrees, 270 degrees and 0 degrees in sequence, so that the plurality of channel circuit systems CH4, CH1, CH2 and CH3 may be turned on in sequence to sample the input signal SIN, thereby generating the corresponding digital code D2. In other words, the sampling sequence of the plurality of channel circuit systems CH1-CH4 for the input signal SIN is adjusted from the first sequence to the second sequence. The calibration circuit system 140 may determine a performance indicator corresponding to the second order according to the digital code D2.

[0055] Similarly, the control logic circuit 142 can adjust the sampling order of the input signal SIN by the multiple channel circuit systems CH1-CH4 by switching the control signal SC to obtain multiple performance indicators corresponding to different orders. The control logic circuit 142 can store all the performance indicators previously obtained, and can confirm an optimal performance indicator among the performance indicators based on the performance indicators. In this way, the control logic circuit 142 can select an optimal order (which corresponds to the optimal performance indicator) from the multiple orders previously tested, and use the control signal SC corresponding to the optimal order to control the clock multiplexer circuit 146 to output the multiple clock signals CK2[1]-CK2[4] as multiple clock signals CK1[1]-CK1[4] in the optimal order during the analog-to-digital conversion period. For example, if the control logic circuit 142 determines that the performance indicator with the best performance among the multiple performance indicators is the aforementioned second performance indicator (for example, the second performance indicator has the highest ENOB, SFDR or SNR, or has the lowest skew error) during the initial period, the control logic circuit 142 can store the control signal SC corresponding to the second order (which corresponds to the second performance indicator). During the analog-to-digital conversion period, the control logic circuit 142 can output the control signal SC corresponding to the second order, thereby adjusting the sampling order of the multiple channel circuit systems CH1-CH4 for the input signal SIN to the second order to improve the circuit performance.

[0056] In some related technologies, a time-interleaved analog-to-digital converter samples an input signal in a preset fixed sampling order. In actual applications, there may be errors in the phases of multiple clock signals that control the sampling order. Therefore, these related technologies will additionally use a phase error correction circuit to pre-correct the phase error. However, when the number of channels increases, the circuit area and power consumption required by the phase error correction circuit will increase significantly. On the other hand, since there will be mismatches between multiple sampling circuits in multiple channels due to process variations and other influences, the preset fixed sampling order may not be suitable for the actual circuit, resulting in a decrease in overall performance.

[0057] Compared to the above-mentioned related art, in some embodiments of the present disclosure, through the above-mentioned configuration, the calibration circuit system 140 can use the above-mentioned multiple operations to adjust the sampling order of the multiple channel circuit systems CH1-CH4 to the input signal SIN. In other words, the calibration circuit system 140 can perform tests during the initial period to find a sampling order that can make the time-interleaved analog-to-digital converter 100 have better performance, and use the adjusted sampling order to generate the digital code D2 during the analog-to-digital conversion period. In this way, the performance of the time-interleaved analog-to-digital converter 100 can be effectively improved without significantly increasing the circuit area and power consumption.

[0058] Figure 3 FIG. 3 is a schematic diagram of a time-interleaved analog-to-digital converter 300 according to some embodiments of the present disclosure. Figure 1 Compared with the time-interleaved analog-to-digital converter 100 , each of the multiple channel circuit systems CH1 ˜ CH4 in the time-interleaved analog-to-digital converter 300 includes more sampling circuits and more analog-to-digital converter circuits.

[0059] Taking the channel circuit system CH1 as an example, the channel circuit system CH1 includes a sampling circuit 310[1], a plurality of sampling circuits 320[1] and 320[2], and a plurality of analog-to-digital converter circuits 330[1] to 330[2]. The sampling circuit 310[1] is selectively turned on according to a corresponding clock signal CK1[1] among a plurality of clock signals CK1[1] to CK1[4] to transmit an input signal SIN to the plurality of sampling circuits 320[1] and 320[2]. The plurality of sampling circuits 320[1] and 320[2] samples the input signal SIN transmitted from the sampling circuit 310[1] according to a plurality of clock signals CK3[1-1] and CK3[1-2] to generate a plurality of signals S1[1-1] and S1[1-2]. The plurality of analog-to-digital converter circuits 330[1] and 330[2] are used to convert the plurality of signals S1[1-1] and S1[1-2] to generate a plurality of digital codes D1[1-1] and D1[1-2] (equivalent to Figure 1 In some embodiments, a plurality of clock signals CK3[1-1] and CK3[1-2] may be generated based on the corresponding clock signal CK1[1] described above. For example, a plurality of clock signals CK3[1-1] and CK3[1-2] may be generated by dividing the clock signal CK1[1], and the plurality of clock signals CK3[1-1] and CK3[1-2] may have a preset phase difference with each other. In this way, a plurality of sampling circuits 320[1] and 320[2] may sequentially sample the input signal SIN transmitted from the sampling circuit 310[1] during the conduction period of the sampling circuit 310[1]. The configuration of the plurality of sampling circuits 320[1] and 320[2] and the plurality of analog-to-digital converter circuits 330[1] to 330[2] may refer to Figure 1 The sampling circuit 110[1] and the analog-to-digital converter 120[1] are described in detail below. Figure 5A and Figure 5B illustrate.

[0060] Each of the multiple channel circuit systems CH1-CH4 may have the same circuit configuration. Similarly, the corresponding relationship between the multiple channel circuit systems CH2-CH4, the multiple clock signals CK1[2]-CK1[4], the multiple clock signals CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2], and the multiple digital codes D1[2-1], D1[2-2], D1[3-1], D1[3-2], D1[4-1] and D1[4-2] can be understood. Figure 1 The output circuit 130 can output a digital code D2 according to multiple digital codes D1[1-1], D1[1-2], D1[2-1], D1[2-2], D1[3-1], D1[3-2], D1[4-1] and D1[4-2], and the correction circuit system 140 is used to adjust the sampling order of the multiple channel circuit systems CH1~CH4 for the input signal SIN according to the digital code D2 during the initial period, and control the channel circuit systems CH1~CH4 to sample the input signal SIN in the adjusted sampling order during the analog-to-digital conversion period.

[0061] In detail, in this example, the calibration circuit system 140 further includes a frequency divider circuit 148. After adjusting the sampling order, the frequency divider circuit 148 can divide the frequency and adjust the phase of the multiple clock signals CK1[1]~CK1[4] to generate multiple clock signals CK3[1-1], CK3[1-2], CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2]. For example, the frequency divider circuit 148 can divide the frequency and adjust the phase of the clock signal CK1[1] to generate multiple clock signals CK3[1-1] and CK3[1-2], wherein the phase difference between the multiple clock signals CK3[1-1] and CK3[1-2] can be approximately 180 degrees. Similarly, after adjusting the sampling order, the frequency divider circuit 148 can perform frequency division and phase adjustment on the clock signal CK1[2] to generate multiple clock signals CK3[2-1] and CK3[2-2], wherein the phase difference between the multiple clock signals CK3[2-1] and CK3[2-2] can be approximately 180 degrees. By analogy, the corresponding relationship between the multiple clock signals CK1[3] and CK1[4] and the multiple clock signals CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2] can be understood. In some embodiments, the frequency divider circuit 148 can be implemented by other frequency divider circuits in the system.

[0062] It should be understood that Figure 3The number of circuits shown is for example only and the present disclosure is not limited thereto. In different embodiments, the time-interleaved ADC 300 may include more channel circuit systems, and a single channel circuit system may include more sampling circuits and / or ADC circuits. Figure 3 The present invention is limited to the embodiments of the present invention.

[0063] Figure 4 According to some embodiments of the present disclosure Figure 1 Flowchart of multiple operations performed by the correction circuit system 140. In some embodiments, Figure 4 The multiple operations in are performed during the aforementioned initial period, but the present disclosure is not limited thereto. In some embodiments, Figure 4 Multiple operations in Figure 3 The correction circuit system 140 is performed by multiple circuits in the correction circuit system 140.

[0064] In operation S410, a control signal SC is output to control the clock multiplexer circuit 146 to output the plurality of clock signals CK2[1]-CK2[4] in a first sequence as a plurality of clock signals CK1[1]-CK1[4]. In operation S415, the plurality of clock signals CK1[1]-CK1[4] are divided to generate a plurality of clock signals CK3[1-1], CK3[1-2], CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2]. In operation S420, a first performance indicator is determined according to the digital code D2 corresponding to the first sequence.

[0065] For example, during the initial period, the control logic circuit 142 may output the control signal SC to control the clock multiplexer circuit 146 to output the plurality of clock signals CK2[1]-CK2[4] in a first sequence as the plurality of clock signals CK1[1]-CK1[4], and the control logic circuit 142 may switch the input signal SIN to a test signal. Similarly, in the first sequence, the plurality of clock signals CK2[1], CK2[2], CK2[3] and CK2[4] are output as the plurality of clock signals CK1[1], CK1[2], CK1[3] and CK1[4], respectively. Under this condition, the phases of the plurality of clock signals CK1[1]-CK1[4] may be 0 degrees, 90 degrees, 180 degrees and 270 degrees in sequence. The frequency divider circuit 148 can divide the clock signal CK1[1] and adjust the phase to generate multiple clock signals CK3[1-1] and CK3[1-2], and divide the clock signal CK1[2] and adjust the phase to generate multiple clock signals CK3[2-1] and CK3[2-2]. Based on similar operations, the frequency divider circuit 148 can generate multiple clock signals CK3[3-1] and CK3[3-2] according to the clock signal CK1[3], and generate multiple clock signals CK3[4-1] and CK3[4-2] according to the clock signal CK1[4]. In this way, the multiple channel circuit systems CH1~CH4 can be turned on in sequence to sample the input signal SIN, thereby generating a corresponding digital code D2. In other words, the sampling order of the input signal SIN by the multiple channel circuit systems CH1~CH4 is adjusted to the first order, so that the control logic circuit 142 can determine the performance indicator corresponding to the first order according to the digital code D2.

[0066] Continue to refer to Figure 4 In operation S430, the control signal SC is switched to control the clock multiplexer circuit 146 to output the multiple clock signals CK2[1]~CK2[4] in a second order as multiple clock signals CK1[1]~CK1[4]. In operation S435, the multiple clock signals CK1[1]~CK1[4] are divided to generate multiple clock signals CK3[1-1], CK3[1-2], CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2]. In operation S440, a second performance indicator corresponding to the second order is determined according to the digital code D2. In operation S450, operations S430, S435 and S440 are repeatedly performed to obtain multiple performance indicators corresponding to different orders. In operation S460, an optimal performance indicator is determined according to the multiple performance indicators previously obtained. In operation S470 , a sequence corresponding to the best performance indicator is selected from a plurality of sequences.

[0067] For example, after obtaining the first performance indicator, the control logic circuit 142 may switch the control signal SC so that the clock multiplexer circuit 146 outputs the plurality of clock signals CK2[1]-CK2[4] in a second sequence as a plurality of clock signals CK1[1]-CK1[4]. For example, in the second sequence, the plurality of clock signals CK2[2], CK2[3], CK2[4] and CK2[1] are output as a plurality of clock signals CK1[1], CK1[2], CK1[3] and CK1[4] respectively. Under this condition, the phases of the plurality of clock signals CK1[1]-CK1[4] may be 90 degrees, 180 degrees, 270 degrees and 0 degrees in sequence. The frequency divider circuit 148 can perform frequency division and phase adjustment on the clock signal CK1[1] to generate a plurality of clock signals CK3[1-1] and CK3[1-2], and perform the same operation according to the clock signals CK1[2], CK1[3] and CK1[4] to generate a plurality of clock signals CK3[2-1] to CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2] respectively. In this way, the plurality of channel circuit systems CH4, CH1, CH2 and CH3 can be turned on in sequence to sample the input signal SIN, thereby generating a corresponding digital code D2. In other words, the sampling order of the input signal SIN by the plurality of channel circuit systems CH1-CH4 is adjusted from the first order to the second order, and the frequency divider circuit 148 can generate a plurality of clock signals CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2] corresponding to the second order. In this way, the calibration circuit system 140 can determine the performance index corresponding to the second order according to the digital code D2.

[0068] Similarly, the control logic circuit 142 can adjust the sampling order of the input signal SIN by the multiple channel circuit systems CH1-CH4 by switching the control signal SC to obtain multiple performance indicators corresponding to different orders. The control logic circuit 142 can store all the performance indicators previously obtained, and can determine a best performance indicator among the performance indicators according to the performance indicators. In this way, the control logic circuit 142 can select an optimal sequence from multiple sequences previously tested, and use the control signal SC corresponding to the optimal sequence to control the clock multiplexer circuit 146 to output multiple clock signals CK2[1]~CK2[4] in the optimal sequence as multiple clock signals CK1[1]~CK1[4] during the analog-to-digital conversion period, and the divider circuit 148 can thereby generate multiple clock signals CK3[1-1], CK3[1-2], CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2] corresponding to the optimal sequence. For example, if the control logic circuit 142 determines that the performance indicator with the best performance among the multiple performance indicators is the aforementioned second performance indicator (for example, the second performance indicator has the highest ENOB, SFDR, SNR, or has the lowest skew error) during the initial period, the control logic circuit 142 can store the control signal SC corresponding to the second order (which corresponds to the second performance indicator). During the analog-to-digital conversion period, the control logic circuit 142 can output the control signal SC corresponding to the second order, thereby adjusting the sampling order of the multiple channel circuit systems CH1~CH4 for the input signal SIN to the second order, and the frequency divider circuit 148 can generate a plurality of clock signals CK3[1-1], CK3[1-2], CK3[2-1], CK3[2-2], CK3[3-1], CK3[3-2], CK3[4-1] and CK3[4-2] corresponding to the second order.

[0069] Figure 5A According to some embodiments of the present disclosure Figure 3 Schematic diagram of a sampling circuit in FIG. In this example, the sampling circuit 310[1] includes a switch 510. A first end of the switch 510 receives an input signal SIN, a second end of the switch 510 is coupled to a plurality of sampling circuits 320[1] and 320[2], and a control end of the switch 510 receives a clock signal CK1[1]. The switch 510 can be selectively turned on according to the clock signal CK1[1] to transmit the input signal SIN to the plurality of sampling circuits 320[1] and 320[2]. In this way, the plurality of sampling circuits 320[1] and 320[2] can sample the input signal SIN in sequence according to the plurality of clock signals CK2[1-1] and CK2[1-2].

[0070] Figure 5BAccording to some embodiments of the present disclosure Figure 3 Schematic diagram of the sampling circuit in. Different from Figure 5A In this example, the sampling circuit 310[1] further includes a capacitor 520. The capacitor 520 is coupled between the second end of the switch 510 and the ground. When the switch 510 is turned on according to the clock signal CK1[1], the switch 510 can transmit the input signal SIN to the capacitor 520. In this way, the capacitor 520 can store the input signal SIN and generate a signal S2 to the multiple sampling circuits 320[1] and 320[2], and the multiple sampling circuits 320[1] and 320[2] can sample the signal S2 in sequence according to the multiple clock signals CK2[1-1] and CK2[1-2].

[0071] The above-mentioned configuration methods of the sampling circuit 310 [1] are for illustrative purposes only, and the present disclosure is not limited thereto. In addition, the number of components presented in the above-mentioned figures is for illustrative purposes only, and the present disclosure is not limited thereto.

[0072] Figure 6 FIG. 6 is a flow chart of a signal conversion method 600 according to some embodiments of the present disclosure. In some embodiments, the signal conversion method 600 may be, but is not limited to, Figure 1 The time-interleaved analog-to-digital converter 100 or Figure 3 The time-interleaved analog-to-digital converter 300 is executed.

[0073] In operation S610, an input signal is sampled through a plurality of channel circuit systems, and a plurality of first digital codes are generated according to the sampled input signal. In operation S620, a second digital code is output according to the first digital codes. In operation S630, a sampling order of the input signal by the channel circuit systems is adjusted according to the second digital code during an initial period, and the channel circuit systems are controlled to sample the input signal in the adjusted sampling order during an analog-to-digital conversion period.

[0074] The operations in the signal conversion method 600 may refer to the description of the aforementioned embodiments, and thus will not be repeated here. Figure 2 , Figure 4 and Figure 6 The multiple operations in the example are only examples and are not limited to being executed in the order in this example. Without violating the operation mode and scope of each embodiment of the present disclosure, Figure 2 , Figure 4 and Figure 6 The various operations in can be appropriately added, replaced, omitted or performed in a different order. Figure 2 , Figure 4 and Figure 6 The various operations in may be performed concurrently or with partial concurrence.

[0075] In summary, the time-interleaved analog-to-digital converter and signal conversion method provided in some embodiments of the present disclosure can adjust the sampling order of multiple channel circuit systems to find a suitable sampling order, thereby improving the performance of the time-interleaved analog-to-digital converter.

[0076] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.

Claims

1. A time-interleaved analog-to-digital converter, comprising: A plurality of channel circuit systems for sampling an input signal to generate a plurality of first digital codes according to the input signal; an output circuit for outputting a second digital code according to the plurality of first digital codes; and A correction circuit system is used to adjust a sampling sequence of the input signal by the multiple channel circuit systems according to the second digital code during an initial period, and control the multiple channel circuit systems to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period.

2. The time-interleaved analog-to-digital converter of claim 1 , wherein each of the plurality of channel circuit systems comprises: a sampling circuit for sampling the input signal according to a corresponding one of a plurality of first clock signals to generate a first signal; and An analog-to-digital converter circuit is used to convert the first signal to generate a corresponding one of the plurality of first digital codes.

3. The time-interleaved analog-to-digital converter of claim 2, wherein the calibration circuit system comprises: a control logic circuit, configured to output a control signal according to the second digital code during the initial period; a clock generator circuit for generating a plurality of second clock signals; and A clock multiplexer circuit is used to output the plurality of second clock signals as the plurality of first clock signals in different sequences according to the control signal during the initial period.

4. The time-interleaved analog-to-digital converter as described in claim 1, wherein the correction circuit system is used to output multiple second clock signals as multiple first clock signals in different orders during the initial period to adjust the sampling order, and the multiple channel circuit systems sample the input signal in sequence according to the multiple first clock signals. 5 . The time-interleaved analog-to-digital converter of claim 1 , wherein the calibration circuit system is used for determining a performance indicator according to the second digital code during the initial period, and determining the adjusted sampling sequence according to the performance indicator. 6 . The time-interleaved analog-to-digital converter of claim 5 , wherein the performance indicator comprises at least one of an effective number of bits, a signal-to-noise ratio, a spurious-free dynamic range, or a skew error.

7. The time-interleaved analog-to-digital converter of claim 1, wherein each of the plurality of channel circuit systems comprises: a first sampling circuit, configured to selectively conduct according to a corresponding clock signal among a plurality of first clock signals to transmit the input signal; a plurality of second sampling circuits for sampling the input signal transmitted via the first sampling circuit according to a plurality of second clock signals to generate a plurality of first signals; and A plurality of analog-to-digital converter circuits are used to convert the plurality of first signals to generate a portion of digital codes among the plurality of first digital codes. 8 . The time-interleaved analog-to-digital converter of claim 7 , wherein the calibration circuit system is further configured to divide the corresponding clock signal to generate the plurality of second clock signals.

9. The time-interleaved analog-to-digital converter of claim 7, wherein the first sampling circuit comprises: A switch is used to selectively conduct according to the corresponding clock signal to transmit the input signal to the plurality of second sampling circuits.

10. A signal conversion method, comprising: Sampling an input signal through a plurality of channel circuit systems, and generating a plurality of first digital codes according to the sampled input signal; Outputting a second digital code according to the plurality of first digital codes; and A sampling sequence of the input signal by the plurality of channel circuit systems is adjusted according to the second digital code during an initial period, and the plurality of channel circuit systems are controlled to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period.

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