Channel decoding method and related circuit

Abstract

The present invention provides a channel decoding method and related circuits, relating to the field of channel decoding technology. The method includes initializing check nodes and variable nodes of a low-density parity check (LDPC) code; performing multiple iterative updates, and determining the variable nodes based on the iteratively updated variable node information to obtain a decoding result. Embodiments of the present invention can reduce the difficulty of hardware implementation of channel decoding.

Description

Technical Field

[0001] The present invention relates to the technical field of channel decoding, and in particular to a channel decoding method and related circuits. Background Art

[0002] In communication systems, channel coding and decoding are key to improving information transmission efficiency and mitigating interference and transmission errors. In related technologies, the transmission of confidence information during channel decoding relies primarily on the sum-product algorithm. However, this algorithm involves nonlinear functions such as hyperbolic functions, making hardware implementation difficult. Summary of the Invention

[0003] The embodiments of the present invention provide a channel decoding method and related circuits to solve the problem that the hardware implementation of the channel decoding method in the prior art is relatively difficult.

[0004] To solve the above-mentioned technical problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a channel decoding method, the method comprising:

[0006] Initialize the check nodes and variable nodes of the low-density parity check LDPC code;

[0007] Perform multiple iterative update processes, and judge the variable nodes based on the iteratively updated variable node information to obtain a decoding result;

[0008] Among them, the iterative update process is as follows:

[0009] performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0010] Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0011] determining second variable node information based on the first intermediate verification information and the first variable node information;

[0012] Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0013] Second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0014] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0015] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0016] The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

[0017] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0018] In a second aspect, an embodiment of the present invention further provides a node update calculation circuit, wherein the node update calculation circuit is configured to:

[0019] performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0020] Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0021] determining second variable node information based on the first intermediate verification information and the first variable node information;

[0022] Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0023] Second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0024] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0025] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0026] The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

[0027] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0028] Optionally, the node update calculation circuit includes:

[0029] a pre-calculation unit configured to calculate a sum of the first variable and the second variable, and a difference between the first variable and the second variable, and determine a minimum value between an absolute value of the first variable and an absolute value of the second variable;

[0030] a selector connected to the pre-computing unit, and configured to transmit first input data and second input data to the post-computing unit, respectively, wherein the first input data is the absolute value of the sum of the first variable and the second variable, and the second input data is the absolute value of the difference between the first variable and the second variable;

[0031] A post-calculation unit, wherein the post-calculation unit is connected to the selector and the pre-calculation unit respectively, and the post-calculation unit is used to perform a shift operation on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

[0032] Optionally, the post-calculation unit includes:

[0033] a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively;

[0034] a product subunit connected to the shift subunit, the product subunit being configured to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value;

[0035] a first summing subunit, connected to the product subunit, and configured to calculate a first sum of the first product and the second product;

[0036] A second summing subunit, wherein the second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and the second summing subunit is used to calculate the sum of the first sum and the minimum value, wherein the minimum value is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0037] In a third aspect, an embodiment of the present invention further provides a channel decoding circuit, which includes the node update calculation circuit described in the second aspect.

[0038] Optionally, the channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit;

[0039] The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

[0040] Optionally, the decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

[0041] Optionally, one of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

[0042] Optionally, the channel decoding circuit further includes a first memory, a second memory and a third memory, the first memory being connected to the control circuit and the variable node update circuit respectively, and being used to store decoding input information; the second memory being connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit respectively, and being used to store decoding output information; the third memory being connected to the control circuit, the variable node update circuit and the check node update circuit respectively, and being used to store a check matrix.

[0043] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the channel decoding method described in the first aspect.

[0044] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the channel decoding method described in the first aspect are implemented.

[0045] In an embodiment of the present invention, the check nodes and variable nodes of a low-density parity check (LDPC) code are initialized; multiple iterative update processes are performed, and the variable nodes are judged based on the iteratively updated variable node information to obtain a decoding result; wherein, an iterative update process is performed as follows: correction processing is performed based on the first check node information and the first variable node information of the check node to obtain corrected first check node information, and the first variable node information is the initial channel information during the first calculation; the corrected first check node information is transformed using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; second variable node information is determined based on the first intermediate check information and the first variable node information; the second variable node information is transformed using a Jacobian function to obtain second intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; second check node information is determined based on the second intermediate check information and the corrected first check node information. In this way, the correction term in the Jacobian function used for updating the check node or variable node is approximated as an exponential function, which can reduce the difficulty of hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Figure 1 It is a Tanner graph of LDPC decoding in related technology;

[0048] Figure 2 is a flow chart of a channel decoding method provided by an embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of a Jacobian correction term curve provided by an embodiment of the present invention;

[0050] Figure 4 1 is a schematic diagram of an approximation curve of a correction term exponential approximation method provided by an embodiment of the present invention;

[0051] Figure 5 1 is a schematic structural diagram of a node update calculation circuit provided by an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of a reconfigurable chip architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0054] For ease of understanding, some contents involved in the embodiments of the present invention are described below:

[0055] 1. Wireless communication

[0056] Humanity has long pursued efficient, reliable, and secure information communication methods, resulting in the emergence of a wide variety of communication tools and methods that continuously drive the development and progress of human society. With the advent, development, and widespread adoption of wireless communications, people can now easily enjoy the convenient services brought by wireless communications, and the landscape of human production and life has undergone tremendous changes.

[0057] Throughout the development of wireless communications, innovations in baseband algorithms and very large-scale integration (VLSI) technology have made system-on-chip (SoC) applications for wireless communications a reality. This provides chip-level solutions for the baseband physical layer, such as application-specific integrated circuits (ASICs), enabling the miniaturization and convenience of wireless communication devices. Therefore, research on wireless communications technology and its VLSI implementation are of extraordinary value.

[0058] 2. Channel encoding and decoding

[0059] In 1948, C.E. Shannon published his seminal paper, "A Mathematical Theory of Communication," which was published in the history of communications research. He proposed a model for communications systems and argued that balancing system effectiveness and reliability is key to communications systems. Channel coding is a key method for ensuring efficient information transmission and suppressing interference and transmission errors. The paper also proposed the noisy channel coding theorem, initiating research on channel coding and decoding.

[0060] 3. Low Density Parity Check (LDPC) Code

[0061] In 1962, MIT scholar Gallager first proposed LDPC codes. However, due to a lack of hardware and other factors, this achievement received little attention. In the 1990s, French scholar Berrou et al. proposed and constructed Turbo codes, which approached the Shannon limit of the channel and sparked a new wave of research in channel coding. Influenced by the research on Turbo codes, Mackay et al. reintroduced and studied LDPC codes. During this period, Tanner proposed a bipartite graph model (the "Tanner graph") in 1981, which provided an intuitive and efficient tool for subsequent graphical model research on LDPC codes. Since its reintroduction, LDPC codes have been proven to possess excellent performance close to the Shannon limit, becoming a major focus in the field of channel coding.

[0062] LDPC codes (Low Density Parity Check Codes), or LDPC codes, have a very sparse check matrix, one of their most notable characteristics. The proportion of nonzero elements in the check matrix decreases as the code length increases, demonstrating a typical sparse property. Theoretical analysis has demonstrated that this sparse nature of the check matrix is ​​a key factor in the excellent performance of LDPC codes, enabling efficient decoding even with long code lengths.

[0063] 4. LDPC code decoding algorithm

[0064] LDPC code decoding algorithms can be categorized as hard-decision decoding and soft-decision decoding. The former, known as the bit-flipping (BF) decoding algorithm, is relatively low-complexity and easy to implement in hardware, but suffers from poor decoding performance and is only suitable for communication systems with excellent channel quality. The latter, known as the belief propagation (BP) decoding algorithm, based on a posteriori probability calculations, offers performance close to that of maximum likelihood decoding and is widely used. LDPC code iterative decoding algorithms are relatively simple to implement, with complexity linearly proportional to code length, making them suitable for hardware implementation.

[0065] 4.1 Hard Decision Decoding Algorithm

[0066] Assume that the signal transmission information sequence is X={x0,x1,...,x n-1}, the received information sequence after passing through the channel is Y={y0,y1,…,y n-1}. The decoding process is as follows:

[0067] (1) First, determine the channel transmission message and obtain the bit sequence;

[0068] (2) Substitute the result of step (1) into the check equation. If the check equation is satisfied, stop the iteration and the decoding is successful. Otherwise, find the variable node with the largest number of invalid values ​​and flip all its bits uniformly.

[0069] (3) If the verification equation in step (2) does not hold, substitute the flipped judgment result into the verification equation again, calculate its verification result, and repeat step (2) until all the verification equations are valid or the maximum number of iterations is reached.

[0070] The problem with this algorithm is that after a certain iteration, if there are multiple nodes with the largest number of invalid values, they will all flip simultaneously, resulting in a high error rate. Some research has proposed improvements to the BF algorithm, such as adding certain weights to variable nodes, but the performance has been mediocre. Therefore, this algorithm is only suitable for use in situations with relatively good channel conditions, such as fiber optic communications.

[0071] 4.2 Soft Decision Decoding Algorithm

[0072] Soft-decision decoding algorithms for LDPC codes are a research hotspot in communication systems. LDPC code decoding is an iterative algorithm based on probabilistic message passing, and its implementation in the logarithmic domain is often called the Sum Product Algorithm (SPA).

[0073] The mean is 0 and the variance is σ 2 The additive white Gaussian noise channel (AWGN) is analyzed under the condition of binary phase shift keying (BPSK) modulation. The dimension of the check matrix H is M×N. The signal transmission information sequence is X={x0,x1,…,x n-1}, the received information sequence after passing through the channel is Y={y0,y1,…,y n-1}, l max is the maximum number of iterations. Figure 1 In the example, v is a variable node and c is a check node. The relevant concepts are defined as follows: ①M(j) represents the set of check nodes linked to variable node j; ②N(i) represents the set of variable nodes linked to check node i; ③N(i)\j represents N(i) after removing element j; ④M(j)\i represents M(j) after removing element i; ⑤ It is a modulo-2 operation; ⑥ The channel initially receives information Indicates the probability that the transmission variable xj takes the value a∈{1,-1}; ⑦ Check node c i To variable node v j The verification information sent is used Indicates that the variable node v j To check node c i The variable information transmitted is used express.

[0074] The steps of LDPC code soft decision decoding are as follows:

[0075] (1) Initialization: l = 0, initialize the information of each LDPC code check node and variable node, and initialize the channel receiving value

[0076] (2) Iterative message update and delivery:

[0077] Step 1 (check node update): For check node c i Connected variable node v j , j∈N(i), transmit verification information one by one Variable node vj To receive information and the initial value of the channel Based on the correction

[0078] Step 2 (variable node update): For variable node v j Each connected check node c i , i∈M(j), transmit variable information one by one Check node c i To receive information Based on the correction

[0079] (3) Judgment and decoding attempt:

[0080] Each variable node v j Receiving information and the initial value received by the channel Calculated based on And for the variable node v j Make a judgment and get the decoding result. Order decision codeword otherwise The resulting decision codeword is x=[x1,x2,…,x N ], if the decoding check formula is satisfied, stop iterative decoding, declare the decoding successful, and output x as the decoding result, otherwise return to step (2) to continue execution. Until the decoding is successful or the number of iterations reaches l max , terminate the decoding operation.

[0081] In the above steps, when the first iteration is performed, the check node c i For other variable nodes v j of The message is unknown, and the variable message value it transmits is calculated with equal probability, that is, Initialized to 0.

[0082] The update calculations for the iterative decoding of the LDPC decoding algorithm vary depending on the message passing metric. Generally, common sum-product decoding algorithms are categorized into two types: probability-based and log-likelihood ratio-based. Probability-based sum-product decoding algorithms require multipliers to pass information between nodes, making them difficult to implement in hardware. Therefore, we will focus on the log-likelihood ratio-based sum-product decoding algorithm.

[0083] Under the sum-product decoding algorithm of log-likelihood ratio measure, Initialized to 0. The initial probability of the prior information of xj=a is In the decoding iteration process, information is transmitted as log likelihood ratio (LLR). When updating the calculation, addition operation is used instead of multiplication operation of probability measure, and no normalization is required. The common information update formula is as follows:

[0084] f j =L(x j |y j )=log(P(x j =0|y j ) / P(x j =1|y j ))=2y j / σ 2

[0085]

[0086] The value of the log-likelihood ratio measure of the decoded symbol reception information is:

[0087]

[0088] When making a decoding decision, if Q j If ≥0, the received signal judgment is 1, otherwise it is 0.

[0089] 4.3 Sum-Product Algorithm

[0090] When using LLR as information measurement for SPA algorithms, there are a number of implementation methods for updating check nodes to simplify operations and improve efficiency. The following discusses several common LLR-SPA algorithms.

[0091] (1) Sum-product algorithm based on Tanh rule

[0092]

[0093] (2) Sum-product algorithm based on Gallager function

[0094]

[0095] (3) Sum-product algorithm based on Jacobian function

[0096] The aforementioned Tanh rule can also be expressed as follows:

[0097]

[0098] This transformation is also called Jacobian transformation. i , there is d c variable node vj Connected to it, the input variable information is Two auxiliary set definitions are proposed: and

[0099] Using auxiliary collections, you can get variable information from the input Get the output information and We can get:

[0100]

[0101] The update formula of the check node is transformed into:

[0102]

[0103] This algorithm is essentially a forward-backward recursive decoding algorithm for single parity-check codes.

[0104] In general, the sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes hardware implementation difficult.

[0105] 4.4 Minimum Sum Algorithm

[0106] To reduce the complexity of LDPC decoding implementation, Fossorier et al. simplified the cumbersome check node processing in the sum-product algorithm, eliminating such nonlinear functions. This resulted in the classic minimum-sum (MS) algorithm, which performs only addition and comparison operations when calculating check node information updates, facilitating hardware implementation. Understanding these simplified algorithms can be inspired by analyzing the Jacobian algorithm. The MS algorithm simplifies the check node information processing in the sum-product decoding algorithm as follows:

[0107]

[0108] Applying this approximation to the iterative decoding process of LDPC, the check node update information calculation formula is transformed into:

[0109]

[0110] According to the above formula, the MS algorithm can perform decoding operations with only the minimum sign and amplitude of the information transmitted by the node. The method for finding the minimum value can generally use the binary tree method. The MS algorithm verifies that the node information update is only based on the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss. In order to compensate for the performance loss, scholars have proposed corresponding offset measures, namely the Normalized Min Sum (NMS) decoding algorithm and the Offset Min Sum (OMS) algorithm as improvements.

[0111] 4.5 Normalized Minimum Sum Algorithm

[0112] The Normalized Min Sum (NMS) decoding algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value of the transmitted information in the check node information update can be multiplied by a value α less than 1. The formula for the check node information update is:

[0113]

[0114] From an optimization perspective, α should change with different decoding environments and iteration times to obtain the optimal decoding result. However, for ease of implementation, common NMS algorithms usually use α as a constant, and its value can be estimated using the density evolution (DE) method.

[0115] 4.6. Minimum Sum Algorithm with Offset

[0116] The Offset Min Sum (OMS) algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value of the information transmitted during the check node information update can be subtracted by a value β. The formula for updating the check node information is:

[0117]

[0118] From an optimization perspective, β should vary with different decoding environments and iteration times to achieve the best decoding results. However, for ease of implementation, the common OMS algorithm often uses β as a constant. This method improves on the NMS algorithm in that information with a magnitude less than β is set to zero, and its impact on the update of variable nodes in the next iteration is ignored.

[0119] It can be seen that the MS algorithm, OMS algorithm and NMS algorithm only need the channel reception value as input, and do not require channel-related information.

[0120] In existing channel decoding schemes, the transmission of confidence information mainly relies on the sum-product algorithm, the minimum sum algorithm, the normalized minimum sum algorithm, and the minimum sum algorithm with offset.

[0121] The sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes hardware implementation difficult.

[0122] The minimum sum algorithm verifies that node information is updated only by the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss.

[0123] The normalized minimum sum decoding algorithm multiplies the minimum value obtained by the minimum sum algorithm in the transmission information of the check node information update by a value less than 1. However, since a lot of channel information is omitted, there is still room for improvement in performance.

[0124] The minimum sum decoding algorithm with offset is based on the minimum sum algorithm to obtain the minimum value of the transmitted information in the check node information update minus an offset value, but since more channel information is omitted, there is still room for improvement in performance.

[0125] In an embodiment of the present invention, a channel decoding method and related circuits are proposed to solve the problem that the hardware implementation of the channel decoding method in the prior art is relatively difficult.

[0126] See also Figure 2 , Figure 2 This is a flow chart of a channel decoding method provided by an embodiment of the present invention. Figure 2 As shown, the method includes the following steps:

[0127] Step 101: Initialize the check nodes and variable nodes of the low-density parity check (LDPC) code.

[0128] The channel decoding method can be used to implement soft decision decoding of LDPC codes.

[0129] Step 102: Perform multiple iterative update processes, and judge the variable nodes based on the iteratively updated variable node information to obtain a decoding result;

[0130] Among them, the iterative update process is as follows:

[0131] performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0132] Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0133] determining second variable node information based on the first intermediate verification information and the first variable node information;

[0134] Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0135] Second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0136] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0137] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0138] The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

[0139] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0140] It should be noted that the core operation of the sum-product algorithm based on the Jacobian function is to introduce the Jacobian transform into the SPA algorithm of LDPC decoding to obtain the following Jacobian function:

[0141]

[0142] This transformation is also called Jacobian transformation. i , there is d cvariable node v j Connected to it, the input variable information is Two auxiliary set definitions are proposed: and It can be considered as the first variable (i.e., L(U)) obtained by forward recursive processing of the variable node information of the variable node or the check node information of the check node. It can be considered as the second variable (i.e., L(V)) obtained by backward recursive processing of the variable node information of the variable node or the check node information of the check node. sign(L(U))sign(L(V))min{|L(U)|,|L(V)|} is the target subfunction.

[0143] Taking the update of the check node as an example, the input information can be passed from the variable node using the auxiliary set Get the output information and The update formula for the check node is:

[0144]

[0145] To further simplify the process, the following functions can be extracted for analysis:

[0146] f c (x) = log(1 + e -x );

[0147] This function is also called the Jacobian correction term, where x>0. Figure 3 is the correction term f c (x) curve, f c (x) is a monotonically decreasing function with respect to x in the range of x greater than 0. It reaches its maximum value of ln(2)≈0.693147 when x is 0 and 0.006715 when x is 5. It is generally assumed to be 0 when x is greater than 5. The analysis below is also primarily within the range of 0≤x≤5.

[0148] Since the correction term itself is a nonlinear function, by observing the curve characteristics of the Jacobian correction term, this embodiment proposes a nonlinear approximation method, and the approximation formula is as follows:

[0149]

[0150] In the embodiment of the present invention, the Jacobian correction term is approximately: Therefore, the correction term log(1+exp{-|L(U)+L(V)|}) in the Jacobian function can be approximated as: That is the first correction term; the correction term log(1+exp{-|L(U)-L(V)|} in the Jacobian function can be approximated as: This method has high approximation accuracy, and the exponential operation can be completed through hardware shift operations. Figure 4 The curves of the Jacobian correction term using the exponential approximation method and the ideal correction term are drawn. It can be seen that the proposed method has good fitting characteristics.

[0151] This embodiment of the present invention proposes a novel confidence information transmission scheme for channel decoding, which is applicable to channel decoding such as LDPC codes. By approximating the correction term through exponential fitting, this scheme achieves fast, highly accurate, and easily hardware-implemented channel decoding, and designs its hardware circuit. This scheme is also applicable to POLAR and fountain codes, etc.

[0152] In an embodiment of the present invention, the check nodes and variable nodes of a low-density parity check (LDPC) code are initialized; multiple iterative update processes are performed, and the variable nodes are judged based on the iteratively updated variable node information to obtain a decoding result; wherein, an iterative update process is performed as follows: correction processing is performed based on the first check node information and the first variable node information of the check node to obtain corrected first check node information, and the first variable node information is the initial channel information during the first calculation; the corrected first check node information is transformed using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; second variable node information is determined based on the first intermediate check information and the first variable node information; the second variable node information is transformed using a Jacobian function to obtain second intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; second check node information is determined based on the second intermediate check information and the corrected first check node information. In this way, the correction term in the Jacobian function used for updating the check node or variable node is approximated as an exponential function, which can reduce the difficulty of hardware implementation.

[0153] An embodiment of the present invention further provides a node update calculation circuit, wherein the node update calculation circuit is configured to:

[0154] performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0155] Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0156] determining second variable node information based on the first intermediate verification information and the first variable node information;

[0157] Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0158] Second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0159] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0160] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0161] The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

[0162] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0163] Optionally, the node update calculation circuit includes:

[0164] a pre-calculation unit configured to calculate a sum of the first variable and the second variable, and a difference between the first variable and the second variable, and determine a minimum value between an absolute value of the first variable and an absolute value of the second variable;

[0165] a selector connected to the pre-computing unit, and configured to transmit first input data and second input data to the post-computing unit, respectively, wherein the first input data is the absolute value of the sum of the first variable and the second variable, and the second input data is the absolute value of the difference between the first variable and the second variable;

[0166] A post-calculation unit, wherein the post-calculation unit is connected to the selector and the pre-calculation unit respectively, and the post-calculation unit is used to perform a shift operation on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

[0167] Optionally, the post-calculation unit includes:

[0168] a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively;

[0169] a product subunit connected to the shift subunit, the product subunit being configured to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value;

[0170] a first summing subunit, connected to the product subunit, and configured to calculate a first sum of the first product and the second product;

[0171] A second summing subunit, wherein the second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and the second summing subunit is used to calculate the sum of the first sum and the minimum value, wherein the minimum value is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

[0172] As a specific embodiment, Figure 5 As shown, the check node update operation will first perform simultaneous addition and subtraction operations on L(U) and L(V), and at the same time, the smaller value of L(U) and L(V) will be obtained based on the sign of the subtraction operation. The calculated value will be used to read the corresponding parameters from the LUT and perform segment selection, multiplication, and addition operations. The selector will control |L(U)+L(V)| and |L(U)-L(V)| to enter the post-calculation unit independently in sequence. In the post-calculation unit, its core operation is to complete the shift operation of the input data according to the input variable x, and multiply it by the algorithm constant log2. After the calculation is completed, the calculation results of |L(U)+L(V)| and |L(U)-L(V)| are added to complete the calculation of the single check node update information.

[0173] During the entire process of updating the verification node information, such calculation operations need to be repeated iteratively, and finally all node transmission information is fed back to the verification node to complete the entire information aggregation work.

[0174] In an embodiment of the present invention, the node update calculation circuit is configured to: perform correction processing based on first check node information and first variable node information of a check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation; transform the corrected first check node information using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, which is an exponential function term; determine second variable node information based on the first intermediate check information and the first variable node information; transform the second variable node information using a Jacobian function to obtain second intermediate check information, wherein the Jacobian function includes a Jacobian correction term, which is an exponential function term; and determine second check node information based on the second intermediate check information and the corrected first check node information. Thus, during the check node or variable node update process, the correction term of the Jacobian function is approximated by exponential fitting, and this node update calculation circuit can achieve fast, high-precision, and hardware-friendly channel decoding.

[0175] An embodiment of the present invention further provides a channel decoding circuit, which includes the node update calculation circuit described in the embodiment of the present invention.

[0176] Optionally, the channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit;

[0177] The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

[0178] Optionally, the decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

[0179] Optionally, one of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

[0180] Optionally, the channel decoding circuit further includes a first memory, a second memory and a third memory, the first memory being connected to the control circuit and the variable node update circuit respectively, and being used to store decoding input information; the second memory being connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit respectively, and being used to store decoding output information; the third memory being connected to the control circuit, the variable node update circuit and the check node update circuit respectively, and being used to store a check matrix.

[0181] As a specific embodiment, for high bandwidth, low latency channel coding (Channel Code), the embodiment of the present invention proposes a reconfigurable chip architecture suitable for its hardware implementation. The proposed reconfigurable channel decoding architecture is as follows Figure 6 In the present embodiment, the concept of reconfigurable decoding stream is proposed, which divides the data inside the decoder into multiple parallel reconfigurable data streams, including at least a data decoding stream (such as Figure 6 Calculator part in M_UNIT) and control decoding flow (such as Figure 6 (The SHIFTControl part in M_UNIT in the figure), each decoding stream can also be divided into multiple decoding sub-streams, and each decoding sub-stream is used to control the data flow or control process of the corresponding computing unit. For the reconfigurable decoding structure proposed in the embodiment of the present invention, the control sub-stream is mainly used to adjust the shift operation depth, which can be further extended to other reconfigurable parameter configuration information. Furthermore, the embodiment of the present invention proposes a reconfigurable multi-sub-stream mixing mechanism, that is, multiple data decoding sub-streams such as M can form a one-to-one or many-to-one mapping with multiple control decoding sub-streams such as N, which can further reduce the hardware overhead brought by the data sub-stream and improve the decoding speed, wherein the data decoding sub-stream can be implemented by the data sub-stream unit (Calculator), and the control decoding sub-stream can be implemented by the control sub-stream unit (SHIFTControl). Specifically, if Figure 6 As shown, the entire decoder module mainly includes a control circuit Decoder_Controller, a check node update circuit CNU_UNIT, a variable node update circuit VNU_UNIT, a decoding intermediate variable circuit M_UNIT, a first memory RAM_IN for storing decoding input information, a second memory RAM_OUT for storing decoding output information, and a third memory ROM_H for storing a check matrix. The approximation algorithm proposed in the embodiment of the present invention is mainly implemented in the decoding intermediate variable unit M_UNIT. Figure 6As shown, one feasible reconfigurable configuration method is to configure data substream 1 (Calculator_1) by control substream 1 (SHIFTControl1), data substream 2 (Calculator_2) by control substream 2 (SHIFTControl2), and so on, one-to-one matching. Another feasible reconfigurable configuration method is to configure data substreams 1 (Calculator_1), data substreams 2 (Calculator_2) through data substream M (Calculator_M) by control substream 1 (SHIFTControl1), while another group of data substreams M+1 (Calculator_M+1), data substreams M+2 (Calculator_M+2) through data substream M+N (Calculator_M+N) are all configured by control substream 2 (SHIFTControl2). This can reduce the number of control substream configurations required for decoding calculations, and the mapping relationship between data substreams and configuration substreams is controlled by Decoder_controller. Reconfiguration conversion is supported between multiple substreams, that is, the decoding substream used for the data path can also be converted into a control path substream, and vice versa.

[0182] The reconfigurable chip architecture suitable for high-bandwidth, low-latency channel coding and decoding proposed in this embodiment, as well as the mapping relationship between multiple decoding sub-streams and sub-streams and the reconfigurable conversion mechanism in this architecture can further improve the decoding rate.

[0183] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program implements the various processes of the channel decoding method embodiment described above and achieves the same technical effects. To avoid repetition, the details are not described here. The computer-readable storage medium may be, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0184] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0185] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0186] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A channel decoding method, characterized in that: The method comprises: Initialize the check nodes and variable nodes of the low-density parity check LDPC code; Perform multiple iterative update processes, and judge the variable nodes based on the iteratively updated variable node information to obtain a decoding result; Among them, the iterative update process is as follows: performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation; Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; determining second variable node information based on the first intermediate verification information and the first variable node information; Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; Determine second check node information based on the second intermediate check information and the corrected first check node information; Among them, the Jacobian correction term is approximately:

2. The method according to claim 1, characterized in that The Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable; The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

3. The method according to claim 2, characterized in that The Jacobian function is the sum of the Jacobian correction term and the target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and the minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

4. A node update calculation circuit, characterized in that: The node update calculation circuit includes a pre-calculation unit, a selector, and a post-calculation unit, and the node update calculation circuit is used to: performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation; Using a Jacobian function to transform the corrected first check node information to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; determining second variable node information based on the first intermediate verification information and the first variable node information; Transforming the second variable node information using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; Determine second check node information based on the second intermediate check information and the corrected first check node information; Among them, the Jacobian correction term is approximately:

5. The node update calculation circuit according to claim 4, characterized in that: The Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable; The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or The first variable is obtained by performing a forward recursive process on the check node information of the check node, and the second variable is obtained by performing a backward recursive process on the check node information of the check node.

6. The node update calculation circuit according to claim 5, characterized in that: The Jacobian function is the sum of the Jacobian correction term and the target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and the minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

7. The node update calculation circuit according to claim 5 or 6, characterized in that: The pre-calculation unit is used to calculate the sum of the first variable and the second variable, and the difference between the first variable and the second variable, and determine the minimum value between the absolute value of the first variable and the absolute value of the second variable; The selector is connected to the pre-calculation unit, and is used to transmit first input data and second input data to the post-calculation unit respectively, wherein the first input data is the absolute value of the sum of the first variable and the second variable, and the second input data is the absolute value of the difference between the first variable and the second variable; The post-calculation unit is connected to the selector and the pre-calculation unit respectively, and is used to perform shift operations on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

8. The node update calculation circuit according to claim 7, characterized in that: The post-calculation unit comprises: a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively; a product subunit connected to the shift subunit, the product subunit being configured to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value; a first summing subunit, connected to the product subunit, and configured to calculate a first sum of the first product and the second product; A second summing subunit, wherein the second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and the second summing subunit is used to calculate the sum of the first sum and the minimum value, wherein the minimum value is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

9. A channel decoding circuit, characterized in that: The channel decoding circuit includes the node update calculation circuit according to any one of claims 4 to 8.

10. The channel decoding circuit according to claim 9, characterized in that: The channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit; The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

11. The channel decoding circuit according to claim 10, characterized in that: The decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

12. The channel decoding circuit according to claim 11, characterized in that: One of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

13. The channel decoding circuit according to claim 10, characterized in that: The channel decoding circuit also includes a first memory, a second memory and a third memory. The first memory is respectively connected to the control circuit and the variable node update circuit, and the first memory is used to store decoding input information; the second memory is respectively connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit, and the second memory is used to store decoding output information; the third memory is respectively connected to the control circuit, the variable node update circuit and the check node update circuit, and the third memory is used to store the check matrix.

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