Electronic circuit for image sensing

Abstract

The invention relates to an electronic circuit for image sensing. An electronic circuit includes image acquisition units, where each unit has a photodetector coupled to a first node of the unit, and an amplification transistor having a gate connected to the first node, a conductive node coupled to an output of the unit, and a node for controlling a back gate voltage. The amplification transistor is configured such that its threshold voltage varies according to the back gate voltage. The control circuit adjusts a voltage applied to a control node of a back gate voltage of the amplification transistor of one of the cells according to a comparison of a voltage present at the cell output and a reference voltage.

Description

[0001] Priority claim

[0002] This application claims priority from French Patent Application No. 2303104, filed on March 30, 2023, the entire contents of which are incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and, more particularly, to image sensors. Background Art

[0004] In some cases, the electronic circuit of the image sensor includes an image acquisition unit called a pixel (circuit) which includes a photodiode used in reverse. For some types of pixels, obtaining the illumination level received by the pixel requires measuring the voltage across the photodiode at a selected time. During the acquisition period, the voltage across the photodiode varies under the effect of the integration of the current generated by the light in the capacitive element of the diode. The measurement of the voltage across the photodiode is performed after the pixel is reset. This reset causes a voltage with a standard deviation equal to where k is the Boltzmann constant, T is the temperature, and C is the capacitance of the photodiode.

[0005] However, certain new prospective organic photosensitive materials for replacing conventionally used semiconductors do not allow the use of pinned diodes, and therefore different pixel structures must be used.

[0006] There is a renewed interest in image sensors that do not include a transfer gate. These pixel structures are, for example, of the "3T" type with three transistors, or also of the capacitive transimpedance amplifier (CTIA) type. However, these pixel structures are affected by the noise caused by the photodiode reset, which is typically 10 times greater than all other noise sources.

[0007] Need to obtain including noise reduction Affects the electronic circuitry of the pixel.

[0008] There is a need to overcome all or some of the disadvantages of known electronic circuits. Summary of the invention

[0009] One embodiment provides an electronic circuit including image acquisition cells, wherein each cell includes: a photodetector coupled to a first node of the cell; an amplifier transistor having: a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back-gate voltage, the amplifier transistor being configured such that its threshold voltage varies as a function of the back-gate voltage of the amplifier transistor; and at least one control circuit configured to adjust the voltage applied to the back-gate voltage of the amplifier transistor for one of the cells in the cell as a function of the voltage present at the output of the cell and a reference voltage.

[0010] An embodiment provides an electronic circuit control method, the method comprising: adjusting, by means of a control circuit, a voltage at a node of a back-gate voltage of an amplifying transistor of an image acquisition unit for controlling the electronic circuit according to a voltage present at an output of the image acquisition unit and a reference voltage, the amplifying transistor being configured so that its threshold voltage varies according to the back-gate voltage, each unit comprising: a photodetector coupled to a first node of the unit, and the amplifying transistor having a conduction node coupled to the output of the unit and having its gate connected to the first node.

[0011] In one embodiment, the amplifier transistor is formed in a technique using a depleted semiconductor-on-insulator substrate.

[0012] In one embodiment, each cell includes a sampling capacitor and a sampling transistor, and a node for controlling a back gate voltage of an amplifying transistor of each cell is coupled to the sampling capacitor and to the output of the control circuit via the sampling transistor.

[0013] In one embodiment, the sampling capacitor stores a sampled correction value of the output of the control circuit at a node for controlling the back gate voltage of the amplifier transistor.

[0014] In one embodiment, the size of the sampling capacitor is independent of the sensitivity of the image acquisition unit.

[0015] In one embodiment, the control circuit includes a differential amplifier having a first input coupled to the output of the cell and having a second input configured to receive a reference voltage, the output of the differential amplifier delivering an output voltage applied to the sampling transistor, and the output voltage being a function of a difference between a voltage present at the cell output and the reference voltage.

[0016] In one embodiment, the first node of each cell is a sensing node, and each cell includes: a readout transistor connected in series with an amplifier transistor; and a reset transistor configured to couple the sensing node to a reset voltage rail, the amplifier transistor being assembled as a source follower device and having a conduction node coupled to the output of the cell via the readout transistor.

[0017] In an embodiment, each cell is of a capacitive mutual impedance amplifier type and includes: a readout transistor connected in series with an amplifying transistor; a reset transistor configured to couple an integration node common to the readout transistors to the amplifying transistor and to couple the reset transistor to a first node; and an integrating capacitance element coupling the integration node and the first node; the amplifying transistor having a conduction node is coupled to the output of the cell via the readout transistor.

[0018] In one embodiment, at least some of the cells are arranged in at least one column of cells, wherein the outputs of the cells are interconnected by at least one first column conductor coupled to a current source and a first control circuit, the first control circuit being configured to sequentially adjust a voltage applied to a node for controlling a back gate voltage of an amplifying transistor of each column cell.

[0019] In one embodiment, the amplifying transistor is insulated by a trench.

[0020] In one embodiment, the capacitance of the sampling capacitor is greater than the capacitance of the associated first node or capacitive element.

[0021] In one embodiment, the photodetector comprises organic material and / or nanoparticles. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0023] Figure 1A is a block diagram of an example of an electronic image acquisition circuit;

[0024] Figure 1B It is a simplified view of a "3T" type pixel;

[0025] Figure 1C It is shown Figure 1B A timing diagram showing an operation example of a circuit;

[0026] Figure 2 is a simplified diagram of an array of image acquisition units of an electronic circuit according to an embodiment of the present specification;

[0027] Figure 3 Yes Description Figure 2 A timing diagram of the operation of the circuit; and

[0028] Figure 4 is a simplified diagram of an array of image acquisition units of an electronic circuit according to an embodiment of the present specification. DETAILED DESCRIPTION

[0029] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions and material properties.

[0030] For clarity, only the steps and elements necessary for understanding the embodiments are described and illustrated in detail.

[0031] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0032] In the following description, when reference is made to terms defining absolute positions (such as terms "edge", "back", "top", "bottom", "left", "right", etc.) or relative positions (such as terms "above", "below", "upper", "lower", etc.) or terms defining directions (such as terms "horizontal", "vertical", etc.), reference is made to the direction of the drawing unless otherwise specified.

[0033] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "in the order of" mean plus or minus 10%, preferably plus or minus 5%.

[0034] Figure 1A is a block diagram of an example of an electronic image acquisition circuit 100. The circuit comprises an image acquisition array 140 (pixel array) comprising an array network of image acquisition cells or pixels at the intersections of row and column conductors. The acquisition device also comprises a control unit 120 (CTRL) which, among other functions, drives a row decoding circuit 130 (ROW DEC) and a circuit 150 of output amplifiers (OUTPUT-AMP ADC) or analog-to-digital converters (usually one per column), delivering signals OUT representative of the illumination of the different cells. These digital signals are processed by devices (not shown) associated with the electronic image acquisition circuit, which comprise, for example, circuits for storing values ​​assigned to the different cells and for image processing.

[0035] Figure 1B is a simplified view of a "3T" (standing for "3 transistors") type pixel 201. The pixel 201 actually comprises three transistors, a first transistor RST, a second transistor SF and a third transistor RD.

[0036] exist Figure 1BIn the example of , the pixel 201 includes a photodiode PD referenced to ground and coupled to a sensing node SN of the pixel 201. The sum of all capacitive elements connected to the sensing node SN, i.e., the junction capacitance of the photodiode, the capacitance of the connected transistor, and the parasitic capacitance, is represented by reference numeral 230. The photodiode PD is used in reverse, and the capacitive element 230 is discharged by a photocurrent according to the received light intensity after reset. The cathode of the photodiode is coupled to the node SN.

[0037] exist Figure 1B In the example of , the first transistor RST is configured to couple the sensing node SN to a reset voltage rail, eg, powered by a voltage VRST.

[0038] exist Figure 1B In the example of , the second transistor SF is assembled as a source follower device, and its gate is connected to the sensing node SN and its source is coupled to the output 250 of the pixel. The drain of the second transistor SF is connected to a power supply rail of a positive potential VSF, for example. In some cases, the voltages VRST and VSF are equal, but in other examples, these voltages may be different from each other.

[0039] The first transistor RST receives a signal RESET having two states for controlling the reset of the voltage at the sensing node SN on its gate. When the signal RESET is in the first state, the first transistor RST is turned on. In the second state of the signal RESET, the transistor RST is turned off.

[0040] exist Figure 1B In the example of the embodiment shown in FIG. 1 , the third transistor RD is connected in series with the second transistor SF. In an example not shown, the drain of the second transistor SF is coupled to the power supply voltage rail VSF through the third transistor RD. The third transistor RD is controlled by the row select signal READ. The third transistor RD is used as a switch capable of biasing the transistor SF, for example, by a column current source connected to the output 250 of the pixel 201. When it is biased, the transistor SF is a source follower device that forwards the signal of the node SN to the node VX of the output 250 of the pixel 201.

[0041] The switching of the third transistor RD from the on state to the off state induces random noise with a standard deviation of It is forwarded by transistor SF to the output of pixel VX.

[0042] Figure 1C It is shown Figure 1B A timing diagram of an operation example of the circuit is shown below.

[0043] At time t1, signals READ and RESET are set to a high state, for example, to turn on transistors RD and RST. Sense node SN is thus set to voltage VRST, and voltage VX settles at level 302 according to the offset generated by the size of transistor SF and the corresponding column current value.

[0044] At time t2, the signal RESET is set to a low state, for example, to turn off the transistor RST. The capacitance at the sensing node SN is in the order of one femtofarad, which results in broadband noise being generated in the channel of the transistor RST at time t2. It is then sampled at the sense node SN and ends up in baseband, integrated to VX as a random voltage shift relative to the noise-free case 290, as shown by curve 292. The integration phase starts at time t2, which causes a decrease in voltage VX when photogenerated charges (in the case where the charges are electrons), until time t5.

[0045] At time t'3 between times t2 and t5, signal READ switches to, for example, a low state to turn off transistor RD and enable access to other rows of the array.

[0046] At time t4 between time t'3 and t5, signal READ switches to a high level, for example, to turn on transistor RD until time t7. Between time t4 and t5, voltage VX is coupled to pixel output VX, for example. Figure 1C The analog-to-digital converter (not shown) converts Figure 1C , the time scales between time t1 and t'3 and between t4 and t7 are different from the time scale between t'3 and t4, so that the relatively long time between t'3 and t4 can be represented. Therefore, although the slopes of curves 290 and 292 between t3 and t4 appear to be greater than the slopes between time t4 and t5, they are actually similar.

[0047] exist Figure 1C In the example of FIG. 1 , a phase of correlated double sampling occurs between time t6 and time t7 to know the value of VX in the absence of photogenerated charge. To this end, the signal RESET switches to a high level at time t5 until time t6 when it switches back to a low level. Between time t5 and t6, the voltage VX is again stable at the same level as between time t1 and t2, thereby At instant t6 and until instant t7, no signal is read out of the pixel, which corresponds to the first digitization of the voltage level VX. Due to the short integration time, the charge integrated between t6 and t7 can be ignored. Between times t6 and t7, the voltage VX is converted, for example, by the analog-to-digital converter used for the first integration phase during the second digitization, and the comparison between the values ​​obtained during the two digitizations gives access to the amount of photogenerated charge. However, the random noise sampled on the voltage SN when the transistor RST switches from the high state to the low state is statistically different between the first and second digitizations. Thus, given a typically very low value of the capacitance C of the sensing node SN, the standard deviation of the difference becomes And this noise dominates all other noise sources. Therefore, it is desirable to provide a solution to reduce the impact of this noise.

[0048] Figure 2 FIG. 1 is a simplified diagram of an array 140 of image acquisition units 210 of an electronic circuit according to an embodiment of the present disclosure. Figure 2 In the example shown, a single cell 210 is shown for clarity. In one example, at least some of the cells 210 are arranged in at least one cell column, wherein the cells are interconnected by at least one first column conductor COL coupled to a current source 245. In an example not shown, at least some of the cells 210 are arranged in multiple cell columns, and the cells of the same column are interconnected by at least one column conductor, for example insulated from the first column conductor, and coupled to another current source or to the same current source 245.

[0049] exist Figure 2 In the example of FIG. 1 , each unit 210 includes Figure 1B The "3T" type pixel. Figure 1B Different, in Figure 2 In the embodiment, the second transistor SF of each cell further comprises a node 262 of the transistor SF, which is coupled to control a back gate voltage VBB of the second transistor SF. The second transistor SF is configured such that its threshold voltage varies according to the back gate voltage applied to the back gate of the transistor.

[0050] The control node 262 corresponds, for example, to the "back" gate of the second transistor SF. In this case, the gate connected to the sensing node SN is referred to as the "front" gate of the second transistor SF. The back gate and the front gate can act separately on the same channel of the second transistor SF and have different associated transconductances. For example, the back gate can be formed by using a depleted semiconductor substrate, preferably a fully depleted insulator (fully depleted silicon on insulator, FDSOI) technology. When the substrate of the second transistor SF is of FDSOI type, the back gate is, for example, formed under an insulating layer between the channel and the substrate. In this example, the front gate is, for example, formed at the surface above the insulator and the channel.

[0051] In another example, the control node 262 corresponds to an electrode that influences a threshold voltage of a channel formed in the semiconductor material of the substrate of the second transistor SF. For example, the portion of the semiconductor material including the electrode is insulated from the rest of the substrate by, for example, a biased insulating trench.

[0052] exist Figure 2 In the example of FIG. 1 , the source of the second transistor SF of each cell of the same column is coupled to the column conductor COL of the array 140 via the third transistor RD. The third transistor RD is controlled by the row select signal READ, for example delivered on the control line 280 common to all cells 210 of the same row. The transistor RD forwards the voltage information of the node SN on the output 250 of the cell 210 to the column conductor COL of the same column having the value VX.

[0053] exist Figure 2 In the example of , the outputs 250 of the cells of the same column are interconnected, for example by the same column conductor COL.

[0054] exist Figure 2 In the example of , the circuit comprises at least one first control circuit 295 having an input coupled to the output 250 of the cells 210 of the same column and having an output coupled to a control node 262 of the back gate voltage of the second transistor SF of the cells 210 of the same column via another column conductor 285 and via a sampling transistor CORR included in each pixel.

[0055] The control circuit 295 is for example configured to regulate the voltage VBB of the control node applied to the back gate voltage of the second transistor SF so that it tends towards the reference voltage VREF, under control of the voltage VX present at the output 250 of the cell selected on the signal READ.

[0056] exist Figure 2In the example of , the control circuit 295 includes a differential amplifier 290 having a first input 292 coupled to the output 250 of the cell and having a second input 294 configured to receive a reference voltage VREF. For example, the differential amplifier 290 has an output terminal configured to deliver an output voltage VCORR that is a function of a control level applied to the voltage VX so that the voltage VX tends toward the reference voltage VREF. In an example, the voltage VREF is selected to be the average level of the voltage present at the storage nodes SN of the cells 210 of the column, which voltage is subtracted from the gate-source voltage of the second transistor SF.

[0057] The control circuit 295 applies the correction voltage VCORR to the cell selected by the transistor RD via the sampling transistor CORR of the same cell.

[0058] exist Figure 2 In the example of , each cell 210 comprises a storage capacitor 255 referenced to ground and a sampling transistor CORR. A node 262 for the back gate voltage of the second transistor SF of the cell is connected to the storage capacitor 255 and to the output of the differential amplifier 290 via the sampling transistor CORR. One of the main conduction nodes of the sampling transistor CORR of each cell of the same column is coupled to the output of the control circuit 295. In an example, the storage capacitor 255 has a capacitance greater than the capacitance of the sensing node SN, which enables, for example, to reduce charge injection through the transistor CORR during sampling and facilitates maintaining the control voltage VBB without affecting the conversion factor (in volts / electrons) of the pixel.

[0059] The sampling transistor CORR receives at its gate a signal SMP with two control states defining time ranges during which, respectively, 1) the output of the amplifier 290 is coupled to the control node 262 of the back gate voltage of the transistor SF and 2) during this state the sampling transistor CORR is switched off and the voltage VCORR is therefore sampled and stored by the capacitor 255. When the storage capacitive element 255 is connected to the back gate of the transistor CORR, the retention of the voltage VCORR is better, since the gain between the back gate and the source is about 10%, compared to about 90% for the front gate. Thus, the fact of having a significant capacitance limits the voltage drift due to leakage currents, which, moreover, is strongly attenuated by the small gain between the back gate 262 and the source of the transistor SF. The control voltage VBB of the node 262 corresponds to the output voltage VCORR of the amplifier 290, sampled by the sampling transistor CORR and stored by the capacitive element 255.

[0060] The control value observed in the voltage VBB sampled on the capacitor element 255 also samples the noise. Where "C1" is here the value of the sampling capacitor 255. However, the sampling capacitor 255 is larger than the capacitance of the sensing node SN, and the noise generated is lower. In addition, it is known that the main noise to be corrected at the sensing node SN is subjected to about 90% amplification of the front gate, and the sampled voltage VBB stored on the back gate 262, its associated noise, is multiplied by the amplification of the back gate (i.e., about 10%). By comparing these two contributions on the node VX, the contribution to the total noise at the output 250 introduced by the correction on the back gate 262 is much lower than the contribution of the noise to be corrected on the sensing node SN, for example, less than 1 / 10.

[0061] Signal SMP is, for example, common to all cells of the same row and is transmitted, for example, on row line 270 .

[0062] In operation, amplifier 290 delivers voltage VCORR to make the output voltage VX of the selected cell equal to reference voltage VREF.

[0063] Figure 3 It is a graphic Figure 2 A timing diagram of the operation of the circuit.

[0064] At time t1, something like Figure 1C At time t2, signals READ, RESET and SMP are set to a high state, for example, to turn on transistors RD, RST and CORR. The cell 210 of the row to be read from is then selected. The sense node SN is thus set to voltage VRST, and the voltage VX is stabilized at a level depending on the offsets 302, 304 due to the difference in the size of transistor SF between the cells.

[0065] At time t2, the signal RESET is set to a low state, for example, to turn off the transistor RST. At time t2, the noise generated in the channel of the transistor RST It is sampled at the output of the pixel and ultimately integrated as a voltage shift to VX.

[0066] At time t3, amplifier 290, which has been pre-activated, for example, before time t2, delivers at its output a voltage VCORR generated based on the comparison between the initial noise voltage VX and the voltage VREF. The noise is sampled at time t2, which sets the amplifier input and then requires a certain time (until t3) to stabilize. The level of the voltage VCORR thus obtained depends on the voltage on the sensing node SN, which includes offsets and noise caused by size differences of transistor SF. The voltage VCORR will modify the threshold voltage of the second transistor SF of the selected cell, which in turn will modify the output voltage of the cell VX by forming a control loop so that VX tends towards VREF.

[0067] At time t3, the amplifier output has settled at the corrected value, signal SMP is set, for example, to low level to switch off sampling transistor CORR, and amplifier 290 is, for example, deactivated. Corrected sampling capacitive element 255 then takes over by storing the control voltage for the entire duration of the integration that begins after sampling.

[0068] like Figure 3 As shown in the example of , at time t3, a charge injection may occur at the control node 262 and cause a change in the voltage VCORR. There is also another, stronger charge injection, which occurs at the time of the falling edge of the signal RESET. Those skilled in the art will implement precautions to limit these charge injections, and for this purpose, a correlated double sampling (CDS) method may be implemented.

[0069] The output level VX obtained during the settling and correction sampling period is mainly deterministic because it corresponds to the noise The random part of has been corrected.

[0070] At time t'3, similar to Figure 1C At time t'3, the signal READ, for example, switches to a low state to turn off the selection transistor RD.

[0071] Similar to Figure 1C The first integration phase starts at time t2, when charges are photogenerated, which causes a decrease in voltage VX (in the case where the charges are electrons) until it is similar to Figure 1C time t5.

[0072] At time t4 between time t'3 and t5, and similarly Figure 1C At time t4, the signal READ, for example, switches to a high level to turn on the transistor RD until similar to Figure 1C Between time t4 and t5, voltage VX is coupled to the output VX of the pixel, for example, by an analog-to-digital converter ( Figure 3 ) conversion.

[0073] exist Figure 3 , the time scale between time t1 and t'3 and between t4 and t8 is different from the time scale between t'3 and t4, so that the relatively long time between t'3 and t4 can be represented. Therefore, although the slope of the curve of the voltage VX between t'3 and t4 appears to be stronger than the slope of the curve of the voltage VX between time t4 and t5, they are actually similar.

[0074] Such as in Figure 2 and Figure 3The electronic circuit and its operation described in the example of make it possible to correct the random thermal noise inherent to the "3T" component while maintaining a certain speed by aligning the output voltage VX of the cell with the reference voltage VREF. Similar problems can be applied to the "CTIA" component.

[0075] Similar to Figure 1C , the correlated double sampling phase occurs between times t7 and t8 to apply the reset value before the integration phase and take into account Noise correction.

[0076] At time t5, after the signal is converted by means of the analog-to-digital converter, the signals RESET and SMP switch back to high level to turn on the transistors RST and CORR, respectively, and the control circuit 295 performs New operation of noise control.

[0077] In a similar Figure 1C At time t6, the signal RESET switches to a low level, for example, to turn off the transistor RST. Then, a new signal is sampled from the sensing node. Before or at time t6, the amplifier is reactivated, for example, to control the output voltage VX of the cell to a voltage VREF between t2 and t3. At time t7, the output level VX obtained at the end of settling and the corrected sampling are deterministic and due to the removal of The random part is equal to the output level VX obtained at time t3.

[0078] At the end of the stabilization time, at time t7 between times t6 and t8, the signal SMP switches to a low level, for example, to turn off the sampling transistor CORR, which enables the storage of the correction VBB to be applied to the capacitive element 255. Between times t7 and t8, an analog-to-digital conversion (not shown) of the voltage VX is performed, which enables the measurement of VX and the correction of the voltage VX in the absence of photogenerated charges. Noise. The Correlated Double Sampling (CDS) function provides only the result of the integration of the photogenerated charge by the difference between the first transition (between t4 and t5) and the second transition (between t7 and t8), The random part has been corrected.

[0079] By comparing the value of VX obtained between t7 and t8 with the value of VX obtained between t4 and t5 during the switch to the high state of signal READ, i.e. after the integration phase, a more precise amount of accumulated charge can be measured without memory storage. Using the same components (cell 210, amplifier 295, control voltages, etc.) between time t2 and t3 and then between time t6 and t7, the differences involved are identical so that their effects will accurately compensate each other by the correlated double sampling operation.

[0080] The operation phase of the electronic circuit between times t5 and t8 enables elimination of transistor size dispersion between cells (fixed pattern noise), in particular with regard to differences between the transistors CORR and / or the second transistors SF of different cells 210 of different columns.

[0081] In summary, before the first digitization, the control loop can combine the deterministic offset caused by manufacturing differences with the generated first random The sum of the noise is divided by the gain of the loop. Similarly, before the second digitization, the control loop 295 can correct for the sum of the deterministic offset due to manufacturing variations and the generated second random noise.

[0082] The difference between the two digitizations corresponds to the signal due to the photogenerated charges.

[0083] Correlated double sampling (CDS) is able to calculate the difference between two digitizations to obtain the photogenerated charge.

[0084] However, one skilled in the art can implement the measurement of the photogenerated charge without correlated double sampling at the expense of lower accuracy. In fact, correlated double sampling can specifically correct for the offset of the amplifier 290 and the charge injection during sampling at VBB.

[0085] Figure 4 FIG. 1 is a simplified diagram of an array 140 of image acquisition units 410 of an electronic circuit according to an embodiment of the present specification. Figure 4 In the example, only one unit 410 is shown for clarity, but Figure 2 Similar to the x units 210 , the plurality of units 410 are arranged, for example, in columns and rows.

[0086] Figure 4 Unit 410 uses Figure 2 210, except that each of the cells 410 includes a CTIA type pixel rather than a "3T" type transistor.

[0087] exist Figure 4In the example of , the CTIA pixel of the unit 410 includes a photodiode PD referenced to ground and coupled to the input node NCTIA of CTIA. The sum of all capacitances connected to the input node NCTIA, i.e., the junction capacitance of the photodiode, the capacitance of the connected transistor, and the parasitic capacitance, is indicated by reference numeral 230. The photodiode PD is used in reverse, and the generated photocurrent is integrated in the integrating capacitance element Cint coupling the node SN to the node NCTIA. The cathode of the photodiode is coupled to the node NCTIA.

[0088] exist Figure 4 In the example of FIG. 4 , the pixel CTIA of the unit 410 includes a first RST transistor configured to couple the input node NCTIA to the sensing node SN common to the transistors RD and DRV. The transistor RST receives a signal RESET having two control states for resetting the voltage at the input node NCTIA on its gate. When the signal RESET is in a first state, the transistor RST is turned on, which resets the charge of Cint. In a second state of the signal RESET, the transistor RST is turned off, which allows the photogenerated charge to be integrated in Cint.

[0089] exist Figure 4 In the example of FIG. 4 , the gate of transistor DRV assembled as a common source device is connected to the input node NCTIA and its drain is coupled to the integration node NINT.

[0090] exist Figure 4 In the example of , the cell 410 includes a transistor RD connected in series with the drain of the transistor DRV at the common node NCTIA. The drain of the transistor DRV is coupled to the column conductor COL connected to the current source 245 through a third transistor RD. The transistor RD is controlled by the row select signal READ.

[0091] When the cell 410 is biased, i.e., when the signal READ is at a logic 1 state, the potential of the node NCTIA is equal to the gate-source voltage of the transistor DRV biased by the current from the current source 245. When the signal RESET is at a logic 1 state, the voltage across Cint is 0 V. When the signal RESET is at a logic 0 state, the photogenerated charge is integrated in the feedback capacitive element Cint. Thus, the signal is detected at the integration node NINT.

[0092] exist Figure 4 In the example, similar to Figure 2 , the transistor DRV of each cell 410 further includes a node 262 for controlling a back gate voltage VBB of the transistor DRV. Figure 2 As shown, the transistor DRV is configured such that its threshold voltage varies according to the back gate voltage.

[0093] exist Figure 4 In the example of FIG. 1 , the circuit includes at least one first control circuit 295 similar to Figure 2 The control circuit 295 is coupled to the output 250 of the cell 410 of the same column and has an input coupled to the output 250 of the cell 410 of the same column and has an output coupled to the node 262 for controlling the back gate voltage of the transistor DRV of the cell 410 of the same column via another column conductor 285. The correction is applied to a given cell when the corresponding sampling transistor CORR is turned on and the cell row with READ=logic 1 state is selected. Figure 4 The control circuit 295 is similar to Figure 2 Of the control circuit, only the input 292 and the output VCORR are shown. Figure 4 The control circuit 295 is configured to adjust the voltage VBB applied to the node 262 according to the comparison between the voltage VX present at the output 250 of the cell selected by the signal READ and the reference voltage VREF, which voltage VBB is the voltage VCORR to be sampled for controlling the back gate voltage of the transistor DRV.

[0094] Similar to Figure 2 For example, Figure 4 The example of can store the correction of the threshold voltage on the back gate of the common source assembled transistor DRV to correct the offset seen on the rail VX. A person skilled in the art will be able to perform the control of the back gate voltage VBB similar to Figure 2 This is discussed in detail in the example.

[0095] Figure 4 The operation of the example is similar to Figure 3 , except that the voltage VX between the signal integration period t2 and t6 increases rather than decreases.

[0096] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0097] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0098] In particular, Figure 2 In the example of or 4, the capacitance of capacitor 255 can be selected to be, for example, larger than the capacitance of sensing node SN or capacitive element Cint to facilitate independent Figure 2 The sensing node SN or Figure 4 In other words, the size of the sampling capacitor 255 is independent of the sensitivity of the image acquisition unit 210 , 410 .

[0099] In particular, although the discussed embodiments are based on the photogeneration of electrons, persons skilled in the art may use their knowledge to modify the discussed circuits in case of generation of holes at the sensing node SN.

[0100] Furthermore, although the case of photodiodes has been described in the various embodiments, those skilled in the art may replace them with photodetectors including organic materials and / or nanoparticles.

Claims

1. An electronic circuit comprising: Image acquisition units, wherein each image acquisition unit comprises: a photodetector coupled to the first node of the image acquisition unit; and an amplifying transistor having a front gate connected to the first node, a conduction node coupled to the output of the image acquisition unit, and a back gate coupled to a node for controlling a back gate voltage; wherein the amplifying transistor has a threshold voltage that varies according to the back gate voltage of the amplifying transistor; and At least one control circuit is configured to adjust a voltage applied as the back gate voltage to the back gate of the amplification transistor of one of the image acquisition cells in dependence on a difference between a voltage present at the output of the image acquisition cell and a reference voltage. 2 . The electronic circuit according to claim 1 , wherein the amplifying transistor is formed in a technology using a depleted semiconductor-on-insulator substrate.

3. The electronic circuit according to claim 1, wherein each image acquisition unit comprises a sampling capacitor and a sampling transistor, and wherein the back gate of the amplification transistor is coupled to the sampling capacitor and coupled to the output of the at least one control circuit via the sampling transistor.

4. The electronic circuit of claim 3, wherein the sampling capacitor stores a sampled correction value of the output of the at least one control circuit for controlling the back-gate voltage applied to the back-gate of the amplifying transistor. 5 . The electronic circuit according to claim 3 , wherein the size of the sampling capacitor is independent of the sensitivity of the image acquisition unit.

6. The electronic circuit of claim 3 , wherein the at least one control circuit comprises a differential amplifier having a first input coupled to the output of the image acquisition unit and having a second input configured to receive the reference voltage, and wherein the output of the differential amplifier passes the output voltage applied by the sampling transistor to the sampling capacitor.

7. The electronic circuit of claim 3, wherein a capacitance of the sampling capacitor is greater than a capacitance of the first node.

8. The electronic circuit according to claim 1, wherein the first node of each image acquisition unit is a sensing node, and each image acquisition unit comprises: a readout transistor connected in series with the amplifying transistor; as well as a reset transistor configured to couple the sense node to a reset voltage rail; The amplifying transistor is assembled as a source follower device and has the conduction node coupled to the output of the image acquisition unit via the readout transistor.

9. The electronic circuit according to claim 1, wherein each image acquisition unit is a capacitive transimpedance amplifier type unit, comprising: a readout transistor connected in series with the amplifying transistor; a reset transistor configured to couple an integration node common to the readout transistors to the amplification transistor and to couple the reset transistor to the first node; as well as an integral capacitor element coupling the integral node and the first node; The amplification transistor having the conduction node is coupled to an output of the image acquisition unit via the readout transistor.

10. The electronic circuit of claim 9 , wherein each image acquisition unit comprises a sampling capacitor and a sampling transistor, and wherein the back-gate voltage applied to the back-gate of the amplification transistor is coupled to the sampling capacitor and coupled to the output of the at least one control circuit via the sampling transistor, and wherein the sampling capacitor has a capacitance greater than the capacitance of the integrating capacitive element.

11. The electronic circuit according to claim 1, wherein at least some of the image acquisition cells are arranged in at least one cell column, wherein outputs of the at least some of the image acquisition cells are interconnected by at least one first column conductor coupled to a current source and the at least one control circuit, the at least one first column conductor being configured to sequentially adjust the voltage applied to the back gate of the amplifying transistor to the back gate voltage of each of the at least some of the image acquisition cells in the at least one cell column.

12. The electronic circuit of claim 1, wherein the amplifier transistor is insulated by a trench.

13. The electronic circuit of claim 1, wherein the photodetector comprises an organic material.

14. The electronic circuit of claim 1, wherein the photodetector comprises nanoparticles.

15. An electronic circuit comprising: Image acquisition units, wherein each image acquisition unit comprises: a photodetector coupled to the first node; and a source follower transistor having a front gate coupled to the first node, a conduction node coupled to the output of the image acquisition unit, and a back gate; and A control circuit is configured to compare the voltage at the output of the image acquisition unit with a reference voltage to generate a back-gate voltage applied to the back-gate of the source follower transistor.

16. The electronic circuit of claim 15, wherein each image acquisition unit comprises a sampling capacitor coupled to the back gate and a sampling transistor coupled between the back gate and the output of the control circuit, and wherein the back gate voltage is stored by the sampling capacitor in response to actuation of the sampling transistor.

17. The electronic circuit of claim 15, wherein the control circuit comprises a differential amplifier having a first input coupled to the output of the image acquisition unit and having a second input configured to receive the reference voltage, the back-gate voltage being generated by a difference between the output of the image acquisition unit and the reference voltage.

18. An electronic circuit comprising: Image acquisition units, wherein each image acquisition unit comprises: a photodetector coupled to the first node; and a common-source transistor having a front gate coupled to the first node, a conduction node coupled to the output of the image acquisition unit, and a back gate; and A control circuit is configured to compare the voltage at the output of the image acquisition unit with a reference voltage to generate a back-gate voltage applied to the back-gate of the common-source transistor.

19. The electronic circuit of claim 18, wherein each image acquisition unit comprises a sampling capacitor coupled to the back gate and a sampling transistor coupled between the back gate and the output of the control circuit, and wherein the back gate voltage is stored by the sampling capacitor in response to actuation of the sampling transistor.

20. The electronic circuit of claim 18, wherein the control circuit comprises a differential amplifier having a first input coupled to the output of the image acquisition unit and having a second input configured to receive the reference voltage, the back-gate voltage being generated by a difference between the output of the image acquisition unit and the reference voltage.

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