Large dynamic range pixel structure, image sensor and electronic device with adaptive reset

Abstract

This invention discloses an adaptive reset large dynamic range pixel structure, an image sensor, and an electronic device. The pixel unit of the large dynamic range pixel structure achieves adaptive control of pixel reset under different light intensity scenarios through column feedback, realizing dynamic range extension in low-light environments. It includes a photodiode, a transmission transistor, a charge storage capacitor, a reset transistor, a first switch, a first capacitor, a first source follower, a second switch, a row selector, a second source follower, a third switch, a latch, a first AND gate, and a second AND gate. A readout selection circuit controls the pixel to sequentially read the reset voltage and signal voltage. A feedback logic circuit receives the comparison result of the previous frame from the column readout circuit and controls whether the pixel resets. In low-light environments, the pixel does not reset and continues exposure for the next frame. Low-light signal quantization is achieved through frame-by-frame accumulation, thereby expanding the pixel's low-light detection capability and improving the dynamic range in low-light environments.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an adaptive reset large dynamic range pixel structure, image sensor, and electronic device suitable for low-light environments. Background Art

[0002] Dynamic range (DR) is one of the key performance parameters of a CIS (CMOS Image Sensor), representing the range of maximum and minimum light intensity signals that the CIS can simultaneously detect within the same frame. A higher DR results in clearer image contrast and detail. The low-light detection capability of a CIS is closely related to the pixel's conversion gain and the quantization accuracy of the ADC (Analog-to-Digital Converter). In low-light environments, the light signal is very small, requiring a high conversion gain to convert the light signal into an electrical signal, which is then quantized by a high-precision ADC to obtain effective light information. The pixel's conversion gain is determined by the capacitance of the charge-to-voltage conversion node, and due to parasitic effects, it is difficult to further improve. The quantization accuracy of the ADC is determined by the number of bits in the counter; improving the ADC's accuracy leads to increased power consumption and area. Therefore, improving the low-light detection capability of pixels presents a significant challenge. Summary of the Invention

[0003] The purpose of this invention is to address the problems of weak low-light detection capability and low dynamic range in low-light environments of traditional pixels. It proposes an adaptive reset large dynamic range pixel structure, an image sensor, and an electronic device. After each frame of exposure, the adaptive reset large dynamic range pixel structure determines whether a pixel should be reset based on the comparison results of a column-level circuit. When the light intensity is low, it does not reset and continues exposure based on the previous frame, thereby achieving the quantization of low-light signals and expanding the dynamic range in low-light environments.

[0004] In a first aspect, the present invention provides an adaptive reset large dynamic range pixel structure, wherein the pixel unit realizes adaptive control of pixel reset under different light intensity scenarios through column feedback, thereby realizing dynamic range expansion in low light environment. The structure includes a photodiode, a transmission tube, a charge storage capacitor, a reset tube, a first switch, a first capacitor, a first source follower, a second switch, a row selector, a second source follower, a third switch, a latch, a first AND gate, and a second AND gate.

[0005] In this configuration, the positive terminal of the photodiode is connected to the source of the transmission transistor, the negative terminal of the photodiode is grounded, the gate of the transmission transistor is connected to the transmission control signal, the drain of the transmission transistor is connected to one end of the charge storage capacitor, the source of the first switch, and the source of the reset transistor, the other end of the charge storage capacitor is grounded, the drain of the first switch is connected to one end of the first capacitor and the gate of the first source follower, the gate of the first switch is connected to the output of the first AND gate, the other end of the first capacitor is grounded, the drain of the first source follower is connected to the power supply voltage, the source of the first source follower is connected to the source of the second switch, the drain of the second switch is connected to the source of the horizontal selection transistor, the gate of the second switch is connected to the second switch signal, and the horizontal selection transistor... The gate of the first switch is connected to the row selection signal, the drain of the row selection transistor is connected to the column bus, the gate of the second source follower is connected to the source of the first switch, the drain of the second source follower is connected to the power supply voltage, the source of the second source follower is connected to the source of the third switch, the drain of the third switch is connected to the source of the row selection transistor, the gate of the third switch is connected to the third switch signal, the input of the latch is the column feedback signal, the clock signal of the latch is the latch signal, the output of the latch is connected to one input of the first AND gate and the second AND gate, the other input of the first AND gate is the first switch signal, the other input of the second AND gate is the reset control signal, the output of the second AND gate is connected to the gate of the reset transistor, and the drain of the reset transistor is connected to the power supply voltage.

[0006] In this process, after each frame exposure ends, the pixel unit determines whether to reset the pixel based on the comparison result of the column-level circuit. If it is not reset, it continues to expose based on the previous frame, thereby realizing the quantization of the low-light signal and expanding the dynamic range of the low-light environment.

[0007] Specifically, the determination of whether a pixel should be reset based on the comparison result of the column-level circuit is made by checking whether the difference between the read reset voltage and the signal voltage is less than the reference voltage. If the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low and the pixel is not reset. If the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high and the pixel is reset.

[0008] The read reset voltage and signal voltage are subtracted by correlated double sampling, and the result of the subtraction is compared with the reference voltage to generate a column feedback signal.

[0009] The column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset transistor is reset.

[0010] The process by which the pixel unit performs signal processing and outputs a reset voltage and a signal voltage includes:

[0011] The first capacitor stores the pixel's reset voltage, and the sampled voltage is read out through the first source follower. The charge storage capacitor stores the pixel's signal voltage, and the signal voltage is read out through the second source follower. When the row selector is turned on, the second and third switch signals control the reset voltage and signal voltage to be read out to the column bus in sequence.

[0012] The output of the pixel unit is connected to the column readout unit, which includes a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a ramp generator, a second comparator, and a counter.

[0013] In this circuit, the column bus Vpix is ​​connected to one end of the fourth and fifth switches. The other end of the fourth switch is simultaneously connected to one end of the second capacitor and the first input terminal of the CDS circuit. The other end of the fifth switch is simultaneously connected to one end of the third capacitor and the second input terminal of the CDS circuit. The fourth switch is controlled by the second switch signal, and the fifth switch is controlled by the third switch signal S3. The other ends of the second and third capacitors are grounded. The output terminal of the CDS circuit is simultaneously connected to the positive input terminal of the first comparator and the positive input terminal of the second comparator. The negative input terminal of the first comparator is connected to the reference voltage Vref. The output of the first comparator is the column feedback signal FS. The negative input terminal of the second comparator is connected to the output Vramp of the ramp generator. The output of the second comparator is connected to the counter.

[0014] The signal processing procedure for the pixel unit includes:

[0015] When the difference between the reset voltage and signal voltage output by the previous frame pixel, calculated by the CDS circuit, exceeds the set threshold Vref, the column feedback signal FS output by the first comparator goes high. During the high level of the clock signal LATCH, the column feedback signal FS is latched in a latch and holds the latched result until the next high level arrives. When the reset signal RST goes high, the second AND gate outputs a high level, the reset transistor in the pixel is turned on, and the transmission transistor is also turned on to reset the photodiode and charge storage capacitor. After the reset is completed, the transmission transistor is turned off, the reset signal RST is pulled low, and then the exposure stage begins. After the exposure is completed, the signal transfer stage begins. First, the reset signal RST and the first switch signal S1 are pulled high, and both the first AND gate and the second AND gate output a high level, controlling the reset transistor and the first switch to turn on, resetting the charge storage capacitor and the first capacitor. After the reset, the reset signal RST and the first switch signal S1 are pulled low. The reset voltage is stored in the first capacitor. Then, the transmission signal TX is pulled high, the transmission transistor is turned on, and the charge accumulated in the photodiode during exposure is transferred to the charge storage capacitor. After the transfer is complete, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor, then the readout stage begins. During readout, the row selection signal SEL is pulled high, the row selection transistor is turned on, and the pixel remains connected to the column bus Vpix. First, the second switch signal S2 is pulled high, and both the second and fourth switches are turned on, reading the reset voltage stored in the first capacitor into the second capacitor. Then, the third switch signal S3 is pulled high, and both the third and fifth switches are turned on, reading the signal voltage stored in the charge storage capacitor into the third capacitor. Next, the CDS circuit in the column readout unit calculates the difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor. The result of this difference is compared with a set threshold Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame. Simultaneously, the result of this difference is compared with the ramp signal Vramp generated by the ramp generator through a second comparator and quantized by a counter.

[0016] When the difference between the reset voltage and signal voltage output by the previous frame's pixel, calculated by the CDS circuit, is less than the set threshold Vref, the column feedback signal FS is low. During the high-level period of the clock signal LATCH, the column feedback signal FS is latched in the latch, and the latch output is low. When the reset signal RST is pulled high, the output of the second AND gate remains low, the charge storage capacitor is not reset, and the signal voltage of the previous frame is still stored, continuing exposure. After exposure, the reset signal RST and the first switch signal S1 are pulled high. Since the latch output is low, the outputs of the first AND gate and the second AND gate remain low, and the reset transistor and the first... The switch will not be turned on, the reset voltage stored in the first capacitor will not be refreshed, and then the transmission signal TX will be pulled high. The charge accumulated by the photodiode during exposure will continue to be transferred to the charge storage capacitor. After the transfer is completed, the readout stage begins. The signal readout process is as follows: first read the reset voltage, then read the signal voltage. After being stored in the second and third capacitors respectively, the difference is calculated by the CDS circuit. The result of the difference is compared with the reference voltage Vref by the first comparator, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result of the difference is compared with the ramp signal Vramp generated by the ramp generator by the second comparator and quantized by the counter.

[0017] A second aspect of the present invention provides an image sensor including the adaptively reset large dynamic range pixel structure.

[0018] A third aspect of the present invention provides an electronic device including the aforementioned image sensor.

[0019] In the pixel structure of this invention, the first capacitor stores the pixel's reset voltage, and the sampled voltage is read out through the first source follower. The charge storage capacitor stores the pixel's signal voltage, and the signal voltage is read out through the second source follower. When the row select transistor is turned on, the second and third switch signals control the reset voltage and signal voltage to be read out sequentially to the column bus. The read-out reset voltage and signal voltage are subtracted using Correlated Double Sample (CDS). The result of the subtraction is compared with a reference voltage to generate a column feedback signal. The column feedback signal is transmitted to the second AND gate under the control of the latch signal. The output of the second AND gate controls whether the reset transistor is reset. If the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low and the pixel is not reset. If the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high and the pixel is reset. The column feedback enables adaptive control of pixel reset under different light intensity scenarios, achieving dynamic range expansion in low-light environments. Attached Figure Description

[0020] Figure 1This is a circuit diagram of a pixel unit in an embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram of the column readout unit in an embodiment of the present invention.

[0022] Figure 3 This is a timing diagram of a pixel unit in an embodiment of the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0024] A first aspect of the present invention provides an adaptive reset large dynamic range pixel junction, including a conventional 4T pixel circuit, a readout selection circuit 201, and a feedback logic circuit 301. The readout selection circuit 201 controls the pixel to sequentially read out a reset voltage and a signal voltage. The feedback logic circuit 301 receives the comparison result of the previous frame from the column readout circuit and controls whether the pixel resets. In low-light environments, the pixel does not reset and begins exposure of the next frame. By accumulating frame by frame, low-light intensity signal quantization is achieved, thereby expanding the pixel's low-light detection capability and improving the dynamic range in low-light environments.

[0025] The adaptive reset large dynamic range pixel structure provided in the embodiments of the present invention refers to... Figure 1 As shown, the pixel structure includes a photodiode 101, a transmission transistor 102, a charge storage capacitor 103, a reset transistor 104, a row select transistor 105, a readout selection circuit 201, and a feedback logic circuit 301. The readout selection circuit 201 includes a first switch 2011, a first capacitor 2012, a first source follower 2013, a second switch 2014, a second source follower 2015, and a third switch 2016. The feedback logic circuit 301 includes a latch 3011, a first AND gate 3012, and a second AND gate 3013.

[0026] Reference Figure 1As shown, the positive terminal of the photodiode (PD) 101 is connected to the source of the transmission transistor 102, the negative terminal of the photodiode 101 is grounded, the gate of the transmission transistor 102 is connected to the transmission control signal TX, the drain of the transmission transistor 102 is simultaneously connected to one end of the charge storage capacitor (FD) 103, the source of the first switch 2011, and the source of the reset transistor 104, the other end of the charge storage capacitor 103 is grounded, and the drain of the first switch 2011 is simultaneously connected to the first capacitor (C1) 2012. One end of the first capacitor 2012 is connected to the gate of the first source follower 2013. The gate of the first switch 2011 is connected to the output of the first AND gate 3012. The other end of the first capacitor 2012 is grounded. The drain of the first source follower 2013 is connected to the power supply voltage. The source of the first source follower 2013 is connected to the source of the second switch 2014. The drain of the second switch 2014 is connected to the source of the horizontal select transistor 105. The gate of the second switch 2014 is connected to the second switch signal S2. The horizontal select transistor 105... The gate of transistor 5 is connected to the row selection signal SEL. The drain of row selection transistor 105 is connected to the column bus Vpix. The gate of the second source follower 2015 is connected to the source of the first switch 2011. The drain of the second source follower 2015 is connected to the power supply voltage. The source of the second source follower 2015 is connected to the source of the third switch 2016. The drain of the third switch 2016 is connected to the source of row selection transistor 105. The gate of the third switch 2016 is connected to the third switch signal S3. Latch 3011 The input is the column feedback signal FS, the clock signal of latch 3011 is the latch signal LATCH, the output of latch 3011 is connected to one input of the first AND gate 3012 and the second AND gate 3013, the other input of the first AND gate 3012 is the first switch signal S1, the other input of the second AND gate 3013 is the reset control signal RST, the output of the second AND gate 3013 is connected to the gate of the reset transistor 104, and the drain of the reset transistor 104 is connected to the power supply voltage.

[0027] Figure 2 This is a circuit diagram of the column readout unit in an embodiment of the present invention. (Refer to...) Figure 2 As shown, the column readout unit includes a fourth switch 401, a fifth switch 402, a second capacitor 403, a third capacitor 404, a CDS circuit 405, a first comparator 406, a ramp generator 407, a second comparator 408, and a counter 409.

[0028] Reference Figure 2As shown, the column bus Vpix is ​​connected to one end of the fourth switch 401 and the fifth switch 402. The other end of the fourth switch 401 is connected to one end of the second capacitor 403 and the first input terminal of the CDS circuit 405. The other end of the fifth switch 402 is connected to one end of the third capacitor 404 and the second input terminal of the CDS circuit 405. The fourth switch 401 is controlled by the second switch signal S2, and the fifth switch 402 is controlled by the third switch signal S3. The other ends of the second capacitor 403 and the third capacitor 404 are grounded. The output terminal of the CDS circuit 405 is connected to the positive input terminal of the first comparator 406 and the positive input terminal of the second comparator 408. The negative input terminal of the first comparator 406 is connected to the reference voltage Vref. The output of the first comparator 406 is the column feedback signal FS. The negative input terminal of the second comparator 408 is connected to the output Vramp of the ramp generator 407. The output of the second comparator 408 is connected to the counter 409.

[0029] The CDS circuit 405, the first comparator 406, the second comparator 408, the ramp generator 407, and the counter 409 are all well-known technologies in the field and will not be described in detail here.

[0030] Figure 3 This is a timing diagram of a pixel unit in an embodiment of the present invention.

[0031] See Figure 3As shown, when the difference between the reset voltage and signal voltage output by the previous frame pixel, after passing through the CDS circuit 405, is greater than the set threshold Vref, the column feedback signal FS output by the first comparator 406 is high. During the high level of the clock signal LATCH, the column feedback signal FS is latched in the latch 3011 and remains latched until the next high level arrives. When the reset signal RST is pulled high, the second AND gate 3013 outputs a high level, the pixel reset transistor 104 is turned on, and the transmission transistor 102 is turned on, triggering the photodiode 1. The process begins with resetting the charge storage capacitor 103. After resetting, the transmission transistor 102 is turned off, and the reset signal RST is pulled low, then the exposure stage begins. After exposure, the signal transfer stage begins. First, the reset signal RST and the first switch signal S1 are pulled high, and both the first AND gate 3012 and the second AND gate 3013 output high levels, controlling the reset transistor 104 and the first switch 2011 to conduct, resetting the charge storage capacitor 103 and the first capacitor 2012. After resetting, the reset signal RST and the first switch signal S1 are pulled low, and the reset voltage is stored in the first capacitor 2012. Then, the transmission signal TX is pulled high, the transmission transistor 102 is turned on, and the charge accumulated by the photodiode 101 during exposure is transferred to the charge storage capacitor 103. After the transfer is completed, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor 103, then the readout stage begins. During readout, the row selection signal SEL is pulled high, the row selection transistor 105 is turned on, and the pixel remains connected to the column bus Vpix. First, the second switch signal S2 is pulled high, turning on both the second switch 2014 and the fourth switch 401, reading the reset voltage stored in the first capacitor 2012 into the second capacitor 403. Then, the third switch signal S3 is pulled high, turning on both the third switch 2016 and the fifth switch 402, reading the signal voltage stored in the charge storage capacitor 103 into the third capacitor 404. Next, the CDS circuit 405 in the readout unit calculates the difference between the reset voltage stored in the second capacitor 403 and the signal voltage stored in the third capacitor 404. The difference is compared with a set threshold Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame. Simultaneously, the difference result is compared with the ramp signal Vramp generated by the ramp generator 407 via the second comparator 408 and quantized by the counter 409.

[0032] When the difference between the reset voltage and signal voltage output by the previous frame pixel, calculated by the CDS circuit 405, is less than the set threshold Vref, the column feedback signal FS is low. During the high level of the clock signal LATCH, the column feedback signal FS is latched in latch 3011, and the output of latch 3011 is low. When the reset signal RST is pulled high, the output of the second AND gate 3013 remains low, the charge storage capacitor 103 is not reset, and the signal voltage of the previous frame is still stored, and exposure continues. After exposure, the reset signal RST and the first switch signal S1 are pulled high, but because the output of latch 3011 is low, the first AND gate 3012... The output of the second AND gate 3013 remains low, so the reset transistor 104 and the first switch 2011 will not conduct, and the reset voltage stored in the first capacitor 2012 will not be refreshed. Then, the transmission signal TX is pulled high, and the charge accumulated in the photodiode 101 during exposure continues to transfer to the charge storage capacitor 103. After the transfer is complete, the readout stage begins. The readout process is as follows: first read the reset voltage, then read the signal voltage. After being stored by the second capacitor 403 and the third capacitor 404 respectively, the difference is calculated by the CDS circuit 405. The result of the difference is compared with the reference voltage Vref by the first comparator 406, and the comparison result FS is fed back to the pixel to control the reset of the next frame. Simultaneously, the result of the difference is compared with the ramp signal Vramp generated by the ramp generator 407 by the second comparator 408 and quantized by the counter 409.

[0033] The adaptive reset large dynamic range pixel structure proposed in this embodiment of the invention determines whether a pixel should be reset after each frame exposure by comparing the results of the column readout circuit. When the light intensity is low, the pixel is not reset and exposure continues on the basis of the previous frame, thereby realizing the quantization of low light signals and effectively expanding the dynamic range of low light environments.

[0034] A second aspect of the present invention provides an image sensor including the adaptive reset large dynamic range pixel structure described in the first aspect of the present invention.

[0035] A third aspect of the present invention provides an electronic device including the image sensor described in the second aspect of the present invention.

[0036] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0037] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0038] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A large dynamic range pixel structure with adaptive reset, characterized in that, Its pixel unit achieves adaptive control of pixel reset under different light intensity scenarios through column feedback, realizing dynamic range expansion in low-light environments. It includes a photodiode, a transmission transistor, a charge storage capacitor, a reset transistor, a first switch, a first capacitor, a first source follower, a second switch, a row select transistor, a second source follower, a third switch, a latch, a first AND gate, and a second AND gate. The positive terminal of the photodiode is connected to the source of the transmission transistor, the negative terminal of the photodiode is grounded, the gate of the transmission transistor is connected to the transmission control signal, and the drain of the transmission transistor is simultaneously connected to one end of the charge storage capacitor and the first source follower. The source of the switch and the source of the reset transistor are connected. The other end of the charge storage capacitor is grounded. The drain of the first switch is connected to one end of the first capacitor and the gate of the first source follower. The gate of the first switch is connected to the output of the first AND gate. The other end of the first capacitor is grounded. The drain of the first source follower is connected to the power supply voltage. The source of the first source follower is connected to the source of the second switch. The drain of the second switch is connected to the source of the row select transistor. The gate of the second switch is connected to the second switch signal. The gate of the row select transistor is connected to the row select signal. The drain of the row select transistor is connected to the column bus. The gate of the second source follower and... The source of the first switch is connected to the power supply voltage. The drain of the second source follower is connected to the power supply voltage. The source of the second source follower is connected to the source of the third switch. The drain of the third switch is connected to the source of the row select transistor. The gate of the third switch is connected to the third switch signal. The input of the latch is the column feedback signal. The clock signal of the latch is the latch signal. The output of the latch is connected to one input of the first AND gate and the second AND gate. The other input of the first AND gate is the first switch signal. The other input of the second AND gate is the reset control signal. The output of the second AND gate is connected to the gate of the reset transistor. The drain of the reset transistor is connected to the power supply voltage. The power supply voltage is applied to the pixel unit. After each frame of exposure, the pixel unit determines whether to reset based on the comparison result of the column-level circuit. This is determined by whether the difference between the read-out reset voltage and the signal voltage is less than the reference voltage. If the difference between the reset voltage and the signal voltage is less than the reference voltage, the column feedback signal is low, the pixel does not reset, and exposure continues based on the previous frame, thereby realizing the quantization of the low-light signal and expanding the dynamic range of the low-light environment. If the difference between the reset voltage and the signal voltage is greater than the reference voltage, the column feedback signal is high, and the pixel resets.

2. The adaptive reset large dynamic range pixel structure according to claim 1, characterized in that, The read reset voltage and signal voltage are subtracted by correlated double sampling, and the result of the subtraction is compared with the reference voltage to generate a column feedback signal.

3. The adaptive reset large dynamic range pixel structure according to claim 2, characterized in that, The column feedback signal is transmitted to the second AND gate under the control of the latch signal, and the output of the second AND gate controls whether the reset transistor is reset.

4. The adaptive reset large dynamic range pixel structure according to claim 3, characterized in that, The process by which the pixel unit performs signal processing and outputs a reset voltage and a signal voltage includes: The first capacitor stores the pixel's reset voltage, and the sampled voltage is read out through the first source follower. The charge storage capacitor stores the pixel's signal voltage, and the signal voltage is read out through the second source follower. When the row selector is turned on, the second and third switch signals control the reset voltage and signal voltage to be read out to the column bus in sequence.

5. The adaptive reset large dynamic range pixel structure according to claim 1, characterized in that, The output of the pixel unit is connected to the column readout unit, which includes a fourth switch, a fifth switch, a second capacitor, a third capacitor, a CDS circuit, a first comparator, a ramp generator, a second comparator, and a counter. In this circuit, the column bus Vpix is ​​connected to one end of the fourth and fifth switches. The other end of the fourth switch is simultaneously connected to one end of the second capacitor and the first input terminal of the CDS circuit. The other end of the fifth switch is simultaneously connected to one end of the third capacitor and the second input terminal of the CDS circuit. The fourth switch is controlled by the second switch signal, and the fifth switch is controlled by the third switch signal S3. The other ends of the second and third capacitors are grounded. The output terminal of the CDS circuit is simultaneously connected to the positive input terminal of the first comparator and the positive input terminal of the second comparator. The negative input terminal of the first comparator is connected to the reference voltage Vref. The output of the first comparator is the column feedback signal FS. The negative input terminal of the second comparator is connected to the output Vramp of the ramp generator. The output of the second comparator is connected to the counter.

6. The adaptive reset large dynamic range pixel structure according to claim 5, characterized in that, The signal processing procedure for the pixel unit includes: When the difference between the reset voltage and signal voltage output by the previous pixel (after passing through the CDS circuit) is greater than the set threshold Vref, the column feedback signal FS output by the first comparator is high. During the high level of the clock signal LATCH, the column feedback signal FS is latched in a latch and remains latched until the next high level arrives. When the reset signal RST is pulled high, the second AND gate outputs a high level, the reset transistor in the pixel is turned on, and the transmission transistor is turned on simultaneously to reset the photodiode and charge storage capacitor. After the reset is completed, the transmission transistor is turned off, the reset signal RST is pulled low, and then the exposure stage begins. After the exposure is completed, the signal transfer stage begins. First, the reset signal RST and the first switch signal S1 are pulled high, and both the first AND gate and the second AND gate output a high level, controlling the reset transistor and the first switch to turn on, resetting the charge storage capacitor and the first capacitor. After the reset, the reset signal RST and the first switch signal S1 are pulled low, and the reset voltage is stored in the first capacitor. Then, the transmission signal TX is pulled high, and the transmission... When the photodiode is turned on, the charge accumulated in the photodiode during exposure is transferred to the charge storage capacitor. After the transfer is complete, the transmission signal TX is pulled low, and the signal voltage is stored in the charge storage capacitor, then the readout stage begins. During readout, the row selection signal SEL is pulled high, the row selection transistor is turned on, and the pixel remains connected to the column bus Vpix. First, the second switch signal S2 is pulled high, and both the second and fourth switches are turned on, reading the reset voltage stored in the first capacitor into the second capacitor. Then, the third switch signal S3 is pulled high, and both the third and fifth switches are turned on, reading the signal voltage stored in the charge storage capacitor into the third capacitor. Then, the CDS circuit in the column readout unit calculates the difference between the reset voltage stored in the second capacitor and the signal voltage stored in the third capacitor. The result of the difference is compared with the set threshold Vref, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result of the difference is compared with the ramp signal Vramp generated by the ramp generator through the second comparator and quantized by the counter. When the difference between the reset voltage and signal voltage output by the previous frame's pixel, calculated by the CDS circuit, is less than the set threshold Vref, the column feedback signal FS is low. During the high-level period of the clock signal LATCH, the column feedback signal FS is latched in the latch, and the latch output is low. When the reset signal RST is pulled high, the output of the second AND gate remains low, the charge storage capacitor is not reset, and the signal voltage of the previous frame is still stored, continuing exposure. After exposure, the reset signal RST and the first switch signal S1 are pulled high. Since the output of the latch is low, the outputs of the first AND gate and the second AND gate remain low, and the reset transistor and the first switch signal S1... When the switch is not turned on, the reset voltage stored in the first capacitor will not be refreshed. Then the transmission signal TX is pulled high, and the charge accumulated by the photodiode during exposure continues to be transferred to the charge storage capacitor. After the transfer is completed, the readout stage begins. Signal readout: first read the reset voltage and then read the signal voltage. After being stored in the second and third capacitors respectively, the difference is calculated by the CDS circuit. The result of the difference is compared with the reference voltage Vref by the first comparator, and the comparison result FS is fed back to the pixel to control the reset of the next frame. At the same time, the result of the difference is compared with the ramp signal Vramp generated by the ramp generator by the second comparator and quantized by the counter.

7. An image sensor, characterized in that, Includes the adaptive reset large dynamic range pixel structure as described in any one of claims 1-6.

8. An electronic device, characterized in that, Includes the image sensor as described in claim 7.

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