Audio device, audio system, audio chip and electronic device

Abstract

The invention provides an audio device, an audio system, an audio chip and an electronic device. An audio device receives a bit clock signal and first audio data from a preceding stage device through a first bus, the audio device comprising: a counter performing pulse counting on the bit clock signal and generating an interrupt signal when a pulse count value reaches a first preset value; the processor is used for calculating a clock skew value between the audio device and the preceding-stage device according to the interrupt signal and the pulse count value; the asynchronous sampling rate converter is used for carrying out sampling rate conversion on the first audio data according to the clock deviation value and outputting second audio data; and the output module is used for converting the second audio data into output. According to the audio device of the embodiment of the invention, the clock skew value between the preceding stage device and the audio device is calculated through pulse counting, and data or signals provided for the output module are adjusted in time according to the clock skew value.

Description

[Technical field]

[0001] The present application relates to the technical field of audio signal processing, and in particular to an audio device, an audio system, an audio chip and an electronic device. [Background technology]

[0002] The synchronization problem of asynchronous clock refers to the problem that in an asynchronous clock system, due to the asynchronous clock signals between various modules, data transmission errors, timing deviations and other problems may occur. For example, when the output signal of one module is transmitted to another module, the clock signals of the two modules may not be synchronized, resulting in inaccurate data transmission or transmission failure.

[0003] Although asynchronous clocks do not need to be synchronized with other devices, in some cases, asynchronous clocks also need to be synchronized. For example, in high-speed data transmission or distributed systems, clock synchronization is required to ensure the correctness and timing accuracy of data transmission. In addition, in some special occasions, such as audio and video synchronization, asynchronous clocks need to be synchronized to achieve transmission synchronization.

[0004] For audio signal data processing, if the synchronization problem of the asynchronous clock is not always solved, anomalies such as missing characters and broken sounds will occur, and the anomalies may occur at a fixed frequency.

[0005] In actual audio processing circuits, existing hardware methods focus on hardware solutions to asynchronous clock circuit asynchronism problems, such as phase control, aligning the edges of two asynchronous clocks through PLL (phase-locked loop) or DLL (delay-locked loop), or double-jump technology (double-trigger technology), etc. Hardware cannot take into account the diversity and complexity of cascade devices in the actual cascade process of different chips, as well as the hardware operability of existing methods.

[0006] Software solves the problem of clock asynchrony. Currently, it mainly adjusts the audio link water level, including adjusting the size and amount of the cache through software, or calculating the number of audio points in a certain interval of the audio link to deduce the sampling rate of the back-end processing module to restore / follow the clock of the front-end device. The audio link water level here refers to the state of the data in the buffer in the audio transmission link. It indicates the amount of data in the current link, usually expressed as a percentage of the data volume to the total capacity of the buffer. In audio transmission, audio data needs to be cached in the buffer and then read and processed within a certain time interval. The size of the buffer is generally related to parameters such as the audio sample rate, the number of audio bits, and the length of the buffer. When the amount of data in the buffer exceeds a certain threshold, we call it a buffer full. When the amount of data in the buffer is lower than a certain threshold, we call it an empty buffer. The purpose of the audio link water level is to measure the state of the audio transmission link to ensure the stability and accuracy of data transmission and processing. When the audio link water level is too high, it may cause problems such as high data delay and audio jamming. When the audio link water level is too low, it may cause problems such as unstable data transmission and intermittent audio. Therefore, the status of the link can be judged by monitoring the audio link water level so that audio transmission parameters, buffer size and other parameters can be adjusted in time to ensure the stability and accuracy of audio transmission.

[0007] However, the existing solutions to the asynchronous clock asynchrony problem still have room for further improvement, especially the need to solve the accuracy problem at a low cost. [Summary of the invention]

[0008] The purpose of the present application is to provide an audio device, an audio system, an audio chip and an electronic device, which can solve the problem of clock asynchrony between a front-end device and a back-end device or the problem of clock jitter or interference during the cascading of audio devices.

[0009] According to one aspect of the present application, an audio device is provided, which receives a bit clock signal and first audio data from a previous device via a first bus. The audio device comprises:

[0010] a counter, for counting pulses of the bit clock signal and generating an interrupt signal when the pulse count value reaches a first preset value;

[0011] A processor, calculating a clock deviation value between the audio device and the front-stage device according to the interrupt signal and the pulse count value;

[0012] an asynchronous sampling rate converter, performing sampling rate conversion on the first audio data according to the clock deviation value, and outputting second audio data;

[0013] The output module converts the second audio data into output.

[0014] Furthermore, the first bus includes an I 2S bus.

[0015] Further, the processor is configured as follows:

[0016] determining a first time interval based on the audio device according to the time between the interruption signals;

[0017] Determine a second time interval based on the front-stage device according to the pulse count value, the sampling rate and sampling depth of the first audio data, and the number of channels;

[0018] The clock deviation value is determined according to a difference between the first time interval and the second time interval.

[0019] Furthermore, the asynchronous sampling rate converter is configured to adjust the number of sampling points output by interpolation according to the clock deviation value.

[0020] Furthermore, the output module includes a digital-to-analog converter.

[0021] According to another aspect of the present application, an audio device is provided, which receives a bit clock signal and first audio data from a previous device via a first bus. The audio device comprises:

[0022] a counter, for counting pulses of the bit clock signal and generating an interrupt signal when the pulse count value reaches a first preset value;

[0023] A processor, calculating a clock deviation value between the audio device and the front-stage device according to the interrupt signal and the pulse count value;

[0024] A phase-locked loop, adjusting an output clock frequency signal according to the clock deviation value;

[0025] An output module converts the first audio data into output according to the clock frequency signal.

[0026] Furthermore, the first bus includes an I 2S bus.

[0027] Further, the processor is configured as follows:

[0028] determining a first time interval based on the audio device according to the time between the interruption signals;

[0029] Determine a second time interval based on the front-stage device according to the pulse count value, the sampling rate and sampling depth of the first audio data, and the number of channels;

[0030] The clock deviation value is determined according to a difference between the first time interval and the second time interval.

[0031] Furthermore, the phase-locked loop is configured as follows:

[0032] A clock source is dynamically selected according to the clock deviation value.

[0033] Furthermore, the output module includes a digital-to-analog converter.

[0034] According to another aspect of the present application, an audio system is provided, comprising: a first source end serving as a front-end device; and the audio device described in any one of the above items.

[0035] Furthermore, the first source end modulates and demodulates the received wireless signal into an audio digital signal, and decodes the audio digital signal and transmits it to the audio device.

[0036] According to another aspect of the present application, an audio chip is provided, comprising any of the aforementioned audio devices.

[0037] According to another aspect of the present application, an electronic device is provided, comprising the audio device described in any one of the above items, the audio system described in any one of the above items, or the audio chip described in any one of the above items.

[0038] The audio device according to the exemplary embodiment calculates the clock deviation value between the pre-stage device and the audio device by pulse counting, and timely adjusts the data or signal provided to the output module according to the clock deviation value.

[0039] According to some embodiments, the clock frequency signal output by the PLL can be feed-forward adjusted according to the clock deviation value, for example, by dynamically selecting a subdivided clock source, thereby more accurately adjusting the PLL of the audio device, with higher control accuracy and smaller fluctuations in the audio link.

[0040] According to some embodiments, the number of audio data sampling points output by the ASRC can be feed-forward adjusted according to the clock deviation value, for example, the conversion ratio of the ASRC sampling points can be dynamically adjusted, and the sampling points can be interpolated and adjusted according to the ratio, so as to more accurately adjust the output sampling points of the ASRC, achieve higher control accuracy, and reduce fluctuations in the audio link.

Brief Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0042] Figure 1 A schematic diagram showing the composition of an audio device according to an exemplary embodiment of the present application is shown.

[0043] Figure 2 A schematic diagram showing the composition of an audio device according to another embodiment of the present application is shown.

[0044] Figure 3 A schematic block diagram illustrating counting pulses of a bit clock signal from an output device according to an example embodiment is shown.

[0045] Figure 4 A control schematic diagram of an audio device according to an example embodiment is shown.

[0046] Figure 5 A flow chart of a method for asynchronous clock synchronization according to an exemplary embodiment of the present application is shown.

[0047] Figure 6 A block diagram of an electronic device according to an exemplary embodiment of the present application is shown.

[0048] Figure 7 A schematic diagram showing the composition of an audio system according to an exemplary embodiment of the present application. [Specific implementation method]

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] The present application provides an audio device, which receives a bit clock signal and first audio data from a front-end device through a first bus, and the audio device includes a counter, a processor, an asynchronous sampling rate converter and an output module. The counter counts pulses of the bit clock signal and generates an interrupt signal when the pulse count value reaches a first preset value. The processor calculates a clock deviation value between the audio device and the front-end device according to the interrupt signal and the pulse count value. The asynchronous sampling rate converter performs sampling rate conversion on the first audio data according to the clock deviation value and outputs second audio data. The output module converts the second audio data into output.

[0051] An asynchronous sample rate converter (ASRC) is a device or module used to convert sample rates between digital audio systems with different sample rates. In a digital audio system, different devices may have different sample rates. For example, some devices may use a 48kHz sample rate, while others may use a 96kHz sample rate. In this case, sample rate conversion is required to convert the digital audio signal of one device to the sample rate required by another device. For example, an ASRC typically uses its own internal clock to sample the input digital audio signal and convert it to a standardized sample rate. The output of the ASRC is directly fed into a DAC, which uses a separate clock signal to convert the digital audio signal into an analog audio signal.

[0052] According to some embodiments, the asynchronous sample rate converter may be configured to adjust the number of sampling points output by interpolation according to the clock deviation value.

[0053] The present application also provides an audio device, which receives a bit clock signal and first audio data from a preceding device through a first bus. The audio device includes a counter, a processor, a phase-locked loop, and an output module. The counter counts pulses of the bit clock signal and generates an interrupt signal when the pulse count value reaches a first preset value. The processor calculates a clock deviation value between the audio device and the preceding device based on the interrupt signal and the pulse count value. The phase-locked loop adjusts the output clock frequency signal based on the clock deviation value. The output module converts the first audio data into output based on the clock frequency signal.

[0054] According to some embodiments, the phase locked loop is configured to dynamically select a clock source according to the clock deviation value.

[0055] According to some embodiments, the processor is configured to determine a first time interval based on the audio device based on the time between interrupt signals; determine a second time interval based on the pre-stage device based on the pulse count value, the sampling rate and sampling depth of the first audio data, and the number of channels; and thereby determine the clock deviation value based on the difference between the first time interval and the second time interval.

[0056] In the above solution, the first bus may be an I2S bus, and the output module may be a digital-to-analog converter (DAC). However, those skilled in the art can easily understand that the technical solution of the present application can also be extended to other scenarios.

[0057] According to the technical solution of the present application, if the audio device is to stably play the digital audio data from the previous device, the "incoming" or "outgoing" audio points or audio frame data inside the audio device must be kept consistent as much as possible, so that the audio "water level" inside the audio device is kept consistent as much as possible. Because of the difference between the audio device clock and the previous device clock, the present application is based on finding the quantization difference of this clock. The counter (for example, a hardware counter) added to the audio device of the present application can count the number of I2S bus bit clocks within a given period of time, and can calculate the clock deviation value between the previous device and the audio device. After obtaining this clock deviation value, the PLL or ASRC of the audio device can be adjusted more accurately. Among them, the former can be based on the gear selection of the clock source, and the latter can be based on the ratio of the number of sampling points for interpolation operations.

[0058] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0059] Figure 1 A schematic diagram showing the composition of an audio device according to an exemplary embodiment of the present application is shown.

[0060] like Figure 1 As shown, the audio device 1000 can be connected to the front-end device 12. The front-end device 12 can be a chip with an audio transmission function, such as a chip for receiving a Bluetooth signal and extracting audio information therefrom. Optionally, the front-end device 12 can also be a local circuit with an audio function, or an audio electronic device. The front-end device 12 can be a device with an audio format conversion function, or an audio device for functions such as mixing.

[0061] Optionally, the audio device 1000 and the front-end device 12 may be connected via a digital audio connection. Optionally, the audio device 1000 and the front-end device 12 may be connected via an I2S bus 13. The transmission signal of the I2S bus 13 includes a bit clock signal and an audio data signal. The bit clock signal and the audio data signal may both be provided by the front-end device 12. Optionally, the I2S bus 13 may also be replaced by a TDM audio bus or other digital audio transmission lines, which will not be described in detail herein.

[0062] The audio device 1000 may include a processor 111 , a counter 112 , a phase-locked loop 113 , a digital-to-analog converter 114 , and a clock source 115 .

[0063] The processor 111 may receive the first audio data from the front-end device 12 via the I2S bus 13. For example, the first audio data may be stored in the buffer I2S FIFO.

[0064] The counter 112 receives the bit clock signal and counts the pulses of the bit clock signal. The counter 112 can count the rising edge or the falling edge of the bit clock signal. Optionally, the counter 112 can also count the rising edge and the falling edge of the bit clock signal at the same time. When the pulse count value reaches the first preset value N, the counter 112 can send an interrupt signal to the processor 111.

[0065] The processor 111 can receive an interrupt signal and can time the interval time T0 between multiple interrupt signals. Optionally, it can be the interval time between two adjacent interrupt signals of multiple interrupt signals that occur continuously with the interval time T0. Alternatively, the interval time T0 can also be the interval time between two non-adjacent interrupt signals. Optionally, the theoretical time T1 corresponding to the interval time in the previous stage device can be calculated. When the interval time T0 is the interval time between two adjacent interrupt signals, the theoretical time T1 corresponding to the interval time in the previous stage device is N / (sampling rate*sampling depth*number of channels). Optionally, a clock deviation value T=T0-T1 can be defined.

[0066] According to an embodiment, the clock deviation value T can be used to adjust the clock frequency signal output by the phase-locked loop 113. For example, the clock source can be dynamically selected according to the clock deviation value T. According to an embodiment, the PLL is designed with multiple subdivided clock sources, and the clock source can be dynamically adjusted according to the clock deviation value T to match the external clock.

[0067] For example, according to the embodiment, taking the 48KHz basic clock as an example, a lookup table can be set according to the clock deviation value T, and corresponding selections can be made from multiple subdivided clock sources such as 48.010KHz, 48.020KHz, 48.003KHz, 47.997KHz, etc. according to the clock deviation value T, so as to more accurately adjust the PLL of the audio device, with higher accuracy and smaller fluctuations in the audio link.

[0068] The clock source 115 can be used to provide a base clock. The phase-locked loop 113 generates a master clock signal based on the clock source 115 .

[0069] The phase-locked loop 113 may have a built-in frequency divider (not shown), and its frequency division coefficient is K. The phase-locked loop 113 may make the main clock signal K times the base clock. Optionally, the phase-locked loop 113 may perform closed-loop feedback regulation through a PID regulation module.

[0070] The digital-to-analog converter 114 can be used to convert a digital audio signal into an analog audio signal. The digital-to-analog converter 114 can obtain the first audio data from the cache I2S FIFO and convert the first audio data into an output. The digital-to-analog converter 114 is connected to the phase-locked loop 113, receives the clock frequency signal of the phase-locked loop 113, and generates an analog audio signal according to the clock frequency signal and the first audio data. The analog signal can be used to drive a sound output device, such as a speaker or a headset, so that the audio signal can be restored and reproduced.

[0071] Alternatively, the audio device 1000 may be an audio relay, an audio conversion device, etc. having an audio processing function.

[0072] Figure 2 A schematic diagram showing the composition of an audio device according to another embodiment of the present application is shown.

[0073] like Figure 2 As shown, the audio device 2000 can be connected to the front-end device 22 via the I2S bus 23. The I2S bus 23 and the front-end device 22 can be similar to the I2S bus 13 and the front-end device 12, respectively, and will not be described in detail here.

[0074] The audio device 2000 may include a processor 211, a counter 212, an asynchronous sampling rate converter (ASRC) 213, a digital-to-analog converter 214, and a clock source 215. The counter 212 and the digital-to-analog converter 214 may be respectively connected to Figure 1 The counter 112 and the digital-to-analog converter 114 are similar.

[0075] The processor 211 may receive the first audio data from the front-end device 22 via the I2S bus 23. For example, the first audio data may be stored in the buffer I2S FIFO.

[0076] The counter 212 receives the bit clock signal and counts the pulses of the bit clock signal. The counter 212 can count the rising edge or the falling edge of the bit clock signal. Optionally, the counter 212 can also count the rising edge and the falling edge of the bit clock signal at the same time. When the pulse count value reaches the first preset value N, the counter 212 can send an interrupt signal to the processor 211.

[0077] The processor 211 can receive an interrupt signal and can time the interval time T0 between multiple interrupt signals. Optionally, it can be the interval time between two adjacent interrupt signals of which the interval time T0 occurs continuously. Alternatively, the interval time T0 can also be the interval time between two non-adjacent interrupt signals. Optionally, the theoretical time T1 corresponding to the interval time in the front-stage device can be calculated. When the interval time T0 is the interval time between two adjacent interrupt signals, the theoretical time T1 corresponding to the interval time in the front-stage device is N / (sampling rate*sampling depth*number of channels). Optionally, a clock deviation value T=T0-T1 can be defined. For example, according to some embodiments, the sampling rate is 48K, the sampling depth is 32 bits, and the number of channels is 2.

[0078] The asynchronous sampling rate converter 213 may perform sampling rate conversion on the first audio data according to the clock deviation value and output the second audio data. For example, the asynchronous sampling rate converter 213 may be configured to adjust the number of sampling points according to the clock deviation value T by interpolation and output.

[0079] For example, according to an embodiment, a lookup table may be set according to the clock deviation value T, and a corresponding selection may be made from multiple ratios such as 1:0.9993, 1:0.9999, 1:1.0000, 1:1.0001, and 1:1.0007 according to the clock deviation value T, and the number of ASRC sampling points may be interpolated and adjusted according to the selected ratio.

[0080] According to some embodiments, the present application further provides an audio chip, which includes the aforementioned audio device. In other words, the aforementioned device can be implemented in the form of an audio chip, for example, as a SoC system.

[0081] According to some embodiments, the present application also provides an electronic device, comprising the aforementioned audio device.

[0082] Figure 3 A schematic block diagram illustrating counting pulses of a bit clock signal from an output device according to an example embodiment is shown.

[0083] See also Figure 3 , the I2S output device 310 (e.g., a wireless microphone receiver) can receive MP3 audio data (MP3 data is encoded into Bluetooth signal transmission) through wireless transmission (e.g., Bluetooth transmission), then modulate and demodulate the wireless signal (e.g., Bluetooth demodulation) into an audio digital signal (e.g., MP3 signal), decode the audio (e.g., decode the MP3 data into a PCM signal), and then transmit it to the I2S input device 320 (e.g., a wireless microphone near-end monitor) through the I2S bus. The I2S output device and the I2S input device here can be respectively equivalent to Figure 1 and 2 The preamplifier and audio device in the.

[0084] See also Figure 3 The (hardware) counter 322 of the I2S input device 320 detects the bit clock BITCLK rate of the I2S output device 310 (detects the rising edge or the falling edge), so that the I2S input device 320 can adjust the output according to the clock deviation of the previous and next devices.

[0085] For example, taking the use scenario of a wireless microphone as an example, the audio digital signal of the I2S output device 310 is transmitted to the I2S input device 320 through the I2S signal, and then output by DAC through the I2S input device 320. The I2S output device 310 is the master of I2S, and the I2S input device 320 is the slave of I2S. The clock BITCLK is provided by the I2S output device 310. Because of the difference in PLL between the I2S output device 310 and the I2S input device 320, the receiving end of the I2S input device 320 needs to adjust the PLL in real time to reflect the frequency change of the I2S output device 310.

[0086] According to the exemplary embodiment, the frequency of the I2S output device 310 can be detected in real time. If a counter that can generate an interrupt is designed inside the chip of the I2S input device 320, and this counter can collect the rising edge or falling edge of the I2S, then the time T0 (absolute time of the I2S input device) when N pulses generate an interrupt can be detected, and the theoretical time of the I2S output device 310 is N / (sampling rate*sampling depth*number of channels)=T1. Then, the clock deviation value of the I2S input device 320 and the I2S output device 310 is T=T0-T1, and according to the calculated T, the PLL output of the I2S input device 320 or the ASRC output of the I2S input device 320 is adjusted.

[0087] For example, if the synchronization adjustment is based on a 5ms frame clock, the error is within 5ms. Assuming the sampling clock is 48K, if the synchronization adjustment is based on the sampling clock, the error is approximately within 22us (considering the processing time). The technical solution of the present application performs synchronization adjustment based on the bit clock. Assuming the sampling clock is 48K, the sampling depth is 32 bits, and the number of channels is 2, the error is approximately within 0.35us (considering the processing time). It can be seen that the technical solution of the present application greatly improves the accuracy of synchronization adjustment.

[0088] In addition, compared with the standard I2S protocol, the solution of the present application does not modify any part of the existing I2S protocol, but only designs a counter to detect the number of rising edges and / or falling edges of I2S in a certain period of time. However, this newly designed counter can provide a very accurate reference for software to calculate clock PLL difference or ASRC interpolation, and the reference accuracy provided is much higher than that of calculating audio points.

[0089] Therefore, according to the exemplary embodiment, by calculating the clock deviation value and sampling feedforward method, the PLL or ASRC can be adjusted in advance, with smaller time intervals, higher accuracy, and smaller fluctuations in the audio link.

[0090] Figure 4 A control schematic diagram of an audio device according to an example embodiment is shown.

[0091] See also Figure 4 , M(S) is the bit clock signal of the I2S signal, where S represents the transfer function of the frequency domain transformation.

[0092] X(S) is an audio frame or an audio point (eg, a raw PCM sample point) that the audio device inputs from the I2S FIFO to the DAC FIFO.

[0093] Y(S) is the change in X(S) caused by the clock deviation between the audio device and the preceding device.

[0094] G0 is the X(S) audio point or audio frame I2S input control channel transfer function.

[0095] G1 is the X(S) audio point or audio frame PI D control channel transfer function.

[0096] G2 is the channel transfer function of the ASRC or phase-locked loop controlled object.

[0097] G3 is the feedback control channel transfer function.

[0098] G4 is the feedforward control channel transfer function of the counter detecting the bit clock signal.

[0099] G5 is the “interference” channel transfer function caused by the bit clock signal of the I2S signal.

[0100] From the above figure, we can see that the transfer function of the system to disturbance is:

[0101]

[0102] When the jitter of M(S) is not 0, it is hoped that the change of Y(S) is still 0, which means that the "audio frame or audio point" of the entire audio control system can still be stably controlled near the expected value X(S) under the clock jitter (or equivalent jitter) of the front-end I2S input signal. Differentiate the transfer function:

[0103]

[0104] When ΔY(S) = 0, the expected value of the transfer function can be obtained as follows:

[0105] Δ(G0*G1*G5+G4)=0

[0106] Because the I2S input bit clock signal and the X(S) audio frame or audio point are in strict proportion, that is:

[0107] Δ(K*G1+G4)=0(K=G0*G5, K is a constant)

[0108] Combined with practical applications, the control model can be divided into the following three cases for discussion:

[0109] In the first case, if there is no feedforward system G4 (counter) to detect the I2S bit clock signal, the transfer function is equivalent to

[0110]

[0111] That is, any bit clock jitter M(S) of I2S will be fed back to the output end Y(S), and G1 and G2 can only be designed to follow the jitter of M(S).

[0112] In the second case, if the minimum time unit of an audio frame or audio point is 22us (assuming a 48K sampling rate), during I2S transmission, if the I2S bit clock signal jitter is less than 22us (assuming a 48K sampling rate), that is, the Δ(K*G1)*G2 discrete audio point or audio frame differential is equal to 0, if G4 feedforward is not added, the change of the output audio point or audio frame Y(S) cannot be corrected in time. It can only wait for the change of the I2S bit clock signal to gradually accumulate to affect an audio point or an audio frame before it can be detected by G3 feedback sampling, and then adjust G1 (PI D) to follow. After adding G4, at a 48K sampling rate, if the clock unit of the bit clock signal transmitted by the I2S signal is 0.35us, G4 can detect small clock changes in time, and the transfer function is equivalent to the following under such small clock signal changes (Δ(K*G1)*G2=0):

[0113]

[0114] It can be seen that after having G4, even a very small clock jitter of the clock signal at the I2S input end can be detected in time, and then the frequency gear or sampling point ratio of G2 can be adjusted to stabilize the output of Y(S).

[0115] In the third case, in contrast to the small jitter in the second case, if the I2S bit clock signal has a relatively large jitter at some point, the system cannot respond immediately and converge the Y(S) value very quickly because the feedback G3 is "lagging". However, with the G4 feedforward, the system can make "forward-looking" pre-corrections and quickly converge the Y(S) value.

[0116] By using the above method, when there is deviation or fluctuation in the bit clock signal transmitted by the I2S bus, the stability of the output signal of the audio device can be achieved.

[0117] Figure 5 A flow chart of a method for asynchronous clock synchronization according to an exemplary embodiment of the present application is shown.

[0118] like Figure 5 The method shown can be applied to the audio device at the rear stage of two cascaded audio devices. The front stage device can send a digital audio signal, such as an I2S digital audio signal, including a bit clock signal and first audio data to the audio device.

[0119] At S510, a bit clock signal is received from a preceding device.

[0120] At S520, the clock deviation value of the bit clock signal is calculated. Optionally, the total time of the clock cycles of several bit clock signals can be timed first. Optionally, the pulses of the bit clock signal can be counted, and an interrupt signal can be generated when the count value reaches a first preset value N.

[0121] During the continuous operation of the front-end device and the audio device, multiple interrupt signals may be generated in sequence. The interval time T0 between two interrupt signals may be timed. The interval time T0 may be the interval time between two adjacent interrupt signals generated in sequence, or the interval time between two non-adjacent interrupt signals.

[0122] Optionally, the theoretical time T1 corresponding to the interval time in the front-stage device can be calculated. The theoretical time T1 can be the interval time calculated based on the agreed protocol parameters on the agreed I2S bus. For example, the agreed I2S agreed protocol parameters between the audio device and the front-stage audio device are: sampling rate 48K, sampling depth 32 bits, number of channels 2. If the interval time T0 corresponds to the total duration of the interval time between the 0th interrupt signal and the Mth interrupt signal, the theoretical time T1 can be M*N / (48K*2*32). Optionally, the time difference T can be defined as T0-T1, and the time difference T can be used as the clock deviation value.

[0123] Optionally, the actual sampling rate on the I2S bus can also be calculated based on the interval time T0. For example, according to the aforementioned agreed parameters, the actual sampling rate is N*M / (T0*32*2). The actual sampling rate can be compared with the agreed sampling rate of 48K, and the deviation between the two can be used as the bit clock deviation value.

[0124] At S530, first audio data is received. For example, the first audio data may be received via DMA.

[0125] At S540, a point ratio for adjusting the number of ASRC sampling points is determined according to the clock deviation value. For example, according to an embodiment, a lookup table may be set according to the clock deviation value T, and a corresponding selection may be made from a plurality of ratios such as 1:0.9993, 1:0.9999, 1:1.0000, 1:1.0001, 1:1.0007, etc., according to the clock deviation value T, and the number of sampling points may be interpolated and adjusted according to the selected ratio.

[0126] At S550, the number of sampling points outputted by the ASRC is interpolated and adjusted according to the point ratio and the first audio data, for example, the number of sampling points of the audio data is increased or decreased according to the point ratio, thereby repairing jitter or interference by adjusting the number of sampling points.

[0127] The present application also provides an electronic device, comprising: a processor; and a memory connected to the processor and storing a program executable by the processor. When the program is executed, the processor implements the aforementioned method.

[0128] The present application also provides a storage medium that stores a program executable by a processor. When the program is executed, the processor can implement the aforementioned method.

[0129] Figure 6 A block diagram of an electronic device according to an exemplary embodiment of the present application is shown.

[0130] like Figure 6 As shown, the electronic device 630 includes a processor 612 and a memory 614. The electronic device 630 may also include a bus 622, a network interface 616, and an I / O interface 618. The processor 612, the memory 614, the network interface 616, and the I / O interface 618 may communicate with each other via the bus 622. The electronic device 630 may be an audio device such as a Bluetooth headset, a wireless microphone near-end monitor, or the like.

[0131] The processor 612 may include one or more CPUs, microprocessors, DSPs or application specific integrated circuits, etc., for executing relevant program instructions.

[0132] The memory 614 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM), and / or a cache memory. The memory 614 is used to store one or more programs including instructions and data. The processor 612 may read the instructions stored in the memory 614 to execute the above-mentioned method according to the embodiment of the present application.

[0133] The electronic device 630 may also communicate with one or more networks via the network interface 616. The network interface 616 may be a wireless network interface, such as a Bluetooth interface.

[0134] The bus 622 may include an address bus, a data bus, a control bus, etc. The bus 622 may provide a path for exchanging information between components.

[0135] It should be noted that, in the specific implementation process, the electronic device 630 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0136] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] Figure 7 A schematic diagram showing the composition of an audio system according to an exemplary embodiment of the present application.

[0138] like Figure 7 As shown, the audio system 5000 may include: a first source terminal 511 as a front-end device; an I2S bus 521 and audio devices 531 and 532. The first source terminal 511 as a device with audio function may be connected to the audio devices 531 and 532 through the I2S bus 521.

[0139] The first source end 511 may be an electronic device with an audio function. For example, the first source end 511 may be a Bluetooth conversion unit. For example, the audio data received by the first source end 511 from the Bluetooth link is transmitted to the audio devices 531 and 532 respectively through the I2S bus 521.

[0140] The audio devices 531 and 532 may be Figure 1 and Figure 2 Optionally, any one of the audio devices 531 and 532 can be an electronic device with an audio processing function. Figure 1 and Figure 2 The audio signals of the devices 531 and 532 can be highly synchronized. In this way, the user can get a better use experience.

[0141] According to some embodiments, the present application also provides an electronic device, comprising the aforementioned audio system.

[0142] In the above scheme, the clock deviation value between the front-stage device and the audio device is calculated by pulse counting, and the data or signal provided to the output module is adjusted in time according to the clock deviation value. According to some embodiments, the clock frequency signal output by the PLL can be feed-forward adjusted according to the clock deviation value, for example, a subdivided clock source is dynamically selected, so that the PLL of the audio device is more accurately adjusted, the control accuracy is higher, and the fluctuation of the audio link is smaller. According to some embodiments, the number of audio data sampling points output by the ASRC can be feed-forward adjusted according to the clock deviation value, for example, the conversion ratio of the ASRC sampling points is dynamically adjusted, and the sampling points are interpolated and adjusted according to the ratio, so that the output sampling points of the ASRC are more accurately adjusted, the control accuracy is higher, and the fluctuation of the audio link is smaller.

[0143] In addition, compared with the standard I2S protocol, the solution of the present application does not modify any part of the existing I2S protocol, but only designs a counter to detect the number of rising edges and / or falling edges of I2S in a certain period of time. However, this newly designed counter can provide a very accurate reference for software to calculate clock PLL difference or ASRC interpolation, and the reference accuracy provided is much higher than that of calculating audio points.

[0144] The above is only an implementation method of the present application. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present application, but these improvements are within the scope of protection of the present application.

Claims

1. An audio device, receiving a bit clock signal and first audio data from a preceding device via a first bus, characterized in that: The audio device comprises: a counter, for counting pulses of the bit clock signal and generating an interrupt signal when the pulse count value reaches a first preset value; A processor, calculating a clock deviation value between the audio device and the front-stage device according to the interrupt signal and the pulse count value; an asynchronous sampling rate converter, performing sampling rate conversion on the first audio data according to the clock deviation value, and outputting second audio data; The output module converts the second audio data into output.

2. The audio device according to claim 1, characterized in that The first bus includes an I2S bus.

3. The audio device according to claim 1, wherein The processor is configured as follows: determining a first time interval based on the audio device according to the time between the interruption signals; Determine a second time interval based on the front-stage device according to the pulse count value, the sampling rate and sampling depth of the first audio data, and the number of channels; The clock deviation value is determined according to a difference between the first time interval and the second time interval.

4. The audio device according to claim 1, characterized in that The asynchronous sampling rate converter is configured to adjust the number of sampling points output by interpolation according to the clock deviation value.

5. The audio device according to claim 1, characterized in that The output module includes a digital-to-analog converter.

6. An audio device, receiving a bit clock signal and first audio data from a preceding device via a first bus, characterized in that: The audio device comprises: a counter, for counting pulses of the bit clock signal and generating an interrupt signal when the pulse count value reaches a first preset value; A processor, calculating a clock deviation value between the audio device and the front-stage device according to the interrupt signal and the pulse count value; A phase-locked loop, adjusting an output clock frequency signal according to the clock deviation value; An output module converts the first audio data into output according to the clock frequency signal.

7. The audio device according to claim 6, characterized in that The first bus includes an I2S bus.

8. The audio device according to claim 6, characterized in that The processor is configured as follows: determining a first time interval based on the audio device according to the time between the interruption signals; Determine a second time interval based on the front-stage device according to the pulse count value, the sampling rate and sampling depth of the first audio data, and the number of channels; The clock deviation value is determined according to a difference between the first time interval and the second time interval.

9. The audio device according to claim 6, characterized in that The phase-locked loop configuration is: A clock source is dynamically selected according to the clock deviation value.

10. The audio device according to claim 6, characterized in that The output module includes a digital-to-analog converter.

11. An audio system, characterized in that: include: A first source end, serving as a pre-stage device; An audio device according to any one of claims 1-10.

12. The audio system according to claim 11, characterized in that The first source end modulates and demodulates the received wireless signal into an audio digital signal, and decodes the audio digital signal and transmits it to the audio device.

13. An audio chip, characterized in that: include: An audio device according to any one of claims 1-10.

14. An electronic device, characterized in that: The method comprises the audio device according to any one of claims 1 to 10, the audio system according to any one of claims 11 to 12, or the audio chip according to claim 13.

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