SONOS memory manufacturing method

Abstract

The present application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a SONOS memory manufacturing method. The method comprises the following steps: providing a semiconductor substrate; forming an inter-gate isolation layer covering the sidewalls of a memory stack structure and a select gate oxide layer covering the semiconductor substrate; depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the memory stack structure; depositing a select gate mask layer on the select gate polysilicon; performing a first self-aligned dry etch to remove the select gate mask layer covering the front surface of the select gate polysilicon; performing a second self-aligned dry etch to make the remaining select gate polysilicon flush with the memory stack structure in the vertical direction; performing a third self-aligned dry etch to make the remaining select gate polysilicon flush with the memory stack structure in the vertical direction; and performing a fourth self-aligned dry etch to make the remaining select gate polysilicon lower in the vertical direction than the memory stack structure.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a SONOS memory. Background Art

[0002] SONOS, an acronym for Silicon-Oxide-Nitride-Oxide-Silicon, is a non-volatile memory closely associated with flash memory. It differs from mainstream flash memory in that it uses silicon nitride as the storage material instead of polysilicon. One of its offshoots is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows for lower programming voltages and higher program-erase cycles than polysilicon flash memory, making it an active research and development hotspot.

[0003] A SONOS memory cell in the related art includes a control gate (CG) and a select gate (SG), wherein the control gate is used to store information and the select gate is used as a switch.

[0004] As chip area continues to shrink, the critical dimensions of the active area and control gate of SONOS memory cells are also shrinking to improve product competitiveness. In order to ensure good performance of the control gate, the select gate must be vertical to provide sufficient contact hole manufacturing process window. However, in related technologies, the select gate usually has Figure 1 The horn-like morphology shown and Figure 2 The arc-shaped morphology shown is not conducive to the subsequent processing of the device. Summary of the Invention

[0005] The present application provides a method for manufacturing a SONOS memory, which can solve the problem of poor verticality of the side morphology of the select gate in the related art.

[0006] In order to solve the technical problems in the background technology, the present application provides a SONOS memory manufacturing method, which includes the following steps:

[0007] Providing a semiconductor substrate, on which a storage area stacking structure is formed, and a spacer is formed between two adjacent storage area stacking structures;

[0008] Manufacturing an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate;

[0009] Depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure;

[0010] Depositing a select gate mask layer on the select gate polysilicon;

[0011] Using the select gate polysilicon as an etch stop layer, performing a first self-aligned dry etching on the select gate mask layer to remove the select gate mask layer covering the front surface of the select gate polysilicon;

[0012] Using the upper surface of the memory area stack structure as an etch stop layer, performing a second self-aligned dry etching on the select gate polysilicon to remove the exposed upper portion of the select gate polysilicon extending beyond the memory area stack structure, so that the remaining select gate polysilicon is flush with the memory area stack structure in the vertical direction;

[0013] removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching;

[0014] Performing a third self-aligned dry etching on the storage area stack structure and the remaining select gate polysilicon to thin the storage area stack structure and the select gate polysilicon in the vertical direction, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction;

[0015] The remaining select gate polysilicon is subjected to a fourth self-aligned dry etching to thin the select gate polysilicon in the longitudinal direction, so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than the stacked structure with the storage area.

[0016] Optionally, the step of providing a semiconductor substrate and forming a storage area stack structure on the semiconductor substrate includes:

[0017] providing a semiconductor substrate;

[0018] removing the pad oxide layer on the upper surface of the semiconductor substrate;

[0019] Depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate;

[0020] defining a storage area photolithography pattern on the control gate mask layer;

[0021] The ONO layer, the control gate polysilicon layer and the control gate mask layer are etched based on the storage area photolithography pattern to form a storage area stacking structure, and a spacer is formed between two adjacent storage area stacking structures.

[0022] Optionally, the step of forming an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate includes:

[0023] According to the morphology of the semiconductor substrate with the storage area stack structure, sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate;

[0024] Using the isolation oxide layer as an etch stop layer, dry-etching the isolation nitride layer, with the remaining isolation nitride layer covering the sidewalls of the storage area stack structure;

[0025] removing the exposed isolation oxide layer by a wet process;

[0026] A select gate oxide layer is formed by deposition, and the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surfaces of the isolation nitride layer.

[0027] Optionally, in the step of depositing select gate polysilicon on the select gate oxide layer and wrapping the storage area stack structure with the select gate polysilicon, the select gate polysilicon covers the periphery of the storage area stack structure and fills the spacer formed between two adjacent storage area stack structures.

[0028] Optionally, in the step of depositing a select gate mask layer on the select gate polysilicon, the select gate mask layer is made of silicon nitride and has a thickness of 100 Å to 200 Å.

[0029] Optionally, in the step of performing a first self-aligned dry etching on the select gate mask layer using the select gate polysilicon as an etch stop layer to remove the select gate mask layer covering the front side of the select gate polysilicon, the first self-aligned dry etching is a non-selective dry etching.

[0030] Optionally, in the step of using the upper surface of the storage area stack structure as an etch stop layer, performing a second self-aligned dry etching on the select gate polysilicon to remove the exposed upper portion of the select gate polysilicon extending beyond the storage area stack structure, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction, the second self-aligned dry etching has a higher etching rate for the select gate polysilicon than for the storage area stack structure.

[0031] Optionally, in the step of removing the remaining select gate mask layer covering the side surfaces of the select gate polysilicon by wet etching, the remaining select gate mask layer covering the side surfaces of the select gate polysilicon is removed by phosphoric acid wet etching.

[0032] Optionally, the storage area stacking structure and the remaining selection gate polysilicon are subjected to a third self-aligned dry etching to thin the storage area stacking structure and the selection gate polysilicon in the longitudinal direction, and in the step where the remaining selection gate polysilicon is flush with the storage area stacking structure in the longitudinal direction, the third self-aligned dry etching is a non-selective dry etching.

[0033] Optionally, in the step of performing a fourth self-aligned dry etching on the remaining selection gate polysilicon to thin the selection gate polysilicon in the longitudinal direction so that the height of the remaining selection gate polysilicon in the longitudinal direction is lower than that of the storage area stacking structure, the fourth self-aligned dry etching has a higher etching rate for the selection gate polysilicon than for the storage area stacking structure.

[0034] The technical solution of the present application includes at least the following advantages: the present application etches the select gate polysilicon in steps by sequentially performing the first self-aligned dry etching, the second self-aligned dry etching, the wet etching, the third self-aligned dry etching and the fourth self-aligned dry etching, which can improve the longitudinal verticality of the side surface of the formed select gate polysilicon, avoid the occurrence of bull-horn morphology and arc-shaped morphology, and provide a larger process possibility window for subsequent manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 A schematic diagram of a select gate structure with a horn-like morphology in the related art is shown;

[0037] Figure 2 A schematic diagram of a select gate structure with an arc-shaped morphology in the related art is shown;

[0038] Figure 3 A flow chart of a method for manufacturing a SONOS memory device according to an embodiment of the present application is shown;

[0039] Figure 4 A schematic diagram of a semiconductor substrate structure with a stacked storage area structure is shown;

[0040] Figure 5 FIG2 shows a schematic cross-sectional structure diagram of the device after step S21 is completed;

[0041] Figure 6 FIG2 shows a schematic cross-sectional structure diagram of the device after step S22 is completed;

[0042] Figure 7 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S24 is completed;

[0043] Figure 8 FIG4 shows a schematic diagram of a cross-sectional structure of the device after step S4 is completed;

[0044] Figure 9 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S5 is completed;

[0045] Figure 10 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S6 is completed;

[0046] Figure 11 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S9 is completed. DETAILED DESCRIPTION

[0047] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0050] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0051] Figure 3 The flowchart of the SONOS memory manufacturing method provided by an embodiment of the present application is shown. Figure 3 As can be seen from the figure, the SONOS memory manufacturing method includes the following steps S1 to S9:

[0052] Step S1: providing a semiconductor substrate, forming a storage area stacking structure on the semiconductor substrate, and forming a spacer between two adjacent storage area stacking structures.

[0053] Reference Figure 4 , which shows a schematic diagram of a semiconductor substrate structure with a stacked storage area structure. Figure 4 As can be seen from the figure, spaced-apart storage region stacking structures CG are formed on the semiconductor substrate 100 , and a spacer is formed between two adjacent storage region stacking structures CG.

[0054] Exemplarily, step S1 may be implemented according to the following steps S11 to S15 .

[0055] Step S11: providing a semiconductor substrate.

[0056] The semiconductor substrate includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer that serves as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0057] Step S12: removing the pad oxide layer on the upper surface of the semiconductor substrate.

[0058] Typically, a pad oxide layer is formed on the provided semiconductor substrate. Before fabricating the memory stack structure CG on the semiconductor substrate, the pad oxide layer needs to be removed. Exemplarily, the pad oxide layer can be removed by a wet process.

[0059] Step S13: depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate.

[0060] The ONO layer includes a bottom oxide layer, a nitride layer, and an upper oxide layer sequentially covering the semiconductor substrate from bottom to top. The control gate mask layer can be made of PESiN. The thickness of the control gate mask layer is 400 Å.

[0061] Step S14: defining a storage area photolithography pattern on the control gate mask layer.

[0062] Step S15: etching the ONO layer, the control gate polysilicon layer and the control gate mask layer based on the storage area photolithography pattern to form a storage area stack structure, and forming a spacer between two adjacent storage area stack structures.

[0063] After step S15 is completed, Figure 2 The device structure shown.

[0064] Step S2: forming an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a selection gate oxide layer covering the semiconductor substrate.

[0065] The inter-gate isolation layer covering the sidewall of the storage area stack structure is a structure formed by an oxide layer-nitride layer-oxide layer.

[0066] Step S2 can be implemented according to the following steps S21 to S24:

[0067] Step S21 : depositing an isolation oxide layer and an isolation nitride layer in sequence on the semiconductor substrate according to the morphology of the semiconductor substrate with the memory area stacking structure.

[0068] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S21 is completed. Figure 5 As can be seen in the figure, the isolation oxide layer 210 and the isolation nitride layer 220 are formed according to the morphology of the semiconductor substrate 100 with the memory region stack structure CG, and cover the semiconductor substrate 100. That is, the isolation oxide layer 210 is located below the isolation nitride layer 220. The isolation oxide layer 210 covers the exposed upper surface of the semiconductor substrate 100 and covers the side surfaces and upper surface of the memory region stack structure CG. The isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 covers the spacer between two adjacent memory region stack structures CG.

[0069] Step S22: using the isolation oxide layer as an etch stop layer, dry-etching the isolation nitride layer, and the remaining isolation nitride layer covers the sidewalls of the storage area stack structure.

[0070] Reference Figure 6 , which shows a schematic diagram of the cross-sectional structure of the device after step S22 is completed. Figure 6 It can be seen that due to the anisotropy of dry etching, the etching rate on the front of the isolation nitride layer 220 is greater than the etching rate on the side of the isolation nitride layer 220. Therefore, after the dry etching is completed, the isolation nitride layer 220 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the storage area stack structure CG is etched away, and the isolation nitride layer 220 covering the side of the storage area stack structure CG is retained.

[0071] Step S23: removing the exposed isolation oxide layer by a wet process.

[0072] During the wet process, the isolation nitride layer 220 covering the side surfaces of the memory region stack structure CG remains, and the remaining isolation nitride layer 220 protects the isolation oxide layer 210 thereunder. Thus, the wet process removes the isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the memory region stack structure CG. The remaining isolation oxide layer 210 and isolation nitride layer 220 cover the side surfaces of the memory region stack structure CG.

[0073] Step S24: depositing a select gate oxide layer, wherein the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surfaces of the isolation nitride layer.

[0074] Exemplarily, the select gate oxide layer may be formed by deposition using an ISSG process.

[0075] Reference Figure 7 , which shows a schematic diagram of the cross-sectional structure of the device after step S24 is completed. Figure 7 It can be seen that the side surfaces of the memory area stack structure CG are sequentially covered with the isolation oxide layer 210 , the isolation nitride layer 220 and the selection gate oxide layer 230 , and the exposed upper surface of the semiconductor substrate 100 is covered with the selection gate oxide layer 230 .

[0076] Step S3: depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure.

[0077] Step S4: depositing a select gate mask layer on the select gate polysilicon.

[0078] Reference Figure 8 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. Figure 8 It can be seen that the selection gate polysilicon 310 deposited in step S4 covers and wraps the storage area stacking structure CG, that is, the selection gate polysilicon 310 covers the periphery of the storage area stacking structure CG, fills the spacer area formed between two adjacent storage area stacking structures CG, and the selection gate mask layer 320 covers the selection gate polysilicon 310.

[0079] Step S5: using the select gate polysilicon as an etch stop layer, performing a first self-aligned dry etching on the select gate mask layer to remove the select gate mask layer covering the front surface of the select gate polysilicon.

[0080] Reference Figure 9 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Figure 9As can be seen in FIG. 1 , the select gate mask layer 320 covering the front surface of the select gate polysilicon 310 is etched away.

[0081] Exemplarily, the first self-aligned dry etching is a non-selective dry etching, that is, the etching rate of the first self-aligned dry etching on the selection gate mask layer and the selection gate polysilicon is consistent. By controlling the etching time, the selection gate mask layer 320 can be etched downward according to the surface morphology of the selection gate polysilicon, so that the etching stop layer is located in the selection gate polysilicon 310.

[0082] Step S6: Using the upper surface of the storage area stack structure as an etching stop layer, perform a second self-aligned dry etching on the select gate polysilicon to remove the exposed upper portion of the select gate polysilicon extending beyond the storage area stack structure, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction.

[0083] from Figure 9 As can be seen in FIG, after the first self-aligned dry etch is completed, the select gate polysilicon 310 is exposed because the select gate mask layer 320 thereon is etched away, and the remaining select gate polysilicon 310 protrudes from the upper portion of the storage region stack structure CG. In step S6, a second self-aligned dry etch is performed to flatten the exposed upper portion of the select gate polysilicon 310 that protrudes from the storage region stack structure CG, so that the remaining select gate polysilicon 310 is flush with the storage region stack structure CG in the vertical direction.

[0084] The second self-aligned dry etching has a higher etching rate for the select gate polysilicon than for the storage area stack structure, and the etching time is controlled so that the remaining select gate polysilicon is flush with the storage area stack structure CG in the vertical direction.

[0085] Reference Figure 10 , which shows a schematic diagram of the cross-sectional structure of the device after step S6 is completed, Figure 10 As can be seen in the figure, the first self-aligned dry etch vertically removes the select gate mask layer 320 and thins the select gate polysilicon 310, so that the select gate polysilicon 310 covering the memory stack structure CG is flush with the memory stack structure CG, and the select gate polysilicon 310 covering the exposed upper surface of the semiconductor substrate 100 is thinned. The remaining select gate mask layer 320 covers the select gate polysilicon 310 on the side of the memory stack structure CG.

[0086] Step S7: removing the remaining select gate mask layer covering the side surfaces of the select gate polysilicon by wet etching.

[0087] Exemplarily, the select gate mask layer covering the side surfaces of the select gate polysilicon may be removed by phosphoric acid etching.

[0088] Step S8: performing a third self-aligned dry etching on the storage area stack structure and the remaining select gate polysilicon to thin the storage area stack structure and the select gate polysilicon in the vertical direction, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction.

[0089] Among them, the third self-aligned dry etching is also non-selective dry etching, that is, the etching rate of the third self-aligned dry etching on the selection gate mask layer and the control gate mask layer located at the top layer of the storage area stack structure is consistent. By controlling the etching time, it is possible to achieve downward etching and thinning of the selection gate mask layer 320 and the storage area stack structure CG according to the flush surface morphology between the selection gate polysilicon and the storage area stack structure, and the thickness of the downward etching does not exceed the thickness of the control gate mask layer located at the top layer of the storage area stack structure CG.

[0090] Step S9: performing a fourth self-aligned dry etching on the remaining select gate polysilicon to thin the select gate polysilicon in the longitudinal direction, so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than the stacked structure of the storage area.

[0091] The fourth self-aligned dry etch has a higher etch rate for the select gate polysilicon than for the memory area stack structure. Thus, when the fourth self-aligned dry etch is completed, the vertical height of the memory area stack structure CG remains substantially unchanged, the vertical height of the select gate polysilicon decreases, and the remaining vertical height of the select gate polysilicon is lower than that of the memory area stack structure.

[0092] Reference Figure 11 , which shows a schematic diagram of the cross-sectional structure of the device after step S9 is completed. Figure 11 It can be seen that after the fourth self-aligned dry etching is completed, the selection gate polysilicon 310 located in the spacer between the two adjacent storage area stacking structures CG and the selection gate polysilicon 310 located on one side of the storage area stacking structure CG away from the spacer are retained, and the height of the remaining selection gate polysilicon 310 is lower than the height of the storage area stacking structure CG.

[0093] The present application etches the select gate polysilicon in steps by sequentially performing a first self-aligned dry etch, a second self-aligned dry etch, a wet etch, a third self-aligned dry etch, and a fourth self-aligned dry etch, thereby improving the longitudinal verticality of the side surface of the formed select gate polysilicon, avoiding the occurrence of bull-horn morphology and arc-shaped morphology, and providing a larger process possibility window for subsequent manufacturing processes.

[0094] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a SONOS memory, characterized in that: The SONOS memory manufacturing method comprises the following steps: Providing a semiconductor substrate, on which a storage area stacking structure is formed, and a spacer is formed between two adjacent storage area stacking structures; Manufacturing an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate; Depositing select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon wraps the storage area stack structure; Depositing a select gate mask layer on the select gate polysilicon; Using the select gate polysilicon as an etch stop layer, performing a first self-aligned dry etching on the select gate mask layer to remove the select gate mask layer covering the front surface of the select gate polysilicon; Using the upper surface of the memory area stack structure as an etch stop layer, performing a second self-aligned dry etching on the select gate polysilicon to remove the exposed upper portion of the select gate polysilicon extending beyond the memory area stack structure, so that the remaining select gate polysilicon is flush with the memory area stack structure in the vertical direction; removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching; Performing a third self-aligned dry etching on the storage area stack structure and the remaining select gate polysilicon to thin the storage area stack structure and the select gate polysilicon in the vertical direction, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction; Performing a fourth self-aligned dry etching on the remaining select gate polysilicon to thin the select gate polysilicon in the longitudinal direction so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than the stacked structure of the storage area; In the step of using the upper surface of the storage area stack structure as an etch stop layer, performing a second self-aligned dry etching on the select gate polysilicon to remove the exposed upper portion of the select gate polysilicon extending beyond the storage area stack structure, so that the remaining select gate polysilicon is flush with the storage area stack structure in the vertical direction, the second self-aligned dry etching has a higher etching rate for the select gate polysilicon than for the storage area stack structure.

2. The method for manufacturing a SONOS memory according to claim 1, wherein: The step of providing a semiconductor substrate and forming a storage area stack structure on the semiconductor substrate includes: providing a semiconductor substrate; removing the pad oxide layer on the upper surface of the semiconductor substrate; Depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer in sequence on the upper surface of the semiconductor substrate; defining a storage area photolithography pattern on the control gate mask layer; The ONO layer, the control gate polysilicon layer and the control gate mask layer are etched based on the storage area photolithography pattern to form a storage area stacking structure, and a spacer is formed between two adjacent storage area stacking structures.

3. The method for manufacturing a SONOS memory according to claim 1, wherein: The step of forming an inter-gate isolation layer covering the sidewalls of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate comprises: According to the morphology of the semiconductor substrate with the storage area stack structure, sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate; Using the isolation oxide layer as an etch stop layer, dry-etching the isolation nitride layer, with the remaining isolation nitride layer covering the sidewalls of the storage area stack structure; removing the exposed isolation oxide layer by a wet process; A select gate oxide layer is formed by deposition, and the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side surfaces of the isolation nitride layer.

4. The method for manufacturing a SONOS memory according to claim 1, wherein: In the step of depositing select gate polysilicon on the select gate oxide layer and wrapping the storage area stack structure with the select gate polysilicon, the select gate polysilicon covers the periphery of the storage area stack structure and fills the spacer formed between two adjacent storage area stack structures.

5. The method for manufacturing a SONOS memory according to claim 1, wherein: In the step of depositing a select gate mask layer on the select gate polysilicon, the select gate mask layer is made of silicon nitride and has a thickness of 100 Å to 200 Å.

6. The method for manufacturing a SONOS memory according to claim 1, wherein: In the step of performing a first self-aligned dry etching on the select gate mask layer using the select gate polysilicon as an etch stop layer to remove the select gate mask layer covering the front surface of the select gate polysilicon, the first self-aligned dry etching is a non-selective dry etching.

7. The method for manufacturing a SONOS memory according to claim 1, wherein: In the step of removing the remaining select gate mask layer covering the side surface of the select gate polysilicon by wet etching, the remaining select gate mask layer covering the side surface of the select gate polysilicon is removed by phosphoric acid wet etching.

8. The method for manufacturing a SONOS memory according to claim 1, wherein: The storage area stacking structure and the remaining selection gate polysilicon are subjected to a third self-aligned dry etching to thin the storage area stacking structure and the selection gate polysilicon in the longitudinal direction. In the step where the remaining selection gate polysilicon is flush with the storage area stacking structure in the longitudinal direction, the third self-aligned dry etching is a non-selective dry etching.

9. The method for manufacturing a SONOS memory according to claim 1, wherein: The fourth self-aligned dry etching is performed on the remaining select gate polysilicon to thin the select gate polysilicon in the longitudinal direction so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than that of the storage area stacking structure. The fourth self-aligned dry etching has a higher etching rate for the select gate polysilicon than for the storage area stacking structure.

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