Non-volatile memory and corresponding manufacturing method

Abstract

The invention relates to a non-volatile memory and a corresponding manufacturing method. A non-volatile memory device includes a memory cell including: a control gate vertically buried in a semiconductor substrate doped with a dopant of a first type; and a dielectric interface capable of trapping charges, covering a side of the control gate facing the semiconductor substrate. The device also includes a vertically implanted region of dopants of a second type opposite the first type in the semiconductor substrate along a side of the control gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French Application No. 2306973, filed on June 30, 2023, which is hereby incorporated by reference. Technical Field

[0003] Embodiments and implementations relate to integrated circuits, in particular to integrated circuits including non-volatile memory devices such as so-called charge trap memories. Background Art

[0004] Conventional non-volatile memories are generally based on the use of transistors including a conductive floating gate region for storing charge in a non-volatile manner in order to encode the stored data.

[0005] In charge trap memories, the charges are stored in "charge traps" at the dielectric interface. For example, the dielectric charge trapping interface may comprise a silicon nitride layer which may be framed on either side by a silicon oxide layer ("sandwiched"), in which case one may mention a technology of the "SONOS" type (standing for "Silicon Oxide Nitride Silicon"). There are other charge trapping technologies such as silicon-rich (often "Si-Rich" in English) dielectrics or so-called silicon "nanocrystal" technologies.

[0006] Typically, conventional charge trap memory includes a conventional planar transistor structure in which a dielectric gate layer is composed of a dielectric charge trapping interface. Therefore, conventional charge trap memory technology does not have a large advantage in terms of surface area compared to floating gate transistor technology.

[0007] Furthermore, conventional charge trap memories may allow programming (arbitrarily, writing a "0" or "1", respectively) at a granularity of one bit, but typically require erasure (arbitrarily, writing a "1" or "0", respectively) at a larger granularity (e.g., the granularity of a page, which is the physically defined size of a row of memory cells).

[0008] This is because conventional erase operations are implemented by the Fowler-Nordheim effect controlled by a high voltage between the control gate and the semiconductor substrate, typically with a negative potential in the control gate and a positive or zero potential in the substrate. Therefore, conventional erase potentials are selective only on a group of memory cells that share the same control gate (typically, a row).

[0009] Therefore, there is a need to benefit from a more compact charge trap memory having a granularity (eg, a granularity of one bit) that is advantageous for both write operations in programming and erasing, while limiting the number of manufacturing steps in order to reduce fabrication costs. Summary of the invention

[0010] According to one aspect, in this regard, a non-volatile memory device, for example fabricated in an integrated circuit in an integrated manner, is proposed, the non-volatile memory device comprising a memory cell, the memory cell comprising: a control gate vertically buried in a semiconductor substrate doped with a first type (e.g., p-type) of dopant; and a dielectric interface capable of trapping charges, covering the side of the control gate facing the semiconductor substrate. Each memory cell also comprises a vertically implanted region of a second type (e.g., n-type) of dopant opposite to the first type, the vertically implanted region being located in the semiconductor substrate along said side of the control gate.

[0011] First, the vertical arrangement of the control gate and dielectric interface structures buried in the substrate greatly reduces the surface area of ​​the substrate occupied by each memory cell.

[0012] Secondly, the vertical implantation region in the semiconductor substrate along the side of the control gate is doped with a type opposite to that of the substrate, which makes it possible to provide a source of minority charge carriers in the substrate without forming an inversion channel in the substrate. Thus, for deletion, it is possible to benefit from the same selectivity as for programming, the selectivity of programming being advantageously obtained by means of the formation of an inversion channel, while deletion does not cause an inversion channel.

[0013] According to one embodiment, each memory cell includes a first conduction region doped with a second type of dopant located at a top surface in the substrate and at one side of the control gate, and a second conduction region doped with the second type of dopant located in the substrate at a depth at the bottom of a trench containing the control gate.

[0014] The first conduction region (e.g. the drain region) in particular makes it possible to selectively access the memory cells individually via tracks (often referred to as bit lines); whereas the second conduction region (e.g. the source region) is advantageously common to all or part of the memory cells belonging to the same group (e.g. a row) or even a memory plane.

[0015] It should also be noted that the first conduction region is located on only one side of the control gate, so that the same control gate structure can be common to two memory cells (each having its drain region on a respective side of the control gate), which are often distinguished by the terms "even" and "odd". This is also advantageous in terms of surface area.

[0016] According to one embodiment, the device further comprises writing means configured to generate deletion conditions suitable for injecting hot charge carriers of a first sign (eg positive sign) from said vertical injection region as a source of charge carriers of the first sign into the dielectric interface.

[0017] Thus, in the case where the first type of dopant (i.e., the type of the substrate) is p-type, and the vertical injection region located along said side of the control gate is n-type, this corresponds to a deletion condition that realizes the injection of hot carriers of positive charge, i.e., the injection of hot "holes" (first sign is positive). And, unlike the deletion by global extraction of the trapped charge by the Fowler-Nordheim effect realized between the control gate and the substrate; the deletion by injection of hot holes corresponds to the recombination of the negative charge (electrons) contained in the trap with the positive charge (holes) injected into the same trap and coming from the source of said positive charge carriers. Therefore, the deletion by injection of hot holes is not global and can be selective for individual memory cells.

[0018] According to one embodiment, the writing device is configured to generate a deletion condition comprising biasing the control gate at a potential of a second sign (eg, negative sign) and biasing the vertical injection region at a potential of a first sign (eg, positive sign).

[0019] This corresponds to the above-mentioned example of conditions for deletion by selective injection of hot holes for each memory cell.

[0020] According to one embodiment, the writing device is configured to generate: biasing the vertical injection region with a non-zero potential of a first sign in the first conduction region and with a zero reference potential in the second conduction region, or biasing the vertical injection region with a non-zero potential of a first sign in the second conduction region and with a zero reference potential in the first conduction region.

[0021] This is because, depending on the voltage orientation between the conducting regions, for example from source to drain (or drain to source, respectively), the electric field will be strongest at the pn junction between drain and substrate (or source and substrate, respectively).

[0022] However, impact ionization, ie the generation of hot carriers, will occur where the electric field is strongest, ie at one or other of the pn junctions.

[0023] Thus, two different impact ionization regions can be provided in the same memory cell, and thus two regions of the dielectric interface for trapping charge by injecting hot carriers can be provided. This advantageously enables each memory cell to independently store two bits.

[0024] Furthermore, when two memory cells share the same control gate structure, the single control gate structure thus enables access to four bits, each of which is selectively individually accessible in erasing, programming, and reading.

[0025] According to one embodiment, the writing device is also configured to generate programming conditions suitable for injecting hot charge carriers of a second sign (e.g., a negative sign) from a channel region formed in the semiconductor substrate along the side of the control gate as a source of charge carriers of the second sign into the dielectric interface.

[0026] According to one embodiment, the writing means is further configured to generate a programming condition comprising biasing the control gate at a potential of a first sign.

[0027] According to one embodiment, the vertical implantation region is doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 Among the second type of dopants, the semiconductor substrate is doped with a concentration less than 5×10 15 Atom / cm 3 of the first type of dopant.

[0028] And, for example, the first conductive region may be doped with a concentration of 10 18 Atom / cm 3 and 10 20 Atom / cm 3 The second conductive region may be doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 The second type of dopant between.

[0029] According to one embodiment, the buried control gate belongs to a trench extending vertically in the substrate and superposes the select gate in the trench.

[0030] According to another aspect, a method for manufacturing a non-volatile memory device including memory cells is also proposed, the manufacturing of each memory cell including: forming a control gate vertically buried in a semiconductor substrate doped with a first type of dopant; forming a dielectric interface capable of capturing charges, covering the side of the control gate facing the semiconductor substrate; and also forming a vertical injection region of a second type of dopant opposite to the first type, the vertical injection region being located in the semiconductor substrate along the side of the control gate.

[0031] According to one embodiment, the manufacturing of each memory cell includes: forming a first conduction region, which is doped with a second type of dopant, located at the top surface in the substrate and at one side of the control gate; and forming a second conduction region, which is doped with a second type of dopant, located at a depth at the bottom of a trench in the substrate containing the control gate.

[0032] According to one embodiment, a write operation is also included, the write operation including generating a deletion condition that produces an injection of hot charge carriers of a first sign (eg, a positive sign) from the vertical injection region as a source of charge carriers of the first sign into the dielectric interface.

[0033] According to one embodiment, the write operation includes generating a delete condition including biasing the control gate at a potential of a second sign (eg, a negative sign) and biasing the vertical implant region at a potential of a first sign.

[0034] According to one embodiment, the write operation comprises generating: biasing the vertical injection region with a non-zero potential of a first sign in the first conduction region and with a zero reference potential in the second conduction region, or biasing the vertical injection region with a non-zero potential of a first sign in the second conduction region and with a zero reference potential in the first conduction region.

[0035] According to one embodiment, the writing device also includes generating programming conditions that produce injection of hot charge carriers of a second sign (e.g., a negative sign) from a channel region formed in the semiconductor substrate along the side of the control gate as a source of charge carriers of the second sign into the dielectric interface.

[0036] According to one embodiment, the write operation further includes generating a programming condition including biasing the control gate at a potential of a second sign.

[0037] According to one embodiment: the formation of the control gate and the formation of the dielectric interface include etching a vertically sunken trench in the semiconductor substrate; and the formation of the vertical injection region of the second type of dopant includes, before forming the dielectric interface in the trench and the corresponding material of the control gate: forming a sacrificial body doped with the second type of dopant filling the trench; diffusing the dopant of the sacrificial body in the semiconductor substrate along the side of the trench; and removing the sacrificial body from the trench.

[0038] According to one implementation, the vertical implanted region is doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 Among the second type of dopants, the semiconductor substrate is doped with a concentration less than 5×10 15Atom / cm 3 of the first type of dopant.

[0039] And, for example, the first conductive region may be doped with a concentration of 10 18 Atom / cm 3 and 10 20 Atom / cm 3 The second conductive region may be doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 The second type of dopant between.

[0040] According to one embodiment, the fabrication of each memory cell further comprises: forming a select gate in a trench extending vertically in the semiconductor substrate; and forming the control gate in the trench on top of the select gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other advantages and features of the present invention will become apparent upon examination of the detailed description of non-limiting embodiments and implementations and from the accompanying drawings, in which:

[0042] Figure 1 illustrates the results of etching a trench in a semiconductor substrate doped with a first type of dopant and including an implanted region in accordance with an embodiment;

[0043] Figure 2 illustrates the result of forming a "sacrificial" oxide layer on the sides and bottom of the trench in accordance with an embodiment;

[0044] Figure 3 illustrates the result of forming a first conductive gate material according to an embodiment;

[0045] Figure 4 illustrates the result of removing the first conductive gate material at a height less than the trench depth in accordance with an embodiment;

[0046] Figure 5 illustrates the results of a first example of a vertical implanted region of a second type of dopant formed in a semiconductor substrate and located along the sides of a trench in accordance with an embodiment;

[0047] FIG. 6A to FIG. 6D A second example of a vertical implantation region of a second type of dopant formed in a semiconductor substrate along the side of a trench is illustrated, wherein Fig. 6A The diagram shows the result of forming a fine sacrificial oxide layer on the sides and bottom of the already formed trench, where Figure 6B The diagram shows the result of forming a sacrificial body highly doped with a second type of dopant in an already formed trench, wherein Figure 6C The result of dopant diffusion from a sacrificial body through a fine sacrificial oxide layer into a semiconductor substrate is shown, and wherein Fig.6D The results after dopant annealing and stabilization are shown;

[0048] Figure 7 illustrates the result after forming vertical implant regions in the semiconductor substrate along the sides of the trench;

[0049] Figure 8 The result of forming the first silicon oxide layer is shown;

[0050] Fig. 9 illustrates the result of forming a silicon nitride layer on the first oxide layer;

[0051] Fig.10 The diagram shows the result of forming a second silicon oxide layer on the silicon nitride layer;

[0052] Fig.11 illustrates the result of forming a second conductive gate material;

[0053] Fig.12 illustrates the result of planarization in which all layers located above the front side of the substrate have been removed;

[0054] Fig.13 illustrates an example of an implementation of a non-volatile memory device including a "SONOS" type memory cell;

[0055] Fig.14 An example of an implementation of a non-volatile memory device including a "SONOS" type memory cell is shown as an example of an implementation of a non-volatile memory device including a "SONOS" type memory cell. Fig.13 Alternatives to the described implementations;

[0056] Fig.15A , Fig. 15B and Fig. 15C The diagram shows the previous Fig.13 The principle of the write operation in the example of the memory cell CEL1 is described, and the write operation generally includes programming and / or erasing, wherein Fig.15A The programming conditions that produce the injection of negatively charged hot carriers into charge traps at the dielectric interface are illustrated, where Fig. 15B The "global" deletion conditions for extracting charge stored in charge traps at dielectric interfaces through the Fowler-Nordheim effect are illustrated, and wherein Fig. 15C illustrates deletion conditions that favorably produce injection of positively charged hot carriers;

[0057] Fig.16A , Fig. 16B , Fig. 16C and Fig.16DThe diagram shows that Fig.14 The selective by bit deletion condition in the case of the implementation of the memory cell without the select gate is described, wherein Fig.16A The first erasure condition of the odd memory cells is shown, where Fig. 16B The second deletion condition of the odd memory cells is shown, wherein Fig. 16C The first erasure condition of the even memory cells is shown, where Fig.16D illustrates a second erasure condition for even-numbered memory cells; and

[0058] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D The diagram shows that Fig.14 The bit-selective programming conditions are described in the case of an implementation of a memory cell without a select gate, wherein Fig.17A illustrates a first programming condition for odd memory cells which may be, for example, the same as the first erase condition for odd memory cells but with the control gate biased at a positive high voltage potential, wherein Fig. 17B A first programming condition of odd memory cells is illustrated which may be, for example, the same as the second erasing condition of odd memory cells but with the control gate biased at a positive high voltage potential, wherein Fig. 17C illustrates a first programming condition for even memory cells which may be, for example, the same as the first deletion condition for even memory cells but with the control gate biased at a positive high voltage potential, and wherein Fig.17D illustrates a second programming condition for the even memory cells which may, for example, be the same as the second erase condition for the even memory cells but with the control gates biased at a positive high voltage potential; and

[0059] Fig.18 Conditions for selectively accessing the first bits of the odd-numbered memory cells in the read mode are illustrated in the first table, and conditions for selectively accessing the second bits of the odd-numbered memory cells in the read mode are illustrated in the second table. DETAILED DESCRIPTION

[0060] Figures 1 to 12 The diagram shows the method for manufacturing Fig.13 and Fig.14 The results of the steps of the method are shown for a "SONOS" (acronym for the common term "Silicon Oxide Nitride Silicon" well known to those skilled in the art) charge trapping type memory cell.

[0061] In this regard, reference Fig.13 .

[0062] Fig.13An example of an implementation of a non-volatile memory device comprising memory cells CEL1 , CEL2 of the “SONOS” type is illustrated.

[0063] The control gate CG is vertically buried in the semiconductor substrate SUB doped with a first type (eg, p-type) dopant.

[0064] In this regard, the control gate CG is advantageously formed in an opening, called a trench, etched vertically to a certain depth in the substrate SUB starting from the front side FA of the substrate.

[0065] The control gate CG may advantageously be common to two memory cells CEL1, CEL2, which are often designated respectively "odd cell" CEL1 and "even cell" CEL2. The two memory cells CEL1, CEL2 are located on either side (horizontally) of the vertical control gate CG.

[0066] A dielectric interface ITFD capable of trapping charges covers the side of the control gate CG facing the semiconductor substrate SUB.

[0067] In this regard, prior to forming the control gate CG, a dielectric interface ITFD is advantageously formed in the trench containing the control gate CG to encapsulate the sides FL1 , FL2 of the control gate CG and the bottom of the control gate CG.

[0068] For example, the dielectric interface ITFD includes a series of layers of silicon oxide O, silicon nitride N, and silicon oxide O. In summary, the silicon nitride N layer is able to store charges in "charge traps", while the oxide O layer has an electrical insulation function of the gate oxide type.

[0069] Furthermore, each memory cell CEL1, CEL2 further comprises a vertical implantation region AdVt of a second type of dopant opposite to the first type (i.e., n-type in this example), which is located in the semiconductor substrate SUB along the sides FL1, FL2 of the control gate CG and therefore along the dielectric interface ITFD.

[0070] It is certain that since each of the memory cells CEL1, CEL2 is located beside a respective side of the control gate CG, the vertical implantation region AdVt of the respective memory cell CEL1, CEL2 is located in the substrate SUB along the respective side FL1, FL2 and along the respective dielectric interface ITFD.

[0071] In addition, the memory cells CEL1 and CEL2 each include a first conduction region D1 and D2, such as a drain region, doped with a second type (in this example, n-type) dopant, which is located at the substrate top interface (i.e., the front side FA) in the substrate SUB and on the corresponding side of the control gate CG.

[0072] The front side FA of the substrate SUB corresponds to the surface on which the metal contacts CNT are coupled in order to connect the elements ( D1 , CG, D2 ) of the semiconductor substrate with the metal tracks of an interconnection grid (not shown, conventional and known per se).

[0073] Furthermore, the memory cells CEL1, CEL2 each comprise a second conduction region S-NISO, for example a source region, doped with dopants of the second type (n-type in this example) and located at the depth of the bottom FD of the trench containing the control gate CG in the substrate SUB.

[0074] For example, the second conductive region S-NISO belongs to a “source plane” of the isolated well (“NISO”) type of a triple well structure, ie, a region implanted at a certain depth in the substrate.

[0075] Furthermore, in this example, the memory cells CEL1 , CEL2 comprise a select gate SG also in the trench containing the control gate CG, between the control gate CG and the bottom FD of the trench.

[0076] The select gate SG is electrically isolated from the substrate SUB and the source region S-NISO by a dielectric gate encapsulation Dsg. The select gate SG is also isolated from the control gate by a dielectric layer.

[0077] For example, in practice: a semiconductor substrate SUB, which is usually made of silicon, may be doped with a concentration of 10 14 Atom / cm 3 and 5×10 15 Atom / cm 3 The first conductive regions D1 and D2 may be doped with boron at a concentration of 10 18 Atom / cm 3 and 10 20 Atom / cm 3 The second conductive region S-NISO may be doped with arsenic at a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 The vertical implant region AdVt may be doped with phosphorus at a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm3 Phosphorus (or arsenic) between.

[0078] Fig.14 An example of an implementation of a non-volatile memory device comprising "SONOS" type memory cells CEL1, CEL2 is shown as an example for Fig.13 Alternatives to the described implementations.

[0079] In this alternative, the memory cells CEL1, CEL2 do not include a select gate SG or a corresponding dielectric gate encapsulation Dsg.

[0080] Other elements of the device and memory cells CEL1, CEL2 bear the same reference numerals and are referred to in detail in the accompanying drawings. Fig.13 The entire remainder of the description given applies to Fig.14 An alternative example in .

[0081] Now, refer to Figures 1 to 12 .

[0082] Figure 1 The result of a step 100 of etching a trench TR in a semiconductor substrate SUB doped with dopants of a first type, ie for example p-type, and comprising an n-doped region S-NISO implanted at a certain depth in the substrate SUB is illustrated.

[0083] Figure 2 The result of step 200 of forming a "sacrificial" oxide layer SACOX on the sides and bottom of the trench TR is shown. However, the sacrificial oxide layer SACOX will form the future selection gate SG ( Figure 3 and below) of gate oxide Dsg( Fig.13 ). For example, the sacrificial layer SACOX may have a thickness between 5 nm and 10 nm.

[0084] Figure 3 The result of step 300 of forming a first conductive gate material P0, for example made of doped polysilicon, is illustrated. The first gate material P0 is deposited in excess to fill the trench and also overflow over the front side FA.

[0085] Figure 4 The result of the etching step 400 of removing the first gate material P0 at a height less than the depth of the trench TR (e.g., a height between 50% and 90% of the trench depth) is illustrated. For example, at this point, the etching 400 is performed within a period parameterized according to an etching rate. In addition, the etching 400 is configured to be selective with respect to silicon oxide so as not to etch or to etch very little of the sacrificial oxide layer SACOX so as to protect the substrate SUB from the effects of the etching 400.

[0086] Figure 5 The result of a first example of step 500 of forming vertical implanted regions AdVt of a dopant of the second type, ie, n-type, in the semiconductor substrate SUB and positioned along the side faces FLTr1 , FLTr2 of the trench TR is illustrated.

[0087] In this first example, this vertical orientation of the implanted region AdVt may be obtained by implementing a first oblique implantation TLTIMP1 to obliquely expose a first side of the trench FLTr1 and a second oblique implantation TLTIMP2 to obliquely expose a second side of the trench FLTr2 .

[0088] FIG. 6A to FIG. 6D A preferred second example of vertical implantation regions AdVt of a second type (ie, n-type) dopant formed in the semiconductor substrate SUB along the sides FLTr1 , FLTr2 of the trench TR is illustrated.

[0089] This is because it may be difficult to achieve uniform channel implantation vertically along the lateral walls of the trench using tilted implantation techniques, particularly depending on the form factor.The second example described advantageously enables uniform formation of the vertical implant region AdVt around the vertical trench.

[0090] Fig. 6A The result of step 610 of forming a fine sacrificial oxide layer SACOX_Thn on the side surfaces FLTr, FLTr and the bottom of the trench TRd that has been formed is illustrated.

[0091] In particular, the fine sacrificial oxide layer SACOX_Thn is better than previously Figure 2 The sacrificial oxide layer SACOX is described to be finer. For example, the fine sacrificial oxide layer SACOX_Thn has a thickness of less than 5 nm. In particular, the fine sacrificial oxide layer SACOX_Thn is not intended to form a dielectric gate region, and in this regard, there is no minimum thickness constraint.

[0092] In with Fig.13 In the embodiment corresponding to the example of Figure 4 The groove TR in Figure 4 Any portion of the sacrificial oxide layer SACOX not covered by the first gate material P0 is removed.

[0093] In with Fig.14 In the embodiment corresponding to the example of Figure 1 The groove TR in the.

[0094] Figure 6BThe result of step 620 of forming a sacrificial body highly doped with a second type (i.e., n-type) dopant SACPOLYN+ in the already formed trench TRd is shown. For example, the sacrificial body SACPOLYN+ is formed of a conductive gate material such as polysilicon and is, for example, formed in the manner previously described for Figure 3 Described in a manner of formation.

[0095] Figure 6C The result of step 630 of diffusing n-type dopants from the sacrificial body SACPOLYN+ through the fine sacrificial oxide layer SACOX_Thn into the semiconductor substrate SUB is illustrated.

[0096] At the end of the diffusion 630 , the distribution of the n-type doping, ie the spatial variation of the concentration of the dopant in the substrate SUB, may have a “droplet” form caused by the acute shape of the trench.

[0097] Fig.6D The result of step 640 is illustrated, in which annealing and stabilization of the dopants are carried out, so that the distribution of the n-type doping obtained by the diffusion of step 630 is made uniform along the side faces FLTr of the trench TRd.

[0098] In addition, step 640 includes, for example, following the same procedure as previously described for Figure 4 The same type of etching is described to remove the sacrificial body.

[0099] Figure 7 The result of step 700 after the formation 500 , 610 - 640 of n-type vertical implanted regions AdVt in the semiconductor substrate SUB along the sides FLTr1 , FLTr2 of the trench TR (ie along the sides of the future control gate CG) and along the future charge trapping dielectric interface ITFD is illustrated.

[0100] In with Fig.13 In the embodiment corresponding to the example in Figure 5 After forming 500 as described above), step 700 corresponds to removing the sacrificial oxide layer SACOX at any place of the sacrificial oxide layer SACOX that is not covered by the first gate material P0; or alternatively, Fig.14 In the embodiment corresponding to the example in FIG. 6A to FIG. 6D After the formation 610 - 640 described above), step 700 corresponds to removing the fine sacrificial oxide layer SACOX_Thn.

[0101] Figure 8 The result of step 800 of forming a first silicon oxide layer O, for example by means of a standard deposition, ie a deposition resulting in the first silicon oxide layer O having a uniform and constant thickness, whatever the orientation of the deposition surface (vertical or horizontal), is illustrated.

[0102] Fig. 9 The result of step 900 of forming a silicon nitride layer N on a first oxide layer O in a standard manner is shown.

[0103] Fig.10 The result of step 1000 of forming a second silicon oxide layer O on a nitride layer N in a standard manner is shown.

[0104] For example, each of the oxide, nitride layers of the stacked ONO may have a thickness between 5 nm and 10 nm.

[0105] In targeting Figure 8 , Fig. 9 and Fig.10 At the end of the described steps 800, 900, 1000, a dielectric interface ITFD has been formed capable of trapping charges, in particular in "charge traps" of the silicon nitride layer N. The dielectric interface is intended to cover the side of the future control gate CG facing the semiconductor substrate SUB.

[0106] Fig.11 The result of step 1100 of forming a second conductive gate material P2 , for example made of doped polysilicon, is illustrated.

[0107] The second gate material P2 is deposited in excess to fill the trench TR (ie the volume remaining inside the trench TR between the sides and the bottom of the stack of dielectric layers ONO at the interface ITFD) and overflow onto the stack of dielectric layers ONO over the front side FA.

[0108] Fig.12 The result of the planarization step 1200 is illustrated in which all layers located above the front side FA of the substrate SUB have been removed.

[0109] This type of removal 1200 is achieved, for example, by a chemical-mechanical planarization technique “CMP”.

[0110] In this way, a vertically buried control gate structure CG is formed in the substrate SUB together with the second gate material P2, as previously described for Fig.13 or Fig.14 and, using the first gate material P0, a selection gate structure SG has been formed, as previously described for Fig.13 Described.

[0111] Thus, after step 1300 of implanting the drain regions D1, D2, forming the metal contacts CNT and the rest of the integrated circuit manufacturing chain, the previously described Fig.13 or when there is no select gate SG Fig.14A memory device is described.

[0112] Furthermore, it should be noted that each select gate SG may be common to a group of even and odd memory cells CEL1, CEL2, often referred to as a "page" (typically, a physically organized row of a memory plane containing all memory cells and comprising a subset referred to as a "word"). A word may, for example, comprise one or more bytes and have a control gate CG common to even and odd memory cells CEL1, CEL2 belonging to the same word.

[0113] Fig.15A , Fig. 15B and Fig. 15C The diagram shows the previous Fig.13 The principles of a write operation in the example of the memory cell CEL1 are described which generally include programming and / or erasing.

[0114] In the remainder of this description, it is conventionally considered that programming of a memory cell corresponds to the writing of a data item "0" (according to an arbitrary example of the convention), while erasure of a memory cell corresponds to the writing of a data item "1" (according to the same example). It is also conventionally considered that programming is obtained by trapping charges with a negative sign (i.e., electrons); and erasure is obtained by repelling the trapped negative charges or, advantageously, by injecting charges with a positive sign (i.e., holes) so as to recombine with the trapped negative charges.

[0115] Also by convention, and consistent with the above Figures 1 to 14 Consistent with the example given (according to which the first type of dopant is p-type and the second type of dopant is n-type), the positive sign of charge and potential (unit: volts) is considered to be the "first sign" and the negative sign of charge and potential (unit: volts) is considered to be the "second sign".

[0116] Fig.15A The programming condition PRHT is illustrated which produces the injection of negatively charged hot carriers (ie, “hot electrons” HTe-) in charge traps at the dielectric interface ITFD.

[0117] The programming condition PRHT includes biasing the control gate CG at a positive high voltage potential, for example substantially +9V (volts), so that hot electrons HTe- can come from a channel region CNL formed in the semiconductor substrate along the sides of the control gate CG. Therefore, the channel region CNL forms a source of hot negative charge carriers.

[0118] Furthermore, the programming condition PRHT may include biasing the drain D1 of the selected memory cell CEL1 at a moderately positive potential, e.g., substantially +4.5 V; applying an activation potential (substantially 1.5 V in an example) in the selection gate SG that enables the channel region CNL to continue along the selection gate SG as far as the source S-NISO; biasing the source S-NISO and the substrate SUB at a zero reference voltage 0V; and floating the potential in the drain D2 of all other memory cells CEL2, and making the blocking potential in the unselected selection gates, e.g., 0V.

[0119] Fig. 15B The diagram shows the “global” deletion condition ERFD that extracts the charges stored in the charge traps at the dielectric interface ITFD through the Fowler-Nordheim effect.

[0120] These global delete conditions ERFD include biasing the control gate CG at a so-called shared negative high voltage potential, eg substantially -10V, and biasing the substrate SUB at a medium positive voltage also shared, eg substantially +5V, so that the trapped electrons are repelled by traps of the nitride layer N to the substrate SUB.

[0121] Furthermore, the conditions for global erasure by the Fowler-Nordheim effect ERFD may further include biasing drains D1 , D2 , select gates SG and sources S-NISO of all memory cells in the erased (selected) row at a shared positive potential of substantially 5V.

[0122] Under conditions where a Fowler-Nordheim effect is obtained between the control gate CG and the substrate SUB, all even and odd memory cells CEL1, CEL2 belonging to the same row are deleted by these conditions ERFD. This is disadvantageous in itself.

[0123] Fig. 15C The diagram illustrates a preferential erasure condition ERFD that favorably produces hot carriers with positive charges (ie, "hot holes" HTh+) that are injected into charge traps at the dielectric interface ITFD to recombine with negative charges in the traps.

[0124] The priority erasure condition ERHT has the advantage of bitwise selectivity, ie, each bit of each memory cell CEL1 can be selectively erased relative to other bits of memory cells CEL2 in the same row or the same memory word.

[0125] This is because the preferential deletion condition ERHT includes biasing the control gate CG at a negative high voltage potential, for example substantially -9V (volts). This strong negative potential of the control gate CG prevents the formation of a channel region CNL in the substrate SUB. However, despite the absence of the channel region CNL (and therefore the absence of a source of charge carriers such as for programming PRHT), a high current can circulate in the injection vertical region AdVt, provided that a sufficiently high drain potential D1 is present. The high positive drain potential D1 causes the formation of hot holes HTh+ by impact ionization. Therefore, the current circulating in the vertical injection region AdVt of the odd cell CEL1 forms a source of hot positive charge carriers HTh+.

[0126] Furthermore, the preferential erasure conditions ERHT are bit-wise selective, since they consist in biasing the drain D1 of the selected memory cell CEL1 at a moderately high positive potential, for example substantially +4.5V.

[0127] In addition, the preferred condition ERHT for selective erasure by bit includes applying an activation potential (e.g., substantially 2.5V) in the select gate SG that can generate an electrically continuous channel region between the vertical injection region AdVt and the source S-NISO along the select gate SG; biasing the source S-NISO and the substrate SUB at a zero reference voltage 0V; and floating the potential in the drain D2 of all other memory cells CEL2. The unselected select gates may be placed at a blocking potential, e.g., 0V.

[0128] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D The diagram shows that Fig.14 The bit-selective priority erasure condition ERHT is described for the implementation of a memory cell without a select gate SG.

[0129] FIG. 16A to FIG. 16D Another advantageous capability of the preferential erasure condition ERHT is also illustrated, allowing two independent bits to be stored in the same odd memory cell CEL1 or even memory cell CEL2.

[0130] This is because, at this point, the first erasure condition ERHT_1_up ( Fig.16A ), the first erasing condition ERHT_2_up of the even memory cell CEL2 ( Fig. 16C ), the second erasing condition ERHT_1_dwn ( Fig. 16B ), the second erasing condition ERHT_2_dwn ( Fig.16D ).

[0131] Fig.16A A first erase condition ERHT_1_up of the odd memory cell CEL1 of the vertical implant area AdVt is illustrated with a non-zero positive potential (eg 4.5 V) in the first conduction area D1 and with a zero reference potential 0 V in the second conduction area S-NISO.

[0132] Furthermore, a negative high voltage, for example, -9V, is applied in the control gate CG, and the first conduction regions D2 of the even memory cells CEL2 sharing the same control gate CG are maintained at a floating potential at a high impedance Hz.

[0133] Fig. 16B The second delete condition ERHT_1_dwn of the odd memory cell CEL1 biasing the vertical implantation area AdVt with a zero positive potential 0V in the first conduction area D1 and with a non-zero reference potential (eg 4.5V) in the second conduction area S-NISO is illustrated.

[0134] Furthermore, a negative high voltage, for example, -9V, is applied in the control gate CG, and the first conduction regions D2 of the even memory cells CEL2 sharing the same control gate CG are maintained at a floating potential at a high impedance Hz.

[0135] Fig. 16C A first erase condition ERHT_2_up of the even memory cells CEL2 of the vertical implantation area AdVt is illustrated in which the even memory cells CEL2 are biased with a non-zero positive potential (eg 4.5 V) in the first conduction area D2 and with a zero reference potential 0 V in the second conduction area S-NISO.

[0136] Furthermore, a negative high voltage, for example, -9V, is applied in the control gate CG, and the first conduction regions D1 of the odd-numbered memory cells CEL1 sharing the same control gate CG are maintained at a floating potential at a high impedance Hz.

[0137] Fig.16D The second delete condition ERHT_2_dwn of the even memory cells CEL2 of the vertical implantation region AdVt biased with a zero positive potential 0V in the first conduction region D2 and with a non-zero reference potential (eg 4.5V) in the second conduction region S-NISO is illustrated.

[0138] Furthermore, a negative high voltage, for example, -9V, is applied in the control gate CG, and the first conduction regions D1 of the odd-numbered memory cells CEL1 sharing the same control gate CG are maintained at a floating potential at a high impedance Hz.

[0139] This is because, depending on the voltage orientation between the conducting regions, eg from source to drain, in the case of the first delete condition ERHT_1_up, ERHT_2_up, the electric field will be strongest at the pn junction between the drain D1, D2 and the substrate SUB.

[0140] And, in the voltage orientation between the conduction regions from drain to source in the case of the second deletion conditions ERHT_1_dwn, ERHT_2_dwn, respectively, the electric field will be strongest at the pn junction between the source S-NISO and the substrate SUB.

[0141] However, impact ionization IMPCT_1_up, IMPCT_1_dwn, IMPCT_2_up, IMPCT_2_dwn, ie the generation of hot carriers, will occur wherever the electric field is strongest, ie at one or the other of the pn junctions.

[0142] Therefore, two different impact ionization regions IMPCT_1_up, IMPCT_1_dwn may be provided in the same odd memory cell CEL1 , and two different impact ionization regions IMPCT_2_up, IMPCT_2_dwn may be provided in the same even memory cell CEL2 , respectively.

[0143] Therefore, each odd memory cell CEL1 or even memory cell CEL2 includes two regions of the dielectric interface ITFD for trapping charges by injecting hot holes. This advantageously allows each memory cell to independently store two bits.

[0144] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D The diagram shows that Fig.14 The bit-selective priority programming condition PRHT in the case of an implementation of a memory cell without a select gate SG is described.

[0145] The programming conditions have the same advantageous ability to store two independent bits in the same odd memory cell CEL1 or even memory cell CEL2.

[0146] In this regard, reference will be made to:

[0147] Fig.17A , which illustrates a first programming condition PRHT_1_up of the odd memory cell CEL1 which may, for example, be the same as the first erasing condition ERHT_1_up of the odd memory cell CEL1 but with the control gate CG biased at a positive high voltage potential (eg, +10V).

[0148] Fig. 17B, which illustrates a first programming condition PRHT_1_up of the odd memory cell CEL1 which may, for example, be the same as the second erasing condition ERHT_1_dwn of the odd memory cell CEL1 but with the control gate CG biased at a positive high voltage potential (eg, +10V).

[0149] Fig. 17C , which illustrates a first programming condition PRHT_2_up of the even memory cell CEL2 which may, for example, be the same as the first erasing condition ERHT_2_up of the even memory cell CEL2 but with the control gate CG biased at a positive high voltage potential (eg, +10V).

[0150] Fig.17D , which illustrates a second programming condition PRHT_2_dwn of the even memory cell CEL2 which may be, for example, the same as the second erase condition ERHT_2_dwn of the even memory cell CEL2 but with the control gate CG biased at a positive high voltage potential (eg, +10V).

[0151] The selectivity and positioning mechanism of the two bits IMPCT_1_up, IMPCT_1_dwn, IMPCT_2_up, IMPCT_2_dwn for each odd cell CEL1 and even cell CEL2 is the same as previously described for FIG. 16A to FIG. 16D The description for deleting ERHT_1_up, ERHT_1_dwn, ERHT_2_up, ERHT_2_dwn is the same as PRHT_1_up, PRHT_1_dwn, PRHT_2_up, PRHT_2_dwn.

[0152] Fig.18 Conditions for selectively accessing the first bit (IMPCT_1_up) of the odd memory cell CEL1 in the read mode are first illustrated in table RD_1_up, and conditions for selectively accessing the second bit (IMPCT_1_dwn) of the odd memory cell CEL1 in the read mode are second illustrated in table RD_1_dwn.

[0153] By reversing the bias between the drain regions D1 and D2 of the tables RD_1_up and RD_1_dwn, the condition for accessing two bits of the even memory cell CEL2 in the read mode is obtained.

[0154] Furthermore, writing means ME of conventional design and not shown are provided for implementing the above description for FIG. 15A to FIG. 18The described write operations ERHT, ERFD, PRTH, ERHT_1_up, ERHT_1_dwn, ERHT_2_up, ERHT_2_dwn, PRTH_1_up, PRTH_1_dwn, PRTH_2_up, PRTH_2_up and read operations RD_1_dwn, RD_1_up may include, for example, a charge pump type high voltage generator, logic for transmitting a high voltage to a memory cell, and state machine type logic for timing and controlling the write and read operations.

[0155] In summary, a non-volatile memory of the charge trapping type has been described in which a single vertical control gate structure CG, optionally superimposed on a selection gate SG in a trench and thus having a very small surface footprint on the front side FA of the substrate SUB, makes it possible to access four bits, each of which is selectively accessed individually during erasure, programming and reading.

Claims

1. A non-volatile memory device, comprising: A memory unit comprising: a control gate vertically buried in a semiconductor substrate doped with a first type of dopant, a dielectric interface capable of trapping charges, covering the side of the control gate facing the semiconductor substrate, and A vertically implanted region of a second type of dopant, the second type being opposite to the first type, is located in the semiconductor substrate along the side of the control gate.

2. The device of claim 1 , wherein each memory cell comprises a first conduction region doped with the second type of dopant and a second conduction region doped with the second type of dopant, wherein the first conduction region is located at a top surface in the substrate and at one side of the control gate, and the second conduction region is located at a depth in the substrate at the bottom of a trench containing the control gate.

3. The device according to claim 1, wherein the vertical implantation region is doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 Among the second type of dopants, the semiconductor substrate is doped with a concentration less than 5×10 15 Atom / cm 3 of the first type of dopant.

4. The device of claim 1, wherein the control gate belongs to a trench extending vertically in the substrate and overlies the select gate in the trench.

5. A non-volatile memory device comprising: A memory unit comprising: a control gate vertically buried in a semiconductor substrate doped with a first type of dopant, a dielectric interface capable of trapping charges, covering the side of the control gate facing the semiconductor substrate, and a vertically implanted region of a second type of dopant, the second type being opposite to the first type, the vertically implanted region being located in the semiconductor substrate along a side of the control gate; as well as A write circuit is configured to generate an erase condition suitable for injecting hot charge carriers of a first sign from the vertical injection region into the dielectric interface, the vertical injection region serving as a source of charge carriers of the first sign.

6. A device according to claim 5, wherein each memory cell includes a first conduction region doped with the second type of dopant and a second conduction region doped with the second type of dopant, the first conduction region being located at a top surface in the substrate and at one side of the control gate, and the second conduction region being located at a depth in the substrate at the bottom of a trench containing the control gate. 7 . The device of claim 5 , wherein the write circuit is configured to generate an erase condition comprising biasing the control gate at a potential of a second sign and biasing the vertical injection region at a potential of the first sign.

8. A device according to claim 7, wherein each memory cell includes a first conduction region doped with the second type of dopant and a second conduction region doped with the second type of dopant, the first conduction region being located at the top surface in the substrate and at one side of the control gate, the second conduction region being located at a depth at the bottom of a trench in the substrate containing the control gate, and wherein the write circuit is configured to generate: biasing the vertical injection region with a non-zero potential of the first sign in the first conduction region and biasing the vertical injection region with a zero reference potential in the second conduction region, or biasing the vertical injection region with a non-zero potential of the first sign in the second conduction region and biasing the vertical injection region with a zero reference potential in the first conduction region.

9. The device of claim 7 , wherein the write circuit is configured to generate programming conditions suitable for injecting hot charge carriers of the second sign from a channel region into the dielectric interface, the channel region being formed along a side of the control gate in the semiconductor substrate as a source of charge carriers of the second sign.

10. The device of claim 9 , wherein each memory cell comprises a first conduction region doped with the second type of dopant and a second conduction region doped with the second type of dopant, the first conduction region being located at a top surface in the substrate and at one side of the control gate, the second conduction region being located at a depth in the substrate at the bottom of a trench containing the control gate, and wherein the write circuit is configured to generate the programming condition, the programming condition comprising biasing the control gate at a potential of the second sign.

11. A method for manufacturing a non-volatile memory device, the non-volatile memory device comprising memory cells, the manufacturing of each memory cell comprising: forming a control gate vertically buried in a semiconductor substrate doped with a first type of dopant; forming a dielectric interface capable of trapping charges, covering a side of the control gate facing the semiconductor substrate; and further A vertical implant region of a second type of dopant is formed, the second type being opposite to the first type, the vertical implant region being located in the semiconductor substrate along a side surface of the control gate.

12. The method of claim 11 , wherein the fabrication of each memory cell comprises: forming a first conductive region doped with the second type of dopant, the first conductive region being located at a top surface in the substrate and at one side of the control gate, and A second conductive region doped with the second type of dopant is formed, the second conductive region being located at a depth of a bottom of a trench in the substrate containing the control gate.

13. The method of claim 12 further comprising a write operation comprising generating an erase condition that produces an injection of hot charge carriers of a first sign from the vertical injection region into the dielectric interface, the vertical injection region serving as a source of charge carriers of the first sign. 14 . The method of claim 13 , wherein the writing operation comprises generating an erase condition, the erase condition comprising biasing the control gate at a potential of a second sign and biasing the vertical injection region at a potential of the first sign.

15. The method of claim 14, wherein the write operation comprises generating: biasing the vertical injection region with a non-zero potential of the first sign in the first conduction region and biasing the vertical injection region with a zero reference potential in the second conduction region, or biasing the vertical injection region with a non-zero potential of the first sign in the second conduction region and biasing the vertical injection region with a zero reference potential in the first conduction region.

16. The method of claim 14 , wherein the write operation further comprises generating a programming condition that produces an injection of hot charge carriers of the second sign from a channel region into the dielectric interface, the channel region being formed in the semiconductor substrate along the side of the control gate as a source of charge carriers of the second sign. 17 . The method according to claim 16 , wherein the writing operation further comprises generating a programming condition, the programming condition comprising biasing the control gate CG at a potential of the second sign.

18. The method of claim 11, wherein: The forming of the control gate and the forming of the dielectric interface include etching a trench vertically sunken in the semiconductor substrate; as well as Forming the vertical implant region of the second type of dopant comprises, before forming the dielectric interface in the trench and the corresponding material of the control gate: forming a sacrificial body filling the trench, the sacrificial body being doped with the second type of dopant; diffusing dopants of the sacrificial body in the semiconductor substrate along sides of the trench; and The sacrificial body is removed from the trench.

19. The method according to claim 11, wherein the vertical implantation region is doped with a concentration of 5×10 15 Atom / cm 3 and 10 18 Atom / cm 3 Among the second type of dopants, the semiconductor substrate is doped with a concentration less than 5×10 15 Atom / cm 3 of the first type of dopant.

20. The method of claim 11, wherein the fabrication of each memory cell further comprises: forming a select gate in a trench extending vertically in the semiconductor substrate; as well as The formation of the control gate is performed in the trench on top of the select gate.

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