Power amplifier circuit

Abstract

The power amplification circuit includes one or more amplification stages. The first amplification stage includes: a first amplifier and a second amplifier that amplify a differential signal; a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier; a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier; a first resonant circuit and a first resistor electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the first amplifier; and a second resonant circuit and a second resistor electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the second amplifier.

Description

Technical Field

[0001] The present disclosure relates to a power amplifier circuit. Background Art

[0002] In a power amplifier circuit including an emitter (source) grounded amplifier circuit, gain may decrease due to the Miller effect caused by parasitic capacitance between the base (gate) and the collector (drain).

[0003] Patent Document 1 describes a technique in which a cross-coupling capacitor is provided in a differential amplifier circuit to compensate for a gate signal drop caused by a parasitic capacitance between the gate and the drain, thereby suppressing the Miller effect and thereby suppressing a decrease in gain.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-191910 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] In a wideband power amplifier circuit, the gain sometimes has a frequency deviation. The gain varies according to the frequency of the input signal, and the frequency deviation refers to the difference in the gain. It is preferred that the gain is fixed and does not depend on the frequency of the input signal. In other words, it is preferred that the frequency deviation is small.

[0009] Patent Document 1 does not describe or suggest suppressing the frequency deviation of the gain.

[0010] The present disclosure has been made in view of the above, and an object of the present disclosure is to suppress frequency deviation of gain.

[0011] Technical solutions to solve problems

[0012] A power amplifier circuit according to one aspect of the present disclosure is a power amplifier circuit including one or more amplifier stages, wherein the power amplifier circuit includes a first amplifier stage, and the first amplifier stage includes: a first amplifier and a second amplifier for amplifying a differential signal; a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier; a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier; a first resonant circuit and a first resistor electrically connected in series between the output terminal and the input terminal of the first amplifier; and a second resonant circuit and a second resistor electrically connected in series between the output terminal and the input terminal of the second amplifier.

[0013] Effects of the Invention

[0014] According to the present disclosure, it is possible to suppress frequency deviation of gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a diagram showing the configuration of a power amplifier circuit according to the first embodiment.

[0016] Figure 2 It is a diagram schematically illustrating the characteristics of the power amplifier circuit according to the first embodiment.

[0017] Figure 3 It is a diagram showing the circuit simulation results of the power amplifier circuit according to the first embodiment.

[0018] Figure 4 It is a diagram showing a configuration of a power amplifier circuit according to a modification of the first embodiment.

[0019] Figure 5 It is a diagram showing the configuration of a power amplifier circuit according to a second embodiment.

[0020] Figure 6 It is a diagram showing the configuration of an amplifier of a power amplifier circuit according to the second embodiment.

[0021] Figure 7 It is a diagram showing the configuration of a bias circuit of a power amplifier circuit according to a second embodiment.

[0022] Figure 8 It is a diagram showing the circuit simulation results of the power amplifier circuit according to the second embodiment.

[0023] Fig. 9 It is a diagram showing the configuration of a power amplifier circuit according to a third embodiment.

[0024] Fig.10 It is a diagram showing the circuit simulation results of the power amplifier circuit according to the third embodiment.

[0025] Fig.11 It is a diagram showing the configuration of a power amplifier circuit according to a fourth embodiment.

[0026] Fig.12 It is a diagram showing the circuit simulation results of the power amplifier circuit according to the fourth embodiment.

[0027] Fig.13 It is a diagram showing the configuration of a power amplifier circuit according to a fifth embodiment.

[0028] Fig.14 It is a diagram showing the circuit simulation results of the power amplifier circuit according to the fifth embodiment.

[0029] Fig.15 It is a diagram showing the structure of a power amplifier circuit according to a sixth embodiment.

[0030] Fig.16 It is a diagram showing the structure of a power amplifier circuit according to the seventh embodiment.

[0031] Fig.17 It is a diagram showing the structure of a power amplifier circuit according to an eighth embodiment.

[0032] Fig.18 It is a diagram showing the structure of a power amplifier circuit according to a ninth embodiment.

[0033] Fig.19 It is a diagram showing the structure of a power amplifier circuit according to a tenth embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, the embodiments of the present disclosure will be described in detail based on the accompanying drawings. It should be noted that the present invention is not limited by the embodiments. Each embodiment is an example, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed.

[0035] <First embodiment>

[0036] Figure 1 1 is a diagram showing a configuration of a power amplifier circuit according to Embodiment 1. The power amplifier circuit 1 is a single-stage differential amplifier circuit.

[0037] A first input high frequency signal RF constituting a differential signal is input to the first input terminal 1a and the second input terminal 1b of the power amplifier circuit 1. in 1 and the second input high frequency signal RF in 2. The power amplifier circuit 1 converts the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2. The power amplifier circuit 1 outputs a first output high frequency signal RF constituting a differential signal from the first output terminal 1c and the second output terminal 1d. out 1 and the second output high frequency signal RF out 2.

[0038] The first input high frequency signal RF in 1 is a signal of the first polarity (eg, positive polarity). The second input high frequency signal RF in 2 is a signal of a second polarity (eg, negative polarity). The first output high frequency signal RF out 1 is the signal of the second polarity. The second output high frequency signal RF out 2 is the signal of the first polarity.

[0039] The first input high frequency signal RF in 1 and the second input high frequency signal RF inThe fractional bandwidth of 2 is exemplified as 40% (percent) to 60%, but the present disclosure is not limited thereto. The fractional bandwidth is a value obtained by dividing the bandwidth by the center frequency. For example, in the case where the frequency band is 3.3 GHz (gigahertz) to 5 GHz, the bandwidth is 1.7 GHz and the center frequency is 4.15 GHz, so the fractional bandwidth becomes about 41%.

[0040] The power amplifier circuit 1 includes amplifiers 11 and 12 , capacitors 21 and 22 , resonant circuits 31 and 32 , and resistors 41 and 42 .

[0041] The amplifier 11 is equivalent to an example of the first amplifier of the present disclosure. The amplifier 12 is equivalent to an example of the second amplifier of the present disclosure. The amplifiers 11 and 12 are equivalent to an example of the first amplifier stage of the present disclosure. The capacitor 21 is equivalent to an example of the first capacitor of the present disclosure. The capacitor 22 is equivalent to an example of the second capacitor of the present disclosure. The resonant circuit 31 is equivalent to an example of the first resonant circuit of the present disclosure. The resonant circuit 32 is equivalent to an example of the second resonant circuit of the present disclosure. The resistor 41 is equivalent to an example of the first resistor of the present disclosure. The resistor 42 is equivalent to an example of the second resistor of the present disclosure.

[0042] The amplifiers 11 and 12 are inverting amplifiers, respectively. The inverting amplifier is exemplified by an emitter (source) grounded amplifier, but the present disclosure is not limited thereto. The amplifiers 11 and 12 amplify differential signals and constitute a pair of differential amplifiers.

[0043] It is illustrated that the electrical characteristics of the amplifier 11 and the amplifier 12 are the same, but the present disclosure is not limited thereto.

[0044] An input terminal of the amplifier 11 is electrically connected to the first input terminal 1 a , and an output terminal of the amplifier 11 is electrically connected to the first output terminal 1 c .

[0045] The input terminal of the amplifier 12 is electrically connected to the second input terminal 1 b , and the output terminal of the amplifier 12 is electrically connected to the second output terminal 1 d .

[0046] One end of the capacitor 21 is electrically connected to the output terminal of the amplifier 11 , and the other end of the capacitor 21 is electrically connected to the input terminal of the amplifier 12 .

[0047] One end of the capacitor 22 is electrically connected to the output terminal of the amplifier 12. The other end of the capacitor 22 is electrically connected to the input terminal of the amplifier 11.

[0048] That is, the capacitors 21 and 22 are cross-coupled cross-coupling capacitors.

[0049] Although it is illustrated that the electrostatic capacitances of the capacitor 21 and the capacitor 22 are the same, the present disclosure is not limited thereto.

[0050] The resonance circuit 31 is an LC parallel resonance circuit in which an inductor 51 and a capacitor 52 are connected in parallel. The resonance frequency of the resonance circuit 31 is set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2, but the present disclosure is not limited thereto. For example, in the first input high frequency signal RF in 1 and the second input high frequency signal RF in In the case where the frequency band of 2 is 3.3 GHz to 5 GHz, the resonance frequency of the resonance circuit 31 is set to 5 GHz.

[0051] One end of the inductor 51 and one end of the capacitor 52 are electrically connected to the output terminal of the amplifier 11. The other end of the inductor 51 and the other end of the capacitor 52 are electrically connected to one end of the resistor 41. The other end of the resistor 41 is electrically connected to the input terminal of the amplifier 11.

[0052] That is, the amplifier 11 is fed back by the resonance circuit 31 and the resistor 41. Specifically, the amplifier 11 functions as a negative feedback circuit.

[0053] The resonance circuit 32 is an LC parallel resonance circuit in which an inductor 61 and a capacitor 62 are connected in parallel. The resonance frequency of the resonance circuit 32 is set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2, but the present disclosure is not limited thereto. For example, in the first input high frequency signal RF in 1 and the second input high frequency signal RF in In the case where the frequency band of 2 is 3.3 GHz to 5 GHz, the resonance frequency of the resonance circuit 32 is set to 5 GHz.

[0054] It is illustrated that the resonance frequencies of the resonance circuit 31 and the resonance circuit 32 are the same, but the present disclosure is not limited thereto.

[0055] One end of the inductor 61 and one end of the capacitor 62 are electrically connected to the output terminal of the amplifier 12. The other end of the inductor 61 and the other end of the capacitor 62 are electrically connected to one end of the resistor 42. The other end of the resistor 42 is electrically connected to the input terminal of the amplifier 12.

[0056] That is, the amplifier 12 is fed back by the resonance circuit 32 and the resistor 42. Specifically, the amplifier 12 functions as a negative feedback circuit.

[0057] It is illustrated that the resistance values ​​of the resistor 41 and the resistor 42 are the same, but the present disclosure is not limited thereto.

[0058] Figure 2 Schematically illustrates the characteristics of the power amplifier circuit of the first embodiment. Figure 2 In the figure, the horizontal axis represents frequency and the vertical axis represents gain.

[0059] A broken line 201 shows the characteristics of the power amplifier circuit 1 when there are no capacitors 21 and 22, resonant circuits 31 and 32, and resistors 41 and 42. In this case, the gain of the power amplifier circuit 1 decreases as the frequency increases as shown by the broken line 201.

[0060] The single-dot chain line 202 shows the characteristics of the power amplifier circuit 1 when the capacitors 21 and 22 are present and the resonant circuits 31 and 32 and the resistors 41 and 42 are not present. The capacitors 21 and 22 can suppress the Miller effect. Therefore, the gain of the power amplifier circuit 1 increases from the dotted line 201 to the single-dot chain line 202 as a whole, as shown by the arrow 204.

[0061] A solid line 203 shows the characteristics of the power amplifier circuit 1 when the capacitors 21 and 22 , the resonance circuits 31 and 32 , and the resistors 41 and 42 are present.

[0062] The resonant frequencies of the resonant circuits 31 and 32 are set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2. Therefore, in each resonant circuit 31 and 32, the LC resonant circuit becomes open in the high frequency region, so the feedback circuit is cut off, and in the low frequency region, the LC resonant circuit becomes capacitive, so the feedback circuit is turned on. Therefore, the gain of the power amplifier circuit 1 is almost unchanged in the high frequency region as shown by arrow 205, and decreases in the low frequency region. As a result, the frequency deviation of the gain of the power amplifier circuit 1 is suppressed as shown by the solid line 203.

[0063] Figure 3 FIG. 1 is a diagram showing the circuit simulation results of the power amplifier circuit according to the first embodiment. Figure 3 In the figure, the horizontal axis represents frequency (GHz) and the vertical axis represents gain (dB (decibel)) when the output is 33dBm.

[0064] A broken line 211 shows the characteristics of the power amplifier circuit 1 when the capacitors 21 and 22 , the resonant circuits 31 and 32 , and the resistors 41 and 42 do not exist.

[0065] A solid line 212 shows the characteristics of the power amplifier circuit 1 when the capacitors 21 and 22 , the resonant circuits 31 and 32 , and the resistors 41 and 42 are present.

[0066] As indicated by a solid line 212 , the power amplifier circuit 1 suppresses the gain in the low frequency region and increases the gain in the high frequency region, thereby being able to suppress the frequency deviation of the gain.

[0067] (Variation)

[0068] In the first embodiment, the resonant circuits 31 and 32 are LC parallel resonant circuits, but the present disclosure is not limited thereto. The resonant circuits may also be LC series resonant circuits.

[0069] Figure 4 1 is a diagram showing a configuration of a power amplifier circuit according to a modification of the first embodiment. The power amplifier circuit 1A is a single-stage differential amplifier circuit.

[0070] The power amplifier circuit 1A and the power amplifier circuit 1 (refer to Figure 1 ) compared to the embodiment of the present invention, the resonant circuits 31 and 32 are replaced by resonant circuits 31A and 32A.

[0071] The resonance circuit 31A corresponds to an example of the first resonance circuit of the present disclosure. The resonance circuit 32A corresponds to an example of the second resonance circuit of the present disclosure.

[0072] The resonant circuit 31A is an LC series resonant circuit in which an inductor 51 and a capacitor 52 are connected in series. The resonant frequency of the resonant circuit 31A is set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2, but the present disclosure is not limited thereto. For example, in the first input high frequency signal RF in 1 and the second input high frequency signal RF in In the case where the frequency band of 2 is 3.3 GHz to 5 GHz, the resonance frequency of the resonance circuit 31A is set to 3.3 GHz.

[0073] The resonant circuit 32A is an LC series resonant circuit in which an inductor 61 and a capacitor 62 are connected in series. The resonant frequency of the resonant circuit 32A is set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in 2, but the present disclosure is not limited thereto. For example, in the first input high frequency signal RF in 1 and the second input high frequency signal RF in In the case where the frequency band of 2 is 3.3 GHz to 5 GHz, the resonance frequency of the resonance circuit 32A is set to 3.3 GHz.

[0074] It is illustrated that the resonance frequencies of the resonance circuit 31A and the resonance circuit 32A are the same, but the present disclosure is not limited thereto.

[0075] Since the resonant frequencies of the resonant circuits 31A and 32A are each set to the first input high frequency signal RF in 1 and the second input high frequency signal RF in2, so in the low frequency region, the LC resonant circuit becomes capacitive, so the feedback path is turned on, and in the high frequency region, the LC resonant circuit becomes open, so the feedback path is cut off. Thus, the power amplifier circuit 1A suppresses the gain in the low frequency region and increases the gain in the high frequency region, thereby suppressing the frequency deviation of the gain.

[0076] <Second embodiment>

[0077] Among the components of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0078] Figure 5 1B is a diagram showing a configuration of a power amplifier circuit according to Embodiment 2. The power amplifier circuit 1B is a single-stage differential amplifier circuit.

[0079] The power amplifier circuit 1B and the power amplifier circuit 1 (refer to Figure 1 ) compared to the embodiment of the present invention, the resonant circuits 31 and 32 are replaced by resonant circuits 31B and 32B.

[0080] The resonance circuit 31B corresponds to an example of the first resonance circuit of the present disclosure. The resonance circuit 32B corresponds to an example of the second resonance circuit of the present disclosure.

[0081] The resonance circuit 31B and the resonance circuit 31 (see Figure 1 ) further includes a capacitor 53. One end of the capacitor 53 is electrically connected to the other end of the inductor 51 and the capacitor 52. The other end of the capacitor 53 is electrically connected to one end of the resistor 41.

[0082] The capacitor 53 functions as a DC cut capacitor.

[0083] The resonance circuit 32B and the resonance circuit 32 (see Figure 1 ) further includes a capacitor 63. One end of the capacitor 63 is electrically connected to the inductor 61 and the other end of the capacitor 62. The other end of the capacitor 63 is electrically connected to one end of the resistor 42.

[0084] The capacitor 63 functions as a DC cut capacitor.

[0085] The effects of capacitors 53 and 63 will be described.

[0086] Figure 6 FIG. 2 is a diagram showing the configuration of an amplifier of a power amplifier circuit according to a second embodiment. Figure 6 , the amplifier 11 and its peripheral circuits are shown. The configuration of the amplifier 12 and its peripheral circuits is the same as that of the amplifier 11 and its peripheral circuits, and thus illustration and description thereof are omitted.

[0087] The amplifier 11 includes a transistor 81 .

[0088] In the embodiment, the transistor is a bipolar transistor, but the present disclosure is not limited thereto. The transistor may also be a FET (Field Effect Transistor). When the transistor is a FET, the source corresponds to the emitter, the gate corresponds to the base, and the drain corresponds to the collector.

[0089] The emitter of the transistor 81 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0090] A power supply voltage Vcc is input to the collector of the transistor 81 .

[0091] The power supply voltage Vbatt is input to the bias circuit 82. The bias circuit 82 outputs a bias current BIAS1 to the base of the transistor 81 via the resistor 83.

[0092] Figure 7 It is a diagram showing the configuration of a bias circuit of a power amplifier circuit according to a second embodiment.

[0093] The bias circuit 82 includes a resistor 91 , transistors 92 , 93 , 95 and 96 , and a capacitor 94 .

[0094] A control current IB1 is input to one end of the resistor 91. The other end of the resistor 91 is electrically connected to a node N1.

[0095] The collector and base of transistor 92 are electrically connected to node N1. That is, transistor 92 is diode-connected. The emitter of transistor 92 is electrically connected to the collector and base of transistor 93. That is, transistor 93 is diode-connected. The emitter of transistor 93 is electrically connected to the reference potential.

[0096] The transistors 92 and 93 generate a fixed voltage. The voltage generated by the transistors 92 and 93 is the voltage of the node N1.

[0097] One end of the capacitor 94 is electrically connected to the node N1. The other end of the capacitor 94 is electrically connected to a reference potential. The capacitor 94 stabilizes the voltage of the node N1.

[0098] The power supply voltage Vbatt is input to the collectors of transistors 95 and 96. The bases of transistors 95 and 96 are electrically connected to the node N1. The emitters of transistors 95 and 96 are connected to the resistor 83 (see Figure 6 ) is electrically connected to one end of the resistor 83. That is, the transistors 95 and 96 are connected in an emitter-follower manner. The transistors 95 and 96 output the bias current BIAS1 from the emitter to one end of the resistor 83.

[0099] Refer again Figure 6The first input high frequency signal RF is input to the base of the transistor 81 via the capacitor 84. in 1.

[0100] In recent years, the power supply voltage Vcc may be changed during the amplification operation. For example, the power supply voltage Vcc is changed according to the first input high frequency signal RF in 1 according to an envelope tracking method in which the envelope curve of the image is changed (adjusted), but the present disclosure is not limited to this.

[0101] When the power supply voltage Vcc is changed without the capacitor 53 , the change in the power supply voltage Vcc is transmitted to the base of the transistor 81 via the inductor 51 and the resistor 41 , and the base bias point of the transistor 81 changes.

[0102] On the other hand, when the capacitor 53 is present, even if the power supply voltage Vcc changes, the change in the power supply voltage Vcc is blocked by the capacitor 53 , so that the change in the base bias point of the transistor 81 is suppressed.

[0103] As described above, by including the capacitor 53 , the resonance circuit 31B can suppress the base bias point of the transistor 81 from changing even when the power supply voltage Vcc changes.

[0104] Therefore, the bias circuit 82 can determine the base bias point of the transistor 81 and can control the operation class (A class, B class, C class, etc.) of the amplifier 11 .

[0105] It should be noted that in the resonant circuit 31A (see Figure 4 ), capacitor 52 functions as a DC cutoff capacitor, and therefore, there is no need to add a DC cutoff capacitor.

[0106] Refer again Figure 5 A matching circuit 121 is electrically connected to the first input terminal 1a and the second input terminal 1b. A signal source 111 is electrically connected to the matching circuit 121. The matching circuit 121 performs impedance matching between the signal source 111 and the power amplifier circuit 1B.

[0107] The signal source 111 outputs a single-ended input high frequency signal RF to the matching circuit 121. in The matching circuit 121 converts the single-ended input high-frequency signal RF in The first input high frequency signal RF is converted into a differential signal in 1 and the second input high frequency signal RF in 2, and output to the first input terminal 1a and the second input terminal 1b respectively.

[0108] The first output terminal 1c and the second output terminal 1d are electrically connected to a matching circuit 122. The load 112 is electrically connected to the matching circuit 122. The matching circuit 122 performs impedance matching between the power amplifier circuit 1B and the load 112.

[0109] The power amplifier circuit 1 outputs a first output high frequency signal RF constituting a differential signal to the matching circuit 122. out 1 and the second output high frequency signal RF out 2. The matching circuit 122 converts the first output high frequency signal RF constituting the differential signal out 1 and the second output high frequency signal RF out 2Converts the input high frequency signal RF into a single-ended out And output to the load 112 .

[0110] Figure 8 FIG. 2 is a diagram showing the circuit simulation results of the power amplifier circuit according to the second embodiment. Figure 8 In the figure, the horizontal axis represents frequency (GHz) and the vertical axis represents gain (dB) when the output is 33dBm.

[0111] A broken line 221 shows the characteristics of the power amplifier circuit 1B when the capacitors 21 and 22 , the resonance circuits 31B and 32B, and the resistors 41 and 42 are not present.

[0112] A solid line 222 shows the characteristics of the power amplifier circuit 1B in the presence of the capacitors 21 and 22 , the resonance circuits 31B and 32B, and the resistors 41 and 42 .

[0113] As indicated by a solid line 222 , the power amplifier circuit 1B can suppress the frequency deviation of the gain by suppressing the gain in the low frequency region and increasing the gain in the high frequency region.

[0114] <Third embodiment>

[0115] Among the components of the third embodiment, the same components as those of the other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0116] Fig. 9 1C is a diagram showing a configuration of a power amplifier circuit according to a third embodiment. The power amplifier circuit 1C is a two-stage differential amplifier circuit.

[0117] Power amplifier circuit 1C and power amplifier circuit 1B (refer to Figure 5 ) also includes amplifiers 13 and 14 and a matching circuit 131.

[0118] The amplifier 13 corresponds to an example of the third amplifier of the present disclosure. The amplifier 14 corresponds to an example of the fourth amplifier of the present disclosure. The amplifiers 13 and 14 correspond to an example of the second amplifier stage of the present disclosure.

[0119] The amplifiers 13 and 14 are inverting amplifiers, respectively. The amplifiers 13 and 14 amplify differential signals and constitute a pair of differential amplifiers.

[0120] It is illustrated that the electrical characteristics of the amplifier 13 and the amplifier 14 are the same, but the present disclosure is not limited thereto.

[0121] The matching circuit 131 is electrically connected between the output terminal of the amplifier 11 and the output terminal of the amplifier 12 and the input terminal of the amplifier 13 and the input terminal of the amplifier 14. The matching circuit 131 performs impedance matching between the output terminal of the amplifier 11 and the input terminal of the amplifier 13, and performs impedance matching between the output terminal of the amplifier 12 and the input terminal of the amplifier 14.

[0122] The amplifier 11 outputs the first input high frequency signal RF to the matching circuit 131. in 1 amplified high frequency signal RF1. The amplifier 12 outputs the second input high frequency signal RF to the matching circuit 131. in 2 Amplified high frequency signal RF2. Based on the high frequency signals RF1 and RF2, the matching circuit 131 outputs high frequency signals RF3 and RF4 constituting differential signals to the amplifiers 13 and 14, respectively.

[0123] The amplifier 13 outputs the first output high-frequency signal RF3 obtained by amplifying the high-frequency signal RF3 to the matching circuit 122. out 1. The amplifier 14 outputs a second high-frequency signal RF4 to the matching circuit 122 after amplifying the high-frequency signal RF4. out 2.

[0124] Fig.10 FIG. 1 is a diagram showing the circuit simulation results of the power amplifier circuit according to the third embodiment. Fig.10 In the figure, the horizontal axis represents frequency (GHz) and the vertical axis represents gain (dB) when the output is 33dBm.

[0125] A broken line 231 shows the characteristics of the power amplifier circuit 1C when the capacitors 21 and 22 , the resonance circuits 31B and 32B, and the resistors 41 and 42 are not present.

[0126] A solid line 232 shows the characteristics of the power amplifier circuit 1C when the capacitors 21 and 22 , the resonance circuits 31B and 32B, and the resistors 41 and 42 are present.

[0127] As indicated by a solid line 232 , the power amplifier circuit 1C can suppress the frequency deviation of the gain by suppressing the gain in the low frequency region and increasing the gain in the high frequency region.

[0128] <Fourth embodiment>

[0129] Among the components of the fourth embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0130] Fig.11 1D is a diagram showing a configuration of a power amplifier circuit according to a fourth embodiment. The power amplifier circuit 1D is a two-stage differential amplifier circuit.

[0131] Power amplifier circuit 1D and power amplifier circuit 1C (refer to Fig. 9 ) also includes capacitors 23 and 24.

[0132] The capacitor 23 corresponds to an example of a third capacitor in the present disclosure. The capacitor 24 corresponds to an example of a fourth capacitor in the present disclosure.

[0133] Although the capacitor 23 and the capacitor 24 are illustrated as having the same electrostatic capacitance, the present disclosure is not limited thereto.

[0134] One end of the capacitor 23 is electrically connected to the output terminal of the amplifier 13 , and the other end of the capacitor 23 is electrically connected to the input terminal of the amplifier 14 .

[0135] One end of the capacitor 24 is electrically connected to the output terminal of the amplifier 14 , and the other end of the capacitor 24 is electrically connected to the input terminal of the amplifier 13 .

[0136] That is, the capacitors 23 and 24 are cross-coupled capacitors.

[0137] Fig.12 FIG. 4 is a diagram showing the circuit simulation results of the power amplifier circuit according to the fourth embodiment. Fig.12 In the figure, the horizontal axis represents frequency (GHz) and the vertical axis represents gain (dB) when the output is 33dBm.

[0138] The dotted line 232 shows the power amplifier circuit 1C (refer to Fig. 9 ) characteristics.

[0139] A solid line 241 shows the characteristics of the power amplifier circuit 1D.

[0140] As indicated by a solid line 241 , the power amplifier circuit 1D can further suppress the frequency deviation of the gain by increasing the gain in the high frequency region compared to the power amplifier circuit 1C.

[0141] <Fifth Embodiment>

[0142] Among the components of the fifth embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0143] Fig.13 1E is a diagram showing a configuration of a power amplifier circuit according to a fifth embodiment. The power amplifier circuit 1E is a two-stage differential amplifier circuit.

[0144] Power amplifier circuit 1E and power amplifier circuit 1D (refer to Fig.11 ) does not include capacitors 21 and 22.

[0145] Fig.14 FIG. 2 is a diagram showing the circuit simulation results of the power amplifier circuit according to the fifth embodiment. Fig.14 In the figure, the horizontal axis represents frequency (GHz) and the vertical axis represents gain (dB) when the output is 33dBm.

[0146] A broken line 231 shows the characteristics of the power amplifier circuit 1E when the capacitors 23 and 24 , the resonance circuits 31B and 32B, and the resistors 41 and 42 are not present.

[0147] A solid line 251 shows the characteristics of the power amplifier circuit 1E when the capacitors 23 and 24 , the resonance circuits 31B and 32B, and the resistors 41 and 42 are present.

[0148] As indicated by a solid line 251 , the power amplifier circuit 1E can suppress the frequency deviation of the gain by suppressing the gain in the low-frequency region.

[0149] <Sixth embodiment>

[0150] Among the components of the sixth embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0151] Fig.15 1F is a diagram showing a configuration of a power amplifier circuit according to Embodiment 6. The power amplifier circuit 1F is a two-stage differential amplifier circuit.

[0152] Power amplifier circuit 1F and power amplifier circuit 1E (refer to Fig.13 ) does not include the amplifier 12, the resonant circuit 32B and the resistor 42. The power amplifier circuit 1E is not included (refer to Fig.13 )'s matching circuit 121 and matching circuit 131.

[0153] That is, the first stage of the power amplifier circuit 1F is a single-ended signal amplifier stage, and the second stage is a differential signal amplifier stage.

[0154] The matching circuit 121 performs impedance matching between the signal source 111 and the power amplifier circuit 1F. The matching circuit 131 performs impedance matching and converts the single-ended high-frequency signal RF1 into high-frequency signals RF3 and RF4 constituting differential signals, and outputs them to the amplifiers 13 and 14, respectively.

[0155] Power amplifier circuit 1F and power amplifier circuit 1C (refer to Fig. 9 ) can also suppress the frequency deviation of the gain.

[0156] <Seventh embodiment>

[0157] Among the components of the seventh embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0158] Fig.16 1 is a diagram showing a configuration of a power amplifier circuit according to a seventh embodiment. The power amplifier circuit 1G is a three-stage differential amplifier circuit.

[0159] Power amplifier circuit 1G and power amplifier circuit 1C (refer to Fig. 9 ) also includes amplifiers 15 and 16 and a matching circuit 132.

[0160] The amplifier 15 corresponds to an example of the fifth amplifier of the present disclosure. The amplifier 16 corresponds to an example of the sixth amplifier of the present disclosure. The amplifiers 15 and 16 correspond to an example of the third amplifier stage of the present disclosure.

[0161] The amplifiers 15 and 16 are inverting amplifiers, respectively. The amplifiers 15 and 16 amplify differential signals and constitute a pair of differential amplifiers.

[0162] It is illustrated that the electrical characteristics of the amplifier 15 and the amplifier 16 are the same, but the present disclosure is not limited thereto.

[0163] The matching circuit 132 is electrically connected between the output terminals of the amplifier 13 and the output terminals of the amplifier 14 and the input terminals of the amplifier 15 and the input terminals of the amplifier 16. The matching circuit 132 performs impedance matching between the output terminal of the amplifier 13 and the input terminal of the amplifier 15, and performs impedance matching between the output terminal of the amplifier 14 and the input terminal of the amplifier 16.

[0164] Amplifier 13 outputs high frequency signal RF5 obtained by amplifying high frequency signal RF3 to matching circuit 132. Amplifier 14 outputs high frequency signal RF6 obtained by amplifying high frequency signal RF4 to matching circuit 132. Matching circuit 132 outputs high frequency signals RF7 and RF8 constituting differential signals to amplifiers 15 and 16, respectively, based on high frequency signals RF5 and RF6.

[0165] The amplifier 15 outputs the first output high-frequency signal RF obtained by amplifying the high-frequency signal RF7 to the matching circuit 122. out 1. The amplifier 16 outputs a second output high-frequency signal RF8 to the matching circuit 122. out 2.

[0166] The power amplifier circuit 1G can suppress the frequency deviation of the gain.

[0167] <Eighth Embodiment>

[0168] Among the components of the eighth embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0169] Fig.17 1H is a diagram showing a configuration of a power amplifier circuit according to an eighth embodiment. The power amplifier circuit 1H is a three-stage differential amplifier circuit.

[0170] Power amplifier circuit 1H and power amplifier circuit 1G (refer to Fig.16 ), the power amplifier circuit 1H does not include the capacitors 21 and 22, the resonant circuits 31B and 32B, and the resistors 41 and 42. In addition, the power amplifier circuit 1H includes capacitors 23 and 24, the resonant circuits 33B and 34B, and the resistors 43 and 44, compared with the power amplifier circuit 1G.

[0171] The resonance circuit 33B corresponds to an example of the third resonance circuit of the present disclosure. The resonance circuit 34B corresponds to an example of the fourth resonance circuit of the present disclosure. The resistor 43 corresponds to an example of the third resistor of the present disclosure. The resistor 44 corresponds to an example of the fourth resistor of the present disclosure.

[0172] The configuration of each of the resonance circuits 33B and 34B is functionally the same as the circuit configuration of each of the resonance circuits 31B and 32B, and thus the description thereof is omitted.

[0173] The power amplifier circuit 1H can suppress the frequency deviation of the gain.

[0174] <Ninth embodiment>

[0175] Among the components of the ninth embodiment, the same components as those of other embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0176] Fig.18 1 is a diagram showing a configuration of a power amplifier circuit according to a ninth embodiment. The power amplifier circuit 1I is a three-stage differential amplifier circuit.

[0177] Power amplifier circuit 1I and power amplifier circuit 1G (refer to Fig.16) also includes capacitors 23 and 24, resonant circuits 33B and 34B, and resistors 43 and 44.

[0178] The power amplifier circuit 1I can suppress the frequency deviation of the gain.

[0179] <Tenth embodiment>

[0180] Among the components of the tenth embodiment, the same components as those of the other embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0181] Fig.19 1 is a diagram showing a configuration of a power amplifier circuit according to a tenth embodiment. The power amplifier circuit 1J is a three-stage differential amplifier circuit.

[0182] The power amplifier circuit 1J and the power amplifier circuit 1I (refer to Fig.18 ) also includes capacitors 25 and 26.

[0183] The capacitor 25 corresponds to an example of a fifth capacitor of the present disclosure. The capacitor 26 corresponds to an example of a sixth capacitor of the present disclosure.

[0184] Although the capacitor 25 and the capacitor 26 are exemplified as having the same electrostatic capacitance, the present disclosure is not limited thereto.

[0185] One end of the capacitor 25 is electrically connected to the output terminal of the amplifier 15 , and the other end of the capacitor 25 is electrically connected to the input terminal of the amplifier 16 .

[0186] One end of the capacitor 26 is electrically connected to the output terminal of the amplifier 16 , and the other end of the capacitor 26 is electrically connected to the input terminal of the amplifier 15 .

[0187] That is, the capacitors 25 and 26 are cross-coupled cross-coupling capacitors.

[0188] The power amplifier circuit 1J can suppress the frequency deviation of the gain.

[0189] <Note>

[0190] In the embodiments, the power amplifier circuit of one to three stages is described, but the present disclosure is not limited thereto and can also be applied to a power amplifier circuit of four or more stages.

[0191] <Configuration example of the present disclosure>

[0192] The present disclosure can also take the following structures. (1)

[0194] A power amplifier circuit comprises one or more amplifier stages, wherein:

[0195] The power amplifier circuit comprises a first amplifier stage,

[0196] The first amplifier stage comprises:

[0197] The first amplifier and the second amplifier amplify the differential signal;

[0198] a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier;

[0199] a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier;

[0200] A first resonant circuit and a first resistor are electrically connected in series with each other and electrically connected between an output terminal and an input terminal of the first amplifier; and

[0201] The second resonance circuit and the second resistor are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the second amplifier. (2)

[0203] Based on the power amplifier circuit described in (1) above,

[0204] The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel. (3)

[0206] Based on the power amplifier circuit described in (2) above,

[0207] The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit. (4)

[0209] Based on the power amplifier circuit described in (2) or (3) above,

[0210] The resonant frequency of the resonant circuit is equal to or higher than the maximum frequency of the frequency band of the input high-frequency signal. (5)

[0212] Based on the power amplifier circuit described in (3) or (4) above,

[0213] The power amplifier circuit also includes a bias circuit.

[0214] At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking. (6)

[0216] Based on the power amplifier circuit described in (1) above,

[0217] The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series. (7)

[0219] Based on the power amplifier circuit described in (6) above,

[0220] The resonance frequency of the resonance circuit is equal to or lower than a minimum frequency of a frequency band of an input high-frequency signal. (8)

[0222] Based on the power amplifier circuit described in (6) or (7) above,

[0223] The power amplifier circuit also includes a bias circuit.

[0224] At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking. (9)

[0226] In the power amplifier circuit described in any one of (1) to (8) above,

[0227] The fractional bandwidth ranges from 40% to 60%. (10)

[0229] In the power amplifier circuit described in any one of (1) to (9) above,

[0230] The power amplifier circuit further includes a second amplifier stage subsequent to the first amplifier stage.

[0231] The second amplifier stage comprises:

[0232] The third amplifier and the fourth amplifier amplify the differential signal;

[0233] a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; and

[0234] The fourth capacitor is electrically connected between the input terminal of the third amplifier and the output terminal of the fourth amplifier. (11)

[0236] Based on the power amplifier circuit described in (10) above,

[0237] The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel. (12)

[0239] Based on the power amplifier circuit described in (11) above,

[0240] The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit. (13)

[0242] Based on the power amplifier circuit described in (10) above,

[0243] The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series. (14)

[0245] Based on the power amplifier circuit described in (12) or (13) above,

[0246] The power amplifier circuit also includes a bias circuit.

[0247] At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking. (15)

[0249] In the power amplifier circuit described in any one of (1) to (9) above,

[0250] The power amplifier circuit further includes a second amplifier stage subsequent to the first amplifier stage.

[0251] The second amplifier stage comprises:

[0252] The third amplifier and the fourth amplifier amplify the differential signal;

[0253] a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier;

[0254] a fourth capacitor electrically connected between an input terminal of the third amplifier and an output terminal of the fourth amplifier;

[0255] A third resonant circuit and a third resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the third amplifier; and

[0256] The fourth resonance circuit and the fourth resistor are electrically connected in series with each other, and are electrically connected between the output terminal and the input terminal of the fourth amplifier. (16)

[0258] Based on the power amplifier circuit described in (15) above,

[0259] The power amplifier circuit further includes a third amplifier stage after the second amplifier stage.

[0260] The third amplifier stage comprises:

[0261] The fifth amplifier and the sixth amplifier amplify the differential signal;

[0262] a fifth capacitor electrically connected between an output terminal of the fifth amplifier and an input terminal of the sixth amplifier; and

[0263] The sixth capacitor is electrically connected between the input terminal of the fifth amplifier and the output terminal of the sixth amplifier. (17)

[0265] Based on the power amplifier circuit described in any one of (10) to (16) above,

[0266] The power amplifier circuit further includes a third amplifier stage after the second amplifier stage.

[0267] The second amplifier stage comprises:

[0268] The third amplifier and the fourth amplifier amplify the differential signal;

[0269] a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier;

[0270] a fourth capacitor electrically connected between an input terminal of the third amplifier and an output terminal of the fourth amplifier;

[0271] A third resonant circuit and a third resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the third amplifier; and

[0272] The fourth resonance circuit and the fourth resistor are electrically connected in series with each other, and are electrically connected between the output terminal and the input terminal of the fourth amplifier. (18)

[0274] A power amplifier circuit includes a plurality of amplifier stages, wherein:

[0275] The power amplifier circuit comprises:

[0276] a first amplifier stage; and

[0277] A second amplifier stage after the first amplifier stage,

[0278] The first amplifier stage comprises:

[0279] a first amplifier; and

[0280] The first resonant circuit and the first resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the first amplifier.

[0281] The second amplifier stage comprises:

[0282] The third amplifier and the fourth amplifier amplify the differential signal;

[0283] a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; and

[0284] The fourth capacitor is electrically connected between the input terminal of the third amplifier and the output terminal of the fourth amplifier. (19)

[0286] Based on the power amplifier circuit described in (18) above,

[0287] The first amplifier stage also includes:

[0288] a second amplifier; and

[0289] The second resonant circuit and the second resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the second amplifier.

[0290] The first amplifier and the second amplifier amplify the differential signal. (20)

[0292] In the power amplifier circuit described in (15), (16), (17), (18) or (19),

[0293] The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel. (twenty one)

[0295] In the power amplifier circuit described in (15), (16), (17), (18) or (19),

[0296] The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series. (twenty two)

[0298] Based on the power amplifier circuit described in (20) or (21) above,

[0299] The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit. (twenty three)

[0301] Based on the power amplifier circuit described in (20), (21) or (22),

[0302] The power amplifier circuit also includes a bias circuit.

[0303] At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking.

[0304] It should be noted that the above-mentioned embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention can be modified / improved within the scope of the present invention, and its equivalents are also included in the present invention.

[0305] Description of Reference Numerals

[0306] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J: power amplifier circuit;

[0307] 11, 12, 13, 14, 15, 16: amplifier;

[0308] 21, 22, 23, 24, 25, 26, 52, 62: capacitors;

[0309] 31, 31A, 31B, 32, 32A, 32B, 33B, 34B: resonance circuit;

[0310] 41, 42, 43, 44: resistance;

[0311] 51, 61: Inductor;

[0312] 121, 122, 131, 132: matching circuit.

Claims

1. A power amplifier circuit, comprising one or more amplifier stages, wherein: The power amplifier circuit comprises a first amplifier stage, The first amplifier stage comprises: The first amplifier and the second amplifier amplify the differential signal; a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier; a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier; A first resonant circuit and a first resistor are electrically connected in series with each other and electrically connected between an output terminal and an input terminal of the first amplifier; and The second resonance circuit and the second resistor are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the second amplifier.

2. The power amplifier circuit according to claim 1, wherein: The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel.

3. The power amplifier circuit according to claim 2, wherein: The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit.

4. The power amplifier circuit according to claim 2 or 3, wherein: The resonant frequency of the resonant circuit is equal to or higher than the maximum frequency of the frequency band of the input high-frequency signal.

5. The power amplifier circuit according to claim 3 or 4, wherein: The power amplifier circuit also includes a bias circuit. At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking.

6. The power amplifier circuit according to claim 1, wherein: The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series.

7. The power amplifier circuit according to claim 6, wherein: The resonance frequency of the resonance circuit is equal to or lower than a minimum frequency of a frequency band of an input high-frequency signal.

8. The power amplifier circuit according to claim 6 or 7, wherein: The power amplifier circuit also includes a bias circuit. At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking.

9. The power amplifier circuit according to any one of claims 1 to 8, wherein: The fractional bandwidth ranges from 40% to 60%.

10. The power amplifier circuit according to any one of claims 1 to 9, wherein: The power amplifier circuit further includes a second amplifier stage subsequent to the first amplifier stage. The second amplifier stage comprises: The third amplifier and the fourth amplifier amplify the differential signal; a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; and The fourth capacitor is electrically connected between the input terminal of the third amplifier and the output terminal of the fourth amplifier.

11. The power amplifier circuit according to claim 10, wherein: The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel.

12. The power amplifier circuit according to claim 11, wherein: The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit.

13. The power amplifier circuit according to claim 10, wherein: The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series.

14. The power amplifier circuit according to claim 12 or 13, wherein: The power amplifier circuit also includes a bias circuit. At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking.

15. The power amplifier circuit according to any one of claims 1 to 9, wherein: The power amplifier circuit further includes a second amplifier stage subsequent to the first amplifier stage. The second amplifier stage comprises: The third amplifier and the fourth amplifier amplify the differential signal; a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; a fourth capacitor electrically connected between an input terminal of the third amplifier and an output terminal of the fourth amplifier; A third resonant circuit and a third resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the third amplifier; and The fourth resonance circuit and the fourth resistor are electrically connected in series with each other, and are electrically connected between the output terminal and the input terminal of the fourth amplifier.

16. The power amplifier circuit according to claim 15, wherein: The power amplifier circuit further includes a third amplifier stage after the second amplifier stage. The third amplifier stage comprises: The fifth amplifier and the sixth amplifier amplify the differential signal; a fifth capacitor electrically connected between an output terminal of the fifth amplifier and an input terminal of the sixth amplifier; and The sixth capacitor is electrically connected between the input terminal of the fifth amplifier and the output terminal of the sixth amplifier.

17. The power amplifier circuit according to any one of claims 10 to 16, wherein: The power amplifier circuit further includes a third amplifier stage after the second amplifier stage. The second amplifier stage comprises: The third amplifier and the fourth amplifier amplify the differential signal; a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; a fourth capacitor electrically connected between an input terminal of the third amplifier and an output terminal of the fourth amplifier; A third resonant circuit and a third resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the third amplifier; and The fourth resonance circuit and the fourth resistor are electrically connected in series with each other, and are electrically connected between the output terminal and the input terminal of the fourth amplifier.

18. A power amplifier circuit, comprising a plurality of amplifier stages, wherein: The power amplifier circuit comprises: a first amplifier stage; and A second amplifier stage after the first amplifier stage, The first amplifier stage comprises: a first amplifier; and The first resonant circuit and the first resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the first amplifier. The second amplifier stage comprises: The third amplifier and the fourth amplifier amplify the differential signal; a third capacitor electrically connected between an output terminal of the third amplifier and an input terminal of the fourth amplifier; and The fourth capacitor is electrically connected between the input terminal of the third amplifier and the output terminal of the fourth amplifier.

19. The power amplifier circuit according to claim 18, wherein: The first amplifier stage also includes: a second amplifier; and The second resonant circuit and the second resistor are electrically connected in series with each other and electrically connected between the output terminal and the input terminal of the second amplifier. The first amplifier and the second amplifier amplify the differential signal.

20. The power amplifier circuit according to any one of claims 15 to 19, wherein: The resonance circuit includes an LC parallel resonance circuit that electrically connects an inductor and a capacitor in parallel.

21. The power amplifier circuit according to any one of claims 15 to 19, wherein: The resonant circuit includes an LC series resonant circuit that electrically connects an inductor and a capacitor in series.

22. The power amplifier circuit according to claim 20, wherein: The resonant circuit also includes another capacitor electrically connected in series with the LC parallel resonant circuit.

23. The power amplifier circuit according to any one of claims 20 to 22, wherein: The power amplifier circuit also includes a bias circuit. At least one of the first amplifier and the second amplifier adjusts the power supply voltage by envelope tracking.

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