Delta-sigma modulation with continuous time input and discrete time loop filter

Abstract

The invention provides delta-sigma modulation with a continuous time input and a discrete time loop filter. An apparatus includes an input circuit, a switched capacitor, an integrator, a quantizer, and a feedback loop. The input circuit receives an analog signal and generates an analog input signal, the input circuit including a resistor-capacitor (RC) integrator. The switched capacitor samples the analog input signal and generates a discrete time sampled input signal. The integrator processes the discrete time sampled input signal. The quantizer converts an output of the integrator into a digital signal. The feedback loop provides the digital signal to the RC integrator and a respective input of the integrator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 365,076, filed on May 20, 2022, entitled “Delta-Sigma ADC with Discrete Time Noise Function and Continuous Time Signal Transfer Function,” under 35 U.S.C. §119(e), the contents and disclosure of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more examples relate to delta-sigma modulation. One or more examples relate to analog-to-digital conversion utilizing delta-sigma modulation. Background Art

[0004] Delta-sigma modulation (Δ∑; or ∑-Δ, ∑Δ) is a technique for encoding an analog signal into a digital signal, such as found in an analog-to-digital converter (ADC). Delta-sigma modulation uses a delta-sigma modulator (DSM) to sample and quantize the input signal and filter the quantization noise. The DSM is utilized in a variety of operating environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram depicting an apparatus for performing delta-sigma modulation to convert an analog signal into a digital signal according to one or more examples.

[0007] Figure 2 is a schematic diagram illustrating an apparatus for converting an analog voltage signal into a digital voltage signal according to one or more examples.

[0008] Figure 3 is depicted as Figure 2 Input circuit or Figure 1 Schematic diagram of an input circuit of an example of an input circuit.

[0009] Figure 4 is a schematic diagram depicting an example DSM according to various examples discussed herein.

[0010] Figure 5 is a flow chart depicting a process for A-sigma analog-to-digital conversion according to one or more examples.

[0011] Figure 6is a diagram illustrating a method for calibrating a continuous time input terminal (such as Figure 2 Block diagram of a device for measuring the gain at the input circuit of FIG.

[0012] Figure 7 is a schematic diagram depicting an example DSM according to various examples discussed herein.

[0013] Figure 8 is a flow chart depicting a process for calibrating gain at a continuous-time input according to one or more examples.

[0014] Fig. 9 is a block diagram depicting an apparatus including additional filtering prior to an input to a continuous-time input circuit according to one or more examples.

[0015] Fig.10 is a schematic diagram depicting an example apparatus according to various examples discussed herein.

[0016] Fig.11 is a block diagram depicting an apparatus according to one or more examples.

[0017] Fig.12 is a schematic diagram of an example apparatus including high-order loop filtering.

[0018] Fig.13 is a schematic diagram of an example arrangement including two DSMs cross-coupled to form an orthogonal DSM.

[0019] Fig.14 is a block diagram depicting a wireless receiver including an ADC using a DSM according to one or more examples.

[0020] Fig.15 is a block diagram depicting an example wireless receiver.

[0021] Fig.16 are block diagrams of circuits that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0022] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0023] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "such as," and "for example" means that the related description is illustrative, and while the scope of the present disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0024] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0025] In addition, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0026] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0027] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof, designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0028] Examples can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operable actions as continuous processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of actions can be rearranged. Processes can correspond to methods, threads, functions, procedures, subroutines, subprograms, without limitation. In addition, the methods disclosed herein can be implemented by hardware, software, or both. If implemented in software, functions can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that are conducive to transferring a computer program from one location to another.

[0029] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0030] Any relative terms used herein (such as "above", "below", "on", "below", "upper", "lower", etc.) are for clarity and ease of understanding of the present disclosure and the drawings, and the relative terms do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0031] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. For example, depending on the particular parameter, attribute, or condition being substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0032] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The terms "on" and "connected" may be used interchangeably with the term "coupled" in this description and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0033] A typical DSM includes a quantizer and a feedback loop between the output and input of the quantizer, the feedback loop including a digital filter. The quantizer generates a quantized signal, which is intended to be a digital signal representing an analog input signal ("DSM input signal") to the DSM. The feedback loop provides the quantized signal to the digital filter. The digital filter processes the quantized signal and generates an error signal representing the difference between the DSM input signal and the quantized signal. The feedback loop provides the error signal to the input of the quantizer. The DSM iteratively reduces the error between the input signal and the quantized output signal via the feedback loop. In the case of a delta-sigma analog-to-digital converter (ADC), the delta-sigma ADC reduces the error until the quantized output signal properly represents the input signal in digital form.

[0034] As non-limiting examples, DSM outputs are utilized in wireless communications, audio or video signal processing, and measurement and control systems. As non-limiting examples, the definition of a high or low frequency band, a threshold for appropriate noise reduction, a threshold for appropriate anti-aliasing, and other related requirements depend, at least in part, on the specific application and operating conditions.

[0035] A DSM typically oversamples the analog input signal at a rate much higher than the Nyquist rate. The Nyquist rate is the minimum sampling rate to avoid aliasing. Aliasing is a phenomenon where high-frequency components of a signal are incorrectly represented as low-frequency components in the sampled signal. Oversampling allows the DSM to capture high-frequency components of the input signal that can be filtered out by the digital filter.

[0036] The digital filter of DSM filters out the noise in the high frequency band of the analog input signal (i.e., low pass filter). A digital filter operating in the continuous time domain or a digital filter operating in the discrete time domain can be selected. When the digital filter operates on a continuous time signal, it produces a continuous time signal that can be oversampled at the input of the quantizer. When the input signal is oversampled at the input of the quantizer, any aliasing that occurs due to the oversampling process only affects the quantization noise, which is usually at a higher frequency than the input signal. In addition, by oversampling at the input of the quantizer, high frequency noise can be more effectively filtered out by the digital filter.

[0037] When a digital filter, especially one implemented in an integrated circuit, operates on a continuous-time signal, the noise transfer function (NTF) of the digital filter is sensitive to process voltage temperature (PVT) variations. The performance of a digital filter operating on a continuous-time signal depends on the values ​​of resistors, capacitors, and transistors, which can vary significantly due to PVT variations. Therefore, PVT variations can affect the performance or accuracy of such digital filters, causing the output signal to contain errors or be unpredictable.

[0038] When a digital filter operates on a discrete-time signal, oversampling may occur at the input of the quantizer, and often also at or before the input of the digital filter or after the digital filter. When oversampling occurs at or before the input of the digital filter, the aliasing that occurs due to the oversampling process affects both the input signal and the quantization noise, potentially distorting the input signal and increasing the noise floor. In addition, the aliasing effect due to oversampling may occur at frequency bands that are too high for the digital filter to be effectively filtered out.

[0039] When a digital filter (including a digital filter implemented in an integrated circuit) operates on a discrete-time signal, the NTF of the digital filter is less sensitive to PVT variations than a digital filter operating on a continuous-time signal because the NTF of the digital filter is insensitive (insensitive or negligible) to PVT variations. It is less sensitive to PVT variations because the sampling instant of the discrete-time signal is fixed and determined by a sampling clock, which is less affected by PVT variations. In addition, a digital filter operating on a discrete-time signal may include noise shaping and dynamic element matching (DEM) to reduce the impact of PVT variations on filter performance.

[0040] One or more examples generally relate to a DSM topology including a continuous time signal transfer function (STF) and a discrete time noise transfer function (NTF). An input circuit including an RC integrator processes an analog signal into an analog input signal in continuous time before the analog input signal is sampled, integrated, and quantized. A feedback loop adjusts the behavior of the loop filter. A first integrator block (RC integrator) and a switched capacitor (for sampling) provide low pass filtering of the analog input signal, and a first integrator block and a second integrator block and a feedback loop provide high pass filtering for quantization noise.

[0041] "Effective oversampling" is different from "oversampling." Oversampling involves periodically sampling a signal at a rate higher than the Nyquist rate (in other words, at a rate higher than the minimum rate required to represent the signal without aliasing). Effective oversampling involves processing the signal in a way that results in effects similar to oversampling—for example, noise shaping to push quantization noise into a higher frequency band where it can be filtered, without the restriction—without actually oversampling the signal, and without the undesirable aliasing effects of oversampling discussed above.

[0042] Reducing the effect of quantization noise on the DSM output signal improves the resolution and accuracy of the DSM.

[0043] Figure 1 is a block diagram depicting an apparatus 100 that performs delta-sigma modulation to convert an analog signal to a digital signal according to one or more examples. The apparatus 100 may be a DSM or a portion thereof, and thus may also be referred to as a DSM 100 or a DSM portion 100.

[0044] The apparatus 100 includes an input circuit 102 , an RC integrator 104 , a switched capacitor 106 , an integrator 108 , a quantizer 110 , and a feedback loop 112 .

[0045] By way of a general description of the intended operation of the device 100:

[0046] Input circuit 102 receives and processes analog signal 114 (an analog voltage signal) and generates analog input signal 116 (also an analog voltage signal).

[0047] The processing performed by the input circuit 102 includes continuous-time active filtering of the analog signal 114. The continuous-time active filtering performs noise shaping and first-order sinc filtering on the analog signal 114 before it is sampled. The noise shaping spreads the noise over a wider frequency range, effectively shaping the noise spectrum to push it to higher frequencies where it can be filtered by the loop filter device 100. The first-order sinc filtering at the device 100 prevents high-frequency noise aliasing of the input signal when sampling at a sampling rate lower than the Nyquist rate.

[0048] The switched capacitor 106 samples the continuous-time analog input signal 116 and generates a discrete-time sampled input signal 118. The discrete-time sampled input signal 118 is an analog voltage signal. The discrete-time sampled input signal 118 is a sequence of samples taken from the continuous-time analog input signal 116 at predetermined time intervals. The respective samples represent a particular sampling time interval, and the analog voltage signal at the output of the switched capacitor 106 represents the portion of the continuous-time analog input signal 116 represented by the sample at the particular sampling time interval. The duration of the sampling time interval is set by the switching frequency of the switched capacitor 106, and the switching frequency is set by the frequency of one or more clock signals (clock signals not depicted) provided to the switched capacitor 106.

[0049] The integrator 108 processes the discrete time sampled input signal 118. More specifically, the integrator 108 holds (e.g., temporarily stores, but is not limited to) a previously sampled discrete time sampled input signal 118 and integrates the sum of the previous sample of the discrete time sampled input signal 118 and the current sample of the discrete time sampled input signal 118 to amplify the corresponding sample of the discrete time sampled input signal 118.

[0050] Quantizer 110 converts the output of integrator 108 (amplified discrete time sampled input signal 120) into a digital signal by mapping the amplified discrete time sampled input signal 120 to a set of discrete voltage levels. Feedback loop 112 provides the output signal back to the respective inputs of input circuit 102 and integrator 108 as feedback signal 122. The digital signal and feedback signal 122 typically include quantization noise (also referred to as "quantization error"), and the loop filter implemented by feedback loop 112 reduces the quantization noise until the digital signal adequately represents the analog signal.

[0051] The signal transfer function (STF) of device 100 generally corresponds to the resistor and capacitor values ​​in input circuit 102, which is referred to herein as a "continuous time signal transfer function" or "CT-STF." The noise transfer function (NTF) of device 100 is defined by the capacitance ratio (discussed below), which is referred to herein as a "discrete time noise transfer function" or "DT-NTF."

[0052] Figure 2 is a schematic diagram depicting an apparatus 200 for converting an analog voltage signal to a digital voltage signal according to one or more examples. The apparatus 200 may also be referred to herein as a "delta-sigma modulator 200" or a "DSM 200."

[0053] like Figure 2As shown, DSM 200 includes: input circuit 202, switched capacitor 216, integrator 230, sampling switch 240 and quantizer 242. Input circuit 202 includes resistor 204, current summing node 206, operational amplifier 208 and capacitor 210. Switched capacitor 216 includes switch 218, capacitor 220, switch 222, switch 224 and switch 226. Integrator 230 includes current summing node 232, capacitor 234 and operational amplifier 236. Feedback loop 262 includes a circuit coupled to receive reference voltage V ref DAC 212 and DAC 238 of respective reference inputs 214 and 228.

[0054] In general, the input circuit 202 processes the analog signal 114 to attenuate and filter the analog signal 114 before it is sampled. Here, the input circuit 202 receives the analog signal 254 and the digital feedback signal 256 and generates the analog input signal 252. The analog signal 254 is an analog voltage signal applied to the DSM input 244 (which may also be referred to herein as the "first terminal 244"). The digital feedback signal 256 is a digital voltage signal that indicates (e.g., is proportional to or the same as, but not limited to) the digital signal output by the DSM 200 and more specifically the quantizer 242.

[0055] The differential inputs ("+-") of the operational amplifier 208 are coupled to the ground connection of the current summing node 206. The resistor 204 couples the DSM input 244 to the input of the current summing node 206. The DAC 212 couples the quantizer 242 to the input of the current summing node 206. The capacitor 210 couples the output 248 of the operational amplifier 208 to the output of the current summing node 206.

[0056] When the analog signal 114, which is a voltage signal, is applied to the DSM input 244, it is applied to the resistor 204, which generates a corresponding current signal. The corresponding current signal is summed with the current of the analog feedback signal 258 at the current summing node 206, and the resulting current is applied to the capacitor 210. The capacitor 210 is charged or discharged by the current flowing through it over a time interval. The voltage generated by the capacitor 210 in response to the resulting current is proportional to the integral of the resulting current over the time interval. In other words, the output voltage is equal to the integrated charge on the capacitor 210, which is proportional to the integral of the analog signal 254. The output of the input circuit 202 is taken from the voltage on the capacitor 210.

[0057] The operational amplifier 208 has a high input impedance, and any resulting current flowing into the differential inputs of the operational amplifier 208 is of negligible magnitude, so the inputs of the operational amplifier 208 may operate as a virtual ground source for the current summing node 206 .

[0058] Input circuit 202 effectively oversamples analog signal 254. Effective oversampling reduces the risk of aliasing and pushes noise into high frequency bands, including the high frequency band where it is attenuated by op amp 208 and capacitor 210, which operate as an active low pass filter for the analog signal.

[0059] The signal transfer function (STF) of DSM 200 generally corresponds to input circuit 202 and depends on the respective values ​​of resistor 204 and capacitor 210, so the STF of DSM 200 is CT-STF.

[0060] The switched capacitor 216 samples the analog input signal and generates a discrete time sampled analog input signal 250 ("discrete time sampled input signal 250"). As described above, the discrete time sampled input signal 250 is a sequence of samples taken from the continuous time analog input signal 252 at predetermined time intervals. The respective samples represent a particular sampling time interval, and the voltage signal at the output of the switched capacitor 216 represents the portion of the analog input signal 252 corresponding to the particular sampling time interval represented by the respective samples. The voltage across the capacitor 220 during the sampling time interval is proportional to the voltage potential of the analog input signal 252 during the sampling time interval. The duration of the sampling time interval is set by the switching frequency of the switched capacitor 106 and more specifically the switches 218, 222, 224, and 226. The switching frequency of the switches 218, 222, 224, and 226 is controlled by a clock signal (not depicted). Both the AC and DC voltages across the capacitor 220 are sampled.

[0061] The integrator 230 processes the discrete time sampled input signal 250 to amplify the discrete time sampled input signal 250 as discussed below. The integrator 230 receives the discrete time sampled input signal 250 and the analog feedback signal 260 and generates an amplified discrete time sampled input signal 250. The differential input terminals of the operational amplifier 236 are coupled to the current summing node 232.

[0062] The input of current summing node 232 is coupled to the output of switched capacitor 216. DAC 238 couples the output (or feedback output) of quantizer 242 to the input of current summing node 206. Capacitor 234 couples the differential output of operational amplifier 236 to the output of current summing node 206.

[0063] The noise transfer function NTF of device DSM 200 generally corresponds to the capacitance ratio of capacitor 234 and capacitor 220 set by a coefficient, as does DT-NTF.

[0064] The capacitor 234 integrates the sum of the previous sample of the discrete time sampled input signal 250 and the current sample of the discrete time sampled input signal 250 to amplify the discrete time sampled input signal 250 .

[0065] The quantizer 242 maps a continuous range of voltage samples of the discrete time sampled input signal 250 to a set of discrete voltage levels. Here, the quantizer 242 receives an amplified version of the discrete time sampled input signal 250 and maps it to a set of discrete voltage levels, which the quantizer 242 uses to generate a high resolution digital output signal 264 provided to the DSM output terminal 246 (which may also be referred to herein as "second terminal 246"). The digital feedback signal 256 is fed back to the input circuit 202 and the integrator 230 via the feedback loop 262. The digital feedback signal 256 may be the same as or indicative of the digital output signal 264 (e.g., proportional to it, but not limited to this).

[0066] Figure 3 is depicted as Figure 2 The input circuit 202 or Figure 1 1 is a schematic diagram of an example input circuit 300 of the input circuit 102 .

[0067] Depicted are resistor 204 , current summing node 206 , operational amplifier 208 , capacitor 210 , DAC 212 , and DSM input 244 .

[0068] DAC 212 is coupled to receive the digital feedback signal. A second input 308 of the current summing node 206 is coupled to an output 316 of the DAC 212. A first input 306 of the current summing node 206 is coupled to the DSM input 244 via the resistor 204. A virtual ground input 304 of the current summing node 206 is coupled to an inverting input 310 of the operational amplifier 208. A non-inverting input 312 of the operational amplifier 208 is coupled to ground 302. An output 314 of the operational amplifier 208 is coupled to an output 320 of the current summing node 206 via the capacitor 210. Other connections to the inverting / non-inverting inputs 310 and 312 may be utilized to provide a virtual ground without exceeding the scope of the present disclosure.

[0069] Figure 4 is a schematic diagram depicting an example DSM 400 according to various examples discussed herein.

[0070] The first integrator stage INTG1 provides an RC integration input path for the input voltage signal Vip. The first integrator stage INTG1 provides a first-order SINC 1 Anti-aliasing filtering, but with higher order SINC where order L>1 L Filtering is within the scope of the present disclosure and is specifically contemplated.The input voltage signal Vip is sampled at the output of the first integrator stage INTG1.

[0071] The NTF of the DSM 400 characterizes the noise transfer from the quantization noise being processed and passed through the loop to the output of the quantizer Q. Since the delta-sigma loop is a switched capacitor circuit, the NTF of the DSM is discrete time and is defined by the ratio of the capacitor values ​​of cap2 and cap3. The NTF is not affected by PVT and is not affected by sampling rate scaling.

[0072] The sampling rate at the output of the first integrator INTG1 is set by the switching frequency of the sampling switch, which is controlled by the frequency of the non-overlapping clock signals C1 and C2. As a non-limiting example, the frequency of the non-overlapping clock signals C1 and C2 may be set via a control register.

[0073] The multiple integrator stages and feedback loops of the DSM 400 operate as a discrete time loop filter. The loop filter of the DSM 400 is discrete time because the processing at the second integrator stage INTG2 and the quantizer Q is performed in discrete time.

[0074] The output of the quantizer Q is fed back to the first integrator stage INTG1 and the second integrator stage INTG2 via the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, respectively. Figure 4 In the particular non-limiting example depicted, DAC 1 and DAC 2 are implemented as switched capacitor DACs whose operation is controlled by clock signals C1 and C2. More specifically, in Figure 4 In the depicted non-limiting example, DAC1 and DAC4 implement capacitor reuse via capacitor reuse on-chip reference voltage generation, but the use of respective charge sampling and charge summing capacitors is within the scope of this disclosure and is specifically contemplated.Switched capacitor DACs such as DAC1 and DAC2 exhibit clock jitter immunity.

[0075] Figure 5 5 is a flow chart depicting a process 500 for delta-sigma modulation or delta-sigma analog-to-digital conversion according to one or more examples. As a non-limiting example, some or all of the operations of process 500 may be performed by DSM 100 or 200.

[0076] Although the example process 500 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 500. In other examples, different components of the example device or system implementing the process 500 may perform functions substantially simultaneously or in a particular sequence.

[0077] In one or more examples, process 500 includes processing an analog signal applied to an input of a delta-sigma modulator (DSM) to generate an analog input signal at operation 502. The analog signal is processed in continuous time and the analog input signal is processed in continuous time.

[0078] In one or more examples, process 500 includes sampling an analog input voltage signal and generating a discrete-time sampled analog input voltage signal at operation 504 .

[0079] In one or more examples, process 500 includes amplifying the discrete-time sampled analog input voltage signal at operation 506 .

[0080] In one or more examples, process 500 includes quantizing the amplified discrete-time sampled analog input voltage signal to generate a digital signal at operation 508 .

[0081] In one or more examples, process 500 includes providing a digital signal as a feedback signal at operation 510 .

[0082] The gain of input circuit 202 is a function of the resistance of resistor 204 and the capacitance of capacitor 210. Generally speaking, the gain may exhibit a variation of plus or minus 30% due to process voltage temperature (PVT) variations that affect one or more of the resistance value of resistor 204 and the capacitance value of capacitor 210. One or more examples involve using a variable resistor for resistor 204 and calibrating the gain at input circuit 202 by setting the resistance value of resistor 204.

[0083] Figure 6 is a block diagram illustrating an apparatus 600 for calibrating a gain at a continuous-time input (eg, a continuous-time input comprising input circuit 102 or input circuit 202 ) according to one or more examples.

[0084] Device 600 includes input circuit 606, logic circuit 618, input 614, and output 616. Input circuit 606 includes first selectable input path 602 and second selectable input path 604. First selectable input path 602 includes RC integrator 608, which includes variable resistor 612. Second selectable input path 604 includes SC integrator 610.

[0085] Input circuit 606 includes a first selectable input path 602 and a second selectable input path 604 , which are each selectably enabled by logic circuit 618 .

[0086] The second selectable input path 604 has a switched capacitor (SC) integrator 610 ("SC integrator 610"), and the performance of the switched capacitor of the SC integrator 610 is dominated by coefficients that are not affected by PVT variations.

[0087] When the first selectable input path 602 is disabled and the second selectable input path 604 is enabled, the gain of the input circuit 606 should not be affected by PVT variations. In contemplated operation, the gain exhibited by the input circuit 606 when the second selectable input path 604 is enabled can be compared to the gain exhibited by the input circuit 606 when the first selectable input path 602 is enabled to determine a difference or "gain error" value, a resistance value for reducing the gain error can be determined, and the resistance value R of the variable resistor 612 can be set to compensate for and reduce the gain error.

[0088] Logic circuit 618 includes calibration logic 620 to control apparatus 600 and more specifically the calibration process at input circuit 606. Logic circuit 618 is coupled to input circuit 606 and can selectively enable / disable first selectable input path 602 and second selectable input path 604.

[0089] Logic circuit 618 is coupled to input 614 and output 616 to observe (e.g., measure, but not limited to) the gain exhibited by input circuit 606 as a ratio of the input signal to the output signal of input circuit 606. When calibrating the gain of input circuit 606, logic circuit 618 enables one of first selectable input path 602 or second selectable input path 604, disables the other, and obtains a measurement value representing the respective voltage levels at input 614 and output 616 during a measurement period. Logic circuit 618 uses the obtained measurement value to calculate a gain value (e.g., as a ratio).

[0090] The logic circuit 618 obtains a first gain measurement value representing the gain of the input circuit 606 when the SC integrator 610 of the second selectable input path 604 is enabled at the input circuit 606 and the first selectable input path 604 is disabled, and obtains a second gain measurement value representing the gain of the input circuit 606 when the RC integrator 608 of the first selectable input path 602 is enabled at the input circuit 606 and the second selectable input path 602 is disabled. The logic circuit 618 calculates a gain error based on a comparison of the first gain measurement value and the second gain measurement value, and sets the resistance value R of the variable resistor 612 based at least in part on the gain error.

[0091] The logic circuit 618 may set the resistance value R of the variable resistor 612 using any suitable technique. As a non-limiting example, the resistance value R may be tuned, wherein the resistance value R is increased or decreased by a predetermined step size in response to the gain error until, after one or more iterations, the gain error is within a predetermined threshold range. For example, below a predetermined upper threshold representing an upper gain limit, and above a predetermined lower threshold representing a lower gain limit. Additionally or alternatively, as another non-limiting example, the resistance value R may be directly calculated based on the gain error using a function that relates the gain error to the resistance value. Additionally or alternatively, as another non-limiting example, the resistance value R may be determined using a lookup table (LUT) that relates a predetermined value of the gain error to a predetermined value of the resistance value R. The LUT may provide a predetermined value or an interpolated value in response to a gain error input at the LUT.

[0092] Figure 7 is a schematic diagram depicting an example DSM 700 according to various examples discussed herein. DSM 700 is a specific, non-limiting example of a DSM including an apparatus (such as apparatus 600) for calibrating gain at a continuous-time input.

[0093] DSM 700 includes a main input path (i.e., a first input path such as first selectable input path 602) and a calibration ("cal") input path (i.e., a second input path such as second selectable input path 604). The calibration input path is a switched capacitor integration path, while the main input path is an RC integration path. The calibration input path can be used for gain tuning and calibration of the RC input path, specifically, by passing a resistor value R for a programmable resistor.

[0094] The input to DSM 700 may be measured via the calibration input path, and the input processed via the main input path may be measured once. The two measurements may be compared, and the resistance value R of the programmable resistor may be set in the main input path to match the gain of the two input paths.

[0095] Figure 8 8 is a flow chart depicting a process 800 for calibrating gain at a continuous-time input circuit, such as input circuit 606, according to one or more examples. As a non-limiting example, some or all operations of process 800 may be performed by logic circuit 618 and calibration logic component 620.

[0096] Although the example process 800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 800. In other examples, different components of the example device or system implementing the process 800 may perform functions substantially simultaneously or in a particular sequence.

[0097] In one or more examples, process 800 includes obtaining a first gain measurement representing a gain of a CT input when an SC input path is enabled (second selectable input path 604, but not limited thereto) and an RC input path is disabled (e.g., first selectable input path 602, but not limited thereto) at an input of the CT at operation 802.

[0098] In one or more examples, process 800 includes obtaining a second gain measurement representing a gain of a CT input when an RC input path is enabled (e.g., first selectable input path 602, but not limited thereto) and an SC input path is disabled (second selectable input path 604, but not limited thereto) at an input of the CT at operation 804.

[0099] In one or more examples, process 800 includes setting a resistance value r of a variable resistor of an RC integrator at an RC input path based at least in part on a comparison of the first gain measurement value and the second gain measurement value at operation 806 .

[0100] Fig. 9 is a block diagram illustrating an apparatus 900 including additional filtering at an input of a continuous-time input terminal according to one or more examples.

[0101] The apparatus 900 includes an additional filter 902 and a CT input circuit 904, and optionally a DT integrator 906 and a quantizer 908. As a non-limiting example, the CT input circuit 904 may be the input circuit 202 or the second selectable input path 604. As a non-limiting example, the DT integrator 906 may be the integrator 230.

[0102] When the device 900 includes the additional filter 902 and the CT input circuit 904, it is a continuous-time input of a DSM having an additional filter before the continuous-time input. When the device 900 includes the additional filter 902, the CT input circuit 904, the DT integrator 906 and the quantizer 908, it is a DSM including additional passive filtering before the continuous-time input.

[0103] As mentioned above, as non-limiting examples, the additional filter 902 may include any combination of filtering elements (e.g., passive filters, active filters, or combinations thereof) for any type of filtering (e.g., low pass, high pass, band pass, or band stop filtering, but not limited to such) based at least in part on particular operating conditions.

[0104] Fig.10 1 is a schematic diagram depicting an example device 1000 according to various examples discussed herein. Device 1000 includes a passive filter at the front end of an RC integral type input path of a DSM. The RC filter illustrated by the passive filter is shown in a box above the passive filter. For example, based at least in part on specific operating conditions, it can operate as a low pass filter, a band pass filter, or a high pass filter. Using an active filter as the front end of the RC integral input path is not beyond the scope of the present disclosure and is specifically contemplated. Using more than one passive or active filter (e.g., a cascaded passive filter, an active filter, or both passive and active filters, but not limited thereto) at the front end of the RC integral input path is not beyond the scope of the present disclosure.

[0105] In one or more examples, the apparatus 1000 may optionally include a Figure 7 Calibration input path of the depicted calibration input path. In one or more examples, additional filtering in front of the RC integrator input path can be disabled or shorted so that it does not affect the gain.

[0106] It may be advantageous to provide higher order DT loop filtering, i.e., including two or more DT loop filters (e.g., integrator 230, but not limited thereto). As a non-limiting example, higher order DT loop filtering may further reduce noise and other unwanted signals, thereby resulting in a more accurate DT error signal for quantizer operation compared to lower order DT loop filters.

[0107] This can help reduce noise and other unwanted signals in the system, resulting in a higher quality output signal. However, higher order filters can also introduce more delay and require more processing power to implement, so there is a tradeoff between filter performance and system complexity. In some cases, a higher order filter may be required to meet the performance requirements of a particular application, while in other cases a simpler filter may be sufficient.

[0108] Fig.11 is a block diagram depicting an apparatus 1100 according to one or more examples.

[0109] The apparatus 1100 includes a CT input circuit 1102, an N-order DT loop filter 1104 (where N≥2), and a quantizer 1106. The N-order DT loop filter 1104 includes 1 to N DT integrators 1108 to provide higher order loop filtering. As non-limiting examples, the CT input circuit 1102 can be the input circuit 202, the input circuit 606, or the CT input circuit 904 with an additional filter 902 before it. As non-limiting examples, the quantizer 1106 can be the quantizer 242.

[0110] Fig.12 1 is a schematic diagram of an example apparatus 1200 comprising a higher order loop filtering via N additional second integrator stages INTG2 connected in series, where N is an integer ≥ 1 and the total number of second integrator stages INTG2 is equal to N+1. The apparatus 1200 may optionally include the above-mentioned Figure 6 and Figure 7 The calibration input path discussed above and additionally or alternatively may be in the form of a Fig. 9 and Fig.10 Optional additional filtering (i.e., passive, active, or a combination of passive or active filtering, but not limited to this) is included at the front end of the discussed RC integration input path. The number N of second integrator stages INTG2 is not limited in any way and, as a non-limiting example, may depend at least in part on specific operating conditions.

[0111] Fig.13 1 is a schematic diagram of an example device 1300 including two DSMs cross-coupled to form an orthogonal DSM. The orthogonal DSM includes an in-phase channel (I channel) and a quadrature channel (Q channel). Each of the I channel and the Q channel includes a Figures 1 to 12 The corresponding input terminals and output terminals of the corresponding integrator stages of the I channel DSM and the Q channel DSM are as shown in FIG. Fig.13 Depicted cross coupling.

[0112] One or more of the I-channel DSM or Q-channel DSM of device 1300 may optionally include the Figure 6 and Figure 7 Additionally or alternatively, one or more of the I-channel DSM or Q-channel DSM of the device 1300 may include at the front end of the RC integrator input path as discussed above. Fig. 9 and Fig.10 The optional additional filtering discussed (i.e., passive, active, or a combination of passive or active filtering, but not limited thereto). Additionally or alternatively, one or more of the I-channel DSM or Q-channel DSM of device 1300 may optionally include as described with respect to Fig.12The number N of second integrator stages INTG2 is not limited in any way and, as a non-limiting example, may depend at least in part on specific operating conditions.

[0113] Fig.14 is a block diagram depicting a wireless receiver 1400 including an ADC using a DSM according to one or more examples.

[0114] The wireless receiver 1400 includes an antenna 1402 , an LNA 1404 , a mixer 1406 , a TIA 1408 , and an ADC 1410 .

[0115] Antenna 1402 receives a wireless signal from the air and converts it into an electrical signal, such as an analog voltage signal. Antenna 1402 captures electromagnetic waves in the air and converts them into voltage. When the electromagnetic waves in the air correspond to wireless signals, the voltage generated by antenna 1402 is a voltage signal.

[0116] Low noise amplifier (LNA) 1404 ("LNA 1404") amplifies the weak electrical signal received from antenna 1402 while adding limited noise to the signal. Amplifying the received signal early in the receiver chain improves the signal-to-noise ratio (SNR) of the received signal.

[0117] Mixer 1406 downconverts the frequency of the received signal to a lower frequency for further processing. Mixer 1406 is a nonlinear device that takes the amplified signal from LNA 1404 and mixes it with a local oscillator (LO) signal to produce an intermediate frequency (IF) current signal that is lower in frequency than the received signal.

[0118] A transimpedance amplifier (TIA) 1408 ("TIA 1408") converts the IF current signal from the mixer into an IF voltage signal that can be digitized by ADC 1410. The TIA may also provide some additional amplification of the received signal and filter out noise.

[0119] An analog-to-digital converter (ADC) 1410 ("ADC 1410") converts the analog voltage signal from the TIA into a digital signal that can be further processed by a digital signal processing (DSP) algorithm. The DSM 200 of the ADC 1410 enables the ADC 1410 to perform some filtering on the analog voltage signal at the front end, which can eliminate the need for a baseband amplifier (BBamp) for such filtering. In one or more examples, the wireless receiver 1400 can include a BBamp, and the BBamp can optionally be selectively bypassed. In one or more examples, in addition to or alternatively to the DSM 200, the ADC 1410 can include a DSM 400, a DSM 700, a DSM 1000, a DSM 1200, or a DSM 1300.

[0120] Fig.15 is a block diagram of a direct conversion Bluetooth Low Energy (BLE) receiver depicting an example wireless receiver 1500, and more specifically including any of DSM 100, DSM 200, DSM 400, DSM 700, DSM 1000, DSM 1200, or DSM 1300 to implement an ADC block. The ADC block provides anti-aliasing filtering and gain, and can optionally selectively bypass the baseband amplifier (BBAMP) and DT path TP1.0.

[0121] Those skilled in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.16 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated.In some examples, some or all of the functional elements disclosed herein may be performed by hardware capable of executing the functional elements.

[0122] Fig.16 1600 is a block diagram of a circuit 1600 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit 1600 includes one or more processors 1602 (sometimes referred to herein as "processors 1602") operably coupled to one or more data storage devices 1604 (sometimes referred to herein as "storage devices 1604"). The storage devices 1604 include machine executable code 1606 stored thereon, and the processor 1602 includes logic circuits 1608. The machine executable code 1606 describes information of functional elements that can be implemented by (e.g., executed by) the logic circuits 1608. The logic circuits 1608 are suitable for implementing (e.g., executing) the functional elements described by the machine executable code 1606. When executing the functional elements described by the machine executable code 1606, the circuit 1600 should be regarded as dedicated hardware for performing the functional elements disclosed herein. In some examples, processor 1602 may execute the functional elements described by machine executable code 1606 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0123] When implemented by logic circuitry 1608 of processor 1602, machine executable code 1606 adapts processor 1602 to perform operations of the examples disclosed herein. As non-limiting examples, machine executable code 1606 may adapt processor 1602 to perform some or all of the operations of one or more of the following: process 500 or process 800.

[0124] Also as a non-limiting example, the machine executable code 1606 may adapt the processor 1602 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: device 100, DSM 200, input circuit 300, DSM 400, device 600, DSM 700, device 900, device 1000, device 1100, device 1200, device 1300, wireless receiver 1400, or wireless receiver 1500. More specifically, the features, functions, or operations disclosed herein are used for one or more of the following: input circuit 202, switch capacitor 216, integrator 230, sampling switch 240 and quantizer 242, resistor 204, current summing node 206, operational amplifier 208, capacitor 210, DAC 212, switch 218, capacitor 220, switch 222, switch 224, switch 226, current summing node 232, capacitor 234, operational amplifier 236, or DAC 238; input circuit 606, logic circuit 618, input terminal 614, output terminal 616, first selectable input path 602, second selectable input path 604, RC integrator 608, variable resistor 612, SC integrator 610; additional filter 902, CT input circuit 904, optional DT integrator 906 and quantizer 908; CT input circuit 1102, N-order DT loop filter 1104 (where N≥2) or quantizer 1106; or antenna 1402, LNA 1404, mixer 1406, TIA 1408 or ADC 1410.

[0125] Processor 1602 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer executes a functional element corresponding to a machine executable code 1606 (e.g., software code, firmware code, hardware description) associated with an example of the present disclosure, the general-purpose computer including the processor is considered a special-purpose computer. It should be noted that a general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, processor 1602 may include any conventional processor, controller, microcontroller, or state machine. Processor 1602 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0126] In some examples, storage device 1604 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited to this). In some examples, processor 1602 and storage device 1604 may be implemented as a single device (e.g., semiconductor device product, system on chip (SOC), but not limited to this). In some examples, processor 1602 and storage device 1604 may be implemented as separate devices.

[0127] In some examples, machine executable code 1606 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 1604, directly accessed by processor 1602, and executed by processor 1602 using at least logic circuit 1608. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 1604, transferred to a memory device (not shown) for execution, and executed by processor 1602 using at least logic circuit 1608. Thus, in some examples, logic circuit 1608 includes electrically configurable logic circuit 1608.

[0128] In some examples, machine executable code 1606 may describe hardware (e.g., circuits) to be implemented in logic circuit 1608 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). As a non-limiting example, a SYSTEMVERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0129] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 1608 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic component, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 1606 may include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0130] In examples where the machine executable code 1606 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1604) implements the hardware description described by the machine executable code 1606. As a non-limiting example, the processor 1602 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1608 may be electrically controlled to implement circuits corresponding to the hardware description into the logic circuit 1608. Also as a non-limiting example, the logic circuit 1608 may include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage device 1604) according to the hardware description of the machine executable code 1606.

[0131] Regardless of whether the machine executable code 1606 includes computer readable instructions or a hardware description, the logic circuit 1608 is suitable for performing the functional elements described by the machine executable code 1606 when implementing the functional elements of the machine executable code 1606. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0132] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “including” should be interpreted as “including but not limited to,” etc.).

[0133] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an example containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); the same is true when a definite article is used to introduce a claim recitation.

[0134] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" means at least two recitations, or two or more recitations, in the absence of other modifiers). Moreover, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or A, B, and C, etc.

[0135] In addition, any discrete word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to contemplate the possibility of including one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B". As used herein, "each" means some or all. As used herein, "each" means all.

[0136] Any characterization of something in this description as "typical," "conventional," "known," etc. does not necessarily mean that the thing is disclosed in the prior art or is understood in the prior art for the aspect discussed. Such characterization also does not necessarily mean that it is well-known, well-understood, or conventionally used in the relevant art. Such characterization should be understood to mean "known to the inventors of the present disclosure."

[0137] Additional non-limiting examples include:

[0138] Embodiment 1: A device, comprising: an input circuit for receiving an analog signal and generating an analog input signal, the input circuit comprising a resistor-capacitor (RC) integrator; a switched capacitor for sampling the analog input signal and generating a discrete-time sampled input signal; an integrator for processing the discrete-time sampled input signal; a quantizer for converting the output of the integrator into a digital signal; and a feedback loop for providing the digital signal to the RC integrator and the corresponding input terminals of the integrator.

[0139] Embodiment 2: The device of embodiment 1, wherein the signal transfer function of the device is continuous time and the noise transfer function of the device is discrete time.

[0140] Embodiment 3: The apparatus of embodiments 1 and 2, wherein the RC integrator comprises: a resistor; an operational amplifier; and a capacitor coupling an output of the operational amplifier with an input of the operational amplifier.

[0141] Embodiment 4: The device according to embodiments 1 to 3, comprising: a current summing node, wherein the resistor, the capacitor, the inverting input terminal of the operational amplifier and the feedback loop are all coupled to the current summing node.

[0142] Embodiment 5: The apparatus according to embodiments 1 to 4, wherein the feedback loop comprises: a first digital-to-analog converter in a signal path to a corresponding input end of the RC integrator; and a second digital-to-analog converter in a corresponding signal path to a corresponding input end of the integrator.

[0143] Embodiment 6: The apparatus according to embodiments 1 to 5, wherein the integrator for processing the discrete-time sampled input signal comprises an integrating operational amplifier for integrating the discrete-time sampled input signal.

[0144] Embodiment 7: The apparatus of Embodiments 1 to 6, wherein the resistor-capacitor (RC) integrator low-pass filters and noise shapes the analog signal.

[0145] Embodiment 8: The apparatus of embodiments 1 to 7, wherein the RC integrator comprises a capacitor coupled to pass a low frequency signal from the input of the RC integrator to the output of the RC integrator and to attenuate high frequency noise.

[0146] Embodiment 9: The apparatus of Embodiments 1 to 8, wherein the resistor of the RC integrator converts the analog signal from a voltage signal to a current signal.

[0147] Embodiment 10: The device according to embodiments 1 to 9, comprising: an additional filter coupled before the input circuit.

[0148] Embodiment 11: A device according to embodiments 1 to 10, wherein the input circuit includes a first selectable input path and a second selectable input path, wherein the first selectable input path includes the RC integrator, and wherein the second selectable input path includes a switched capacitor (SC) integrator.

[0149] Embodiment 12: According to the device described in embodiments 1 to 11, the device includes a logic circuit, which is used to: obtain a first gain measurement value representing the gain of the input circuit when the second input path is enabled at the input circuit and the first input path is disabled at the input circuit; obtain a second gain measurement value representing the gain of the input circuit when the first input path is enabled at the input circuit and the second input path is disabled at the input circuit; and set the resistance value R of the variable resistor of the RC integrator of the first input path at least partially based on a comparison of the first gain measurement value and the second gain measurement value.

[0150] Embodiment 13: A method, comprising: processing an analog voltage signal applied to an input terminal of a Δ-Σ modulator (DSM) to generate an analog input voltage signal; sampling the analog input voltage signal to generate a discrete-time sampled analog input voltage signal; amplifying the discrete-time sampled analog input voltage signal; quantizing the amplified discrete-time sampled analog input voltage signal to generate a digital signal; and providing the digital signal as a feedback signal.

[0151] Embodiment 14: The method of Embodiment 13, wherein processing the analog voltage signal applied to the input of the DSM to generate the analog input voltage signal comprises: performing a resistor-capacitor integration on the analog voltage signal.

[0152] Embodiment 15: The method according to embodiments 13 and 14, the method comprising: processing the analog voltage signal in continuous time.

[0153] Embodiment 16: A device comprising: a first terminal for receiving an analog signal; a second terminal for providing a digital signal representing the analog signal; and a Δ-Σ modulator coupled between the first terminal and the second terminal, wherein the Δ-Σ modulator exhibits a continuous-time signal transfer function and a discrete-time noise transfer function.

[0154] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Instead, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. In addition, features from one example may be combined with features of another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: an input circuit for receiving an analog signal and generating an analog input signal, the input circuit comprising a resistor-capacitor (RC) integrator; a switched capacitor for sampling the analog input signal and generating a discrete-time sampled input signal; an integrator for processing the discrete-time sampled input signal; a quantizer for converting the output of the integrator into a digital signal; as well as A feedback loop for providing the digital signal to the RC integrator and the corresponding input terminal of the integrator.

2. The apparatus of claim 1, wherein a signal transfer function of the apparatus is continuous time and a noise transfer function of the apparatus is discrete time.

3. The apparatus of claim 1 , wherein the RC integrator comprises: Resistors; Operational amplifier; and A capacitor couples the output terminal of the operational amplifier to the input terminal of the operational amplifier.

4. The device according to claim 3, comprising: Current summing node, The resistor, the capacitor, the inverting input of the operational amplifier and the feedback loop are all coupled to the current summing node.

5. The apparatus of claim 1 , wherein the feedback loop comprises: a first digital-to-analog converter in a signal path to a respective input of said RC integrator; as well as A second digital-to-analog converter is provided in a respective signal path to a respective input of the integrator.

6. The apparatus of claim 1, wherein the integrator for processing the discrete-time sampled input signal comprises an integrating operational amplifier for integrating the discrete-time sampled input signal.

7. The apparatus of claim 1, wherein the resistor-capacitor (RC) integrator low-pass filters and noise shapes the analog signal. 8 . The apparatus of claim 7 , wherein the RC integrator comprises a capacitor coupled to pass a low frequency signal from the input terminal of the RC integrator to the output terminal of the RC integrator and to attenuate high frequency noise.

9. The apparatus of claim 1, wherein a resistor of the RC integrator converts the analog signal from a voltage signal to a current signal.

10. The device according to claim 1, comprising: An additional filter is coupled before the input circuit.

11. The apparatus of claim 1, wherein the input circuit comprises a first selectable input path and a second selectable input path, wherein the first selectable input path comprises the RC integrator, wherein the second selectable input path comprises a switched capacitor (SC) integrator.

12. The apparatus of claim 11, comprising a logic circuit configured to: obtaining a first gain measurement representing a gain of the input circuit when the second input path is enabled at the input circuit and the first input path is disabled at the input circuit; obtaining a second gain measurement representing a gain of the input circuit when the first input path is enabled at the input circuit and the second input path is disabled at the input circuit; as well as A resistance value R of a variable resistor of the RC integrator of the first input path is set based at least in part on a comparison of the first gain measurement value and the second gain measurement value.

13. A method comprising: processing an analog voltage signal applied to an input of a delta-sigma modulator (DSM) to generate an analog input voltage signal; Sampling the analog input voltage signal to generate a discrete-time sampled analog input voltage signal; amplifying the discrete time sampled analog input voltage signal; quantizing the amplified discrete-time sampled analog input voltage signal to generate a digital signal; as well as The digital signal is provided as a feedback signal.

14. The method of claim 13, wherein processing the analog voltage signal applied to the input terminal of the DSM to generate the analog input voltage signal comprises: The analog voltage signal is resistor-capacitor integrated.

15. The method according to claim 13, comprising: Processes analog voltage signals in continuous time.

16. A device, comprising: A first terminal for receiving an analog signal; a second terminal for providing a digital signal representing the analog signal; as well as a delta-sigma modulator coupled between the first terminal and the second terminal, The delta-sigma modulator exhibits a continuous-time signal transfer function and a discrete-time noise transfer function.

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