Three-dimensional memory device including laterally spaced source lines and method of manufacturing same

Abstract

A memory device includes a first memory block including a first word line and a first source layer section; and a second memory block including a second word line and a second source layer section electrically isolated from the first source layer section. The first word line in the first memory block is electrically connected to a corresponding second word line in the second memory block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 350,573, filed in the U.S. Patent and Trademark Office on July 11, 2023, entitled “THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY SEPARATED SOURCE LINES AND METHOD OF MAKING THE SAME,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 379,805, filed on October 17, 2022. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory devices including laterally spaced-apart source lines and methods of fabricating the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory device includes: a first memory block, the first memory block including a first word line and a first source layer segment; and a second memory block, the second memory block including a second word line and a second source layer segment electrically isolated from the first source layer segment. The first word line in the first memory block is electrically connected to a corresponding second word line in the second memory block.

[0006] According to another aspect of the present disclosure, a method for forming a memory device includes: forming a laterally alternating sequence of source layer segments and source isolation dielectric structures; forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers; forming a memory opening through the vertically alternating sequence; forming a memory opening in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; dividing the vertical alternating sequence into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction; and replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the backside trenches and extending above at least one source isolation dielectric structure in the source isolation dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming a semiconductor device, a lower level dielectric layer, a lower level metal interconnect structure, and a source level material layer in process according to the first embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A A top view of the first exemplary structure. The vertical plane A-A' is Figure 1A A plane of a vertical section.

[0009] Figure 1C It is along Figure 1B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0010] Figure 2A is a vertical cross-sectional view of the first exemplary structure after forming a laterally alternating sequence of source layer segments and source isolation dielectric structures according to the first embodiment of the present disclosure.

[0011] Figure 2B yes Figure 2A A top view of the first exemplary structure. The vertical plane A-A' is Figure 2A A plane of a vertical section.

[0012] Figure 2C It is along Figure 2B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0013] Figure 3 is a vertical cross-sectional view of the first exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the first embodiment of the present disclosure.

[0014] Figure 4 is a vertical cross-sectional view of the first exemplary structure after patterning the first stepped surface, the first backward stepped dielectric material portion, and the interlayer dielectric layer according to the first embodiment of the present disclosure.

[0015] Figure 5A is a vertical cross-sectional view of the first exemplary structure after forming a first layer memory opening and a first layer support opening according to the first embodiment of the present disclosure.

[0016] Figure 5B yes Figure 5A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Figure 5A A plane of a vertical section.

[0017] Figure 6 is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial memory opening filling portion and a first layer support opening filling portion according to the first embodiment of the present disclosure.

[0018] Figure 7 is a vertical cross-sectional view of the first exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to the first embodiment of the present disclosure.

[0019] Figure 8 is a vertical cross-sectional view of the first exemplary structure after forming a second layer memory opening and a second layer support opening according to the first embodiment of the present disclosure.

[0020] Fig. 9 is a vertical cross-sectional view of the first exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to the first embodiment of the present disclosure.

[0021] FIG. 10A to FIG. 10D are sequential vertical cross-sectional views of a pair of inter-layer memory openings during formation of a pair of memory opening filling structures according to a first embodiment of the present disclosure.

[0022] Fig.11A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0023] Fig. 11B It is along Fig.11A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.11A A plane of a vertical section.

[0024] Fig. 12A is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0025] Fig. 12B It is along Fig. 12A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 12A A plane of a vertical section.

[0026] Fig. 12C It is along Fig. 12B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0027] Fig.12D It is along Fig. 12B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane DD'.

[0028] FIG. 13A to FIG. 13E Sequential vertical cross-sectional views showing regions of a first exemplary structure during formation of a source level material layer according to a first embodiment of the present disclosure.

[0029] Fig.14A is a vertical cross-sectional view of the first exemplary structure after forming a source level material layer according to the first embodiment of the present disclosure.

[0030] Fig. 14B It is along Fig.14A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.14A A plane of a vertical section.

[0031] Fig. 14C It is along Fig. 14B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0032] Fig.14D It is along Fig. 14B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane DD'.

[0033] Fig.15 is a vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0034] Fig.16A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer in a backside recess according to the first embodiment of the present disclosure.

[0035] Fig. 16B It is along Fig.16AThe horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0036] Fig. 16C It is along Fig. 16B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0037] Fig.16D It is along Fig. 16B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane DD'.

[0038] Fig.17A is a vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure in the backside trench according to the first embodiment of the present disclosure.

[0039] Fig. 17B It is along Fig.17A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.17A A plane of a vertical section.

[0040] Fig. 17C It is along Fig. 17B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0041] Fig.17D It is along Fig. 17B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane DD'.

[0042] Fig.17E yes 17A to 17D An enlarged vertical cross-sectional view of a region of a first exemplary structure.

[0043] Fig.17F yes Fig. 17C A schematic block diagram of a first exemplary structure is shown.

[0044] Figure 17G is a vertical cross-sectional view of an alternative configuration of the first exemplary structure.

[0045] Fig.18A is a vertical cross-sectional view of the first exemplary structure after forming a contact via structure and a higher level metal interconnect structure according to the first embodiment of the present disclosure.

[0046] Fig.18B It is along Fig.18A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.18AA plane of a vertical section.

[0047] Fig.18C It is along Fig.18B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane CC'.

[0048] Fig.19 is a vertical cross-sectional view of a second exemplary structure after forming a source level material layer and a source isolation dielectric structure on a substrate according to a second embodiment of the present disclosure.

[0049] Fig. 20 is a vertical cross-sectional view of a second exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the second embodiment of the present disclosure.

[0050] Fig.21 is a vertical cross-sectional view of a second exemplary structure after patterning a first stepped surface, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a second embodiment of the present disclosure.

[0051] Fig.22A is a vertical cross-sectional view of a second exemplary structure after forming a first-layer memory opening and a first-layer support opening according to the second embodiment of the present disclosure.

[0052] Fig. 22B It is along Fig.22A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.22A A plane of a vertical section.

[0053] Fig.23 is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial memory opening-filling portion and a first-layer support opening-filling portion according to the second embodiment of the present disclosure.

[0054] Fig.24 is a vertical cross-sectional view of a second exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to a second embodiment of the present disclosure.

[0055] Fig.25A is a vertical cross-sectional view of a second exemplary structure after forming a second layer memory opening and a second layer support opening according to the second embodiment of the present disclosure.

[0056] Fig.25B yes Fig.25A A top view of a second exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.25AA plane of a vertical section.

[0057] Fig.26 is a vertical cross-sectional view of a second exemplary structure after forming an inter-layer memory opening according to the second embodiment of the present disclosure.

[0058] Fig.27A is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to the second embodiment of the present disclosure.

[0059] Fig.27B yes Fig.27A A top view of a second exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.27A A plane of a vertical section.

[0060] Fig.28A is a vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer and backside trenches according to the second embodiment of the present disclosure.

[0061] Fig.28B yes Fig.28A A top view of a second exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.28A A plane of a vertical section.

[0062] Fig.28C It is along Fig.28B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0063] Fig.29 is a vertical cross-sectional view of a second exemplary structure after forming a backside recess according to the second embodiment of the present disclosure.

[0064] Fig. 30A is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer in a backside recess according to a second embodiment of the present disclosure.

[0065] Fig. 30B yes Fig. 30A A top view of a second exemplary structure. The sawtooth vertical plane AA' corresponds to Fig. 30A A plane of a vertical section.

[0066] Fig.31A is a vertical cross-sectional view of the second exemplary structure after forming a backside trench fill structure in the backside trench according to the second embodiment of the present disclosure.

[0067] Fig.31B yes Fig.31A A top view of a second exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.31AA plane of a vertical section.

[0068] Fig. 31C It is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0069] Fig.32A is a vertical cross-sectional view of a second exemplary structure after forming a drain contact via structure and a layer contact via structure according to the second embodiment of the present disclosure.

[0070] Fig.32B yes Fig.32A The zigzag vertical plane AA' corresponds to Fig.32A A plane of a vertical section.

[0071] Fig.33 is a vertical cross-sectional view of a second exemplary structure after forming a memory die according to the second embodiment of the present disclosure.

[0072] Fig.34 is a vertical cross-sectional view of a second exemplary structure after bonding a logic die to a memory die according to the second embodiment of the present disclosure.

[0073] Fig.35 is a vertical cross-sectional view of a second exemplary structure after removing a memory-side substrate of a memory die according to the second embodiment of the present disclosure.

[0074] Fig.36 is a vertical cross-sectional view of the second exemplary structure after forming a top source contact.

[0075] Fig.37 is a vertical cross-sectional view of a second exemplary structure after forming a source isolation trench according to the second embodiment of the present disclosure.

[0076] Fig.38 is a vertical cross-sectional view of a second exemplary structure after forming a source isolation dielectric structure according to the second embodiment of the present disclosure.

[0077] Fig.39 is a vertical cross-sectional view of an alternative embodiment of the second exemplary structure after forming a source isolation dielectric structure according to the second embodiment of the present disclosure.

[0078] Fig.40 yes Fig.38 A schematic block diagram of a second exemplary structure is shown. DETAILED DESCRIPTION

[0079] Embodiments of the present disclosure relate to a three-dimensional memory device including laterally spaced-apart source lines and a method of manufacturing the same, various aspects of which are described in detail below.

[0080] The drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0081] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0082] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0083] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stacked" element refers to an element that extends vertically through a memory level.

[0084] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material (i.e., providing a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0085] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0086] refer to Figures 1A to 1C , shows a first exemplary structure according to the first embodiment of the present disclosure. The first exemplary structure includes a semiconductor substrate 8 and a peripheral circuit 710 formed thereon. The first exemplary structure includes a memory array region 100 in which a three-dimensional memory array is to be formed subsequently, a staircase region 200 of a stepped surface in which a conductive layer and a contact via structure are to be formed subsequently, and a connection region 400 in which a peripheral contact via structure is to be formed subsequently.

[0087] The semiconductor substrate 8 includes a substrate semiconductor layer 9 at least at its upper portion. Various doped wells can be formed in the upper portion of the substrate semiconductor layer 9. A shallow trench isolation structure 720 can be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between semiconductor devices. The peripheral circuit 710 includes field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channel regions 746, and gate structures 750. The field effect transistors can be arranged in a CMOS configuration. Each gate structure 750 can include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758.

[0088] The peripheral circuit 710 may include additional semiconductor devices other than the p-type field effect transistor and the n-type field effect transistor, which may be used to support the operation of the memory structure to be formed subsequently. The peripheral circuit 710 includes a driver circuit, which is also referred to as a peripheral circuit. As used herein, a peripheral circuit refers to any one, each or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer and / or a latch, or may be any other semiconductor circuit that can be implemented outside the memory array structure of the memory device. For example, the semiconductor device may include a word line switching device for electrically biasing the word lines of the three-dimensional memory structure to be formed subsequently.

[0089] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a lower-level dielectric material layer 760. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0090] The dielectric layer stack (which includes the lower level dielectric material layer 760) serves as a matrix of lower level metal interconnect structures 780 that provide electrical routing between various nodes of the semiconductor device and the landing pads of the through memory level contact via structures to be subsequently formed. The lower level metal interconnect structures 780 are embedded within the dielectric layer stack of the lower level dielectric material layer 760 and include lower level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0091] For example, the lower-level metal interconnect structure 780 may be embedded within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect structure 780 are sequentially embedded. Each dielectric material layer selected from among the first dielectric material layers 764 may include any one of doped silicate glass, undoped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide such as aluminum oxide.

[0092] In one embodiment, the first dielectric material layer 764 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding the dielectric constant of undoped silicate glass (silicon oxide) of 3.9. The lower level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes of device or gate electrode contacts), intermediate lower level metal line structures 784, and lower level metal via structures 786. A subset of the lower level metal line structures 784 and / or lower level metal via structures 786 may be configured to serve as landing pads for subsequently formed through memory level contact via structures.

[0093] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from among the at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

[0094] The peripheral circuit 710 may include peripheral devices for memory level components to be formed later. The lower level metal interconnect structure 780 is embedded in the lower level dielectric layer 760. The combination of the lower level dielectric layer 760 and the lower level metal interconnect structure 780 covers the peripheral circuit 710.

[0095] The lower level metal interconnect structure 780 may be electrically connected to an active node (e.g., transistor active region 742 or gate electrode 754) of the peripheral circuit 710 (e.g., a CMOS device) and is positioned at the level of the lower level dielectric layer 760. A through memory level contact via structure may then be formed directly on the lower level metal interconnect structure 780 to provide electrical connection to a memory device to be subsequently formed.

[0096] A source level material layer 110' may be formed in a process including a layer stack of material layers above the lower level dielectric layer 760. The source level material layer 110' may include various layers that are subsequently modified to form the source level material layer. The source level material layer when formed includes a source contact layer that serves as a common source region for a vertical field effect transistor of a three-dimensional memory device.

[0097] In one embodiment, the source level material layer 110' in the process may include, from bottom to top, a lower source level material layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, an upper sacrificial liner 105, an upper source level material layer 116, a source level insulating layer 117 and an optional source select level conductive layer 118.

[0098] The lower source level material layer 112 and the higher source level material layer 116 may include doped semiconductor materials, such as doped polysilicon or doped amorphous silicon. The doped semiconductor material of the lower source level material layer 112 is referred to herein as a first doped semiconductor material, and the doped semiconductor material of the higher source level material layer 116 is referred to herein as a second doped semiconductor material, which may be the same as or different from the first doped semiconductor material.

[0099] The conductivity type of the lower source level material layer 112 and the higher source level material layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source level material layer 112 and the higher source level material layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source level material layer 112 and the higher source level material layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses may also be employed.

[0100] The source level sacrificial layer 104 includes sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can include a dielectric material such as silicon nitride or a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0101] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses can also be used.

[0102] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0103] The source level material layer 110' may be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer) during the process. As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and an area of ​​the first element and the area of ​​the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8).

[0104] The in-process source level material layer 110' may be patterned to provide openings in areas where through memory level contact via structures and through dielectric contact via structures are subsequently formed. Patterned portions of the in-process source level material layer 110' are present in each memory array region 100 where a three-dimensional memory stacked structure is subsequently formed. At least one second dielectric material layer 768 may include: a blanket layer portion that is below the in-process source level material layer 110'; and a patterned portion that fills gaps between patterned portions of the in-process source level material layer 1110'.

[0105] The source level material layer 110' may be patterned in the process so that the opening extends over the staircase region 200 where the contact via structure for contacting the word line conductive layer is to be formed laterally. In one embodiment, the staircase region 200 may be laterally spaced apart from the memory array region 100 along a first horizontal direction hd1. A horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2.

[0106] refer to FIG. 2A to FIG. 2C, a photoresist layer (not shown) may be applied to the top surface of the source level material layer 110' during the process and may be photolithographically patterned to form linear openings that extend laterally along a first horizontal direction (e.g., a word line direction) hd1 and are laterally spaced apart along a second horizontal direction (e.g., a bit line direction) hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to a boundary between the memory array region 100 and the staircase region 200.

[0107] An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer through the in-process source level material layer 110'. Laterally extending trenches (referred to herein as source isolation trenches) are formed in large quantities from the material of the in-process source level material layer 110' etched by the anisotropic etching process. The surface of at least one second dielectric layer 768 may be physically exposed at the bottom of each of the source isolation trenches. The source isolation trench may have a tapered sidewall, and the tapered angle of the tapered sidewall (measured from the vertical direction) is in the range of 0.5 degrees to 15 degrees, for example, from 1 degree to 10 degrees. Each patterned portion of the in-process source level material layer 110' is referred to herein as a source layer segment 111. Each source layer segment 111 extends laterally along a first horizontal direction hd1, and may have a corresponding width along a second horizontal direction hd2. The source layer segments 111 may be laterally spaced apart from each other, and may be arranged as a one-dimensional periodic array having periodicity along the second horizontal direction hd2.

[0108] The photoresist layer may then be removed, for example, by ashing. A dielectric fill material (e.g., silicon oxide) may be deposited in the source isolation trench, and an excess portion of the dielectric fill material may be removed from above a horizontal plane including the top surface of the source layer segment 111 by performing a planarization process. The planarization process may be a recess etching process and / or a chemical mechanical polishing (CMP) process. Each remaining portion of the dielectric fill material filling a corresponding one of the source isolation trenches constitutes a source isolation dielectric structure 12. A laterally alternating sequence of source layer segments 111 and source isolation dielectric structures 12 may be formed. In one embodiment, each source isolation dielectric structure in the source isolation dielectric structure 12 extends laterally along a first horizontal direction hd1. One isolation dielectric structure, a plurality of isolation dielectric structures, and / or each isolation dielectric structure in the isolation dielectric structure 12 may have a variable width that increases with a vertical distance from the substrate 8 along a second horizontal direction hd2. In other words, a top portion of one, a plurality of, and / or each of the source isolation dielectric structures 12 may be wider than a bottom portion of a corresponding one of the source isolation dielectric structures 12 .

[0109] refer to Figure 3 , subsequently forming an alternating stack of first material layers and second material layers. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first vertical alternating sequence. The levels of the first vertical alternating sequence are referred to herein as first level levels, and the levels of the alternating stack to be subsequently formed immediately above the first level levels are referred to herein as second level levels, and so on.

[0110] The first vertical alternating sequence may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are clearly contemplated herein.

[0111] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed above the source level material layer during the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0112] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0113] The first vertical alternating sequence (132, 142) may include a first insulating layer 132 composed of a first material and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0114] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0115] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0116] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0117] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first vertical alternating sequence (132, 142) may have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0118] A first insulating capping layer 170 may then be formed over the alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 may be in the range of 20 nm to 300 nm, although lesser and greater thicknesses may also be employed.

[0119] refer to Figure 4 , the first insulating cap layer 170 and the first vertical alternating sequence (132, 142) may be patterned to form a first stepped surface in the staircase region 200. The staircase region 200 may include a corresponding first stepped region and a second stepped region, in which a first stepped surface is formed, and in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively extending the etching region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped cavity.

[0120] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the region overlying the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first vertical alternating sequence (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0121] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 includes a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include doped silicate glass, which has a greater etching rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

[0122] refer to Figure 5A and Figure 5B , the first layer openings (149, 129) can be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110'. For example, a photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110' by a first anisotropic etching process to form the first layer openings (149, 129) simultaneously (i.e., during the first anisotropic etching process).

[0123] The first layer openings (149, 129) may include first layer memory openings 149 and first layer support openings 129. The first layer memory openings 149 are openings formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The bottom surface of the first layer openings (149, 129) may be a recessed surface of the source level sacrificial layer 104. Therefore, each first layer opening (149, 129) may have a bottom surface between a horizontal plane including the bottom surface of the source level sacrificial layer 104 and a horizontal plane including the top surface of the source level sacrificial layer 104. In another embodiment, the bottom surface of the first layer openings (149, 129) may be formed within the lower source level material layer 112.

[0124] The first layer support openings 129 are openings formed in the staircase region 200 and subsequently used to form support structures that are subsequently used to provide structural support to the first exemplary structure during replacement of the sacrificial material layer with the conductive layer. In the case where the first spacer material is formed as the first conductive layer, the first layer support openings 129 may be omitted. A subset of the first layer support openings 129 may be formed through the horizontal surface of the first stepped surface of the first alternating stack (132, 142).

[0125] In one embodiment, the first layer memory openings 149 can be formed into clusters that are laterally spaced apart from each other along a second horizontal direction hd2. Each cluster of the first layer memory openings 149 can include a respective two-dimensional array of first layer memory openings 149 having a first pitch along one horizontal direction and a second pitch along another horizontal direction. In one embodiment, the direction of the first memory structure pitch can be a first horizontal direction (e.g., a word line direction) hd1, and the direction of the second memory structure pitch can be a second horizontal direction (e.g., a bit line direction) hd2, or vice versa.

[0126] The interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate than the first insulating layer 132 (which may include undoped silicate glass). In one embodiment, the bottom surface of each first-level memory opening 149 may be formed between the top surface and the bottom surface of the source-level sacrificial layer 104. In this case, the surface of the source-level sacrificial layer 104 may be exposed at the bottom portion of each first-level memory opening 149. Figure 4 The positions of the steps S in the first vertical alternating sequence (132, 142) are shown in dotted lines in B.

[0127] refer to Figure 6, a sacrificial first layer opening filling portion (148, 128) may be formed in the first layer opening (149, 129). For example, a sacrificial filling material may be simultaneously deposited in each of the first layer openings (149, 129). The sacrificial filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142.

[0128] In one embodiment, the sacrificial fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop layer (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be employed prior to depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0129] In another embodiment, the sacrificial fill material may include a silicon oxide material having a higher etching rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer insulating layer 180. For example, the sacrificial fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etching rate at least 100 times higher than the etching rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process) in 100:1 dilute hydrofluoric acid. In this case, a thin etch stop layer (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0130] In yet another embodiment, the sacrificial fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed with respect to the material of the first alternating stack (132, 142).

[0131] Portions of the deposited sacrificial fill material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0132] The remaining portions of the sacrificial filling material include sacrificial first layer opening filling portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening filling portion 128. The top surface of the sacrificial first layer opening filling portion (148, 128) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening filling portions (148, 128) may or may not include a cavity therein.

[0133] refer to Figure 7 , a second layer structure may be formed above the first layer structure (132, 142, 170, 165, 148, 128). The second layer structure may include an additional vertical alternating sequence of additional insulating layers and additional spacer material layers, which may be sacrificial material layers. The second vertical alternating sequence is also referred to as a second alternating stack. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0134] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0135] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0136] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0137] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) may have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0138] The same set of processing steps as those used to form the first stepped surface in the first stepped region may be used, while appropriately adjusting the pattern of at least one mask layer, to form a second stepped surface in the second stepped region of each stair region 200. A second backward stepped dielectric material portion 265 may be formed over the second stepped surface in the stair region 200.

[0139] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265. The second insulating capping layer 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may include silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride.

[0140] Optionally, a drain selection level isolation structure 72 may be formed through the second insulating cap layer 270 and through a subset of the layers in the upper portion of the second vertical alternating sequence (232, 242). The second sacrificial material layer 242 cut by the drain selection level shallow trench isolation structure 72 corresponds to a level at which a drain selection level conductive layer is subsequently formed. The drain selection level isolation structure 72 includes a dielectric material such as silicon oxide. The drain selection level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0141] In general, at least one vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source level material layer 10' during the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the staircase area on at least one alternating stack (132, 142, 232, 242). Each of the insulating layers (132, 232) and the spacer material layers (such as sacrificial material layers (142, 242)) can be formed as a respective single continuous material layer. In this case, the insulating layers (132, 232) can be referred to as continuous insulating layers, and the spacer material layers can be referred to as continuous spacer material layers (e.g., continuous sacrificial material layers).

[0142] refer to Figure 8 , second layer openings (249, 229) may be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first layer openings (149, 129), which are the same as the sacrificial first layer opening filling portions (148, 128). Thus, the photoresist layer may be patterned using a photolithographic mask used to pattern the first layer openings (149, 129).

[0143] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form second layer openings (249, 229). The second layer openings (249, 229) can include second layer memory openings 249 and second layer support openings.

[0144] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support opening 229 is formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. Figure 7 The positions of the steps S in the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242) are shown in dotted lines in B.

[0145] refer to Fig. 9 The sacrificial fill material can be removed from below the second layer memory opening 249 and the second layer support opening 229 using an etching process that selectively etches the sacrificial fill material with respect to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49, also referred to as an interlayer memory opening 49, is formed in each volume from which a sacrificial first layer memory opening fill portion 148 is removed. A support opening 19, also referred to as an interlayer support opening 19, is formed in each volume from which a sacrificial first layer support opening fill portion 128 is removed.

[0146] FIG. 10A to FIG. 10D Sequential cross-sectional views of the memory openings 49 are provided during the formation of the memory opening filling structure 58 or the support pillar structure 20. The same structural changes occur in each memory opening 49.

[0147] refer to Fig. 10A , showing Fig. 9 The memory opening 49 in the first exemplary device structure. The memory opening 49 extends through the first layer structure and the second layer structure.

[0148] refer to Fig. 10B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0149] Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. As used herein, a first surface and a second surface "vertically coincide" if there is a second surface above or below the first surface and if there is a vertical plane that intersects both the first surface and the second surface. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2nm to 20nm, but smaller and larger thicknesses can also be used.

[0150] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0151] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0152] refer to Fig. 10C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or deposited by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0153] refer to Fig. 10D , a doped semiconductor material may be deposited in a cavity covering the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0154] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the drain region 63 may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0155] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0156] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. In the process, the source level material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 58 together constitute a memory level component.

[0157] refer to Fig.11A and Fig. 11B , shows a first exemplary structure after forming a memory opening filling structure 58 in the memory opening 49 and forming a support pillar structure 20 in the support opening 19. While forming the memory opening filling structure 58, each of the support openings 19 is filled with a corresponding support pillar structure 20. Each support pillar structure 20 may have the same structural elements as the memory opening filling structure 58. Each support pillar structure 20 is a dummy structure (i.e., an electrically inert structure) and therefore does not subsequently contact any contact via structure.

[0158] refer to FIG. 12A to FIG. 12D A first contact-level dielectric layer 280 may be formed over the second layer structure (232, 242, 270, 265, 72). The contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be employed.

[0159] A photoresist layer (not shown) may be applied over the contact level dielectric layer 280 and may be photolithographically patterned to form openings in regions extending across the memory array region 100 and the staircase region 200. The openings in the photoresist layer may extend laterally along the first horizontal direction hd1 between each adjacent cluster of memory opening fill structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the contact level dielectric layer 280, the second alternating stack (232, 242, 270, 265, 72), the first alternating stack (132, 142, 170, 165), and the source level material layer 110' during the process. Portions of the contact level dielectric layer 280, the second alternating stacks (232, 242, 270, 265, 72), the first alternating stacks (132, 142, 170, 165), and the source level material layer 110' in the process below the openings in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of memory opening fill structures 58. The clusters of memory opening fill structures 58 may be laterally spaced apart by backside trenches 79 along a second horizontal direction hd2.

[0160] In general, at least one vertical alternating sequence of continuous insulating layers (132, 232) and continuous spacer material layers (such as continuous sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 142), (232, 242)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) by forming backside trenches 79 extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The contact-level dielectric layer 280 is divided into a plurality of contact-level dielectric layers 280 by the backside trenches 280. Each of the plurality of contact-level dielectric layers 280 overlies a corresponding alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) and overlies a corresponding array of memory opening filling structures 58.

[0161] In general, by forming backside trenches 79 extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2, a vertical alternating sequence of continuous insulating layers (132, 232) and continuous spacer material layers (such as continuous sacrificial material layers (142, 242)) can be divided into insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) alternately stacked {(132, 142), (232, 242)}. Fig. 12CIn one aspect of the present disclosure shown, the backside trenches 79 and the source layer segments 111 are staggered along a second horizontal direction (eg, a bit line direction) hd2 such that each backside trench 79 is formed between an adjacent pair of source layer segments 111 .

[0162] The first exemplary structure includes multiple instances of a unit structure US extending laterally along a first horizontal direction (e.g., a word line direction) hd1 and repeating along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each instance of the unit structure US includes a corresponding alternating stack {(132, 142), (232, 242)} of insulating layers (132, 232) and sacrificial material layers (142, 242) alternating along a vertical direction. The corresponding alternating stack {(132, 142), (232, 242)} is laterally spaced apart from the alternating stack {(132, 142), (232, 242)} in an adjacent instance of the unit structure US by a corresponding backside trench 79.

[0163] refer to Fig.13A , a backside trench spacer 77 may be formed on the sidewalls of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the contact-level dielectric layer 280, and may be anisotropically etched to form the backside trench spacers 77. The backside trench spacers 77 include a material different from that of the source-level sacrificial layer 104. For example, the backside trench spacers 77 may include silicon oxide, a dielectric metal oxide, or silicon nitride.

[0164] refer to Fig. 13BIn an isotropic etching process, an etchant that selectively etches the material of the source level sacrificial layer 104 with respect to the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the first and second insulating capping layers (170, 270), the upper dielectric liner layer 105, and the lower dielectric liner layer 103 can be introduced into the backside trench 79. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, the backside trench spacers 77 comprise silicon nitride, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process that employs thermal trimethyl-2-hydroxyethylammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH) can be employed to selectively remove the source level sacrificial layer 104 with respect to the backside trench spacers 77 and the upper and lower dielectric liner layers (105, 103). Alternatively, if the source level sacrificial material layer 104 comprises silicon nitride, the backside trench spacers 77 comprise silicon oxide or dielectric metal oxide, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process (which employs hot phosphoric acid) may be employed to selectively remove the source level sacrificial layer 104 with respect to the backside trench spacers 77 and the upper and lower dielectric liner layers (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0165] refer to Fig. 13C , a sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 through the backside trenches 79 and the source cavity 109 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the bottom surface and cylindrical side surfaces of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower dielectric liner layers (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower dielectric liner layers (105, 103). The top surface of the lower source level material layer 112 and the bottom surface of the higher source level material layer 116 can be physically exposed to the source cavity 109. After removing the physically exposed portion of the memory film 50, the outer sidewall of each vertical semiconductor channel 60 is physically exposed to the source cavity 109. A dielectric material stack 150 is formed under each physically exposed cylindrical surface of the vertical semiconductor channel 60. Each dielectric material stack 150 is a remaining portion of the memory film 50 and includes the same dielectric material stack as the memory film 50.

[0166] Therefore, the higher source level material layer 116 can act as an etch stop layer during the selective etching of the memory film 50 through the source cavity 109 and can prevent lateral expansion of the source cavity 109. This prevents a short circuit between the source select level conductive layer 118 and a source contact layer that is subsequently formed in the source cavity 109 during a subsequent step.

[0167] refer to Fig.13D The source contact layer 114 may be formed by a selective deposition process of a doped semiconductor material having a second conductivity type, which is referred to herein as a third doped semiconductor material. The doped semiconductor material may include amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy. The third doped semiconductor material of the source contact layer 114 may be grown from a physically exposed semiconductor surface surrounding the source cavity 109. The average atomic concentration of the second conductivity type dopant in the source contact layer 114 may be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, but smaller and larger dopant concentrations may also be used.

[0168] In-process source level material layer 110' is replaced with source level material layer 10. Source level material layer 110 includes a layer stack, which includes, from bottom to top, a lower source level material layer 112, a source contact layer 114, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118. The combination of lower source level material layer 112, source contact layer 114, and higher source level material layer 116 constitutes a source layer (112, 114, 116). When source level sacrificial layer 104 is replaced with source contact layer 114, in-process source level material layer 110' is converted into a source level material layer 110 including source layer (112, 114, 116).

[0169] refer to Fig.13E and FIG. 14A to FIG. 14D , the backside trench spacers 77 can be removed selectively to the semiconductor material of the source contact layer 114. For example, if the backside trench spacers 77 include silicon nitride, a wet etching process (which uses hot phosphoric acid) can be used to remove the backside trench spacers 77. If the backside trench spacers 77 include silicon oxide, a wet etching process (which uses dilute hydrofluoric acid) can be used to remove the backside trench spacers 77. The sidewalls of the first and second alternating stacks (132, 142, 232, 242), the higher source level material layer 116, the source level insulating layer 117, and the optional source select level conductive layer 118 can be physically exposed after removing the backside trench spacers 77.

[0170] A thermal oxidation process may be performed to convert physically exposed surface portions of various semiconductor materials into semiconductor oxide portions. Specifically, physically exposed surface portions of source contact layer 114, higher source level material layer 116, and source select level conductive layer 118 (if present) are converted into thermal semiconductor oxide material portions. As used herein, "thermal semiconductor oxide" refers to a material formed by thermal oxidation of a semiconductor material. Unlike semiconductor oxide materials formed by chemical vapor deposition, thermal semiconductor oxide materials do not contain carbon or hydrogen above trace levels unless the semiconductor material from which the semiconductor oxide material is derived contains carbon prior to the thermal oxidation process.

[0171] The thermal oxidation process forms a semiconductor oxide plate 122 at the bottom of each backside trench 79 and a semiconductor oxide track 124 on the sidewalls of the source select level conductive layer 118. For clarity, the semiconductor oxide track 124 is not shown in FIG 14. The semiconductor oxide plate 122 includes various thermal semiconductor oxide material portions formed by thermal conversion of surface portions of the source contact layer 114 and the higher source level material layer 116.

[0172] The layer stack including the lower source level material layer 112, the source contact layer 114 and the upper source level material layer 116 constitutes a source layer (112, 114, 116), which is a buried source layer used as a common source region that connects each of the vertical semiconductor channels 60 and has a doping of the second conductivity type. The average dopant concentration of the buried source layer (112, 114, 116) can be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 range, although smaller and larger dopant concentrations may also be used.

[0173] like Fig. 14CAs shown, after replacing each source level sacrificial layer in the source level sacrificial layer 104 with a corresponding source contact layer 114, each source layer segment in the source layer segment 111 is converted into a corresponding source layer segment (111A, 111B), which can also be called a source line. The adjacent first source layer segment 111A and the second source layer segment 111B are laterally isolated and separated from each other along the second horizontal direction hd2 by the corresponding source isolation structure 12. Each source layer segment in the source layer segment (111A, 111B) includes: a lower source level material layer 112, which includes a first doped semiconductor material; a higher source level material layer 116, which includes a second doped semiconductor material; and a source contact layer 114, which includes a third doped semiconductor material. In one embodiment, within each instance of the cell structure US, each vertical semiconductor channel 60 in the first memory opening filling structure 58A contacts the source contact layer 114 within the corresponding first source layer segment 111A; and each vertical semiconductor channel 60 in the second memory opening filling structure 58B contacts the source contact layer 114 within the corresponding second source layer segment 111B. The cell structure US is located between two adjacent backside trenches 79. Each backside trench 79 laterally separates the conductive layers (e.g., word lines and select gate electrodes) (146, 246) of adjacent cell structures and is located above the corresponding source layer segment (e.g., 111A or 111B) and may partially extend into the corresponding source layer segment. However, in the first embodiment, each source layer segment (e.g., 111A) extends below the corresponding backside trench 79 between at least two adjacent cell structures US. Therefore, each source layer segment (e.g., 111A) serves as the source layer of at least two different adjacent cell structures US.

[0174] In one embodiment, each of the memory opening filling structures 58 includes a corresponding memory film 50 that laterally surrounds a corresponding vertical semiconductor channel 60, has a corresponding annular concave bottom surface that contacts a corresponding source contact layer 114, and has a corresponding cylindrical outer surface that contacts a corresponding higher source level material layer 116.

[0175] refer to Fig.15, an etchant that selectively etches the material of the first and second sacrificial material layers (142, 242) relative to the material of the first and second insulating layers (132, 232), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the first and second sacrificial material layers (142, 242) can include silicon nitride, and the first and second insulating layers (132, 232), the first and second insulating cap layers (170, 270), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can include silicon oxide material. The first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed.

[0176] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced in the vapor phase into the backside trench 79. For example, if the first and second sacrificial material layers (142, 242) include silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0177] Each of the first backside recess and the second backside recess (143, 243) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second backside recesses (143, 243) can be greater than the height of the corresponding backside recess (143, 243). A plurality of first backside recesses 143 can be formed in a volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which the material of the second sacrificial material layer 242 is removed. Each of the first and second backside recesses (143, 243) can extend substantially parallel to the top surface of the substrate 8. The backside recess (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the insulating layer (132 or 232) covering it. In one embodiment, each of the first and second backside recesses (243, 243) may have a uniform height throughout.

[0178] refer to FIG. 16A to FIG. 16D, a backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses and the backside trenches 79 and over the contact-level dielectric layer 280. At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trenches 79, and over the contact-level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element.

[0179] A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 280. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0180] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metal material may include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0181] The deposited metal material of the continuous metal material layer may be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 280. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure.

[0182] A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode can be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55. The source select level conductive layer 118 is used as a source select gate electrode.

[0183] Each memory opening filling structure in the memory opening filling structure 58 (which includes a corresponding memory stack structure 55) includes a vertical stack of memory elements at each level of the conductive layer (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The semiconductor devices in the peripheral device area 700 below may include word line switch devices that are configured to control bias voltages to corresponding word lines. The memory level component includes all structures located above the topmost surface of the lower level metal interconnect structure 780 and is located above the substrate semiconductor layer 9 and vertically spaced apart from the substrate semiconductor layer. The memory level component includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). The at least one alternating stack (132, 146, 232, 246) includes a staircase region including steps in which each underlying conductive layer (146, 246) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246) within the memory level assembly.

[0184] In general, the sacrificial material layer (142, 242) can be replaced with a conductive layer (146, 246) to form an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) that are laterally spaced apart from each other by backside trenches 79. The unit structure US extending laterally along the first horizontal direction hd1 can be repeated along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, each instance of the unit structure US includes a corresponding alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) alternating along a vertical direction. The respective alternating stacks {(132, 146), (232, 246)} in one unit structure US are laterally spaced apart from the alternating stacks {(132, 146), (232, 246)} in an adjacent unit structure US by respective backside trenches 79.

[0185] refer to FIG. 17A to FIG. 17E , a layer of insulating spacer material, such as a silicon oxide layer, may be formally deposited in the backside trench 79 and above the contact level dielectric layer 280. An anisotropic etching process may be performed to remove horizontally extending portions of the insulating spacer material layer from above the contact level dielectric layer 280 and from the bottom of the backside trench 79. In one embodiment, a central portion of the semiconductor oxide plate 122 may be incidentally etched to physically expose a top surface segment of an underlying portion of the source contact layer 114. Each remaining vertically extending tubular portion of the insulating spacer material layer constitutes a backside insulating spacer 74.

[0186] At least one conductive material (such as at least one metal material) may then be deposited in the cavity in the backside trench 79. The at least one conductive material may include at least one metal barrier material (e.g., a metal nitride material such as TiN, TaN, MoN, and / or WN) and at least one metal filling material (e.g., W, Cu, Co, Ru, Mo, etc.). Excess portions of the at least one metal material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 280 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one metal material constitutes a backside contact via structure 76. Each continuous combination of the backside insulating spacer 74 and the backside contact via structure 76 constitutes a backside trench filling structure (74, 76). Each backside trench 79 within the backside trench 79 may be filled with a corresponding backside trench filling structure (74, 76).

[0187] Generally, the backside trench filling structures (74, 76) can be formed in the backside trench 79. Each of the backside trench filling structures (74, 76) includes a corresponding backside insulating spacer 74 and a corresponding backside contact via structure 76. In one embodiment, each of the backside contact via structures 76 is formed directly on a corresponding surface of the source contact layer 114. In one embodiment, each recessed surface segment of the source layer (112, 114, 116) contacted by the corresponding backside contact via structure 76 is a surface of the source contact layer 114. In one embodiment, each backside contact via structure 76 is laterally surrounded by a corresponding backside insulating spacer 74 and is laterally spaced apart from the corresponding adjacent pair of alternating stacks {(132, 146), (232, 246)} by the corresponding backside insulating spacer. Each backside insulating spacer 74 laterally surrounds the corresponding backside contact via structure 76 therein.

[0188] Fig.17F yes Fig. 17C Schematic block diagram of a first exemplary structure is shown. Each region of the conductive layer (146, 246) extending over a corresponding source isolation dielectric structure 12 and serving as a word line of a memory device is referred to as a "word line bridge" region 102. The drain side select gate electrode SGD (i.e., at least one topmost second conductive layer 246D) does not extend across the word line bridge region 102. Fig. 17C , Fig.17F and Figure 17G As shown, the source side select gate electrode SGS (i.e., the optional source select level conductive layer 118 and / or at least one bottommost first conductive layer 146S) may or may not extend across the word line bridge region 102. For example, the source isolation dielectric structure 12 may separate the source select level conductive layer 118, which may serve as the bottommost source side select gate electrode SGS. Instead, the word line (i.e., conductive layer (146, 246)) vertically located between the source and drain side select gate electrodes ((118, 146S) and 246D) extends across the word line bridge region 102. Fig.17F Each cell array region in the embodiment includes a portion of the memory array region 100 including word lines ( 146 , 246 ) and memory opening filling structures 58 .

[0189] Figure 17G is an alternative configuration of the first exemplary structure, in which two or more drain selection level isolation dielectric structures 72 are embedded in each memory block MB. Therefore, in this alternative embodiment, each memory block MB may have more than four rows of active memory opening filling structures 58, for example, eight rows of active memory opening filling structures 58.

[0190] Common Reference FIG. 17A to FIG. 17G, each unit structure US includes a plurality of memory blocks MB. For example, in the first embodiment, each unit structure US includes two memory blocks MB. The two memory blocks MB in each unit structure US share the same word line, but include separate source layers 111. Therefore, the memory blocks MB in the same unit structure US are individually addressed using separate source layers 111. Therefore, each source layer segment (111A, 111B, 111C) is electrically connected to a separate corresponding source line switching device (e.g., transistor or circuit) 711 (e.g., 711A, 711B, 711C) in the peripheral circuit 710 located in the peripheral region 700 through a corresponding source interconnect 713 (e.g., source line), as shown in FIG. Fig.17F As shown in . However, because the memory blocks MB in the same unit structure US share the same word line, for each word line extending through the two memory blocks MB, they also share the same word line switching device (e.g., transistor or circuit) 746 (e.g., 746A, 746B, 746C) in the peripheral circuit 710 in the peripheral area 700. Compared with using a separate word line switching device for each word line in each memory block MB, this configuration reduces the area of ​​the word line switching device by half without increasing the memory block MB capacity to avoid complicating power and performance. Therefore, the cost and area of ​​the peripheral circuit 710 located in the peripheral area 700 are reduced.

[0191] Therefore, in the first embodiment, the word line is bridged over two memory blocks MB in the same unit structure US, which reduces the number of word line switching devices 746 by half.

[0192] The source layer 111 is isolated above every two memory blocks MB in the adjacent unit structure US. Fig.17F As shown, this allows the source layer 111 to bias each source layer segment (e.g., 111A, 111B, 111C) through a corresponding source line switching device 711 (e.g., 711A, 711B, 711C). This requires adding only one source line switching device 711 for two memory blocks MB, which occupies a much smaller space than the word line switching device 746 used to switch each word line. Therefore, the source line switching device 711 does not significantly contribute to an increase in the area or cost of the peripheral area 700. The word line bridged (i.e., paired) memory blocks MB in the same unit structure US are laterally offset from the source layer 111 paired memory blocks MB in the adjacent unit structure US along the bit line direction hd2 to allow the memory cell operation bias (i.e., electrical bias conditions) to be differentiated for each memory block MB. Therefore, the first embodiment utilizes half of the word line switching devices commonly used in conventional devices to achieve a single memory block capacity.

[0193] In a first embodiment, within each instance of the unit structure US, the conductive layer (146, 246) extends laterally continuously between the corresponding adjacent pairs of backside trench filling structures (74, 76). In one embodiment, each unit structure US includes no more than one of the backside trench filling structures (74, 76), that is, each backside trench filling structure (74, 76) is adjacent to and shared between two adjacent unit structures US. In one embodiment, each instance of the unit structure US includes a contact level dielectric layer 280, which covers the corresponding alternating stack {(132, 146), (232, 246)} and contacts the sidewalls of each backside trench filling structure (74, 76) within the corresponding adjacent pair of backside trench filling structures (74, 76). In one embodiment, each alternating stack {(132, 146), (232, 246)} contacts no more than two backside trench filling structures (74, 76) of the backside trench filling structures (74, 76) of the memory device. Each source layer segment (111A, 111B) contacts the bottom surfaces of two alternating stacks {(132, 146), (232, 246)} in two corresponding adjacent unit structures US, and laterally contacts the sidewalls of two isolation dielectric structures in the isolation dielectric structure 12.

[0194] In one embodiment, each backside trench filling structure (74, 76) between corresponding adjacent pairs of source isolation dielectric structures 12 is located in the middle between corresponding adjacent pairs of source isolation dielectric structures 12 along the second horizontal direction hd2. Each source isolation dielectric structure 12 may be located between adjacent pairs of backside trench filling structures (74, 76) and in the middle between adjacent pairs of backside trench filling structures (74, 76) along the second horizontal direction hd2.

[0195] refer to 18A to 18C, a via-level dielectric layer 282 may be formed over the contact-level dielectric layer 280. A photoresist layer (not shown) may be applied over the via-level dielectric layer 282. The photoresist layer is photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure may be formed through the via-level dielectric layer 282 and the contact-level dielectric layer in the memory array region 100, and an opening for forming a layer contact via structure may be formed through the via-level dielectric layer 282, the contact-level dielectric layer 280, and the backward stepped dielectric material portion (165, 265) in the staircase region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the via-level dielectric layer 282, the contact-level dielectric layer 280, and the underlying dielectric material portion. The drain region 63 and the conductive layer (146, 246) may be used as an etch stop structure. A drain contact via cavity may be formed over each drain region 63, and a layer contact via cavity may be formed over each conductive layer (146, 246) at the stepped surface below the first and second backward stepped dielectric material portions (165, 265). The photoresist layer may then be removed, for example, by ashing.

[0196] At least one conductive material may be deposited in the layer contact via cavity and the drain contact via cavity. The at least one conductive material may include at least one metallic material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the via level dielectric layer 282 by a planarization process. The planarization process may employ a recess etching process and / or a chemical mechanical planarization process. The remaining portion of the at least one conductive material in the drain contact via cavity constitutes the drain contact via structure 88. The remaining portion of the at least one conductive material in the layer contact via cavity constitutes the layer contact via structure 86.

[0197] A connecting via structure (referred to herein as a through memory level connecting via structure 488) may be formed through the backward stepped dielectric material portion (165, 265) on a corresponding one of the lower level metal interconnect structures 780. A higher level metal interconnect structure (96, 98) and a higher level dielectric material layer may be formed over the via level dielectric layer 282. For example, the higher level dielectric material layer may include a bit line level dielectric layer 290 and an additional dielectric material layer (not shown). The higher level metal interconnect structure (96, 98) may include a bit line 98, a bit line level metal line 96, and additional metal lines and via structures (not shown) formed over the bit line 98 and the bit line level metal line 96.

[0198] In one embodiment, each of the alternating stacks {(132, 146), (232, 246)} has a respective stepped surface having a lateral extent along a first horizontal direction hd1 that decreases with vertical distance from the semiconductor substrate 8. The backward stepped dielectric material portion (165, 265) overlies the stepped surface of the alternating stack {(132, 146), (232, 246)}. The through-memory level connection via structure 488 extends vertically through a respective one of the backward stepped dielectric material portions (165, 265). The peripheral circuit is electrically connected to the conductive layer (146, 246) and the memory element vertical stack (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) through the lower level metal interconnect structure 780 and through the higher level metal interconnect structure.

[0199] Common Reference Figures 1A to 18CAnd according to various embodiments of the present disclosure, a memory device is provided, which includes multiple instances of a unit structure US extending laterally along a first horizontal direction hd1 and repeated along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each instance of the unit structure US includes a corresponding alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) alternating along a vertical direction. The corresponding alternating stack {(132, 146), (232, 246)} is laterally spaced apart from the alternating stack {(132, 146), (232, 246)} in an adjacent instance of the unit structure US by a corresponding backside trench 79, and the corresponding backside trench is filled with a corresponding backside trench filling structure (74, 76). A laterally alternating sequence of source layers (112, 114, 116) and source isolation dielectric structures 12 is located below the alternating stacks {(132, 146), (232, 246)} such that each source isolation dielectric structure 12 contacts and is located below a middle portion of a corresponding one of the alternating stacks {(132, 146), (232, 246)}, and each source layer (112, 114, 116) extends between a corresponding adjacent pair of source isolation dielectric structures 12. Each instance of the unit structure US includes: first memory opening filling structures 58, which extend vertically through the corresponding alternating stacks {(132, 146), (232, 246) on the first side of the corresponding underlying source isolation dielectric structure 12 and extend into the corresponding first source layer (112, 114, 116); and second memory opening filling structures 58, which extend vertically through the corresponding alternating stacks {(132, 146), (232, 246) on the second side of the corresponding underlying source isolation dielectric structure 12 and extend into the corresponding second source layer (112, 114, 116), which is laterally spaced and electrically isolated from the corresponding source layer (112, 114, 116) by the corresponding underlying source isolation dielectric structure 12. Each of the first memory opening filling structures 58 and the second memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements.

[0200] In one embodiment, the source isolation dielectric structure 12 extends laterally along a first horizontal direction hd1; and at least one of the source isolation dielectric structures 12 has a variable width along a second horizontal direction hd2, which variable width decreases with the vertical distance from the interface of a corresponding one of the alternating stacks {(132,146),(232,246).

[0201] In one embodiment, each of the source layers (112, 114, 116) includes: a lower source level material layer 112 including a first doped semiconductor material; an upper source level material layer 116 including a second doped semiconductor material; and a source contact layer 114 including a third doped semiconductor material and located between the upper source level material layer 116 and the lower source level material layer 112. In one embodiment, each of the back side trench filling structures (74, 76) includes a back side contact via structure 76 and a back side insulating spacer 74 laterally surrounding the back side contact via structure 76.

[0202] In one embodiment, the backside contact via structure 76 within each of the backside trench fill structures (74, 76) contacts the surface of the corresponding source contact layer 114. In one embodiment, within each instance of the unit structure US, each vertical semiconductor channel 60 in the first memory opening fill structure 58 contacts the source contact layer 114 within the corresponding first source layer (112, 114, 116); and each vertical semiconductor channel 60 in the second memory opening fill structure 58 contacts the source contact layer 114 within the corresponding second source layer (112, 114, 116).

[0203] In one embodiment, each of the memory opening filling structures 58 includes a corresponding memory film 50 that laterally surrounds a corresponding vertical semiconductor channel 60, has a corresponding annular concave bottom surface that contacts a corresponding source contact layer 114, and has a corresponding cylindrical outer surface that contacts a corresponding higher source level material layer 116.

[0204] In one embodiment, within each instance of the unit structure US, the conductive layer (146, 246) extends laterally continuously between the corresponding adjacent pairs of backside trench filling structures (74, 76). In one embodiment, each unit structure US includes no more than one backside trench filling structure (74, 76) among the backside trench filling structures (74, 76) of the memory device. In one embodiment, each instance of the unit structure US includes a contact level dielectric layer overlying the corresponding alternating stack {(132, 146), (232, 246)} and contacting the sidewalls of each backside trench filling structure (74, 76) within the corresponding adjacent pair of backside trench filling structures (74, 76).

[0205] In one embodiment, each alternating stack {(132, 146), (232, 246)} contacts no more than two backside trench filling structures (74, 76) of the memory device; and each source layer (112, 114, 116) contacts the bottom surface of no more than two alternating stacks {(132, 146), (232, 246)} of the alternating stacks {(132, 146), (232, 246)} of the memory device, and contacts no more than two source isolation dielectric structures 12 of the source isolation dielectric structures 12 of the memory device.

[0206] In one embodiment, each backside trench filling structure (74, 76) located between corresponding adjacent pairs of source isolation dielectric structures 12 is located in the middle between corresponding adjacent pairs of source isolation dielectric structures 12 along the second horizontal direction hd2; and each source isolation dielectric structure 12 located between corresponding adjacent pairs of backside trench filling structures (74, 76) is located in the middle between adjacent pairs of backside trench filling structures (74, 76) along the second horizontal direction hd2.

[0207] In one embodiment, the memory device also includes: a semiconductor substrate 8, which is below multiple instances of the unit structure US; and a peripheral circuit, which is located on the semiconductor substrate 8 and is electrically connected to the conductive layer (146, 246) and the vertical stack of memory elements through a lower metal interconnect structure 780 below the multiple instances of the unit structure US, a connecting via structure 488 located at the same level as the multiple instances of the unit structure US, and a higher metal interconnect structure (96, 98) above the multiple instances of the unit structure US.

[0208] In one embodiment, each of the alternating stacks {(132, 146), (232, 246)} has a corresponding stepped surface having a lateral extent that decreases with the vertical distance from the semiconductor substrate 8 along the first horizontal direction hd1; the backward stepped dielectric material portion (165, 265) covers the stepped surface of the alternating stack {(132, 146), (232, 246)}; and the connecting through-hole structure 488 extends vertically through a corresponding one of the backward stepped dielectric material portions 488.

[0209] refer to Fig.19, a second exemplary structure according to a second embodiment of the present disclosure includes a substrate 908 including a substrate material layer 909. The substrate 8 may include a semiconductor substrate, an insulating substrate, and / or a conductive substrate. Generally speaking, the substrate 908 may be any substrate that can be used as a carrier substrate. In one embodiment, the substrate material layer 909 may include a single crystal semiconductor material layer (such as a single crystal semiconductor layer). Optionally, the substrate 908 may include a dielectric material layer (e.g., a silicon oxide layer; not shown) in an upper portion thereof.

[0210] The semiconductor material layer 10 is located on the top surface of the substrate 908. The semiconductor material layer 10 may include a doped well (e.g., a doped silicon well) in the top surface of a silicon wafer used as the substrate material layer 909. Alternatively, the semiconductor material layer 10 may include an epitaxial silicon layer located on the top surface of the substrate 908 or a silicon layer of a silicon-on-insulator substrate 908.

[0211] refer to Fig. 20 , executable reference Figure 3 The processing steps are described to form a first vertical alternating sequence of first insulating layers 132 and first spacer material layers 142 .

[0212] refer to Fig.21 , executable reference Figure 4 The processing steps are described to pattern the first stepped surface and form the first back stepped dielectric material portion 165 and the interlayer dielectric layer 180 .

[0213] refer to Fig.22A and Fig. 22B , executable Figure 5A and Figure 5B The processing steps are performed to form the first layer memory opening 49 and the first layer support opening 129. In one embodiment, each of the first layer memory opening 49 and the first layer support opening 129 can be directly formed into a corresponding layer stack of the source level material layer 110' in the process (as divided by the source isolation dielectric structure 12), and can be laterally offset from the source isolation dielectric structure 12.

[0214] refer to Fig.23 , executable reference Figure 6 The processing steps are described to form sacrificial first layer memory opening filling portion 148 and sacrificial first layer support opening filling portion 128 .

[0215] refer to Fig.24 , executable reference Figure 7 The processing steps are described to form a second vertical alternating sequence of second insulating layers 232 and second spacer material layers 242 , a second stepped surface, a second backward stepped dielectric material portion 265 , and a drain select level isolation structure 72 .

[0216] refer to Fig.25A and Fig.25B , executable reference Figure 8 The processing steps are described to form the second layer memory opening 149 and the second layer support opening 229 .

[0217] refer to Fig.26 , executable reference Fig. 9 The processing steps are described to form the inter-layer memory opening 49 and the inter-layer support opening 19 .

[0218] refer to Fig.27A and Fig.27B , executable FIG. 10A to FIG. 10D as well as Fig.11A and Fig. 11B The processing steps are performed to form memory opening filling structures 58 and support pillar structures 20. Each of the memory opening filling structures 58 includes a corresponding vertical stack of memory elements (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60.

[0219] refer to FIG. 28A to FIG. 28C , executable reference FIG. 12A to FIG. 12D The processing steps are described to form a contact level dielectric layer 280 over the memory opening fill structure 58 and to form backside trenches 79. By forming the backside trenches 79, the vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 142), (232, 242)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)). The surface of the semiconductor material layer 10 can be physically exposed around the bottom portion of each backside trench 79.

[0220] refer to Fig.29 , execute reference Fig.15 The processing steps are described to form the backside recess (143, 243) by removing the sacrificial material layer (142, 242).

[0221] refer to Fig. 30A and Fig. 30B , executable reference FIG. 16A to FIG. 16DThe described processing steps are used to form a conductive layer (146, 246) in the backside recess (143, 243). Alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are formed, and these alternating stacks are laterally spaced apart from each other by backside trenches 79. The alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are laterally spaced apart from each other along the second horizontal direction hd2 by backside trenches 79, which extend laterally along the first horizontal direction hd1.

[0222] refer to FIG. 31A to FIG. 31C , at least one dielectric filling material such as silicon oxide may be deposited in the backside trench 79 to form a backside trench filling structure 176. Each instance of the unit structure US includes a backside trench filling structure 176 substantially consisting of at least one dielectric material. Alternatively, each backside trench filling structure 176 may be located between two adjacent unit structures US, so that each unit structure US includes two halves of the backside trench filling structure 176.

[0223] refer to Fig.32A and Fig.32B , you can execute reference 18A to 18C Processing steps are described to form via level dielectric layer 282 , drain contact via structure 88 , layer contact via structure 86 , bit line level dielectric layer 290 , bit line 98 , and bit line level metal line 96 .

[0224] refer to Fig.33 , an additional dielectric material layer 960 and an additional metal interconnect structure (986, 988) may be subsequently formed. The additional dielectric material layer 960 may include an interconnect level dielectric material layer 964, a passivation dielectric layer 966, and a pad level dielectric material layer 968. The additional dielectric material layer 960 is also referred to as a memory side dielectric material layer 960. The additional metal interconnect structure (986, 988) may include a memory side metal line 988 and a memory side metal via structure 986. A memory side bonding pad 998 may be formed in the pad level dielectric material layer 968. In one embodiment, the memory side bonding pad 998 may include a metal bonding pad (e.g., a copper bonding pad) configured for metal-to-metal bonding (such as copper-to-copper bonding). A memory die 900 is provided.

[0225] refer to Fig.34, a logic die 700 is provided, the logic die including a logic side substrate 708, the logic side substrate including a logic side substrate semiconductor layer 709 and a peripheral circuit 710 formed on the top surface of the logic side substrate semiconductor layer 709. The peripheral circuit 710 may be configured to control the operation of the conductive layer (146, 246) and the vertical stack of memory elements (the vertical stack of memory elements may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)), and may have the same set of components as the peripheral circuit 710 described above and may provide the same functionality. In the second exemplary structure, the dielectric material layer corresponding to the lower level dielectric material layer 760 in the first and second exemplary structures is referred to as the logic side dielectric material layer 760, and the metal interconnect structure corresponding to the lower level metal interconnect structure 780 in the first and second exemplary structures is referred to as the logic side metal interconnect structure 780. The logic side dielectric material layer 760 may include a pad level dielectric material layer 769 embedded with a logic side bonding pad 798. In one embodiment, the memory side bonding pads 798 may include metal bonding pads (e.g., copper bonding pads) configured for metal-to-metal bonding (e.g., copper-to-copper bonding). The pattern of the logic side bonding pads 798 as seen in the top view may be a mirror image pattern of the pattern of the memory side bonding pads 998 as seen in the top view.

[0226] Logic die 700 may be bonded to memory die 900 by aligning logic side bond pads 798 with memory side bond pads 998 and inducing metal-to-metal bonds between mating pairs of logic side bond pads 798 and memory side bond pads 998 using a bond anneal.

[0227] refer to Fig.35 , removing the semiconductor material layer 10, and then removing the substrate 900 of the memory die 900. In one embodiment, the substrate material layer 909 of the substrate 909 of the memory die 900 can be thinned or removed from the back side, for example, by grinding, polishing, cleaving, at least one anisotropic etching process and / or at least one isotropic etching process, followed by selective etching of the semiconductor material layer 10. The bottom tip of the memory opening filling structure 58 is exposed. The exposed portion of the memory film is then removed by selective etching to expose the bottom tip of the vertical semiconductor channel 60.

[0228] refer to Fig.36, a source layer 210 is formed on the exposed bottom tip of the vertical semiconductor channel 60. The source layer 210 may include one or more suitable layers. For example, the source layer 210 may include a semiconductor source layer 210A, such as a doped polysilicon layer of a first conductivity type, which contacts the exposed bottom tip of the vertical semiconductor channel 60. Optionally, the source layer 210 may also include a conductive layer 210B, such as a source electrode or source line including a metal (e.g., copper, tungsten, aluminum, etc.), a metal silicide (e.g., titanium, nickel or tungsten silicide) and / or a conductive metal nitride (e.g., TiN, WN, TaN or MoN).

[0229] refer to Fig.37 , a photoresist layer 217 may be formed over the back side of the source layer 210. The photoresist layer 217 may be photolithographically patterned along the second horizontal direction hd2 with a periodicity equal to an integer fraction (e.g., 1 / 2, 1 / 3, 1 / 4) of the periodicity of the backside trench fill structures 176 along the second horizontal direction hd2. Typically, the integer fraction may be 1 / N, where N is an integer greater than 1. The number N may be the number of two-dimensional arrays of memory opening filling structures 58 separated by word line bridge regions 102 between adjacent pairs of backside trench fill structures 176. In one embodiment, the pattern of the photoresist layer 217 is a repetition of a unit photoresist pattern repeated along the second horizontal direction hd2.

[0230] The patterned photoresist layer 217 may include slit-shaped openings extending laterally along a first horizontal direction hd1 and spaced laterally apart along a second horizontal direction hd2. Each slit-shaped opening in the photoresist layer 217 may extend laterally along the first horizontal direction hd1 and have a uniform width along the second horizontal direction hd2. A subset of the slit-shaped openings in the photoresist layer 217 overlies the corresponding underlying backside trench fill structure 176 and may be wider than the backside trench fill structure.

[0231] An anisotropic etching process may be performed to transfer the pattern of the opening in the patterned photoresist layer 217 through the source layer 210. A source isolation trench 211 may be formed through the source layer 210. In one embodiment, the horizontal surface of the nearest insulating layer 32 of the alternating stack {(132, 146), (23, 2 246)} may be physically exposed at the bottom of each source isolation trench 211. In one embodiment, the entire end surface of each backside trench filling structure 176 may be physically exposed and / or vertically recessed under a corresponding one of the source isolation trenches 211. The source layer 210 may be divided into a plurality of source layer segments 311. Each continuous patterned portion of the source layer 210 divided by the source isolation trench 211 constitutes a source layer segment 311. The patterned photoresist layer 217 may then be removed, for example, by ashing.

[0232] refer to Fig.38 , at least one dielectric filling material, such as silicon oxide, may be deposited in the source isolation trench 211. A planarization process may be performed to remove a portion of the at least one dielectric filling material from above a horizontal plane including a top surface (backside surface) of the source layer segment 311. The planarization process may include, for example, a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one dielectric filling material filling the corresponding source isolation trench 211 constitutes a source isolation dielectric structure 212. In one embodiment, the source isolation dielectric structure 212 may have a variable width along the second horizontal direction hd2 that increases with a vertical distance from the alternating stack {(132, 146), (232, 246)}.

[0233] A laterally alternating sequence of source layer segments 311 and source isolation dielectric structures 212 is formed. Each of the source layer segments 311 and the source isolation dielectric structures 212 extends laterally along a first horizontal direction hd1. The source layer segments 311 and the source isolation dielectric structures 212 alternate along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, each of the source layer segments 311 includes a semiconductor source layer segment 210A in contact with the vertical semiconductor channel 60 and an optional conductive source layer segment (e.g., a source electrode or source line) 210B covering the semiconductor source layer segment.

[0234] In the second embodiment, each unit structure US includes three memory blocks MB, wherein word lines of the memory blocks extend across the word line bridge region 102. Each memory block MB includes a separate source layer segment 311 (eg, 311A, 311B, 311C).

[0235] refer to Fig.39 , which is an alternative configuration of the second exemplary structure, wherein two or more drain selection level isolation dielectric structures 72 are embedded in each memory block MB. Therefore, in this alternative embodiment, each memory block MB may have more than four rows of active memory opening filling structures 58, for example, eight rows of active memory opening filling structures 58.

[0236] Fig.40 yes Fig.38Schematic block diagram of a second exemplary structure is shown. The drain side select gate electrode SGD (i.e., at least one topmost second conductive layer 246D) does not extend across the word line bridge region 102. The source side select gate electrode SGS (i.e., the optional source select level conductive layer 118 and / or at least one bottommost first conductive layer 146S) also does not extend across the word line bridge region 102. Instead, the word line (i.e., conductive layer (146, 246)) vertically located between the source and drain side select gate electrodes ((118, 146S) and 246D) extends across the word line bridge region 102. Fig.40 Each cell array region in the embodiment includes a portion of the memory array region 100 including word lines ( 146 , 246 ) and memory opening filling structures 58 .

[0237] Common Reference Figures 38 to 40 , each unit structure US includes multiple memory blocks MB. For example, in the second embodiment, each unit structure US includes three memory blocks MB. The three memory blocks MB in each unit structure US share the same word line, but include separate source layer segments 311. Therefore, the memory blocks MB in the same unit structure US are individually addressed using separate source layer segments 311. Therefore, each source layer segment (311A, 311B, 311C) is electrically connected to a separate corresponding source line switching device (e.g., transistor or circuit) 711 (e.g., 711A, 711B, 711C) in the peripheral circuit 710 located in the logic die 700 through a corresponding source interconnect (e.g., source line) 713, as shown in FIG. Fig.40 As shown in . However, because the memory blocks MB in the same unit structure US share the same word line, for each word line extending through the three memory blocks MB, they also share the same word line switching device (e.g., transistor or circuit) 746 (e.g., 746A, 746B) in the peripheral circuit 710 in the logic die 700. Compared with using a separate word line switching device for each word line in each memory block MB, this configuration reduces the area of ​​the word line switching device by two-thirds without increasing the memory block MB capacity to avoid complicating power and performance. Therefore, the cost and area of ​​the peripheral circuit 710 located in the memory die 700 are reduced.

[0238] Therefore, in the second embodiment, the word line is bridged over three memory blocks MB in the same unit structure US, which reduces the number of word line switching devices 746 by half. The source layer segment 311 is isolated between all memory blocks MB in the same and adjacent unit structures US. Therefore, the size of the memory block MB is defined by its corresponding source layer segment 311. Fig.40As shown, this allows each source layer segment (e.g., 311A, 311B, 311C) to be individually biased by a corresponding source line switch device 711 (e.g., 711A, 711B, 711C). This requires adding only one source line switch device 711 for each memory block MB, which occupies much less space than the word line switch device 746 used to switch each word line. Therefore, the source line switch device 711 does not significantly contribute to the increase in area or cost of the logic die 700. Therefore, the second embodiment uses one-third of the word line switching devices typically used in conventional devices to achieve a single memory block capacity.

[0239] In the first and second embodiments, the memory device includes: a first memory block MB including a first word line (146, 246) and a first source layer segment (111A, 311A); and a second memory block MB including a second word line (146, 246) and a second source layer segment (111B, 311B) electrically isolated from the first source layer segment (111A, 311A). The first word line in the first memory block is electrically connected to the corresponding second word line in the second memory block.

[0240] In one embodiment, the first memory block and the second memory block further include a memory opening filling structure 58, each memory opening filling structure including a corresponding vertical semiconductor channel 60 and a corresponding memory element vertical stack (e.g., a portion of the memory film 50). The first word line is electrically connected to the corresponding second word line across the first word line bridge region 102 located between the first memory block and the second memory block. The first source layer segment is electrically isolated from the second source layer segment by the first source isolation dielectric structure (12, 212). In one embodiment, the memory device further includes a third memory block MB, which includes a third word line (146, 246) and a memory opening filling structure 58.

[0241] In the first embodiment, the second word line is electrically isolated from the third word line by a backside trench filling structure (74, 76) located in a backside trench 79 extending between the second and third memory blocks MB. The second source layer segment 111B is located in both the second and third memory blocks.

[0242] The memory device of the first embodiment further includes word line switching devices 746 and source line switching devices 711. Each of the word line switching devices 746 controls both a corresponding first word line and a corresponding second word line electrically connected to the corresponding first word line across the first word line bridge region 102. The first source layer segment 111A is controlled by a first source line switching device 711A of the source line switching devices 711, and the second source layer segment 111B is controlled by a second source line switching device 711B of the source line switching devices 711.

[0243] In the second embodiment, the third memory block MB further includes a third source layer section 311C which is electrically isolated from the second source layer section 311B by the second source isolation dielectric structure 212. The second word lines are electrically connected to the corresponding third word lines across the second word line bridge region 102 between the second and third memory blocks.

[0244] The memory device of the second embodiment further includes a word line switching device 746 and a source line switching device 711. Each of the word line switching devices 746 controls a corresponding first word line, a corresponding second word line electrically connected to the corresponding first word line across the first word line bridge region 102, and a corresponding third word line electrically connected to the corresponding second word line across the second word line bridge region 102. The first source layer section 311A ​​is controlled by a first source line switching device 711A in the source line switching devices 711. The second source layer section 311B is controlled by a second source line switching device 711B in the source line switching devices 711. The third source layer section 311C is controlled by a third source line switching device 711C in the source line switching devices 711.

[0245] In the first and second embodiments, the first memory block MB and the second memory block MB are located in a first unit structure US, which includes one of multiple instances of a unit structure extending laterally along a first horizontal direction hd1 and repeating along a second horizontal direction hd2 perpendicular to the first horizontal direction. Each instance of the unit structure US includes a corresponding alternating stack of insulating layers (132, 232) and conductive layers (146, 246) alternating along a vertical direction. The corresponding alternating stack is laterally spaced apart from the alternating stack in the adjacent instance of the unit structure by a corresponding backside trench 79, which is filled with a corresponding backside trench filling structure {(74, 76), 176}. A laterally alternating sequence of source layer segments (111, 311) and source isolation dielectric structures (12, 212) is located below the alternating stack.

[0246] In one embodiment, each instance of the cell structure includes: a first memory opening filling structure 58, which vertically extends through the corresponding alternating stack on the first side of the corresponding underlying source isolation dielectric structure (12, 212) and extends into the corresponding first source layer segment (111A, 311A); and a second memory opening filling structure 58, which vertically extends through the corresponding alternating stack on the second side of the corresponding underlying source isolation dielectric structure (12, 212) and extends into the corresponding second source layer segment (111B, 311B), the corresponding second source layer segment being laterally spaced apart and electrically isolated from the corresponding first source layer segment (111A, 311A) by the corresponding underlying source isolation dielectric structure (12, 212).

[0247] In the first embodiment, each of the first memory opening filling structure 58 and the second memory opening filling structure 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (parts of memory films). Each source isolation dielectric structure 12 contacts and is located below a middle portion of a corresponding one of the alternating stacks, and each source layer segment 111 extends between a corresponding adjacent pair of source isolation dielectric structures 12. The source isolation dielectric structures 12 extend laterally along a first horizontal direction hd1.

[0248] In a first embodiment, each source layer segment in the source layer segment 111 includes: a lower source level material layer 112, which includes a first doped semiconductor material; a higher source level material layer 116, which includes a second doped semiconductor material; and a source contact layer 114, which includes a third doped semiconductor material and is located between the higher source level material layer 116 and the lower source level material layer 112.

[0249] In the first embodiment, each of the backside trench filling structures includes a backside contact via structure 76 and a backside insulating spacer 74 laterally surrounding the backside contact via structure. The backside contact via structure 76 within each of the backside trench filling structures contacts the surface of the corresponding source contact layer 114. Each vertical semiconductor channel 60 in the first memory opening filling structure 58 contacts the source contact layer 114 within the corresponding first source layer segment 111A. Each vertical semiconductor channel 60 in the second memory opening filling structure 58 contacts the source contact layer 114 within the corresponding second source layer segment 111B. In the first embodiment, the word lines (146, 246) extend laterally and continuously between the corresponding adjacent pairs of backside trench filling structures (74, 76) in the first unit structure US.

[0250] In the first embodiment, the semiconductor substrate 9 is located below the multiple instances of the unit structure US. The peripheral circuit 710 is located on the semiconductor substrate 9 and is electrically connected to the conductive layer (146, 246) and the first and second source layer segments (111A, 111B) through the lower metal interconnect structure 780 below the multiple instances of the unit structure US, the connecting via structure (86, 488) located at the same level as the multiple instances of the unit structure, and the higher metal interconnect structure 96 above the multiple instances of the unit structure US.

[0251] In a second embodiment, the first unit US structure also includes a third memory block MB, which includes a third word line (146, 246) electrically connected to the second word line, a third source layer segment 311C electrically isolated from the second source layer segment 311B by a second source isolation dielectric structure 212, and a third memory opening filling structure 58 vertically extending through the corresponding alternating stacks on the second side of the second source isolation dielectric structure 212 and extending into the third source layer segment 311C.

[0252] In the second embodiment, the backside trench fill structure 176 contacts the first source isolation dielectric structure 212 in the source isolation dielectric structure and contacts the alternating stack in the first unit structure US and another alternating stack located in an adjacent instance of the unit structure US. In the second embodiment, the logic die 700 is bonded to the memory die 900 including the unit structure US.

[0253] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprise" or "include" contemplate all embodiments in which the words "consist essentially of..." or the words "consist of..." replace the words "comprise" or "include". A third embodiment using a specific structure and / or configuration is shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such replacement is not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, comprising: a first storage block, the first storage block comprising a first word line and a first source layer section; and a second storage block including a second word line and a second source layer section electrically isolated from the first source layer section, The first word line in the first storage block is electrically connected to a corresponding second word line in the second storage block.

2. The memory device according to claim 1, wherein: The first memory block and the second memory block further include memory opening filling structures, each of the memory opening filling structures including a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; The first word line is electrically connected to the corresponding second word line across a first word line bridge region between the first memory block and the second memory block; and The first source layer section is electrically isolated from the second source layer section by a first source isolation dielectric structure. 3 . The memory device of claim 2 , further comprising a third memory block including a third word line and a memory opening filling structure.

4. The memory device according to claim 3, wherein: The second word line is electrically isolated from the third word line by a backside trench fill structure located in a backside trench extending between the second memory block and the third memory block; and The second source layer section is located in both the second memory block and the third memory block.

5. The memory device according to claim 4, further comprising a word line switching device and a source line switching device, wherein: Each of the word line switching devices controls both a corresponding first word line and a corresponding second word line electrically connected to the corresponding first word line across the first word line bridge region; The first source layer segment is controlled by a first source line switching device of the source line switching devices; and The second source layer segment is controlled by a second one of the source line switching devices.

6. The memory device according to claim 3, wherein: The third storage block further includes a third source layer section, the third source layer section being electrically isolated from the second source layer section by a second source isolation dielectric structure; and The second word line is electrically connected to a corresponding third word line across a second word line bridge region between the second memory block and the third memory block.

7. The memory device according to claim 6, further comprising a word line switching device and a source line switching device, wherein: Each of the word line switching devices controls a corresponding first word line, a corresponding second word line electrically connected to the corresponding first word line across the first word line bridge region, and a corresponding third word line electrically connected to the corresponding second word line across the second word line bridge region; The first source layer segment is controlled by a first source line switch device among the source line switch devices; The second source layer segment is controlled by a second source line switching device of the source line switching devices; and The third source layer segment is controlled by a third source line switching device among the source line switching devices.

8. The memory device of claim 1, wherein: The first storage block and the second storage block are located in a first unit structure, the first unit structure comprising one instance of a plurality of instances of the unit structure extending laterally along a first horizontal direction and repeated along a second horizontal direction perpendicular to the first horizontal direction; Each instance of the unit structure comprises a respective alternating stack of insulating layers and conductive layers alternating along a vertical direction; the respective alternating stacks being laterally spaced apart from alternating stacks in adjacent instances of the unit structure by respective backside trenches filled with respective backside trench-fill structures; and A laterally alternating sequence of source layer segments and source isolation dielectric structures underlying the alternating stack.

9. The memory device of claim 8, wherein each instance of the cell structure comprises: a first memory opening filling structure extending vertically through the respective alternating stacks and into the respective first source layer segments on a first side of the respective underlying source isolation dielectric structure; and A second memory opening filling structure, wherein the second memory opening filling structure extends vertically through the corresponding alternating stack and into a corresponding second source layer segment on a second side of the corresponding underlying source isolation dielectric structure, and the second source layer segment is laterally spaced apart and electrically isolated from the corresponding first source layer segment by the corresponding underlying source isolation dielectric structure.

10. The memory device of claim 9, wherein: Each of the first memory opening filling structure and the second memory opening filling structure includes a respective vertical semiconductor channel and a respective vertical stack of memory elements; Each source isolation dielectric structure contacts and underlies a middle portion of a corresponding one of the alternating stacks, and each source layer segment extends between a corresponding adjacent pair of source isolation dielectric structures; and The source isolation dielectric structure extends laterally along the first horizontal direction.

11. The memory device of claim 9, wherein each of the source layer segments comprises: a lower source level material layer, the lower source level material layer comprising a first doped semiconductor material; an upper source level material layer, the upper source level material layer comprising a second doped semiconductor material; and A source contact layer includes a third doped semiconductor material and is located between the higher source level material layer and the lower source level material layer.

12. The memory device of claim 11, wherein: Each of the backside trench filling structures includes a backside contact via structure and a backside insulating spacer laterally surrounding the backside contact via structure; The back contact via structure in each of the back trench filling structures contacts a surface of a corresponding source contact layer; Each vertical semiconductor channel in the first memory opening filling structure contacts a source contact layer within the corresponding first source layer segment; and Each vertical semiconductor channel in the second memory opening filling structure contacts a source contact layer within the corresponding second source layer segment. 13 . The memory device of claim 9 , wherein the first word line and the second word line extend laterally continuously between corresponding adjacent pairs of backside trench fill structures in the first cell structure.

14. The memory device according to claim 9, further comprising: a semiconductor substrate underlying the plurality of instances of the unit structure; and A peripheral circuit is located on the semiconductor substrate and is electrically connected to the conductive layer and the first source layer segment and the second source layer segment through a lower metal interconnect structure below the multiple instances of the unit structure, a connecting via structure located at the same level as the multiple instances of the unit structure, and a higher metal interconnect structure above the multiple instances of the unit structure.

15. The memory device according to claim 9, wherein the first unit structure further comprises a third memory block, the third memory block comprising: a third word line electrically connected to the second word line; a third source layer section, the third source layer section being electrically isolated from the second source layer section by a second source isolation dielectric structure; and A third memory opening filling structure extends vertically through the corresponding alternating stacks on the second side of the second source isolation dielectric structure and into the third source layer segment.

16. The memory device of claim 15, further comprising a backside trench fill structure contacting a first one of the source isolation dielectric structures and contacting the alternating stack in the first cell structure and another alternating stack within an adjacent instance of the cell structure.

17. The memory device of claim 16, further comprising a logic die bonded to a memory die, the memory die containing the cell structure.

18. A method of forming a memory device, the method comprising: forming a laterally alternating sequence of source layer segments and source isolation dielectric structures; forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers; forming a reservoir opening through the vertical alternating sequence; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures comprises a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; alternatingly stacking in a process of dividing the vertical alternating sequence into insulating layers and sacrificial material layers by forming backside trenches extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction; as well as The sacrificial material layer is replaced with a conductive layer to form an alternating stack of insulating and conductive layers, the alternating stack being laterally spaced apart from one another by the backside trenches and extending over at least one of the source isolation dielectric structures. 19 . The method of claim 18 , wherein the backside trenches and the source layer segments are staggered along the second horizontal direction such that each backside trench is formed between an adjacent pair of source layer segments.

20. The method of claim 18, further comprising bonding a logic die to a memory die including the memory opening filling structure, wherein at least three source layer segments are located between adjacent backside trenches.

Images