A dual parameter sensor array and method of making the same

Abstract

The application provides a dual-parameter sensor array and a preparation method thereof, wherein the dual-parameter sensor array comprises a substrate, a voltage division resistor array, a Schottky diode array and a pressure-sensitive film; the voltage division resistor array comprises a plurality of voltage division resistors arranged in an array; the Schottky diode array comprises a plurality of Schottky diodes respectively located on the voltage division resistors; each Schottky diode comprises a cathode, an anode and a semiconductor structure between the cathode and the anode; the cathode is electrically connected to a first end of the corresponding voltage division resistor; a first end of the anode is electrically connected to the cathode through the semiconductor structure; and a second end of the anode is electrically connected to a second end of the corresponding voltage division resistor; and the pressure-sensitive film covers the Schottky diode array during pressure testing. The application solves the problem that the sensitivity and spatial resolution of the pressure-sensitive sensor in the dual-parameter sensor array cannot be considered simultaneously, and the temperature sensor is easily coupled to the pressure signal.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a dual-parameter sensor array and its fabrication method. Background Technology

[0002] Human skin possesses remarkable capabilities, enabling it to detect a wide range of physical parameters at high resolution and capture intricate details of objects in contact. This skin-like sensing ability is crucial for emerging artificial intelligence applications, including electronic skin, human-computer interaction, and soft robotics. Researchers have developed a series of flexible sensors based on different materials, structures, and manufacturing processes, achieving impressive performance comparable to human skin. However, many sensing devices are limited to detecting single signals and cannot provide comprehensive information about the object in contact. For example, in electronic skin applications, sensors must simultaneously detect at least two fundamental physical parameters: pressure and temperature. Pressure detection is essential for estimating the object's weight and shape, while temperature feedback provides crucial thermal information. Furthermore, only by using flexible sensor arrays with high spatial resolution can multifunctional manipulation of objects, much like human skin, be achieved.

[0003] The challenge of dual-parameter sensors lies in decoupling the pressure and temperature signals. However, since pressure and temperature measurements often rely on changes in the resistance of the sensing material, distinguishing the source of the stimulus becomes complex. One solution is to use separate sensing mechanisms for each parameter, for example, through combinations such as thermoelectric and piezoresistive effects, or by integrating a piezoresistive field-effect transistor with thermal resistance characteristics. However, in both of these approaches, the sensitivity and spatial resolution of the piezoresistive sensor cannot be simultaneously optimized, and the coupling of the temperature sensor to the pressure signal is unavoidable. These two major issues are currently the main challenges in the design of dual-parameter sensor arrays. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a dual-parameter sensor array, comprising:

[0005] Substrate;

[0006] A voltage divider resistor array located on the substrate, the voltage divider resistor array comprising a plurality of voltage divider resistors arranged in an array;

[0007] a Schottky diode array on the array of voltage dividing resistors, the Schottky diode array comprising a plurality of Schottky diodes respectively on a plurality of the voltage dividing resistors, the Schottky diode comprising a cathode, an anode, and a semiconductor structure between the cathode and the anode, the cathode electrically connected to a first end of the corresponding voltage dividing resistor, a first end of the anode electrically connected to the cathode through the semiconductor structure, and a second end of the anode electrically connected to a second end of the corresponding voltage dividing resistor;

[0008] a pressure sensitive film covering the Schottky diode array during pressure testing.

[0009] Optionally, the Schottky diode further comprises a semiconductor structure connected between the cathode and the anode.

[0010] Optionally, a resistive insulating layer is provided between the cathode and the voltage dividing resistor, a first via is provided on the resistive insulating layer, a first conductive component is provided in the first via, and the cathode is electrically connected to the first end of the voltage dividing resistor through the first conductive component.

[0011] Optionally, the semiconductor structure is on the cathode, the anode is above the semiconductor structure, an etching blocking layer is provided between the anode and the semiconductor structure, a second via and a third via are provided on the etching blocking layer, the second via is in communication with the semiconductor structure, a second conductive component is provided in the second via, a first end of the anode is electrically connected to the semiconductor structure through the second conductive component, the third via is in communication with the second end of the voltage dividing resistor, a third conductive component is provided in the third via, and a second end of the anode is electrically connected to the second end of the voltage dividing resistor through the third conductive component.

[0012] Optionally, the resistive insulating layer is on the substrate and covers the voltage dividing resistor.

[0013] Optionally, the etching blocking layer is on the resistive insulating layer and covers the semiconductor structure and the cathode.

[0014] Optionally, a protective layer is further provided on the anode, the protective layer is on the etching blocking layer, the protective layer covers the anode, and a fourth via is further provided on the protective layer to expose the anode.

[0015] Optionally, a high work function metal material is used for the metal material of the anode to form a Schottky barrier.

[0016] Optionally, a low work function metal or composite material is used for the metal material of the cathode to form an Ohmic contact.

[0017] Optionally, the conductive material in the pressure sensitive film comprises two materials with opposite temperature coefficients.

[0018] Another embodiment of the present application also provides a method for preparing a dual-parameter sensor array, comprising:

[0019] providing a substrate;

[0020] forming a voltage division resistor array on the substrate, the voltage division resistor array comprising a plurality of voltage division resistors arranged in an array;

[0021] forming a Schottky diode array on the voltage division resistor array, the Schottky diode array comprising a plurality of Schottky diodes respectively located on the plurality of voltage division resistors, each Schottky diode comprising a cathode, an anode, and a semiconductor structure between the cathode and the anode, the cathode being electrically connected to a first end of the corresponding voltage division resistor, a first end of the anode being electrically connected to the cathode through the semiconductor structure, and a second end of the anode being electrically connected to a second end of the corresponding voltage division resistor;

[0022] forming a pressure sensitive film, the pressure sensitive film covering the Schottky diode array during pressure testing.

[0023] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0024] In the present application, the Schottky diode is sensitive to temperature (because temperature changes the degree of movement of semiconductor carriers in the Schottky diode), but is not sensitive to pressure (i.e., has a low response to pressure), thus avoiding the influence on the pressure signal and eliminating the coupling problem of the pressure signal; at the same time, the present application uses a pressure sensitive film that is not sensitive to temperature as a pressure sensitive sensor array, thus avoiding the influence on the temperature signal and eliminating the coupling problem of the temperature signal, thereby solving the signal decoupling problem of pressure and temperature.

[0025] Since the Schottky diodes are arranged in an array on the entire substrate, the density and pixel points of the Schottky diodes (i.e., temperature sensitive sensors) are improved, thus improving the sensitivity of the temperature sensitive sensors while also taking into account the spatial resolution. During pressure testing, the pressure sensitive film completely covers the Schottky diode array, thus improving the distribution density and pixel points of the pressure sensitive sensors, thus improving the sensitivity of the pressure sensitive sensors while also taking into account the spatial resolution. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to explain some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0027] Figure 1 is a top view of preparing a partial pressure resistor provided by an embodiment of the present application;

[0028] Figure 2 is a sectional view along the a-a1 axis of Figure 1

[0029] Figure 3 is a sectional view along the b-b1 axis of Figure 1

[0030] Figure 4 is a top view of preparing a cathode provided by an embodiment of the present application;

[0031] Figure 5 is a sectional view along the a-a1 axis of Figure 4

[0032] Figure 6 is a sectional view along the b-b1 axis of Figure 4

[0033] Figure 7 is a top view of preparing a semiconductor structure provided by an embodiment of the present application;

[0034] Figure 8 is a sectional view along the a-a1 axis of Figure 7

[0035] Figure 9 is a sectional view along the b-b1 axis of Figure 7

[0036] Figure 10 is a top view of preparing an etching stop layer and an anode provided by an embodiment of the present application;

[0037] Figure 11 is a sectional view along the a-a1 axis of Figure 10

[0038] Figure 12 is a sectional view along the b-b1 axis of Figure 10

[0039] Figure 13 is a top view of preparing a protective layer provided by an embodiment of the present application;

[0040] Figure 14 is a sectional view along​​​​​​​​Figure 13 A cross-sectional view of the a-a1 axis;

[0041] Figure 15 It is along Figure 13 A cross-sectional view of the b-b1 axis;

[0042] Figure 16 This is an equivalent circuit diagram of a single pressure-sensitive sensor provided in an embodiment of the present invention;

[0043] Figure 17 This is an equivalent circuit diagram of a pressure-sensitive sensor array provided in an embodiment of the present invention;

[0044] Figure 18 This is an equivalent circuit diagram of a single temperature sensor provided in an embodiment of the present invention;

[0045] Figure 19 This is an equivalent circuit diagram of a temperature sensor provided in an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The terms "above" and "over," and any variations thereof, are intended to describe positional relationships and do not imply direct contact between the described objects.

[0048] As described in the background section, in dual-parameter sensor arrays, there is a problem that the sensitivity and spatial resolution of pressure sensors cannot be simultaneously achieved, and temperature sensors are prone to coupling with pressure signals.

[0049] In one embodiment, firstly, in the dual-parameter sensor array, the area of the temperature-sensitive sensor is larger, and the distribution area left for the pressure-sensitive sensor is smaller, thereby limiting the area ratio of the pressure-sensitive sensor in the dual-parameter sensor array. Since the sensitivity of the pressure-sensitive sensor is positively correlated with the area ratio of the pressure-sensitive sensor in the dual-parameter sensor array, the sensitivity of the pressure-sensitive sensor is limited. Meanwhile, when the area of the pressure-sensitive sensor is increased, the spatial resolution thereof cannot be considered. Secondly, the temperature sensor in the dual-parameter sensor array is also affected by the pressure, and thus the coupling of the pressure signal and the temperature signal occurs, thereby bringing difficulties to the signal decoupling in the dual-parameter sensor array.

[0050] To solve the above problems, the present application provides a dual-parameter sensor array, comprising:

[0051] a substrate;

[0052] a voltage division resistor array located on the substrate, the voltage division resistor array comprising a plurality of voltage division resistors arranged in an array;

[0053] a Schottky diode array located on the voltage division resistor array, the Schottky diode array comprising a plurality of Schottky diodes respectively located on the plurality of voltage division resistors, each Schottky diode comprising a cathode, an anode, and a semiconductor structure located between the cathode and the anode, the cathode being electrically connected to a first end of the corresponding voltage division resistor, a first end of the anode being electrically connected to the cathode through the semiconductor structure, and a second end of the anode being electrically connected to a second end of the corresponding voltage division resistor;

[0054] a pressure-sensitive thin film, which covers the Schottky diode array during pressure testing.

[0055] In the present application, since the Schottky diode is sensitive to temperature (because temperature changes the degree of movement of semiconductor carriers in the Schottky diode), but is not sensitive to pressure (i.e., has a low response to pressure), the influence on the pressure signal is avoided, and the coupling problem of the pressure signal is eliminated. Meanwhile, the present application uses a pressure-sensitive thin film that is not sensitive to temperature as the pressure-sensitive sensor array, thereby avoiding the influence on the temperature signal and eliminating the coupling problem of the temperature signal, and thus solving the signal decoupling problem of pressure and temperature.

[0056] Since the Schottky diodes are arranged in an array on the entire substrate, the density and pixel points of the Schottky diodes (i.e., temperature-sensitive sensors) are improved, and thus the sensitivity of the temperature-sensitive sensors is improved while the spatial resolution thereof is considered. During pressure testing, the pressure-sensitive thin film completely covers the Schottky diode array, and thus the distribution density and pixel points of the pressure-sensitive sensors are improved, and thus the sensitivity of the pressure-sensitive sensors is improved while the spatial resolution thereof is considered.

[0057] In order to make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0058] Please refer to Figures 1 to 15 An embodiment of the present application provides a preparation method of a dual-parameter sensor array, comprising:

[0059] providing a substrate 1;

[0060] forming a voltage division resistor array on the substrate 1, the voltage division resistor array comprising a plurality of voltage division resistors 2 arranged in an array;

[0061] forming a Schottky diode array on the voltage division resistor array, the Schottky diode array comprising a plurality of Schottky diodes respectively located on the plurality of voltage division resistors 2, each Schottky diode comprising a cathode 4, an anode 8, and a semiconductor structure 6 located between the cathode 4 and the anode 8, the cathode 4 being electrically connected to a first end of the corresponding voltage division resistor 2, a first end of the anode 8 being electrically connected to the cathode 4 through the semiconductor structure 6, and a second end of the anode 8 being electrically connected to a second end of the corresponding voltage division resistor 2;

[0062] forming a pressure-sensitive thin film, the pressure-sensitive thin film covering the Schottky diode array during pressure testing.

[0063] The preparation method of the dual-parameter sensor array will be described in detail below with reference to the drawings.

[0064] providing a substrate 1, the material of the substrate 1 being a glass substrate or a polyimide.

[0065] when the substrate 1 is a glass substrate, a clean glass plate is selected as the substrate 1.

[0066] when the material of the substrate 1 is polyimide, the forming method of the substrate 1 comprises the following steps: first, providing a glass substrate, and spin-coating a polyimide reagent on the glass substrate; second, treating the glass substrate with the spin-coated polyimide reagent according to a set annealing temperature; and third, preparing a buffer layer composed of silicon nitride and silicon dioxide on the substrate after the annealing treatment by using a plasma-enhanced chemical vapor deposition process, to obtain the substrate 1, which is a flexible polyimide substrate.

[0067] Please refer toFigures 1 to 3 A plurality of voltage dividing resistors 2 are formed on the substrate 1.

[0068] In one embodiment, the method of forming the voltage dividing resistor 2 comprises: preparing a voltage dividing resistor layer on the substrate 1; etching the voltage dividing resistor layer by using a mask plate to form the voltage dividing resistor 2 on the substrate 1.

[0069] In one embodiment, the voltage dividing resistor layer is prepared on the substrate 1 by a sputtering process, and the voltage dividing resistor layer is etched by using a wet etching technique to form the voltage dividing resistor 2 on the substrate 1.

[0070] In one example, the thickness of the voltage dividing resistor 2 is 190nm to 210nm. By adjusting the thickness of the voltage dividing resistor 2 within the range of 190nm to 210nm, the resistance value of the resistor and the resistance value of the pressure sensitive film can be controlled to be in the same order of magnitude, thereby improving the pressure sensitivity.

[0071] Preferably, the thickness of the voltage dividing resistor 2 is 200nm.

[0072] The material of the voltage dividing resistor 2 belongs to the mature technology in the art, and therefore, the material of the voltage dividing resistor 2 is not specifically limited in the present embodiment. In one specific example, the material of the voltage dividing resistor 2 is Indium Tin Oxide (ITO), and the method of forming the voltage dividing resistor 2 comprises: sputtering an ITO layer on the substrate 1; and etching the ITO layer by using a mask plate to form the voltage dividing resistor 2 on the substrate 1. Of course, the material of the voltage dividing resistor 2 is not limited to Indium Tin Oxide, but can also be other materials, such as Indium Zinc Oxide (IZO) or Indium Oxide (In2O3).

[0073] The plurality of voltage dividing resistors 2 form a voltage dividing resistor array, and after forming the voltage dividing resistor array, a Schottky diode array is prepared on the voltage dividing resistor array. The Schottky diode array comprises a plurality of Schottky diodes respectively located on the plurality of voltage dividing resistors 2, and each Schottky diode comprises a cathode 4, an anode 8, and a semiconductor structure 6 located between the cathode 4 and the anode 8. The cathode 4 is electrically connected to the first end of the corresponding voltage dividing resistor 2, the first end of the anode 8 is electrically connected to the cathode 4 through the semiconductor structure 6, and the second end of the anode 8 is electrically connected to the second end of the corresponding voltage dividing resistor 2.

[0074] In one embodiment, a resistive insulating layer 3 is provided between the cathode 4 and the voltage dividing resistor 2, a first via hole is provided on the resistive insulating layer 3, a first conductive part 5 is provided in the first via hole, and the cathode 4 is electrically connected to the first end of the voltage dividing resistor 2 through the first conductive part 5.

[0075] Reference is made to Figures 4 to 6 In an example, the resistive insulating layer 3 is formed on the substrate 1, covering the voltage dividing resistor 2; the resistive insulating layer 3 is provided with a first via, which exposes the first end of the voltage dividing resistor 2.

[0076] The material of the resistive insulating layer 3 belongs to the mature technology in the field, and thus the material of the resistive insulating layer 3 is not specifically limited in the embodiment, and in an example, the material of the resistive insulating layer 3 is silicon oxide. Of course, the material of the resistive insulating layer 3 is not limited to silicon oxide, and can also be other materials, such as silicon nitride.

[0077] The forming method of the resistive insulating layer 3 includes: depositing a resistive insulating material layer on the substrate 1, covering the voltage dividing resistor 2; using a mask plate to etch the resistive insulating material layer on the first end of the voltage dividing resistor 2 to form a plurality of first vias.

[0078] In a typical example, a plasma enhanced chemical vapor deposition process is used to deposit the resistive insulating material layer on the substrate 1.

[0079] In an embodiment, the thickness of the resistive insulating material layer is 190 nm to 210 nm.

[0080] In a typical example, the thickness of the resistive insulating material layer is 200 nm.

[0081] In an embodiment, the method of forming a plurality of first vias includes: forming a hard mask layer on the resistive insulating material layer, using the mask plate to form a first via pattern on the hard mask layer by using a wet etching process; and using the hard mask layer with the pattern of a plurality of first vias as a mask to etch the resistive insulating material layer by using a dry etching process to form a plurality of first vias on the resistive insulating material layer, thereby forming the resistive insulating layer 3.

[0082] In an embodiment, after the resistive insulating layer 3 with a plurality of first vias is formed on the substrate 1, the method further includes: forming a cathode 4 above the voltage dividing resistor 2 on the resistive insulating layer 3, at this time the first end of the voltage dividing resistor 2 has formed an electrical connection with the cathode 4 through the first via.

[0083] The method of forming the cathode 4 includes: forming a cathode material layer on the resistive insulating layer 3; and etching the cathode material layer by using a mask plate and a wet etching process to form the cathode 4, at this time the cathode 4 has formed an electrical connection with the first end of the voltage dividing resistor 2 through the first via.

[0084] The material of the cathode material layer belongs to the mature technology in the field, therefore, the embodiment does not make specific limitation to the material of the cathode material layer, the cathode material layer can be the composite material of molybdenum and indium tin oxide, aluminum and indium tin oxide, titanium and indium tin oxide, of course, the material of the cathode material layer is not limited to the composite material, but also can be the metal with low work function, as long as it can realize the formation of ohmic contact.

[0085] In a typical example, the cathode material layer is formed on the resistive insulating layer 3 by sputtering process.

[0086] In a typical example, molybdenum, aluminum or titanium is sputtered on the resistive insulating layer 3 by sputtering process, and then indium tin oxide is sputtered by sputtering process, so as to form the cathode material layer.

[0087] In a typical example, the thickness of the sputtered molybdenum, aluminum or titanium is 200 nm, and the thickness of the sputtered indium tin oxide is 50 nm.

[0088] Please refer to Figures 7 to 9 In a typical example, the semiconductor structure 6 is prepared on the cathode 4, and the method comprises: forming a semiconductor material layer on the cathode 4 by sputtering process; and etching the semiconductor material layer by mask plate and wet etching process to obtain the semiconductor structure 6.

[0089] The semiconductor material belongs to the mature technology in the field, therefore, the embodiment does not make specific limitation to the semiconductor material, in a specific example, the semiconductor material is at least one of N-type semiconductor Si, GaAs and InGaZnO, and the thickness is 60 nm.

[0090] Please refer to Figures 10 to 12 In an example, an etching stop layer 7 is formed on the resistive insulating layer 3, the etching stop layer 7 covers the cathode 4 and the semiconductor structure 6; the etching stop layer 7 is provided with a second via hole and a third via hole, the second via hole exposes the semiconductor structure 6, that is, the second via hole communicates with the semiconductor structure 6; the third via hole exposes the second end of the voltage dividing resistor 2, that is, the third via hole communicates with the second end of the voltage dividing resistor 2.

[0091] In some specific examples, the material of the etching stop layer 7 is silicon oxide.

[0092] The method for forming the etching stop layer 7 includes: depositing an etching stop material layer on the resistance insulation layer 3, the etching stop material layer covering the negative electrode 4 and the semiconductor structure 6; etching the etching stop material layer by using a mask plate to form a plurality of second vias and third vias for subsequent connection of the positive electrode 8. The etching stop material layer on the semiconductor structure 6 is etched to form a plurality of second vias for electrical conduction between the positive electrode 8 and the semiconductor structure 6; the etching stop material layer and the resistance insulation material layer on the second end of the voltage dividing resistor 2 are etched to form a plurality of third vias for electrical conduction between the positive electrode 8 and the second end of the voltage dividing resistor 2.

[0093] In a typical example, a plasma enhanced chemical vapor deposition process is used to deposit the etching stop material layer on the resistance insulation layer 3.

[0094] In an embodiment, the thickness of the etching stop material layer is 190 nm to 210 nm.

[0095] In a typical example, the thickness of the etching stop material layer is 200 nm.

[0096] In an embodiment, the method for forming the plurality of second vias includes: forming a hard mask layer on the etching stop material layer, using the mask plate to form a second via and a third via pattern on the hard mask layer by using a wet etching process; and using the hard mask plate with the second via and the third via pattern as a mask to etch the etching stop material layer by using a dry etching process to form a plurality of second vias and third vias on the etching stop material layer, thereby forming the etching stop layer 7.

[0097] In an embodiment, after the etching stop layer 7 with the plurality of second vias and third vias is formed on the resistance insulation layer 3, the positive electrode 8 is formed on the etching stop layer 7, a first end of the positive electrode 8 is electrically connected to the semiconductor structure 6 through the second via, and a second end of the positive electrode 8 is electrically connected to the second end of the voltage dividing resistor 2 through the third via. The plurality of positive electrodes 8 can be arranged in an array with intervals or can be integrally connected to form a circular structure, and the present embodiment does not make specific limitations in this regard.

[0098] The method for forming the positive electrode 8 includes: forming a positive electrode material layer on the etching stop layer 7; and etching the positive electrode material layer by using a mask plate and a wet etching process to form the positive electrode 8, wherein a first end of the positive electrode 8 is electrically connected to the semiconductor structure 6 through the second via, and a second end of the positive electrode 8 is electrically connected to the second end of the voltage dividing resistor 2 through the third via.

[0099] The anode material layer uses a high work function metal material to form a Schottky barrier. The high work function metal material is not specifically limited, and can be Pd or Pt, for example.

[0100] In one example, the anode material layer is formed on the etching stop layer 7 by a sputtering process.

[0101] In one example, Pd or Pt is sputtered on the etching stop layer 7 by a sputtering process, and then the anode pattern is obtained by a mask and a wet etching technique to form the anode 8.

[0102] Please refer to Figures 13 to 15 In one example, the protective layer 11 is prepared on the anode 8, and the method includes: forming the protective layer 11 on the etching stop layer 7, the protective layer 11 covering the anode 8; etching the protective layer 11 by using a mask to form a fourth via hole 12 for exposing the anode 8 to facilitate subsequent electrical performance testing, and connecting a pressure-sensitive film or an external resistor 13 to the array for testing during the electrical performance testing.

[0103] In one example, the protective layer 11 is deposited on the etching stop layer 7 by a plasma-enhanced chemical vapor deposition process.

[0104] In one example, the material of the protective layer 11 is an insulating material, such as silicon oxide.

[0105] In one example, the thickness of the protective layer 11 is 190 nm to 210 nm.

[0106] In one example, the thickness of the protective layer 11 is 200 nm.

[0107] The pressure-sensitive film includes at least two opposite temperature coefficient materials, MWCNTs (multi-walled carbon nanotubes) and silver nanowires, and the MWCNTs and the silver nanowires are mixed to form a zero-temperature-coefficient pressure-sensitive film composite, which is not easily affected by temperature.

[0108] The preparation method of the pressure-sensitive film includes: mixing MWCNTs and silver nanowires, uniformly mixing the MWCNTs and the silver nanowires by using a magnetic stirring table, and then filtering the mixture by using a water-based filter membrane, so that a conductive film is formed on the water-based filter membrane. After waiting for the filter membrane to completely dry, a PDMS mixture (a main agent and a curing agent) is poured on the conductive film, and then the PDMS mixture is cured on a hot plate. Finally, the PDMS is peeled off from the filter membrane to obtain a pressure-sensitive film that is not sensitive to temperature.

[0109] In summary, in the preparation method of the dual-parameter sensor array provided by the application, since the Schottky diode is sensitive to temperature but not sensitive to pressure, i.e., has a low response to pressure, the influence on the pressure signal is avoided, and the coupling problem of the pressure signal is eliminated; at the same time, the pressure-sensitive film which is not sensitive to temperature is used as the pressure-sensitive sensor, the influence on the temperature signal is avoided, and the coupling problem of the temperature signal is eliminated, thereby solving the signal decoupling problem of pressure and temperature.

[0110] Since the Schottky diodes are distributed in an array on the entire substrate 1, the density and pixel points of the Schottky diodes are improved, so that the sensitivity of the temperature-sensitive sensor is improved while the spatial resolution is taken into account. In the pressure test, the pressure-sensitive film completely covers the Schottky diode array, so that the distribution density and pixel points of the pressure-sensitive sensor are improved, so that the sensitivity of the pressure-sensitive sensor is improved while the spatial resolution is taken into account.

[0111] In an embodiment of the application, a dual-parameter sensor array is provided, which comprises a substrate 1, a voltage division resistor array located on the substrate 1, a Schottky diode array located on the voltage division resistor array, and a pressure-sensitive film. Figures 1 to 15 The voltage division resistor array comprises a plurality of voltage division resistors 2 arranged in an array.

[0112] The Schottky diode array located on the voltage division resistor array comprises a plurality of Schottky diodes respectively located on a plurality of voltage division resistors 2. The Schottky diode comprises a cathode 4, an anode 8, and a semiconductor structure 6 located between the cathode 4 and the anode 8. The cathode 4 is electrically connected to the first end of the corresponding voltage division resistor 2. The first end of the anode 8 is electrically connected to the cathode 4 through the semiconductor structure 6. The second end of the anode 8 is electrically connected to the second end of the corresponding voltage division resistor 2.

[0113] The pressure-sensitive film covers the Schottky diode array in the pressure test.

[0114] In an embodiment, a resistive insulating layer 3 is provided between the cathode 4 and the voltage division resistor 2. A first via hole is provided on the resistive insulating layer 3. A first conductive part 5 is provided in the first via hole. The cathode 4 is electrically connected to the first end of the voltage division resistor 2 through the first conductive part 5.

[0115] In a specific embodiment, the resistive insulating layer 3 is located on the substrate 1 and covers the voltage division resistor 2.

[0116] In one embodiment, the Schottky diode further comprises a semiconductor structure 6 located on the cathode 4, the anode 8 is located above the semiconductor structure 6, and an etching stop layer 7 is provided between the anode 8 and the semiconductor structure 6. The etching stop layer 7 is provided with a second via and a third via. The second via is in communication with the semiconductor structure 6, and a second conductive part 10 is provided in the second via. The first end of the anode 8 is electrically connected to the semiconductor structure 6 through the second conductive part 10. The third via is in communication with the second end of the voltage dividing resistor 2, and a third conductive part 9 is provided in the third via. The second end of the anode 8 is electrically connected to the second end of the voltage dividing resistor 2 through the third conductive part 9.

[0117] In one embodiment, the etching stop layer 7 is located on the resistor insulating layer 3 and covers the semiconductor structure 6 and the cathode 4.

[0118] The anode 8 is further provided with a protective layer 11 located on the etching stop layer 7. The protective layer 11 covers the anode 8, and a fourth via 12 is provided on the protective layer 11 to expose the anode 8.

[0119] During pressure testing, the piezoelectric film covers the Schottky diode array, and the fourth via 12 is provided on the Schottky diode array. When the piezoelectric film is pressed, the piezoelectric film will contact the anode 8 through the fourth via 12. Therefore, the piezoelectric sensor of the piezoelectric film is also arrayed.

[0120] Test method:

[0121] I. Pressure test:

[0122] The piezoelectric film covers the Schottky diode array. When the piezoelectric film is pressed, the piezoelectric film will contact the anode 8 through the fourth via 12. The schematic diagram of a single point of the piezoelectric sensor is as shown in Figure 16 The schematic diagram of an array of piezoelectric sensors is as shown in Figure 17 The end of the piezoelectric film (V in , V in1 , V in2 , V in3 ) is applied with voltage. When the piezoelectric film is subjected to external pressure, the resistance will change. At this time, a voltage signal that changes with pressure can be measured at the test point (the exposed anode 8 of the fourth via 12).

[0123] II. Temperature test:

[0124] The anode 8 is connected to the external resistor 13 through the fourth via 12. The schematic diagram of a single point of the temperature sensor is as shown inFigure 18 As shown in the figure, the schematic diagram of the temperature-sensitive sensor array is as attached Figure 19 As shown in the figure, voltage is applied to one end of the external resistance 13 (Vin in the figure, Vin1, Vin2, Vin3 in the figure), and when temperature changes, the voltage signal changing with temperature can be measured at the test point.

[0125] In the present application, both the pressure-sensitive sensor and the temperature-sensitive sensor are based on Schottky diode, which can be formed at one time to reduce cost.

[0126] In a specific embodiment, the temperature-sensitive sensor pixel points and the pressure-sensitive sensor array adopt a chessboard layout mode, and meanwhile, the uniform sensing performance of both on the plane is considered, so that the sensing of both parameters is more uniform.

[0127] The present application adopts Schottky diode, and compared with the prior art, the opening voltage is smaller, and the detectable range is larger.

[0128] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A dual parameter sensor array, characterized by, include: Substrate; A voltage divider resistor array located on the substrate, the voltage divider resistor array comprising a plurality of voltage divider resistors arranged in an array; A Schottky diode array is located on the voltage divider resistor array. The Schottky diode array includes a plurality of Schottky diodes respectively located on a plurality of the voltage divider resistors. Each Schottky diode includes a cathode, a anode, and a semiconductor structure located between the cathode and the anode. The cathode is electrically connected to the first end of the corresponding voltage divider resistor. The first end of the anode is electrically connected to the cathode through the semiconductor structure. The second end of the anode is electrically connected to the second end of the corresponding voltage divider resistor. A pressure-sensitive film is used to cover the Schottky diode array during pressure testing.

2. The dual-parameter sensor array of claim 1, wherein, A resistive insulating layer is provided between the cathode and the voltage divider resistor. A first via is provided on the resistive insulating layer. A first conductive component is provided in the first via. The cathode is electrically connected to the first end of the voltage divider resistor through the first conductive component.

3. The dual-parameter sensor array of claim 2, wherein, The semiconductor structure is located on the cathode, and the anode is located above the semiconductor structure. An etch barrier layer is provided between the anode and the semiconductor structure. A second via and a third via are provided on the etch barrier layer. The second via communicates with the semiconductor structure and contains a second conductive component. The first end of the anode is electrically connected to the semiconductor structure through the second conductive component. The third via communicates with the second end of the voltage divider resistor and contains a third conductive component. The second end of the anode is electrically connected to the second end of the voltage divider resistor through the third conductive component.

4. The dual-parameter sensor array of claim 3, wherein, The resistive insulating layer is located on the substrate and covers the voltage divider resistor.

5. The dual-parameter sensor array of claim 4, wherein, The etching barrier layer is located on the resistive insulating layer and covers the semiconductor structure and the cathode.

6. The dual-parameter sensor array of claim 5, wherein, The anode is further provided with a protective layer, which is located on the etching barrier layer and covers the anode. The protective layer is also provided with a fourth via that exposes the anode.

7. The dual-parameter sensor array of claim 1, wherein, The anode is made of a high work function metal to form a Schottky barrier.

8. The dual-parameter sensor array of claim 1, wherein, The cathode is made of a low work function metal or a composite material to form an ohmic contact.

9. The dual-parameter sensor array of claim 1, wherein, The conductive material in the pressure-sensitive film includes two materials with opposite temperature coefficients.

10. The method of claim 1 to 9, wherein include: Provide substrate; A voltage divider resistor array is formed on the substrate, the voltage divider resistor array comprising a plurality of voltage divider resistors arranged in an array; A Schottky diode array is formed on the voltage divider resistor array. The Schottky diode array includes a plurality of Schottky diodes respectively located on a plurality of the voltage divider resistors. Each Schottky diode includes a cathode, a anode, and a semiconductor structure located between the cathode and the anode. The cathode is electrically connected to the first end of the corresponding voltage divider resistor. The first end of the anode is electrically connected to the cathode through the semiconductor structure. The second end of the anode is electrically connected to the second end of the corresponding voltage divider resistor. A pressure sensitive film is formed overlying the array of Schottky diodes during a pressure test.

Images