Memristor array test method and system

Abstract

The invention relates to a memristor array test method and system, and the method and system can test a plurality of similar memristor arrays which are made of the same memristor material but are produced through different development technologies at the same time, and output a performance comparison test report of the similar memristor arrays. And different memristor arrays produced by adopting the same development process but different memristor materials can be tested at the same time, a performance comparison test report of the different memristor arrays is output, and the memristor arrays can be tested according to the performance comparison test report of the similar memristor arrays or the performance comparison test report of the different memristor arrays. Compared with the prior art, the performance of similar memristor arrays of various development processes or different memristor arrays of various memristor materials can be compared and analyzed, and the optimal development process and the optimal memristor material can be quickly screened out, so that the development efficiency of the high-performance memristor array can be effectively improved.

Description

Technical Field

[0001] The present application belongs to the technical field of memristor array testing, and in particular, relates to a memristor array testing method and system. Background Art

[0002] Memristor array is a new type of nonlinear resistor with memory function. Its resistance value can change with the direction and amount of charge flowing through it, so as to remember the amount of charge flowing through it at every moment. When there is no more charge flowing through it, the resistance value can remain unchanged. Therefore, memristor array is a new type of electronic device with nonlinear dynamic resistive switching characteristics, high speed, low power consumption, high integration, and storage and computing fusion functions. The performance of memristor arrays is of great significance to the fields of information storage, logical computing and their integration, brain-like functional devices, etc.

[0003] At present, the test of memristor arrays generally analyzes the current characteristics of a single memristor array. It is impossible to compare the performance of multiple similar memristor arrays produced with the same memristor material but different development processes, nor is it possible to compare the performance of heterogeneous memristor arrays produced with the same development process but different memristor materials. As a result, it is impossible to quickly screen out the best development process and the best memristor material, making the research and development efficiency of high-performance memristor arrays very low. Summary of the invention

[0004] The purpose of the present application is to provide a memristor array testing method and system; the memristor array testing method and system provided in the present application can simultaneously test multiple similar memristor arrays produced using the same memristor material but different development processes, and output a similar memristor array performance comparison test report, and can also simultaneously test heterogeneous memristor arrays produced using the same development process but different memristor materials, and output a heterogeneous memristor array performance comparison test report. Through the similar memristor array performance comparison test report or the heterogeneous memristor array performance comparison test report, the performance of similar memristor arrays of multiple development processes or heterogeneous memristor arrays of multiple memristor materials can be compared and analyzed, and the best development process and the best memristor material can be quickly screened out, thereby effectively improving the research and development efficiency of high-performance memristor arrays.

[0005] The technical solutions provided by this application are as follows: A memristor array testing method is applied to a memristor array testing system, wherein the testing system comprises a test start control module, a test control module and a simulator, and the method comprises: After receiving the similar memristor array test start instruction, the test start control module obtains the similar memristor array test file, and generates the similar memristor array test item list and the similar memristor array test mode instruction according to the similar memristor array test file; The test control module identifies the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, controls to open similar test channels in the test control module that are connected to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator; After receiving the similar test channel opening instruction, the simulator sends similar test signals to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays, processes them and outputs them; The test start control module obtains a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list; After receiving the heterogeneous memristor array test start instruction, the test start control module obtains a heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; The test control module identifies the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, controls to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator; After receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the plurality of heterogeneous memristor arrays, processes the data and outputs the data; The test start control module obtains a heterogeneous memristor array performance comparison test report according to a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list.

[0006] Optionally, the test control module includes a test control processing module and a test channel control module; The test control module identifies the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, controls to open similar test channels in the test control module that are connected to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator, including: The test control processing module identifies the simulator according to the similar memristor array test mode instruction, and if the simulator is identified, sends the similar memristor array test mode instruction to the test channel control module; The test channel control module identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control module corresponding to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the simulator; The test control module identifies the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, controls to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator, including: The test control processing module identifies the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, sends the heterogeneous memristor array test mode instruction to the test channel control module; The test channel control module identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator.

[0007] Optionally, the test start control module includes a microprocessor, a data selector and an input encryption interface; After receiving the similar memristor array test start instruction, the test start control module obtains the similar memristor array test file, and generates the similar memristor array test item list and the similar memristor array test mode instruction according to the similar memristor array test file, including: After receiving the same type of memristor array test start instruction, the microprocessor sends the same type of data import instruction to the data selector; After receiving the same type of data import instruction, the data selector opens a data import channel connected to the input encryption interface, and sends the same type of data import instruction to the input encryption interface; After receiving the same type of data import instruction, the input encryption interface obtains the same type of memristor array test file and encrypts it before outputting it to the data selector; The data selector sends the received encrypted memristor array test file of the same type to the microprocessor; The microprocessor generates a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; After receiving the heterogeneous memristor array test start instruction, the test start control module obtains the heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file, including: After receiving the heterogeneous memristor array test start instruction, the microprocessor sends a heterogeneous data import instruction to the data selector; After receiving the heterogeneous data import instruction, the data selector opens a data import channel connected to the input encryption interface and sends the heterogeneous data import instruction to the input encryption interface; After receiving the heterogeneous data import instruction, the input encryption interface obtains the heterogeneous memristor array test file and performs encryption processing and then outputs it to the data selector; The data selector sends the received encrypted heterogeneous memristor array test file to the microprocessor; The microprocessor generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

[0008] Optionally, the test start control module further includes a data storage and a first output encryption interface and a second output encryption interface; After the test start control module obtains a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list, the method further includes: The microprocessor stores the performance comparison test report of the same type of memristor arrays in the data storage device, and sends a similar type of data export instruction to the data selector; After receiving the same type of data export instruction, the data selector opens a same type of data export channel connected to the first output encryption interface, and sends the same type of data export instruction to the first output encryption interface; After receiving the same type of data export instruction, the first output encryption interface encrypts and outputs the same type of memristor array performance comparison test report; After the test start control module obtains a heterogeneous memristor array performance comparison test report according to a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list, the method further includes: The microprocessor stores the heterogeneous memristor array performance comparison test report in the data storage device, and sends a heterogeneous data export instruction to the data selector; After receiving the heterogeneous data export instruction, the data selector opens a heterogeneous data export channel connected to the second output encryption interface, and sends the heterogeneous data export instruction to the second output encryption interface; After receiving the heterogeneous data export instruction, the second output encryption interface encrypts and outputs the heterogeneous memristor array performance comparison test report.

[0009] Optionally, the simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; The test control processing module identifies the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, sends the heterogeneous memristor array test mode instruction to the test channel control module, including: The MCU generates and outputs a first identification instruction according to the heterogeneous memristor array test mode instruction; The first FPGA identification unit identifies the first FPGA according to the first identification instruction, and sends a first identification success signal to the MCU when the first FPGA is identified, and sends a first identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit identifies the second FPGA according to the first identification instruction, and when the second FPGA is identified, sends a second identification success signal to the MCU, and when the second FPGA is not identified, sends a second identification failure signal to the MCU; After receiving the first recognition success signal and the second recognition success signal, the MCU sends a first control signal to the first switch and the second switch, and sends the heterogeneous memristor array test mode instruction to the CPLD; or, after receiving the first recognition success signal or the second recognition success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a second control signal to the first switch or the second switch, and sends the heterogeneous memristor array test mode instruction to the CPLD; After receiving the first control signal, the first switch switches to the channel between the first FPGA and the CPLD, or after receiving the second control signal, the first switch switches to the channel between the first FPGA and the CPLD; After receiving the first control signal, the second switch switches to the channel between the second FPGA and the CPLD, or after receiving the second control signal, the second switch switches to the channel between the second FPGA and the CPLD; The CPLD sends the received heterogeneous memristor array test mode instruction to the test channel control module.

[0010] Optionally, the test control processing module further includes a merging unit; The test control processing module identifies the simulator according to the similar memristor array test mode instruction, and if the simulator is identified, sends the similar memristor array test mode instruction to the test channel control module, including: The MCU generates and outputs a second identification instruction according to the same type of memristor array test mode instruction; The first FPGA identification unit identifies the first FPGA according to the second identification instruction, and sends a third identification success signal to the MCU when the first FPGA is identified, and sends a third identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit identifies the second FPGA according to the second identification instruction, and sends a fourth identification success signal to the MCU when the second FPGA is identified, and sends a fourth identification failure signal to the MCU when the second FPGA is not identified; After receiving the third recognition success signal and the fourth recognition success signal, the MCU sends a third control signal to the first switch and the second switch, and sends the same type of memristor array test mode instruction to the CPLD; After receiving the third control signal, the first switch switches to the channel between the first FPGA and the merging unit; After receiving the third control signal, the second switch switches to the channel between the second FPGA and the merging unit; After receiving the third recognition success signal or the fourth recognition success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a fourth control signal to the first switch or the second switch, and sends the same type of memristor array test mode instruction to the CPLD; After receiving the fourth control signal, the first switch switches to the channel between the first FPGA and the merging unit, or the second switch switches to the channel between the second FPGA and the merging unit after receiving the fourth control signal; The CPLD sends the received similar memristor array test mode instruction to the test channel control module.

[0011] Optionally, After receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the plurality of heterogeneous memristor arrays, processes and outputs the data, including: After receiving the heterogeneous test channel start instruction, the first FPGA and / or the second FPGA generates a first heterogeneous test signal and / or a second heterogeneous test signal, and outputs the signal to the CPLD; The CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The first FPGA processes the first heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; The second FPGA processes the second heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; Wherein, the heterogeneous test signal includes the first heterogeneous test signal and the second heterogeneous test signal, the heterogeneous memristor array includes the first heterogeneous memristor array and the second heterogeneous memristor array, the heterogeneous test data includes the first heterogeneous test data and the second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; After receiving the similar test channel opening instruction, the simulator sends similar test signals to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays, processes and outputs the data, including: After receiving the similar test channel opening instruction, the first FPGA and / or the second FPGA generates a first similar test signal and / or a second similar test signal, and outputs the signal to the merging unit; The merging unit merges the first similar test signal and the second similar test signal and then outputs the merged signal to the CPLD, or outputs the first similar test signal or the second similar test signal to the CPLD; The CPLD sends the merged similar test signal to each similar memristor array through the test channel control module, or sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receives similar test data of each similar memristor array sent by the test channel control module, and sends a plurality of similar test data to the merging unit; After the merging unit merges the plurality of the same type of test data, the merged same type of test data is divided into first same type of test data and second same type of test data, the first same type of test data is sent to the first FPGA, the second same type of test data is sent to the second FPGA, or the merged same type of test data is sent to the first FPGA or the second FPGA; The first FPGA processes the first test data of the same type and outputs it to the microprocessor, or processes the merged test data of the same type and outputs it to the microprocessor; The second FPGA processes the second test data of the same type and outputs it to the microprocessor, or processes the merged test data of the same type and outputs it to the microprocessor; Among them, the similar test signals include the first similar test signal and the second similar test signal, and the similar test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

[0012] Optionally, the test channel control module includes: a converter, an amplifier and a test channel control unit; The test channel control module identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control module that are connected to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the simulator, including: The converter sends the received test mode instruction of the same type of memristor array to the test channel control unit through the amplifier; The test channel control unit identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control unit that are connected to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the first FPGA and the second FPGA; The test channel control module identifies a plurality of heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if a plurality of the heterogeneous memristor arrays are identified, controls opening of the heterogeneous test channels in the test channel control module corresponding to the plurality of the heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator, including: The converter sends the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; The test channel control unit identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the first FPGA and the second FPGA.

[0013] Optionally, The CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA, including: The CPLD sends the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; The converter performs digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and then outputs the converted signal; The amplifier amplifies the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then outputs it; The test channel control unit sends the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array, respectively, or sends the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; The test channel control unit receives a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; The amplifier amplifies the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then outputs the amplified signals; The converter performs analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converts them into first heterogeneous test data and second heterogeneous test data, and outputs them to the CPLD; The CPLD sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The CPLD sends the merged similar test signal to each similar memristor array through the test channel control module, or sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receives similar test data of each similar memristor array sent by the test channel control module, and sends a plurality of similar test data to the merging unit, including: The CPLD sends the combined similar test signal to the converter, or sends the first similar test signal or the second similar test signal to the converter; The converter performs digital-to-analog conversion on the combined similar test signal and outputs it, or performs digital-to-analog conversion on the first similar test signal or the second similar test signal and outputs it; The amplifier amplifies the converted similar test signal and then outputs it, or amplifies the converted first similar test signal or the converted second similar test signal and then outputs it; The test channel control unit sends the amplified similar test signal to each of the similar memristor arrays, or sends the amplified first similar test signal or the amplified second similar test signal to each of the similar memristor arrays; The test channel control unit receives the same type of test feedback signals output by each of the same type of memristor arrays; The amplifier amplifies each of the test feedback signals of the same type and then outputs the amplified signals; The converter performs analog-to-digital conversion on each amplified test feedback signal of the same type, converts the signal into test data of the same type and outputs the data to the CPLD; The CPLD sends each of the same type of test data to the merging unit.

[0014] Optionally, the test start control module further includes a third output encryption interface, and the method further includes: When receiving the memristor array fault analysis instruction, the microprocessor obtains a similar memristor array fault analysis report according to the similar test data and the preset similar data range, or obtains a heterogeneous memristor array fault analysis report according to the heterogeneous test data and the preset heterogeneous data range, and sends a fault analysis export instruction to the data selector; After receiving the fault analysis export instruction, the data selector opens a fault analysis export channel connected to the third output encryption interface, and sends the same type of memristor array fault analysis report or the different type of memristor array fault analysis report to the third output encryption interface; The third output encryption interface encrypts the same type of memristor array fault analysis report or the different type of memristor array fault analysis report and then outputs it.

[0015] The present application also provides a memristor array test system, including a test start control module, a test control module and a simulator; The test start control module is used to obtain a similar memristor array test file after receiving a similar memristor array test start instruction, and generate a similar memristor array test item list and a similar memristor array test mode instruction according to the similar memristor array test file; The test control module is used to identify the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, control to open the similar test channels in the test control module that are connected to the multiple similar memristor arrays, and send a similar test channel opening instruction to the simulator; The simulator is used to send similar test signals to the plurality of similar memristor arrays through the test control module after receiving the similar test channel opening instruction, receive similar test data of the plurality of similar memristor arrays, process and output; The test start control module is further used to obtain a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list; The test start control module is further used to obtain a heterogeneous memristor array test file after receiving a heterogeneous memristor array test start instruction, and generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; The test control module is also used to identify the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, control to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and send a heterogeneous test channel opening instruction to the simulator; The simulator is further used to send a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module after receiving the heterogeneous test channel start instruction, receive the heterogeneous test data of the plurality of heterogeneous memristor arrays, process the data and output the data; The test start control module is further used to obtain a heterogeneous memristor array performance comparison test report based on a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list.

[0016] Optionally, the test control module includes a test control processing module and a test channel control module; The test control processing module is used to identify the simulator according to the same type of memristor array test mode instruction, and if the simulator is identified, send the same type of memristor array test mode instruction to the test channel control module; The test channel control module is used to identify multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, control to open the similar test channels in the test channel control module that are connected to the multiple similar memristor arrays, and send a similar test channel opening instruction to the simulator; The test control processing module is further used to identify the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, send the heterogeneous memristor array test mode instruction to the test channel control module; The test channel control module is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator.

[0017] Optionally, the test start control module includes a microprocessor, a data selector and an input encryption interface; The microprocessor is used to send a similar data import instruction to the data selector after receiving a similar memristor array test start instruction; The data selector is used to open the data import channel connected to the input encryption interface after receiving the same type of data import instruction, and send the same type of data import instruction to the input encryption interface; The input encryption interface is used to obtain the same type of memristor array test file and output the data selector after encrypting it after receiving the same type of data import instruction; The data selector is further used to send the received encrypted memristor array test file of the same type to the microprocessor; The microprocessor is further used to generate a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; The microprocessor is further configured to send a heterogeneous data import instruction to the data selector after receiving a heterogeneous memristor array test start instruction; The data selector is further used to open a data import channel connected to the input encryption interface after receiving the heterogeneous data import instruction, and send the heterogeneous data import instruction to the input encryption interface; The input encryption interface is further used to obtain the heterogeneous memristor array test file after receiving the heterogeneous data import instruction and output it to the data selector after encryption processing; The data selector is further used to send the received encrypted heterogeneous memristor array test file to the microprocessor; The microprocessor is also used to generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

[0018] Optionally, the test start control module further includes a data storage and a first output encryption interface and a second output encryption interface; The microprocessor is further used to store the performance comparison test report of the same type of memristor arrays in the data storage device, and send a similar type of data export instruction to the data selector; The data selector is further configured to, after receiving the same type of data export instruction, open a same type of data export channel connected to the first output encryption interface, and send the same type of data export instruction to the first output encryption interface; The first output encryption interface is used to encrypt and output the performance comparison test report of the same type of memristor array after receiving the same type of data export instruction; The microprocessor is further used to store the heterogeneous memristor array performance comparison test report in the data storage device, and send a heterogeneous data export instruction to the data selector; The data selector is further configured to, after receiving the heterogeneous data export instruction, open a heterogeneous data export channel connected to the second output encryption interface, and send the heterogeneous data export instruction to the second output encryption interface; The second output encryption interface is used to encrypt and output the heterogeneous memristor array performance comparison test report after receiving the heterogeneous data export instruction.

[0019] Optionally, the simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; The MCU is used to generate and output a first identification instruction according to the heterogeneous memristor array test mode instruction; The first FPGA identification unit is used to identify the first FPGA according to the first identification instruction, and send a first identification success signal to the MCU when the first FPGA is identified, and send a first identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit is used to identify the second FPGA according to the first identification instruction, and when the second FPGA is identified, send a second identification success signal to the MCU; when the second FPGA is not identified, send a second identification failure signal to the MCU; The MCU is further configured to send a first control signal to the first switch and the second switch after receiving the first recognition success signal and the second recognition success signal, and send the heterogeneous memristor array test mode instruction to the CPLD; The first switch is used to switch to the channel between the first FPGA and the CPLD after receiving the first control signal; The second switch is used to switch to the channel between the second FPGA and the CPLD after receiving the first control signal; The MCU is further configured to control closing the second FPGA or the first FPGA after receiving the first recognition success signal or the second recognition success signal, send a second control signal to the first switch or the second switch, and send the heterogeneous memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the CPLD after receiving the second control signal; The second switch is further used to switch to the channel between the second FPGA and the CPLD after receiving the second control signal; The CPLD is used to send the received heterogeneous memristor array test mode instruction to the test channel control module.

[0020] Optionally, the test control processing module further includes a merging unit; The MCU is further used to generate and output a second identification instruction according to the similar memristor array test mode instruction; The first FPGA identification unit is further configured to identify the first FPGA according to the second identification instruction, and when the first FPGA is identified, send a third identification success signal to the MCU, and when the first FPGA is not identified, send a third identification failure signal to the MCU; The second FPGA identification unit is further used to identify the second FPGA according to the second identification instruction, and when the second FPGA is identified, send a fourth identification success signal to the MCU, and when the second FPGA is not identified, send a fourth identification failure signal to the MCU; The MCU is further configured to send a third control signal to the first switch and the second switch after receiving the third recognition success signal and the fourth recognition success signal, and send the same type of memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the merging unit after receiving the third control signal; The second switch is further configured to switch to a channel between the second FPGA and the merging unit after receiving the third control signal; The MCU is further configured to control the second FPGA or the first FPGA to be turned off after receiving the third recognition success signal or the fourth recognition success signal, send a fourth control signal to the first switch or the second switch, and send the same type of memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the merging unit after receiving the fourth control signal; The second switch is further configured to switch to a channel between the second FPGA and the merging unit after receiving the fourth control signal; The CPLD is also used to send the received similar memristor array test mode instruction to the test channel control module.

[0021] Optionally, The first FPGA is used to generate a first heterogeneous test signal after receiving the heterogeneous test channel start instruction, and output it to the CPLD; The second FPGA is used to generate a second heterogeneous test signal after receiving the heterogeneous test channel start instruction, and output it to the CPLD; The CPLD is further used to send the first heterogeneous test signal and / or the second heterogeneous test signal to each of the heterogeneous memristor arrays through the test channel control module; The CPLD is further used to send the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or send the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The first FPGA is further used to process the first heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; The second FPGA is further used to process the second heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; Wherein, the heterogeneous test signal includes the first heterogeneous test signal and the second heterogeneous test signal, the heterogeneous memristor array includes the first heterogeneous memristor array and the second heterogeneous memristor array, the heterogeneous test data includes the first heterogeneous test data and the second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; The first FPGA is further configured to generate a first similar test signal after receiving the similar test channel opening instruction, and output the signal to the merging unit; The second FPGA is further used to generate a second similar test signal after receiving the similar test channel opening instruction, and output it to the merging unit; The merging unit is used to merge the first similar test signal and the second similar test signal and then output them to the CPLD, or to output the first similar test signal or the second similar test signal to the CPLD; The CPLD is further used to send the merged similar test signal to each similar memristor array through the test channel control module, or send the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receive similar test data of each similar memristor array sent by the test channel control module, and send a plurality of similar test data to the merging unit; The merging unit is further used to merge the plurality of the same type of test data, and then divide the merged same type of test data into first same type of test data and second same type of test data, send the first same type of test data to the first FPGA, send the second same type of test data to the second FPGA, or send the merged same type of test data to the first FPGA or the second FPGA; The first FPGA is further used to process the first test data of the same type and output it to the microprocessor, or process the merged test data of the same type and output it to the microprocessor; The second FPGA is further used to process the second similar test data and output it to the microprocessor, or process the merged similar test data and output it to the microprocessor; Among them, the similar test signals include the first similar test signal and the second similar test signal, and the similar test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

[0022] Optionally, the test channel control module includes: a converter, an amplifier and a test channel control unit; The converter is used to send the received test mode instruction of the same type of memristor array to the test channel control unit through the amplifier; The test channel control unit is used to identify multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, control to open similar test channels in the test channel control unit that are connected to the multiple similar memristor arrays, and send similar test channel opening instructions to the first FPGA and the second FPGA; The converter is further used to send the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; The test channel control unit is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the first FPGA and the second FPGA.

[0023] Optionally, The CPLD is further used to send the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; The converter is used for performing digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and then outputting the converted signal; The amplifier is used to amplify the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then output it; The test channel control unit is used to send the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively, or send the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; The test channel control unit is further configured to receive a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; The amplifier is further used to amplify the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then output them; The converter is further used to perform analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converting them into first heterogeneous test data and second heterogeneous test data and outputting them to the CPLD; The CPLD is further used to send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The CPLD is further used to send the combined similar test signal to the converter, or send the first similar test signal or the second similar test signal to the converter; The converter is further used to perform digital-to-analog conversion on the combined similar test signal and then output it, or perform digital-to-analog conversion on the first similar test signal or the second similar test signal and then output it; The amplifier is further used to amplify the converted similar test signal and output it, or to amplify the converted first similar test signal or the converted second similar test signal and output it; The test channel control unit is further used to send the amplified similar test signal to each of the similar memristor arrays, or send the amplified first similar test signal or the amplified second similar test signal to each of the similar memristor arrays; The test channel control unit is further used to receive similar test feedback signals output by each of the similar memristor arrays; The amplifier is also used to amplify each of the test feedback signals of the same type and then output them; The converter is also used to perform analog-to-digital conversion on each amplified test feedback signal of the same type, and convert it into each test data of the same type and output it to the CPLD; The CPLD is also used to send each of the same type of test data to the merging unit.

[0024] Optionally, the test start control module further includes a third output encryption interface; The microprocessor is further configured to obtain a similar memristor array fault analysis report based on the similar test data and a preset similar data range, or obtain a heterogeneous memristor array fault analysis report based on the heterogeneous test data and a preset heterogeneous data range, and send a fault analysis export instruction to the data selector when receiving a memristor array fault analysis instruction; The data selector is further configured to, after receiving the fault analysis export instruction, open a fault analysis export channel connected to the third output encryption interface, and send the same type of memristor array fault analysis report or the different type of memristor array fault analysis report to the third output encryption interface; The third output encryption interface is used to encrypt and output the similar memristor array fault analysis report or the heterogeneous memristor array fault analysis report.

[0025] Compared with the prior art, the present application provides a memristor array testing method and system, which obtains a similar memristor array test file after receiving a similar memristor array test start instruction through a test start control module, and generates a similar memristor array test item list and a similar memristor array test mode instruction according to the similar memristor array test file, and then the test control module identifies a simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, the test control module controls to open similar test channels corresponding to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator, and after receiving the similar test channel opening instruction, the simulator sends a similar test signal to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays and outputs them after processing, and the test start control module obtains the same memristor array test items according to the multiple processed similar test data and the similar memristor array test item list. A performance comparison test report of similar memristor arrays; after receiving a test start instruction of a heterogeneous memristor array, a test start control module obtains a heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; then the test control module identifies a simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction; if the simulator and multiple heterogeneous memristor arrays are identified, the test control module controls the opening of heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator; after receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the multiple heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the multiple heterogeneous memristor arrays and outputs them after processing; the test start control module obtains a performance comparison test report of the heterogeneous memristor array according to the multiple processed heterogeneous test data and the heterogeneous memristor array test item list. In the present application, multiple similar memristor arrays produced using the same memristor material but different development processes can be tested simultaneously to output a similar memristor array performance comparison test report, and heterogeneous memristor arrays produced using the same development process but different memristor materials can be tested simultaneously to output a heterogeneous memristor array performance comparison test report. Through the similar memristor array performance comparison test report or the heterogeneous memristor array performance comparison test report, the performance of similar memristor arrays of multiple development processes or heterogeneous memristor arrays of multiple memristor materials can be compared and analyzed, and the best development process and the best memristor material can be quickly screened out, thereby effectively improving the research and development efficiency of high-performance memristor arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A flow chart of a memristor array testing method disclosed in an embodiment of the present application; Figure 2 A structural block diagram of a memristor array test system connected to similar memristor arrays disclosed in an embodiment of the present application; Figure 3 A structural block diagram of a memristor array test system connected to a heterogeneous memristor array disclosed in an embodiment of the present application; Figure 4 A structural block diagram of another memristor array test system connected to a similar memristor array disclosed in an embodiment of the present application; Figure 5 A structural block diagram of another memristor array test system connected to a heterogeneous memristor array disclosed in an embodiment of the present application; Figure 6 A structural block diagram of a test start control module disclosed in an embodiment of the present application; Figure 7 A structural block diagram of a test control processing module and a simulator connected to a heterogeneous memristor array disclosed in an embodiment of the present application; Figure 8 A structural block diagram of a test control processing module and a simulator connected to a similar memristor array disclosed in an embodiment of the present application; Fig. 9 A structural block diagram of a test channel control module connected to a heterogeneous memristor array disclosed in an embodiment of the present application; Fig.10 This is a structural block diagram of a test channel control module connected to a similar memristor array disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] It should be noted that when an element is referred to as being "fixed on" or "set on" another element, it can be directly on the other element or indirectly set on the other element; when an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0030] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.

[0032] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which this application can be implemented. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by this application.

[0033] like Figure 1 As shown, an embodiment of the present application provides a memristor array test method, which is applied to a memristor array test system. The test system includes a test start control module, a test control module and a simulator. The method includes: S11, after receiving the similar memristor array test start instruction, the test start control module obtains the similar memristor array test file, and generates the similar memristor array test item list and the similar memristor array test mode instruction according to the similar memristor array test file; In this embodiment, a human-computer interaction interface electrically connected to the test start control module can be set up, and a "similar memristor array test start" button on the human-computer interaction interface can be clicked to send a similar memristor array test start instruction to the test start control module. After receiving the similar memristor array test start instruction, the test start control module obtains a similar memristor array test file, and can generate a similar memristor array test item list and a similar memristor array test mode instruction by screening the manufacturing process data in the similar memristor array test file, and send the similar memristor array test mode instruction to the test control module.

[0034] The same type of memristor array test file can be a similar memristor material development process performance comparison test file, the same type of memristor array test item list can be a similar memristor material development process performance comparison test item list, the same type of memristor array test file can be stored in an external storage device (such as a USB flash drive) connected to the test start control module through an interface, and the same type of memristor array test file can also be pre-stored in a storage device in the test start control module.

[0035] S12, the test control module identifies the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, controls to open the similar test channels in the test control module that are connected to the multiple similar memristor arrays, and sends the similar test channel opening instruction to the simulator; In this embodiment, after receiving the similar memristor array test mode instruction sent by the test start control module, the test control module respectively identifies the simulator and multiple similar memristor arrays. If the simulator and multiple similar memristor arrays can be identified, and data communication can be established between the test control module and the simulator, and data communication can be established between the test control module and multiple similar memristor arrays, then the test control module controls the opening of similar test channels corresponding to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator.

[0036] S13, after receiving the same type of test channel opening instruction, the simulator sends the same type of test signal to multiple similar memristor arrays through the test control module, receives the same type of test data of multiple similar memristor arrays, processes and outputs them; In this embodiment, after receiving the same type of test channel opening instruction, the simulator sends the same type of test signal, and the same type of test signal is transmitted to multiple similar memristor arrays through the test control module. After receiving the same type of test signal, the multiple similar memristor arrays respectively feedback and output similar test data. The same type of test data of multiple similar memristor arrays is transmitted to the simulator through the test control module. After receiving the same type of test data of multiple similar memristor arrays, the simulator processes the same type of test data of multiple similar memristor arrays and outputs it to the test start control module. The same type of test data can be the development process test data of the memristor array of the same type of memristor material.

[0037] S14, the test start control module obtains a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and a similar memristor array test item list; In this embodiment, the test start control module can write multiple processed similar test data into corresponding positions in the similar memristor array test item list to obtain a similar memristor array performance comparison test report on the similar memristor material development process performance comparison.

[0038] S15, after receiving the heterogeneous memristor array test start instruction, the test start control module obtains the heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; In this embodiment, a heterogeneous memristor array test start instruction can be sent to the test start control module by clicking the "heterogeneous memristor array test start" button on the human-computer interaction interface. After receiving the heterogeneous memristor array test start instruction, the test start control module obtains the heterogeneous memristor array test file, and can generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction by screening the memristor material data in the heterogeneous memristor array test file, and send the heterogeneous memristor array test mode instruction to the test control module.

[0039] The heterogeneous memristor array test file can be a heterogeneous memristor material test file with the same development process, the heterogeneous memristor array test item list can be a heterogeneous memristor material performance comparison test item list, the heterogeneous memristor array test file can be stored in an external storage device (such as a USB flash drive) connected to the test start control module through an interface, and the heterogeneous memristor array test file can also be pre-stored in a storage device in the test start control module.

[0040] S16, the test control module identifies the simulator and the multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and the multiple heterogeneous memristor arrays are identified, controls to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator; In this embodiment, after receiving the heterogeneous memristor array test mode instruction sent by the test start control module, the test control module respectively identifies the simulator and multiple heterogeneous memristor arrays. If the simulator and multiple heterogeneous memristor arrays can be identified, and data communication can be established between the test control module and the simulator, and data communication can be established between the test control module and the multiple heterogeneous memristor arrays, then the test control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator.

[0041] S17, after receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to a plurality of heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the plurality of heterogeneous memristor arrays, processes the data and outputs the data; In this embodiment, after receiving the heterogeneous test channel start instruction, the simulator sends a heterogeneous test signal, and the heterogeneous test signal is transmitted to multiple heterogeneous memristor arrays through the test control module. After receiving the heterogeneous test signal, the multiple heterogeneous memristor arrays respectively feedback and output heterogeneous test data. The heterogeneous test data of the multiple heterogeneous memristor arrays are transmitted to the simulator through the test control module. After receiving the heterogeneous test data of the multiple heterogeneous memristor arrays, the simulator processes the heterogeneous test data of the multiple heterogeneous memristor arrays and outputs them to the test start control module. The heterogeneous test data can be the heterogeneous memristor material test data of the heterogeneous memristor material memristor array.

[0042] S18. The test start control module obtains a heterogeneous memristor array performance comparison test report according to the plurality of processed heterogeneous test data and the heterogeneous memristor array test item list.

[0043] In this embodiment, the test start control module can write a plurality of processed heterogeneous test data into corresponding positions in the heterogeneous memristor array test item list to obtain a heterogeneous memristor array performance comparison test report on the performance comparison of heterogeneous memristor materials.

[0044] Compared with the prior art, the present application provides a memristor array testing method and system, which obtains a similar memristor array test file after receiving a similar memristor array test start instruction through a test start control module, and generates a similar memristor array test item list and a similar memristor array test mode instruction according to the similar memristor array test file, and then the test control module identifies a simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, the test control module controls to open similar test channels corresponding to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator, and after receiving the similar test channel opening instruction, the simulator sends a similar test signal to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays and outputs them after processing, and the test start control module obtains the same memristor array test items according to the multiple processed similar test data and the similar memristor array test item list. A performance comparison test report of similar memristor arrays; after receiving a test start instruction of a heterogeneous memristor array, a test start control module obtains a heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; then the test control module identifies a simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction; if the simulator and multiple heterogeneous memristor arrays are identified, the test control module controls the opening of heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator; after receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the multiple heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the multiple heterogeneous memristor arrays and outputs them after processing; the test start control module obtains a performance comparison test report of the heterogeneous memristor array according to the multiple processed heterogeneous test data and the heterogeneous memristor array test item list. In the present application, multiple similar memristor arrays produced using the same memristor material but different development processes can be tested simultaneously to output a similar memristor array performance comparison test report, and heterogeneous memristor arrays produced using the same development process but different memristor materials can be tested simultaneously to output a heterogeneous memristor array performance comparison test report. Through the similar memristor array performance comparison test report or the heterogeneous memristor array performance comparison test report, the performance of similar memristor arrays of multiple development processes or heterogeneous memristor arrays of multiple memristor materials can be compared and analyzed, and the best development process and the best memristor material can be quickly screened out, thereby effectively improving the research and development efficiency of high-performance memristor arrays.

[0045] As an implementation mode, in the embodiment of the present application, the test control module includes a test control processing module and a test channel control module; Step S12 includes: S121, the test control processing module identifies the simulator according to the same type of memristor array test mode instruction, and if the simulator is identified, sends the same type of memristor array test mode instruction to the test channel control module; In this embodiment, after receiving the same type of memristor array test mode instruction sent by the test start control module, the test control processing module identifies the simulator. If the simulator can be identified and data communication can be established between the test control processing module and the simulator, the same type of memristor array test mode instruction is sent to the test channel control module.

[0046] S122, the test channel control module identifies multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, controls the opening of similar test channels in the test channel control module that are connected to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator; In this embodiment, after receiving the similar memristor array test mode instruction sent by the test control processing module, the test channel control module identifies multiple similar memristor arrays. If multiple similar memristor arrays are identified and data communication can be established between the test channel control module and the multiple similar memristor arrays, the test channel control module controls the opening of similar test channels corresponding to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator.

[0047] Step S16 includes: S161, the test control processing module identifies the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, sends the heterogeneous memristor array test mode instruction to the test channel control module; In this embodiment, after receiving the heterogeneous memristor array test mode instruction sent by the test start control module, the test control processing module identifies the simulator. If the simulator can be identified and data communication can be established between the test control processing module and the simulator, the heterogeneous memristor array test mode instruction is sent to the test channel control module.

[0048] S162, the test channel control module identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator.

[0049] In this embodiment, after receiving the heterogeneous memristor array test mode instruction sent by the test control processing module, the test channel control module identifies multiple heterogeneous memristor arrays. If multiple heterogeneous memristor arrays are identified and data communication can be established between the test channel control module and the multiple heterogeneous memristor arrays, the test channel control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator.

[0050] As an implementation mode, in an embodiment of the present application, the test start control module includes a microprocessor, a data selector and an input encryption interface; Step S11 includes: S111, after receiving the same type of memristor array test start instruction, the microprocessor sends the same type of data import instruction to the data selector; In this embodiment, the human-computer interaction interface can be specifically electrically connected to the microprocessor, and a similar memristor array test start instruction can be sent to the microprocessor through the human-computer interaction interface. After receiving the similar memristor array test start instruction, the microprocessor sends a similar data import instruction to the data selector.

[0051] S112, after receiving the same type of data import instruction, the data selector opens the data import channel connected to the input encryption interface, and sends the same type of data import instruction to the input encryption interface; In this embodiment, after receiving the same type of data import instruction, the data selector opens the data import channel in the data selector connected to the input encryption interface, and sends the same type of data import instruction to the input encryption interface.

[0052] S113, after receiving the same type of data import instruction, the input encryption interface obtains the same type of memristor array test file and encrypts it before outputting it to the data selector; In this embodiment, after receiving the same type of data import instruction, the input encryption interface can obtain the same type of memristor array test file from the external storage device (such as a USB flash drive) connected to the interface. A first encryption chip can be integrated in the input encryption interface. After obtaining the same type of memristor array test file, the same type of memristor array test file is encrypted by the first encryption chip in the input encryption interface and then output to the data selector.

[0053] S114, the data selector sends the received encrypted memristor array test file of the same type to the microprocessor.

[0054] In this embodiment, the data selector sends the received encrypted memristor array test file of the same type to the microprocessor through the data import channel.

[0055] S115, the microprocessor generates a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; In this embodiment, the microprocessor can generate a similar memristor array test item list and a similar memristor array test mode instruction by screening the manufacturing process data in the encrypted similar memristor array test file, and send the similar memristor array test mode instruction to the test control processing module.

[0056] Step S15 includes: S151, after receiving the heterogeneous memristor array test start instruction, the microprocessor sends a heterogeneous data import instruction to the data selector; In this embodiment, a heterogeneous memristor array test start instruction can be sent to the microprocessor through the human-computer interaction interface. After receiving the heterogeneous memristor array test start instruction, the microprocessor sends a heterogeneous data import instruction to the data selector.

[0057] S152, after receiving the heterogeneous data import instruction, the data selector opens the data import channel connected to the input encryption interface, and sends the heterogeneous data import instruction to the input encryption interface; In this embodiment, after receiving the heterogeneous data import instruction, the data selector opens the data import channel in the data selector connected to the input encryption interface, and sends the heterogeneous data import instruction to the input encryption interface.

[0058] S153, after receiving the heterogeneous data import instruction, the input encryption interface obtains the heterogeneous memristor array test file and performs encryption processing and then outputs it to the data selector; In this embodiment, after receiving the heterogeneous data import instruction, the input encryption interface can obtain the heterogeneous memristor array test file from the external storage device (such as a USB flash drive) connected to the interface. After obtaining the heterogeneous memristor array test file, the heterogeneous memristor array test file is encrypted by the first encryption chip in the input encryption interface and then output to the data selector.

[0059] S154, the data selector sends the received encrypted heterogeneous memristor array test file to the microprocessor.

[0060] In this embodiment, the data selector sends the received encrypted heterogeneous memristor array test file to the microprocessor through the data import channel.

[0061] S155. The microprocessor generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

[0062] In this embodiment, the microprocessor can generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction by screening the memristor material data in the encrypted heterogeneous memristor array test file, and send the heterogeneous memristor array test mode instruction to the test control processing module.

[0063] As an implementation mode, in the embodiment of the present application, the test start control module further includes a data storage and a first output encryption interface and a second output encryption interface; After step S14, the method further comprises: S21, the microprocessor stores the performance comparison test report of similar memristor arrays in the data storage device, and sends a similar data export instruction to the data selector; In this embodiment, the microprocessor transmits the performance comparison test report of the same type of memristor arrays through the data storage bus and stores it in the data storage device, and sends the same type of data export instruction to the data selector.

[0064] S22, after receiving the same type of data export instruction, the data selector opens the same type of data export channel connected to the first output encryption interface, and sends the same type of data export instruction to the first output encryption interface; In this embodiment, after receiving the same type of data export instruction, the data selector opens the same type of data export channel in the data selector connected to the first output encryption interface, and sends the same type of data export instruction to the first output encryption interface.

[0065] S23, after receiving the same type of data export instruction, the first output encryption interface encrypts and outputs the same type of memristor array performance comparison test report; In this embodiment, a second encryption chip can be integrated in the first output encryption interface. After receiving the same type of data export instruction, the first output encryption interface encrypts the same type of memristor array performance comparison test report through the second encryption chip in the first output encryption interface and outputs it to an external storage device (such as a USB flash drive).

[0066] After step S18, the method further includes: S31, the microprocessor stores the heterogeneous memristor array performance comparison test report in the data storage device, and sends a heterogeneous data export instruction to the data selector; In this embodiment, the microprocessor transmits the heterogeneous memristor array performance comparison test report through the data storage bus and stores it in the data storage device, and sends a heterogeneous data export instruction to the data selector.

[0067] S32, after receiving the heterogeneous data export instruction, the data selector opens the heterogeneous data export channel connected to the second output encryption interface, and sends the heterogeneous data export instruction to the second output encryption interface; In this embodiment, after receiving the heterogeneous data export instruction, the data selector opens a heterogeneous data export channel in the data selector that is connected to the second output encryption interface, and sends the heterogeneous data export instruction to the second output encryption interface.

[0068] S33. After receiving the heterogeneous data export instruction, the second output encryption interface encrypts and outputs the heterogeneous memristor array performance comparison test report.

[0069] In this embodiment, a third encryption chip can be integrated in the second output encryption interface. After receiving the heterogeneous data export instruction, the second output encryption interface encrypts the heterogeneous memristor array performance comparison test report through the third encryption chip in the second output encryption interface and outputs it to an external storage device (such as a USB flash drive).

[0070] As an implementation mode, in the embodiment of the present application, the simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; In this embodiment, FPGA is the abbreviation of Field-Programmable Gate Array, i.e., field programmable gate array; MCU is the abbreviation of Microcontroller Unit, i.e., micro control unit; CPLD is the abbreviation of Complex Programmable Logic Device, i.e., complex programmable logic device.

[0071] Step S161 includes: S1611, MCU generates and outputs a first identification instruction according to the heterogeneous memristor array test mode instruction; In this embodiment, the MCU generates a first identification instruction according to the heterogeneous memristor array test mode instruction sent by the microprocessor and outputs the first identification instruction to the first FPGA identification unit and the second FPGA identification unit.

[0072] S1612: The first FPGA identification unit identifies the first FPGA according to the first identification instruction, and sends a first identification success signal to the MCU when the first FPGA is identified; and sends a first identification failure signal to the MCU when the first FPGA is not identified; In this embodiment, the first FPGA identification unit identifies the first FPGA according to the first identification instruction. When the first FPGA is identified and data communication can be established between the first FPGA identification unit and the first FPGA, it is determined that the first FPGA is in place and in a normal health state. The first FPGA identification unit sends a first identification success signal to the MCU. When the first FPGA is not identified, the first identification failure signal is sent to the MCU.

[0073] In this embodiment, the first FPGA and the second FPGA may be two FPGAs with the same performance.

[0074] S1613: The second FPGA identification unit identifies the second FPGA according to the first identification instruction, and sends a second identification success signal to the MCU when the second FPGA is identified; and sends a second identification failure signal to the MCU when the second FPGA is not identified; In this embodiment, the second FPGA identification unit identifies the second FPGA according to the first identification instruction. When the second FPGA is identified and data communication can be established between the second FPGA identification unit and the second FPGA, it is determined that the second FPGA is in place and in normal health. The second FPGA identification unit sends a second identification success signal to the MCU. When the second FPGA is not identified, a second identification failure signal is sent to the MCU.

[0075] S1614, after receiving the first recognition success signal and the second recognition success signal, the MCU sends a first control signal to the first switch and the second switch, and sends a heterogeneous memristor array test mode instruction to the CPLD, or, after receiving the first recognition success signal or the second recognition success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a second control signal to the first switch or the second switch, and sends a heterogeneous memristor array test mode instruction to the CPLD; In this embodiment, if both the first FPGA and the second FPGA are identified, the MCU will receive the first identification success signal and the second identification success signal. After receiving the first identification success signal and the second identification success signal, the MCU sends the first control signal to the first switching switch and the second switching switch, and sends the heterogeneous memristor array test mode instruction to the CPLD. If only one of the first FPGA and the second FPGA is identified, that is, only the first FPGA is identified or only the second FPGA is identified, the MCU will receive the first identification success signal or the second identification success signal. After receiving the first identification success signal or the second identification success signal, the MCU controls the second FPGA to be turned off or controls the first FPGA to be turned off, sends the second control signal to the first switching switch or the second switching switch, and sends the heterogeneous memristor array test mode instruction to the CPLD.

[0076] S1615: After receiving the first control signal, the first switch switches to the channel between the first FPGA and the CPLD, or after receiving the second control signal, the first switch switches to the channel between the first FPGA and the CPLD; In this embodiment, when both the first FPGA and the second FPGA are identified, the first switching switch will receive the first control signal, and after receiving the first control signal, the first switching switch will switch to the channel between the first FPGA and the CPLD; when only the first FPGA is identified, the first switching switch will receive the second control signal, and after receiving the second control signal, the first switching switch will switch to the channel between the first FPGA and the CPLD.

[0077] S1616: After receiving the first control signal, the second switch switches to the channel between the second FPGA and the CPLD, or after receiving the second control signal, the second switch switches to the channel between the second FPGA and the CPLD; In this embodiment, when both the first FPGA and the second FPGA are identified, the second switching switch will receive the first control signal, and after receiving the first control signal, the second switching switch will switch to the channel between the second FPGA and the CPLD; when only the second FPGA is identified, the second switching switch will receive the second control signal, and after receiving the second control signal, the second switching switch will switch to the channel between the second FPGA and the CPLD.

[0078] S1617. The CPLD sends the received heterogeneous memristor array test mode instruction to the test channel control module.

[0079] In this embodiment, the CPLD sends the heterogeneous memristor array test mode instruction sent by the MCU to the test channel control module.

[0080] As an implementation mode, in the embodiment of the present application, the test control processing module further includes a merging unit; Step S121 includes: S1211, MCU generates and outputs a second identification instruction according to the same type of memristor array test mode instruction; In this embodiment, the MCU generates a second identification instruction according to the same type of memristor array test mode instruction sent by the microprocessor and outputs the second identification instruction to the first FPGA identification unit and the second FPGA identification unit.

[0081] S1212: The first FPGA identification unit identifies the first FPGA according to the second identification instruction, and sends a third identification success signal to the MCU when the first FPGA is identified; and sends a third identification failure signal to the MCU when the first FPGA is not identified; In this embodiment, the first FPGA identification unit identifies the first FPGA according to the second identification instruction. When the first FPGA is identified and data communication can be established between the first FPGA identification unit and the first FPGA, a third identification success signal is sent to the MCU. When the first FPGA is not identified, a third identification failure signal is sent to the MCU.

[0082] S1213, the second FPGA identification unit identifies the second FPGA according to the second identification instruction, and when the second FPGA is identified, sends a fourth identification success signal to the MCU; when the second FPGA is not identified, sends a fourth identification failure signal to the MCU; In this embodiment, the second FPGA identification unit identifies the second FPGA according to the second identification instruction. When the second FPGA is identified and data communication can be established between the second FPGA identification unit and the second FPGA, a fourth identification success signal is sent to the MCU. When the second FPGA is not identified, a fourth identification failure signal is sent to the MCU.

[0083] S1214, after receiving the third identification success signal and the fourth identification success signal, the MCU sends a third control signal to the first switch and the second switch, and sends a similar memristor array test mode instruction to the CPLD, or, after receiving the third identification success signal or the fourth identification success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a fourth control signal to the first switch or the second switch, and sends a similar memristor array test mode instruction to the CPLD; In this embodiment, if both the first FPGA and the second FPGA are identified, the MCU will receive a third identification success signal and a fourth identification success signal. After receiving the third identification success signal and the fourth identification success signal, the MCU sends a third control signal to the first switching switch and the second switching switch, and sends the same type of memristor array test mode instruction to the CPLD. If only one of the first FPGA and the second FPGA is identified, that is, only the first FPGA is identified or only the second FPGA is identified, the MCU will receive the third identification success signal or the fourth identification success signal. After receiving the third identification success signal or the fourth identification success signal, the MCU controls the second FPGA to be turned off or controls the first FPGA to be turned off, sends a fourth control signal to the first switching switch or the second switching switch, and sends the same type of memristor array test mode instruction to the CPLD.

[0084] S1215: After receiving the third control signal, the first switch switches to the channel between the first FPGA and the merging unit, or after receiving the fourth control signal, the first switch switches to the channel between the first FPGA and the merging unit; In this embodiment, when both the first FPGA and the second FPGA are identified, the first switching switch will receive the third control signal, and after receiving the third control signal, the first switching switch will switch to the channel between the first FPGA and the merging unit; when only the first FPGA is identified, the first switching switch will receive the fourth control signal, and after receiving the fourth control signal, the first switching switch will switch to the channel between the first FPGA and the merging unit.

[0085] S1216: After receiving the third control signal, the second switch switches to the channel between the second FPGA and the merging unit, or after receiving the fourth control signal, the second switch switches to the channel between the second FPGA and the merging unit; In this embodiment, when both the first FPGA and the second FPGA are identified, the second switching switch will receive the third control signal, and after receiving the third control signal, the second switching switch will switch to the channel between the second FPGA and the merging unit; when only the second FPGA is identified, the second switching switch will receive the fourth control signal, and after receiving the fourth control signal, the second switching switch will switch to the channel between the second FPGA and the merging unit.

[0086] S1217. The CPLD sends the received similar memristor array test mode instruction to the test channel control module.

[0087] In this embodiment, the CPLD sends the same type of memristor array test mode instruction sent by the MCU to the test channel control module.

[0088] As an implementation manner, in the embodiment of the present application, step S17 includes: S171, after receiving the heterogeneous test channel start instruction, the first FPGA and / or the second FPGA generates a first heterogeneous test signal and / or a second heterogeneous test signal, and outputs the signal to the CPLD; In this embodiment, when both the first FPGA and the second FPGA are identified, that is, when both the first FPGA and the second FPGA are in place and in a normal health state, the first FPGA generates a first heterogeneous test signal and outputs it to the CPLD after receiving the heterogeneous test channel start instruction, and the second FPGA generates a second heterogeneous test signal and outputs it to the CPLD after receiving the heterogeneous test channel start instruction; if only the first FPGA is in place and in a normal health state, the first FPGA generates a first heterogeneous test signal and outputs it to the CPLD after receiving the heterogeneous test channel start instruction; if only the second FPGA is in place and in a normal health state, the second FPGA generates a second heterogeneous test signal and outputs it to the CPLD after receiving the heterogeneous test channel start instruction.

[0089] S172, the CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; In this embodiment, when the first FPGA and the second FPGA are both in place and in a normal health state, the CPLD sends the first heterogeneous test signal to the first heterogeneous memristor array through the test channel control module. After receiving the first heterogeneous test signal, the first heterogeneous memristor array feeds back and outputs the first heterogeneous test data to the test channel control module. The first heterogeneous test data is sent to the CPLD through the test channel control module. The CPLD sends the received first heterogeneous test data to the first FPGA. The CPLD sends the second heterogeneous test signal to the second heterogeneous memristor array through the test channel control module. After receiving the second heterogeneous test signal, the second heterogeneous test data is fed back and outputs the second heterogeneous test data to the test channel control module. The second heterogeneous test data is sent to the CPLD through the test channel control module. The CPLD sends the received second heterogeneous test data to the second FPGA. The first heterogeneous test signal and the second heterogeneous test signal can be the same test signal. The first heterogeneous memristor array and the second heterogeneous memristor array produced with different memristor materials are tested respectively by the first FPGA and the second FPGA with the same performance, without interfering with each other, and the test efficiency of the memristor array can be effectively improved.

[0090] When only the first FPGA is in place and in a normal health state, the CPLD sends the first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module. After receiving the first heterogeneous test signal, the first heterogeneous memristor array feeds back and outputs the first heterogeneous test data to the test channel control module. After receiving the first heterogeneous test signal, the second heterogeneous memristor array feeds back and outputs the second heterogeneous test data to the test channel control module. The first heterogeneous test data and the second heterogeneous test data are sent to the CPLD through the test channel control module, and the CPLD sends the received first heterogeneous test data and the second heterogeneous test data to the first FPGA.

[0091] When only the second FPGA is in place and in a normal health state, the CPLD sends the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module. After receiving the second heterogeneous test signal, the first heterogeneous memristor array feeds back and outputs the first heterogeneous test data to the test channel control module. After receiving the second heterogeneous test signal, the second heterogeneous memristor array feeds back and outputs the second heterogeneous test data to the test channel control module. The first heterogeneous test data and the second heterogeneous test data are sent to the CPLD through the test channel control module. The CPLD sends the received first heterogeneous test data and the second heterogeneous test data to the second FPGA.

[0092] S173, the first FPGA processes the first heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; In this embodiment, when the first FPGA and the second FPGA are both in place and in normal health, the first FPGA processes the first heterogeneous test data and outputs it to the microprocessor; when only the first FPGA is in place and in normal health, the first FPGA processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor.

[0093] S174, the second FPGA processes the second heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; In this embodiment, when the first FPGA and the second FPGA are both in place and in normal health, the second FPGA processes the second heterogeneous test data and outputs it to the microprocessor; when only the second FPGA is in place and in normal health, the second FPGA processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor.

[0094] The heterogeneous test signal includes a first heterogeneous test signal and a second heterogeneous test signal, the heterogeneous memristor array includes a first heterogeneous memristor array and a second heterogeneous memristor array, the heterogeneous test data includes a first heterogeneous test data and a second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; Step S13 includes: S131, after receiving the same type of test channel opening instruction, the first FPGA and / or the second FPGA generates a first same type test signal and / or a second same type test signal, and outputs it to the merging unit; In this embodiment, when both the first FPGA and the second FPGA are identified, that is, when both the first FPGA and the second FPGA are in place and in normal health, the first FPGA generates a first similar test signal and outputs it to the merging unit after receiving the similar test channel start instruction, and the second FPGA generates a second similar test signal and outputs it to the merging unit after receiving the similar test channel start instruction; if only the first FPGA is in place and in normal health, the first FPGA generates a first similar test signal and outputs it to the merging unit after receiving the similar test channel start instruction; if only the second FPGA is in place and in normal health, the second FPGA generates a second similar test signal and outputs it to the merging unit after receiving the similar test channel start instruction.

[0095] In this embodiment, the first similar test signal and the second similar test signal may be the same similar test signals generated by the first FPGA and the second FPGA having the same performance. By setting the first FPGA and the second FPGA, the test speed and test efficiency of the same type of memristor arrays can be accelerated.

[0096] S132, the merging unit merges the first similar test signal and the second similar test signal and outputs the merged signal to the CPLD, or outputs the first similar test signal or the second similar test signal to the CPLD; In this embodiment, if the merging unit receives the first test signal of the same type and the second test signal of the same type, the first test signal of the same type and the second test signal of the same type are merged and processed and then the merged test signal of the same type is output to the CPLD; if the merging unit only receives the first test signal of the same type or the second test signal of the same type, the first test signal of the same type or the second test signal of the same type is output to the CPLD.

[0097] S133, the CPLD sends the merged similar test signal to each similar memristor array through the test channel control module, or sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receives similar test data of each similar memristor array sent by the test channel control module, and sends multiple similar test data to the merging unit; In this embodiment, if the CPLD receives a merged similar test signal, the CPLD sends the merged similar test signal to each similar memristor array through the test channel control module. After receiving the merged similar test signal, each similar memristor array feeds back and outputs similar test data to the test channel control module, and sends it to the CPLD through the test channel control module. The CPLD receives the similar test data of each similar memristor array sent by the test channel control module, and sends multiple similar test data to the merging unit; if the CPLD receives the first similar test signal or the second similar test signal, the CPLD sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module. After receiving the first similar test signal or the second similar test signal, each similar memristor array feeds back and outputs similar test data to the test channel control module, and sends it to the CPLD through the test channel control module. The CPLD receives the similar test data of each similar memristor array sent by the test channel control module, and sends multiple similar test data to the merging unit.

[0098] S134, after the merging unit merges the multiple test data of the same type, it divides the merged test data of the same type into first test data of the same type and second test data of the same type, sends the first test data of the same type to the first FPGA, sends the second test data of the same type to the second FPGA, or sends the merged test data of the same type to the first FPGA or the second FPGA; In this embodiment, when the first FPGA and the second FPGA are both in place and in a normal health state, the merging unit merges a plurality of similar test data, divides the merged similar test data into first similar test data and second similar test data, sends the first similar test data to the first FPGA, and sends the second similar test data to the second FPGA. By dividing the merged similar test data into first similar test data and second similar test data, and sending the first similar test data to the first FPGA for processing and sending the second similar test data to the second FPGA for processing, the processing speed of the similar test data can be accelerated, thereby effectively improving the test speed and test efficiency of the similar memristor array.

[0099] S135, the first FPGA processes the first test data of the same type and outputs it to the microprocessor, or processes the merged test data of the same type and outputs it to the microprocessor; In this embodiment, if the first FPGA receives the first test data of the same type, the first FPGA processes the first test data of the same type and outputs it to the microprocessor; if the first FPGA receives the merged test data of the same type, the first FPGA processes the merged test data of the same type and outputs it to the microprocessor.

[0100] S136, the second FPGA processes the second test data of the same type and outputs it to the microprocessor, or processes the combined test data of the same type and outputs it to the microprocessor; In this embodiment, if the second FPGA receives the second test data of the same type, the second FPGA processes the second test data of the same type and outputs it to the microprocessor; if the second FPGA receives the merged test data of the same type, the merged test data of the same type is processed and output to the microprocessor.

[0101] Among them, the same type of test signals include a first same type of test signal and a second same type of test signal, and the same type of test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

[0102] As an implementation mode, in the embodiment of the present application, the test channel control module includes: a converter, an amplifier and a test channel control unit; Step S122 includes: S1221, the converter sends the received similar memristor array test mode instruction to the test channel control unit through the amplifier; In this embodiment, after receiving the same type of memristor array test mode instruction sent by the CPLD, the converter sends the same type of memristor array test mode instruction to the test channel control unit through the amplifier.

[0103] S1222, the test channel control unit identifies multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, controls to open similar test channels in the test channel control unit that are connected to the multiple similar memristor arrays, and sends similar test channel opening instructions to the first FPGA and the second FPGA; In this embodiment, after receiving the similar memristor array test mode instruction, the test channel control unit identifies multiple similar memristor arrays. If multiple similar memristor arrays are identified and data communication can be established between the test channel control unit and the multiple similar memristor arrays, the test channel control unit controls the opening of similar test channels corresponding to the multiple similar memristor arrays, and sends similar test channel opening instructions to the first FPGA and the second FPGA.

[0104] Step S162 includes: S1621, the converter sends the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; In this embodiment, after receiving the heterogeneous memristor array test mode instruction sent by the CPLD, the converter sends the heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier.

[0105] S1622. The test channel control unit identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends the heterogeneous test channel opening instruction to the first FPGA and the second FPGA.

[0106] In this embodiment, after receiving the heterogeneous memristor array test mode instruction, the test channel control unit identifies multiple heterogeneous memristor arrays. If multiple heterogeneous memristor arrays are identified and data communication can be established between the test channel control unit and the multiple heterogeneous memristor arrays, the test channel control unit controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends the heterogeneous test channel opening instruction to the first FPGA and the second FPGA.

[0107] As an implementation manner, in the embodiment of the present application, step S172 includes: S1721. The CPLD sends the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; In this embodiment, if the CPLD receives the first heterogeneous test signal and the second heterogeneous test signal, the CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the converter; if the CPLD receives the first heterogeneous test signal or the second heterogeneous test signal, the CPLD sends the first heterogeneous test signal or the second heterogeneous test signal to the converter.

[0108] S1722, the converter performs digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and outputs the converted signal; In this embodiment, the converter performs digital-to-analog conversion on the received first heterogeneous test signal and the second heterogeneous test signal and outputs them to the amplifier, or the converter performs digital-to-analog conversion on the received first heterogeneous test signal or the second heterogeneous test signal and outputs them to the amplifier.

[0109] S1723, the amplifier amplifies the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then outputs the amplified signal; In this embodiment, the amplifier amplifies the received converted first heterogeneous test signal and the converted first heterogeneous test signal and outputs them to the test channel control unit; or, the amplifier amplifies the received converted first heterogeneous test signal or the converted first heterogeneous test signal and outputs them to the test channel control unit.

[0110] S1724, the test channel control unit sends the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively, or sends the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; In this embodiment, the test channel control unit sends the received amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively; or, the test channel control unit sends the received amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array, or, the test channel control unit sends the received amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array.

[0111] S1725, the test channel control unit receives a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; In this embodiment, after the first heterogeneous memristor array receives the amplified first heterogeneous test signal or the amplified second heterogeneous test signal, the first heterogeneous memristor array will feedback output the first heterogeneous test feedback signal to the test channel control unit, and after the second heterogeneous memristor array receives the amplified first heterogeneous test signal or the amplified second heterogeneous test signal, the second heterogeneous memristor array will feedback output the second heterogeneous test feedback signal to the test channel control unit, and the test channel control unit sends the received first heterogeneous test feedback signal and the second heterogeneous test feedback signal to the amplifier.

[0112] S1726, the amplifier amplifies the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then outputs the amplified signals; In this embodiment, the amplifier amplifies the received first heterogeneous test feedback signal and the received second heterogeneous test feedback signal respectively, and outputs the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal to the converter.

[0113] S1727, the converter performs analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converting them into first heterogeneous test data and second heterogeneous test data and outputting them to the CPLD; In this embodiment, the converter performs analog-to-digital conversion on the amplified first heterogeneous test feedback signal, converts it into first heterogeneous test data and outputs it to the CPLD, and the converter performs analog-to-digital conversion on the amplified second heterogeneous test feedback signal, converts it into second heterogeneous test data and outputs it to the CPLD.

[0114] S1728. The CPLD sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; In this embodiment, when the first FPGA and the second FPGA are both in place and in normal health, the CPLD sends the received first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively; when only the first FPGA is in place and in normal health, the CPLD sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA; when only the second FPGA is in place and in normal health, the CPLD sends the first heterogeneous test data and the second heterogeneous test data to the second FPGA.

[0115] Step S133 includes: S1331, the CPLD sends the combined similar test signal to the converter, or sends the first similar test signal or the second similar test signal to the converter; In this embodiment, the CPLD sends the received combined test signal of the same type to the converter, or the CPLD sends the received first test signal of the same type to the converter, or the CPLD sends the received second test signal of the same type to the converter.

[0116] S1332, the converter performs digital-to-analog conversion on the combined similar test signal and outputs it, or performs digital-to-analog conversion on the first similar test signal or the second similar test signal and outputs it; In this embodiment, the converter performs digital-to-analog conversion on the received merged test signal of the same type and outputs it to the amplifier; or, the converter performs digital-to-analog conversion on the received first test signal of the same type and outputs it to the amplifier; or, the converter performs digital-to-analog conversion on the received second test signal of the same type and outputs it to the amplifier.

[0117] S1333, the amplifier amplifies the converted similar test signal and then outputs it, or amplifies the converted first similar test signal or the converted second similar test signal and then outputs it; In this embodiment, the amplifier amplifies the received converted test signal of the same type and outputs it to the test channel control unit; or, the amplifier amplifies the received converted first test signal of the same type and outputs it to the test channel control unit; or, the amplifier amplifies the received converted second test signal of the same type and outputs it to the test channel control unit.

[0118] S1334, the test channel control unit sends the amplified similar test signal to each similar memristor array, or sends the amplified first similar test signal or the amplified second similar test signal to each similar memristor array; In this embodiment, the test channel control unit sends the received amplified similar test signal to each similar memristor array; or, the test channel control unit sends the received amplified first similar test signal to each similar memristor array; or, the test channel control unit sends the received amplified second similar test signal to each similar memristor array.

[0119] S1335, the test channel control unit receives similar test feedback signals output by each similar memristor array; In this embodiment, after receiving the amplified similar test signal or the amplified first similar test signal or the amplified second similar test signal, each similar memristor array feeds back and outputs a similar test feedback signal to the test channel control unit, and the test channel control unit sends the received similar test feedback signals output by each similar memristor array to the amplifier.

[0120] S1336, the amplifier amplifies each test feedback signal of the same type and then outputs it; In this embodiment, the amplifier amplifies each received test feedback signal of the same type, and then outputs each test feedback signal of the same type after the amplifier to the converter.

[0121] S1337, the converter performs analog-to-digital conversion on each amplified similar test feedback signal, converts it into each similar test data and outputs it to the CPLD; In this embodiment, the converter performs analog-to-digital conversion on each amplified test feedback signal of the same type received, converts the signal into each test data of the same type, and then outputs the test data of the same type to the CPLD.

[0122] S1338, CPLD sends each similar test data to the merging unit.

[0123] In this embodiment, the CPLD sends each received test data of the same type to the merging unit.

[0124] As an implementation manner, in the embodiment of the present application, the test start control module further includes a third output encryption interface, and the method further includes: S41, when receiving the memristor array fault analysis instruction, the microprocessor obtains a similar memristor array fault analysis report according to similar test data and a preset similar data range, or obtains a heterogeneous memristor array fault analysis report according to heterogeneous test data and a preset heterogeneous data range, and sends a fault analysis export instruction to the data selector; In this embodiment, if the microprocessor receives a memristor array fault analysis instruction after the microprocessor receives similar test data, the microprocessor obtains a similar memristor array fault analysis report based on the similar test data and a preset similar data range, and sends a fault analysis export instruction to the data selector; if the microprocessor receives a memristor array fault analysis instruction after the microprocessor receives heterogeneous test data, the microprocessor obtains a heterogeneous memristor array fault analysis report based on the heterogeneous test data and a preset heterogeneous data range, and sends a fault analysis export instruction to the data selector.

[0125] In this embodiment, the preset homogeneous data range is a homogeneous data range pre-stored in the microprocessor, and the preset heterogeneous data range is a heterogeneous data range pre-stored in the microprocessor.

[0126] S42, after receiving the fault analysis export instruction, the data selector opens the fault analysis export channel connected to the third output encryption interface, and sends the same type of memristor array fault analysis report or the different type of memristor array fault analysis report to the third output encryption interface; In this embodiment, after receiving the fault analysis export instruction, the data selector opens the fault analysis export channel connected to the third output encryption interface, and sends the fault analysis report of the same type of memristor array to the third output encryption interface; or, after receiving the fault analysis export instruction, the data selector opens the fault analysis export channel connected to the third output encryption interface, and sends the fault analysis report of a different type of memristor array to the third output encryption interface.

[0127] S43, the third output encryption interface encrypts the same type of memristor array fault analysis report or the different type of memristor array fault analysis report and then outputs it.

[0128] In this embodiment, a fourth encryption chip may be integrated in the third output encryption interface. The same type of memristor array fault analysis report is encrypted and outputted through the fourth encryption chip in the third output encryption interface, and can be outputted to an external memory (such as a USB flash drive); Alternatively, the heterogeneous memristor array fault analysis report is encrypted and outputted through the fourth encryption chip in the third output encryption interface, and can be outputted to an external memory (such as a USB flash drive).

[0129] like Figure 2 and Figure 3 As shown, the present application also provides a memristor array test system, including a test start control module, a test control module and a simulator; A test start control module is used to obtain a similar memristor array test file after receiving a similar memristor array test start instruction, and generate a similar memristor array test item list and a similar memristor array test mode instruction according to the similar memristor array test file; A test control module is used to identify the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction. If the simulator and multiple similar memristor arrays are identified, the similar test channels in the test control module corresponding to the multiple similar memristor arrays are controlled to be opened, and a similar test channel opening instruction is sent to the simulator; In this embodiment, the plurality of similar memristor arrays may be N similar memristor arrays, including similar memristor array 1 to similar memristor array N, where N is a positive integer greater than 1.

[0130] The simulator is used to send similar test signals to multiple similar memristor arrays through a test control module after receiving a similar test channel opening instruction, receive similar test data of multiple similar memristor arrays, process and output; The test start control module is further used to obtain a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and a similar memristor array test item list; The test start control module is further used to obtain a heterogeneous memristor array test file after receiving a heterogeneous memristor array test start instruction, and generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; The test control module is also used to identify the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If the simulator and multiple heterogeneous memristor arrays are identified, the test control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator; In this embodiment, the plurality of heterogeneous memristor arrays may be N heterogeneous memristor arrays, namely, including heterogeneous memristor array 1 to heterogeneous memristor array N, where N is a positive integer greater than 1.

[0131] The simulator is further used to send a heterogeneous test signal to a plurality of heterogeneous memristor arrays through a test control module after receiving a heterogeneous test channel opening instruction, receive heterogeneous test data of the plurality of heterogeneous memristor arrays, process and output the data; The test start control module is also used to obtain a heterogeneous memristor array performance comparison test report based on a plurality of processed heterogeneous test data and a heterogeneous memristor array test item list.

[0132] like Figure 4 and Figure 5 As shown, as an implementation mode, in the embodiment of the present application, the test control module includes a test control processing module and a test channel control module; A test control processing module is used to identify the simulator according to the same type of memristor array test mode instruction, and if the simulator is identified, the same type of memristor array test mode instruction is sent to the test channel control module; A test channel control module is used to identify multiple similar memristor arrays according to a similar memristor array test mode instruction. If multiple similar memristor arrays are identified, the similar test channels in the test channel control module corresponding to the multiple similar memristor arrays are controlled to be opened, and a similar test channel opening instruction is sent to the simulator; The test control processing module is further used to identify the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, send the heterogeneous memristor array test mode instruction to the test channel control module; The test channel control module is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator.

[0133] like Figure 6 As shown, as an implementation mode, in the embodiment of the present application, the test start control module includes a microprocessor, a data selector and an input encryption interface; The microprocessor is used to send a similar data import instruction to the data selector after receiving a similar memristor array test start instruction; In this embodiment, the microprocessor transmits the same type of data import instruction to the data selector via the instruction signal line.

[0134] A data selector, for opening a data import channel connected to the input encryption interface after receiving a similar data import instruction, and sending the similar data import instruction to the input encryption interface; An input encryption interface is used to obtain the same type of memristor array test file and encrypt it before outputting it to the data selector after receiving the same type of data import instruction; The data selector is also used to send the received encrypted test file of the same type of memristor array to the microprocessor; In this embodiment, the data selector sends the received encrypted memristor array test file of the same type to the microprocessor through the IO port link.

[0135] The microprocessor is further used to generate a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; The microprocessor is further used to send a heterogeneous data import instruction to the data selector after receiving a heterogeneous memristor array test start instruction; The data selector is further used to open a data import channel connected to the input encryption interface after receiving the heterogeneous data import instruction, and send the heterogeneous data import instruction to the input encryption interface; The input encryption interface is also used to obtain the heterogeneous memristor array test file after receiving the heterogeneous data import instruction and output it to the data selector after encryption processing; The data selector is further used to send the received encrypted heterogeneous memristor array test file to the microprocessor; In this embodiment, the data selector sends the received encrypted heterogeneous memristor array test file to the microprocessor through the IO port link.

[0136] The microprocessor is also used to generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

[0137] like Figure 6 As shown, as an implementation mode, in the embodiment of the present application, the test start control module further includes a data storage and a first output encryption interface and a second output encryption interface; The microprocessor is also used to store the performance comparison test report of similar memristor arrays in the data storage device, and send the similar data export instruction to the data selector; The data selector is further used to open a similar data export channel connected to the first output encryption interface after receiving the similar data export instruction, and send the similar data export instruction to the first output encryption interface; A first output encryption interface is used to encrypt and output a performance comparison test report of similar memristor arrays after receiving a similar data export instruction; The microprocessor is further used to store the heterogeneous memristor array performance comparison test report in the data storage device and send the heterogeneous data export instruction to the data selector; The data selector is further used to open a heterogeneous data export channel connected to the second output encryption interface after receiving the heterogeneous data export instruction, and send the heterogeneous data export instruction to the second output encryption interface; The second output encryption interface is used to encrypt and output the heterogeneous memristor array performance comparison test report after receiving the heterogeneous data export instruction.

[0138] like Figure 7 and Figure 8 As shown, as an implementation mode, in the embodiment of the present application, the simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; MCU, used for generating and outputting a first identification instruction according to the heterogeneous memristor array test mode instruction; A first FPGA identification unit is used to identify the first FPGA according to the first identification instruction, and when the first FPGA is identified, send a first identification success signal to the MCU, and when the first FPGA is not identified, send a first identification failure signal to the MCU; A second FPGA identification unit is used to identify the second FPGA according to the first identification instruction, and when the second FPGA is identified, send a second identification success signal to the MCU, and when the second FPGA is not identified, send a second identification failure signal to the MCU; The MCU is further configured to send a first control signal to the first switch and the second switch after receiving the first recognition success signal and the second recognition success signal, and send a heterogeneous memristor array test mode instruction to the CPLD; A first switch, used to switch to a channel between the first FPGA and the CPLD after receiving a first control signal; A second switch, used to switch to a channel between the second FPGA and the CPLD after receiving the first control signal; The MCU is further used to control the second FPGA or the first FPGA to be turned off after receiving the first recognition success signal or the second recognition success signal, send a second control signal to the first switch or the second switch, and send a heterogeneous memristor array test mode instruction to the CPLD; The first switch is further used to switch to the channel between the first FPGA and the CPLD after receiving the second control signal; The second switch is further used to switch to the channel between the second FPGA and the CPLD after receiving the second control signal; The CPLD is used for sending the received heterogeneous memristor array test mode instruction to the test channel control module.

[0139] like Figure 7 and Figure 8 As shown, as an implementation mode, in the embodiment of the present application, the test control processing module further includes a merging unit; The MCU is further used to generate and output a second identification instruction according to the similar memristor array test mode instruction; The first FPGA identification unit is further used to identify the first FPGA according to the second identification instruction, and when the first FPGA is identified, send a third identification success signal to the MCU, and when the first FPGA is not identified, send a third identification failure signal to the MCU; The second FPGA identification unit is further used to identify the second FPGA according to the second identification instruction, and when the second FPGA is identified, send a fourth identification success signal to the MCU, and when the second FPGA is not identified, send a fourth identification failure signal to the MCU; The MCU is further configured to send a third control signal to the first switch and the second switch after receiving the third recognition success signal and the fourth recognition success signal, and send a similar memristor array test mode instruction to the CPLD; The first switch is further used to switch to the channel between the first FPGA and the merging unit after receiving the third control signal; The second switch is further used to switch to the channel between the second FPGA and the merging unit after receiving the third control signal; The MCU is further configured to control closing the second FPGA or the first FPGA after receiving the third recognition success signal or the fourth recognition success signal, send a fourth control signal to the first switch or the second switch, and send a similar memristor array test mode instruction to the CPLD; The first switch is further used to switch to the channel between the first FPGA and the merging unit after receiving the fourth control signal; The second switch is further used to switch to the channel between the second FPGA and the merging unit after receiving the fourth control signal; The CPLD is also used to send the received similar memristor array test mode instruction to the test channel control module.

[0140] like Figure 7 and Figure 8 As shown, as an implementation mode, in the embodiment of the present application, The first FPGA is used to generate a first heterogeneous test signal after receiving a heterogeneous test channel start instruction, and output it to the CPLD; The second FPGA is used to generate a second heterogeneous test signal after receiving a heterogeneous test channel start instruction, and output it to the CPLD; The CPLD is further used to send the first heterogeneous test signal and / or the second heterogeneous test signal to each heterogeneous memristor array through the test channel control module; The CPLD is further used to send the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or send the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The first FPGA is further used to process the first heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; The second FPGA is further used to process the second heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; The heterogeneous test signal includes a first heterogeneous test signal and a second heterogeneous test signal, the heterogeneous memristor array includes a first heterogeneous memristor array and a second heterogeneous memristor array, the heterogeneous test data includes a first heterogeneous test data and a second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; In this embodiment, the first heterogeneous memristor array and the second heterogeneous memristor array are memristor arrays produced using the same development process but different memristor materials. The first heterogeneous memristor array and the second heterogeneous memristor array may each include one heterogeneous memristor array or a plurality of heterogeneous memristor arrays.

[0141] The first FPGA is further used to generate a first similar test signal after receiving a similar test channel opening instruction, and output it to the merging unit; The second FPGA is further used to generate a second similar test signal after receiving a similar test channel opening instruction, and output it to the merging unit; A merging unit, used for merging the first test signal of the same type and the second test signal of the same type and then outputting the combined signal to the CPLD, or outputting the first test signal of the same type or the second test signal of the same type to the CPLD; The CPLD is further used to send the merged similar test signal to each similar memristor array through the test channel control module, or send the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receive similar test data of each similar memristor array sent by the test channel control module, and send multiple similar test data to the merging unit; The merging unit is further used to merge multiple test data of the same type, and then divide the merged test data of the same type into first test data of the same type and second test data of the same type, send the first test data of the same type to the first FPGA, send the second test data of the same type to the second FPGA, or send the merged test data of the same type to the first FPGA or the second FPGA; The first FPGA is further used to process the first test data of the same type and output it to the microprocessor, or process the merged test data of the same type and output it to the microprocessor; The second FPGA is further used to process the second test data of the same type and output it to the microprocessor, or process the combined test data of the same type and output it to the microprocessor; Among them, the same type of test signals include a first same type of test signal and a second same type of test signal, and the same type of test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

[0142] like Fig. 9 and Fig.10 As shown, as an implementation mode, in the embodiment of the present application, the test channel control module includes: a converter, an amplifier and a test channel control unit; A converter, used for sending the received test mode instruction of the same type of memristor array to the test channel control unit through the amplifier; A test channel control unit, used to identify multiple similar memristor arrays according to a similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, control the opening of similar test channels in the test channel control unit that are connected to the multiple similar memristor arrays, and send a similar test channel opening instruction to the first FPGA and the second FPGA; The converter is further used to send the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; The test channel control unit is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and the heterogeneous test channel opening instruction is sent to the first FPGA and the second FPGA.

[0143] like Fig. 9 and Fig.10 As shown, as an implementation mode, in the embodiment of the present application, The CPLD is further configured to send the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; A converter, used for performing digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and then outputting the converted signal; An amplifier, used for amplifying the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then outputting it; In this embodiment, a plurality of amplifiers are provided, and the specific number of the amplifiers may be the same as the number of the same type of memristor arrays and different type of memristor arrays to be tested.

[0144] A test channel control unit, configured to send the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array, respectively, or send the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; The test channel control unit is further used to receive a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; The amplifier is further used to amplify the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then output them; The converter is further used to perform analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converting them into first heterogeneous test data and second heterogeneous test data and outputting them to the CPLD; The CPLD is further used to send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or to send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The CPLD is further used to send the combined similar test signal to the converter, or send the first similar test signal or the second similar test signal to the converter; The converter is further used to perform digital-to-analog conversion on the combined similar test signal and then output it, or to perform digital-to-analog conversion on the first similar test signal or the second similar test signal and then output it; The amplifier is further used to amplify the converted similar test signal and then output it, or to amplify the converted first similar test signal or the converted second similar test signal and then output it; The test channel control unit is further used to send the amplified similar test signal to each similar memristor array, or send the amplified first similar test signal or the amplified second similar test signal to each similar memristor array; The test channel control unit is also used to receive similar test feedback signals output by each similar memristor array; The amplifier is also used to amplify and output various test feedback signals of the same type; The converter is also used to perform analog-to-digital conversion on each amplified test feedback signal of the same type, and convert it into each test data of the same type and output it to the CPLD; The CPLD is also used to send each similar test data to the merging unit.

[0145] like Figure 6 As shown, as an implementation mode, in the embodiment of the present application, the test start control module further includes a third output encryption interface; The microprocessor is further used to obtain a similar memristor array fault analysis report based on similar test data and a preset similar data range, or obtain a heterogeneous memristor array fault analysis report based on heterogeneous test data and a preset heterogeneous data range, and send a fault analysis export instruction to the data selector when receiving the memristor array fault analysis instruction; The data selector is further used to open a fault analysis export channel connected to the third output encryption interface after receiving the fault analysis export instruction, and send a similar memristor array fault analysis report or a heterogeneous memristor array fault analysis report to the third output encryption interface; The third output encryption interface is used to encrypt and output the same type of memristor array fault analysis report or the different type of memristor array fault analysis report.

[0146] In an embodiment of the present application, the memristor array testing system also includes a fixing seat for fixing multiple similar memristor arrays or multiple heterogeneous memristor arrays, and a status indicator light connected to the multiple similar memristor arrays or multiple heterogeneous memristor arrays. When the similar memristor arrays or heterogeneous memristor arrays are being tested, the corresponding connected status indicator light will light up yellow. The fixing seat and the status indicator light are not shown in the accompanying drawings.

[0147] It should be understood that the use of "system", "device", "unit" and / or "module" in this application is only a method for distinguishing different components, elements, parts, parts or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.

[0148] The embodiments in this specification are described in a progressive manner, and each embodiment focuses on the For the differences between other embodiments, the same or similar parts between the embodiments may be referred to each other.

[0149] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memristor array testing method, characterized in that: Applied to a memristor array test system, the test system includes a test start control module, a test control module and a simulator, and the method includes: After receiving the similar memristor array test start instruction, the test start control module obtains the similar memristor array test file, and generates the similar memristor array test item list and the similar memristor array test mode instruction according to the similar memristor array test file; The test control module identifies the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, controls to open similar test channels in the test control module that are connected to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator; After receiving the similar test channel opening instruction, the simulator sends similar test signals to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays, processes them and outputs them; The test start control module obtains a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list; After receiving the heterogeneous memristor array test start instruction, the test start control module obtains a heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; The test control module identifies the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, controls to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator; After receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the plurality of heterogeneous memristor arrays, processes the data and outputs the data; The test start control module obtains a heterogeneous memristor array performance comparison test report according to a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list.

2. The testing method according to claim 1, characterized in that: The test control module includes Test control processing module and test channel control module; The test control module identifies the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, controls to open similar test channels in the test control module that are connected to the multiple similar memristor arrays, and sends a similar test channel opening instruction to the simulator, including: The test control processing module identifies the simulator according to the similar memristor array test mode instruction, and if the simulator is identified, sends the similar memristor array test mode instruction to the test channel control module; The test channel control module identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control module corresponding to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the simulator; The test control module identifies the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, controls to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator, including: The test control processing module identifies the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, sends the heterogeneous memristor array test mode instruction to the test channel control module; The test channel control module identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator.

3. The testing method according to claim 2, characterized in that: The test start control module includes a microprocessor, a data selector and an input encryption interface; After receiving the similar memristor array test start instruction, the test start control module obtains the similar memristor array test file, and generates the similar memristor array test item list and the similar memristor array test mode instruction according to the similar memristor array test file, including: After receiving the same type of memristor array test start instruction, the microprocessor sends the same type of data import instruction to the data selector; After receiving the same type of data import instruction, the data selector opens a data import channel connected to the input encryption interface, and sends the same type of data import instruction to the input encryption interface; After receiving the same type of data import instruction, the input encryption interface obtains the same type of memristor array test file and encrypts it before outputting it to the data selector; The data selector sends the received encrypted memristor array test file of the same type to the microprocessor; The microprocessor generates a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; After receiving the heterogeneous memristor array test start instruction, the test start control module obtains the heterogeneous memristor array test file, and generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file, including: After receiving the heterogeneous memristor array test start instruction, the microprocessor sends a heterogeneous data import instruction to the data selector; After receiving the heterogeneous data import instruction, the data selector opens a data import channel connected to the input encryption interface and sends the heterogeneous data import instruction to the input encryption interface; After receiving the heterogeneous data import instruction, the input encryption interface obtains the heterogeneous memristor array test file and performs encryption processing and then outputs it to the data selector; The data selector sends the received encrypted heterogeneous memristor array test file to the microprocessor; The microprocessor generates a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

4. The testing method according to claim 3, characterized in that: The test start control module also includes a data storage and a first output encryption interface and a second output encryption interface; After the test start control module obtains a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list, the method further includes: The microprocessor stores the performance comparison test report of the same type of memristor arrays in the data storage device, and sends a similar type of data export instruction to the data selector; After receiving the same type of data export instruction, the data selector opens a same type of data export channel connected to the first output encryption interface, and sends the same type of data export instruction to the first output encryption interface; After receiving the same type of data export instruction, the first output encryption interface encrypts and outputs the same type of memristor array performance comparison test report; After the test start control module obtains a heterogeneous memristor array performance comparison test report according to a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list, the method further includes: The microprocessor stores the heterogeneous memristor array performance comparison test report in the data storage device, and sends a heterogeneous data export instruction to the data selector; After receiving the heterogeneous data export instruction, the data selector opens a heterogeneous data export channel connected to the second output encryption interface, and sends the heterogeneous data export instruction to the second output encryption interface; After receiving the heterogeneous data export instruction, the second output encryption interface encrypts and outputs the heterogeneous memristor array performance comparison test report.

5. The testing method according to claim 3, characterized in that: The simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; The test control processing module identifies the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, sends the heterogeneous memristor array test mode instruction to the test channel control module, including: The MCU generates and outputs a first identification instruction according to the heterogeneous memristor array test mode instruction; The first FPGA identification unit identifies the first FPGA according to the first identification instruction, and sends a first identification success signal to the MCU when the first FPGA is identified, and sends a first identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit identifies the second FPGA according to the first identification instruction, and sends a second identification success signal to the MCU when the second FPGA is identified, and sends a second identification failure signal to the MCU when the second FPGA is not identified; After receiving the first recognition success signal and the second recognition success signal, the MCU sends a first control signal to the first switch and the second switch, and sends the heterogeneous memristor array test mode instruction to the CPLD; or, after receiving the first recognition success signal or the second recognition success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a second control signal to the first switch or the second switch, and sends the heterogeneous memristor array test mode instruction to the CPLD; After receiving the first control signal, the first switch switches to the channel between the first FPGA and the CPLD, or after receiving the second control signal, the first switch switches to the channel between the first FPGA and the CPLD; After receiving the first control signal, the second switch switches to the channel between the second FPGA and the CPLD, or after receiving the second control signal, the second switch switches to the channel between the second FPGA and the CPLD; The CPLD sends the received heterogeneous memristor array test mode instruction to the test channel control module.

6. The testing method according to claim 5, characterized in that: The test control processing module also includes a merging unit; The test control processing module identifies the simulator according to the similar memristor array test mode instruction, and if the simulator is identified, sends the similar memristor array test mode instruction to the test channel control module, including: The MCU generates and outputs a second identification instruction according to the same type of memristor array test mode instruction; The first FPGA identification unit identifies the first FPGA according to the second identification instruction, and sends a third identification success signal to the MCU when the first FPGA is identified, and sends a third identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit identifies the second FPGA according to the second identification instruction, and sends a fourth identification success signal to the MCU when the second FPGA is identified, and sends a fourth identification failure signal to the MCU when the second FPGA is not identified; After receiving the third recognition success signal and the fourth recognition success signal, the MCU sends a third control signal to the first switch and the second switch, and sends the same type of memristor array test mode instruction to the CPLD; After receiving the third control signal, the first switch switches to the channel between the first FPGA and the merging unit; After receiving the third control signal, the second switch switches to the channel between the second FPGA and the merging unit; After receiving the third recognition success signal or the fourth recognition success signal, the MCU controls to turn off the second FPGA or the first FPGA, sends a fourth control signal to the first switch or the second switch, and sends the same type of memristor array test mode instruction to the CPLD; After receiving the fourth control signal, the first switch switches to the channel between the first FPGA and the merging unit, or the second switch switches to the channel between the second FPGA and the merging unit after receiving the fourth control signal; The CPLD sends the received similar memristor array test mode instruction to the test channel control module.

7. The testing method according to claim 6, characterized in that: After receiving the heterogeneous test channel opening instruction, the simulator sends a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module, receives the heterogeneous test data of the plurality of heterogeneous memristor arrays, processes and outputs the data, including: After receiving the heterogeneous test channel start instruction, the first FPGA and / or the second FPGA generates a first heterogeneous test signal and / or a second heterogeneous test signal, and outputs the signal to the CPLD; The CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The first FPGA processes the first heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; The second FPGA processes the second heterogeneous test data and outputs it to the microprocessor, or processes the first heterogeneous test data and the second heterogeneous test data and outputs them to the microprocessor; Wherein, the heterogeneous test signal includes the first heterogeneous test signal and the second heterogeneous test signal, the heterogeneous memristor array includes the first heterogeneous memristor array and the second heterogeneous memristor array, the heterogeneous test data includes the first heterogeneous test data and the second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; After receiving the similar test channel opening instruction, the simulator sends similar test signals to the multiple similar memristor arrays through the test control module, receives similar test data of the multiple similar memristor arrays, processes and outputs the data, including: After receiving the similar test channel opening instruction, the first FPGA and / or the second FPGA generates a first similar test signal and / or a second similar test signal, and outputs the signal to the merging unit; The merging unit merges the first similar test signal and the second similar test signal and then outputs the merged signal to the CPLD, or outputs the first similar test signal or the second similar test signal to the CPLD; The CPLD sends the merged similar test signal to each similar memristor array through the test channel control module, or sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receives similar test data of each similar memristor array sent by the test channel control module, and sends a plurality of similar test data to the merging unit; After the merging unit merges the plurality of the same type of test data, the merged same type of test data is divided into first same type of test data and second same type of test data, the first same type of test data is sent to the first FPGA, the second same type of test data is sent to the second FPGA, or the merged same type of test data is sent to the first FPGA or the second FPGA; The first FPGA processes the first test data of the same type and outputs it to the microprocessor, or processes the merged test data of the same type and outputs it to the microprocessor; The second FPGA processes the second test data of the same type and outputs it to the microprocessor, or processes the merged test data of the same type and outputs it to the microprocessor; Among them, the similar test signals include the first similar test signal and the second similar test signal, and the similar test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

8. The testing method according to claim 7, characterized in that: The test channel control module includes: a converter, an amplifier and a test channel control unit; The test channel control module identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control module that are connected to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the simulator, including: The converter sends the received test mode instruction of the same type of memristor array to the test channel control unit through the amplifier; The test channel control unit identifies a plurality of similar memristor arrays according to the similar memristor array test mode instruction, and if a plurality of similar memristor arrays are identified, controls opening of similar test channels in the test channel control unit that are connected to the plurality of similar memristor arrays, and sends a similar test channel opening instruction to the first FPGA and the second FPGA; The test channel control module identifies a plurality of heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if a plurality of the heterogeneous memristor arrays are identified, controls opening of the heterogeneous test channels in the test channel control module corresponding to the plurality of the heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the simulator, including: The converter sends the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; The test channel control unit identifies multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit controls the opening of the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and sends a heterogeneous test channel opening instruction to the first FPGA and the second FPGA.

9. The testing method according to claim 8, characterized in that: The CPLD sends the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receives the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA, including: The CPLD sends the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; The converter performs digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and then outputs the converted signal; The amplifier amplifies the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then outputs it; The test channel control unit sends the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array, respectively, or sends the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; The test channel control unit receives a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; The amplifier amplifies the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then outputs the amplified signals; The converter performs analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converts them into first heterogeneous test data and second heterogeneous test data, and outputs them to the CPLD; The CPLD sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or sends the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The CPLD sends the merged similar test signal to each similar memristor array through the test channel control module, or sends the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receives similar test data of each similar memristor array sent by the test channel control module, and sends a plurality of similar test data to the merging unit, including: The CPLD sends the combined similar test signal to the converter, or sends the first similar test signal or the second similar test signal to the converter; The converter performs digital-to-analog conversion on the combined similar test signal and outputs it, or performs digital-to-analog conversion on the first similar test signal or the second similar test signal and outputs it; The amplifier amplifies the converted similar test signal and then outputs it, or amplifies the converted first similar test signal or the converted second similar test signal and then outputs it; The test channel control unit sends the amplified similar test signal to each of the similar memristor arrays, or sends the amplified first similar test signal or the amplified second similar test signal to each of the similar memristor arrays; The test channel control unit receives the same type of test feedback signals output by each of the same type of memristor arrays; The amplifier amplifies each of the test feedback signals of the same type and then outputs the amplified signals; The converter performs analog-to-digital conversion on each amplified test feedback signal of the same type, converts the signal into test data of the same type and outputs the data to the CPLD; The CPLD sends each of the same type of test data to the merging unit.

10. The testing method according to any one of claims 4 to 9, characterized in that: The test start control module further includes a third output encryption interface, and the method further includes: When receiving the memristor array fault analysis instruction, the microprocessor obtains a similar memristor array fault analysis report according to the similar test data and the preset similar data range, or obtains a heterogeneous memristor array fault analysis report according to the heterogeneous test data and the preset heterogeneous data range, and sends a fault analysis export instruction to the data selector; After receiving the fault analysis export instruction, the data selector opens a fault analysis export channel connected to the third output encryption interface, and sends the same type of memristor array fault analysis report or the different type of memristor array fault analysis report to the third output encryption interface; The third output encryption interface encrypts the same type of memristor array fault analysis report or the different type of memristor array fault analysis report and then outputs it.

11. A memristor array testing system, characterized in that: It includes a test start control module, a test control module and a simulator; The test start control module is used to obtain a similar memristor array test file after receiving a similar memristor array test start instruction, and generate a similar memristor array test item list and a similar memristor array test mode instruction according to the similar memristor array test file; The test control module is used to identify the simulator and multiple similar memristor arrays according to the similar memristor array test mode instruction, and if the simulator and multiple similar memristor arrays are identified, control to open the similar test channels in the test control module that are connected to the multiple similar memristor arrays, and send a similar test channel opening instruction to the simulator; The simulator is used to send similar test signals to the plurality of similar memristor arrays through the test control module after receiving the similar test channel opening instruction, receive similar test data of the plurality of similar memristor arrays, process and output; The test start control module is further used to obtain a performance comparison test report of similar memristor arrays according to a plurality of processed similar test data and the similar memristor array test item list; The test start control module is further used to obtain a heterogeneous memristor array test file after receiving a heterogeneous memristor array test start instruction, and generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the heterogeneous memristor array test file; The test control module is also used to identify the simulator and multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction, and if the simulator and multiple heterogeneous memristor arrays are identified, control to open the heterogeneous test channels in the test control module that are connected to the multiple heterogeneous memristor arrays, and send a heterogeneous test channel opening instruction to the simulator; The simulator is further used to send a heterogeneous test signal to the plurality of heterogeneous memristor arrays through the test control module after receiving the heterogeneous test channel start instruction, receive the heterogeneous test data of the plurality of heterogeneous memristor arrays, process the data and output the data; The test start control module is further used to obtain a heterogeneous memristor array performance comparison test report based on a plurality of processed heterogeneous test data and the heterogeneous memristor array test item list.

12. The test system according to claim 11, characterized in that: The test control module includes a test control processing module and a test channel control module; The test control processing module is used to identify the simulator according to the same type of memristor array test mode instruction, and if the simulator is identified, send the same type of memristor array test mode instruction to the test channel control module; The test channel control module is used to identify multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, control to open the similar test channels in the test channel control module that are connected to the multiple similar memristor arrays, and send a similar test channel opening instruction to the simulator; The test control processing module is further used to identify the simulator according to the heterogeneous memristor array test mode instruction, and if the simulator is identified, send the heterogeneous memristor array test mode instruction to the test channel control module; The test channel control module is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control module is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the simulator.

13. The test system according to claim 12, characterized in that: The test start control module includes a microprocessor, a data selector and an input encryption interface; The microprocessor is used to send a similar data import instruction to the data selector after receiving a similar memristor array test start instruction; The data selector is used to open the data import channel connected to the input encryption interface after receiving the same type of data import instruction, and send the same type of data import instruction to the input encryption interface; The input encryption interface is used to obtain the same type of memristor array test file and encrypt and output it to the data selector after receiving the same type of data import instruction; The data selector is further used to send the received encrypted memristor array test file of the same type to the microprocessor; The microprocessor is further used to generate a similar memristor array test item list and a similar memristor array test mode instruction according to the encrypted similar memristor array test file; The microprocessor is further configured to send a heterogeneous data import instruction to the data selector after receiving a heterogeneous memristor array test start instruction; The data selector is further used to open a data import channel connected to the input encryption interface after receiving the heterogeneous data import instruction, and send the heterogeneous data import instruction to the input encryption interface; The input encryption interface is further used to obtain the heterogeneous memristor array test file after receiving the heterogeneous data import instruction and output it to the data selector after encryption processing; The data selector is further used to send the received encrypted heterogeneous memristor array test file to the microprocessor; The microprocessor is also used to generate a heterogeneous memristor array test item list and a heterogeneous memristor array test mode instruction according to the encrypted heterogeneous memristor array test file.

14. The test system according to claim 13, characterized in that: The test start control module also includes a data storage and a first output encryption interface and a second output encryption interface; The microprocessor is further used to store the performance comparison test report of the same type of memristor arrays in the data storage device, and send a similar type of data export instruction to the data selector; The data selector is further configured to, after receiving the same type of data export instruction, open a same type of data export channel connected to the first output encryption interface, and send the same type of data export instruction to the first output encryption interface; The first output encryption interface is used to encrypt and output the performance comparison test report of the same type of memristor array after receiving the same type of data export instruction; The microprocessor is further used to store the heterogeneous memristor array performance comparison test report in the data storage device, and send a heterogeneous data export instruction to the data selector; The data selector is further configured to, after receiving the heterogeneous data export instruction, open a heterogeneous data export channel connected to the second output encryption interface, and send the heterogeneous data export instruction to the second output encryption interface; The second output encryption interface is used to encrypt and output the heterogeneous memristor array performance comparison test report after receiving the heterogeneous data export instruction.

15. The test system according to claim 13, characterized in that: The simulator includes a first FPGA and a second FPGA, and the test control processing module includes a microcontroller unit MCU, a first FPGA identification unit, a second FPGA identification unit, a first switch, a second switch and a complex programmable logic device CPLD; The MCU is used to generate and output a first identification instruction according to the heterogeneous memristor array test mode instruction; The first FPGA identification unit is used to identify the first FPGA according to the first identification instruction, and send a first identification success signal to the MCU when the first FPGA is identified, and send a first identification failure signal to the MCU when the first FPGA is not identified; The second FPGA identification unit is used to identify the second FPGA according to the first identification instruction, and when the second FPGA is identified, send a second identification success signal to the MCU; when the second FPGA is not identified, send a second identification failure signal to the MCU; The MCU is further configured to send a first control signal to the first switch and the second switch after receiving the first recognition success signal and the second recognition success signal, and send the heterogeneous memristor array test mode instruction to the CPLD; The first switch is used to switch to the channel between the first FPGA and the CPLD after receiving the first control signal; The second switch is used to switch to the channel between the second FPGA and the CPLD after receiving the first control signal; The MCU is further configured to control closing the second FPGA or the first FPGA after receiving the first recognition success signal or the second recognition success signal, send a second control signal to the first switch or the second switch, and send the heterogeneous memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the CPLD after receiving the second control signal; The second switch is further used to switch to the channel between the second FPGA and the CPLD after receiving the second control signal; The CPLD is used to send the received heterogeneous memristor array test mode instruction to the test channel control module.

16. The test system according to claim 15, characterized in that: The test control processing module also includes a merging unit; The MCU is further used to generate and output a second identification instruction according to the similar memristor array test mode instruction; The first FPGA identification unit is further configured to identify the first FPGA according to the second identification instruction, and when the first FPGA is identified, send a third identification success signal to the MCU, and when the first FPGA is not identified, send a third identification failure signal to the MCU; The second FPGA identification unit is further used to identify the second FPGA according to the second identification instruction, and when the second FPGA is identified, send a fourth identification success signal to the MCU, and when the second FPGA is not identified, send a fourth identification failure signal to the MCU; The MCU is further configured to send a third control signal to the first switch and the second switch after receiving the third recognition success signal and the fourth recognition success signal, and send the same type of memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the merging unit after receiving the third control signal; The second switch is further configured to switch to a channel between the second FPGA and the merging unit after receiving the third control signal; The MCU is further configured to control the second FPGA or the first FPGA to be turned off after receiving the third recognition success signal or the fourth recognition success signal, send a fourth control signal to the first switch or the second switch, and send the same type of memristor array test mode instruction to the CPLD; The first switch is further configured to switch to a channel between the first FPGA and the merging unit after receiving the fourth control signal; The second switch is further configured to switch to a channel between the second FPGA and the merging unit after receiving the fourth control signal; The CPLD is also used to send the received similar memristor array test mode instruction to the test channel control module.

17. The test system according to claim 16, characterized in that: The first FPGA is used to generate a first heterogeneous test signal after receiving the heterogeneous test channel start instruction, and output it to the CPLD; The second FPGA is used to generate a second heterogeneous test signal after receiving the heterogeneous test channel start instruction, and output it to the CPLD; The CPLD is further used to send the first heterogeneous test signal and / or the second heterogeneous test signal to each of the heterogeneous memristor arrays through the test channel control module; The CPLD is further used to send the first heterogeneous test signal and the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or send the first heterogeneous test signal or the second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array through the test channel control module, receive the first heterogeneous test data of the first heterogeneous memristor array and the second heterogeneous test data of the second heterogeneous memristor array sent by the test channel control module, and send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The first FPGA is further used to process the first heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; The second FPGA is further used to process the second heterogeneous test data and output it to the microprocessor, or process the first heterogeneous test data and the second heterogeneous test data and output them to the microprocessor; Wherein, the heterogeneous test signal includes the first heterogeneous test signal and the second heterogeneous test signal, the heterogeneous memristor array includes the first heterogeneous memristor array and the second heterogeneous memristor array, the heterogeneous test data includes the first heterogeneous test data and the second heterogeneous test data, and the heterogeneous test signal is a high-frequency pulse signal and / or a low-frequency pulse signal and / or an alternating current signal and / or a direct current signal; The first FPGA is further configured to generate a first similar test signal after receiving the similar test channel opening instruction, and output the signal to the merging unit; The second FPGA is further used to generate a second similar test signal after receiving the similar test channel opening instruction, and output it to the merging unit; The merging unit is used to merge the first similar test signal and the second similar test signal and then output them to the CPLD, or to output the first similar test signal or the second similar test signal to the CPLD; The CPLD is further used to send the merged similar test signal to each similar memristor array through the test channel control module, or send the first similar test signal or the second similar test signal to each similar memristor array through the test channel control module, receive similar test data of each similar memristor array sent by the test channel control module, and send a plurality of similar test data to the merging unit; The merging unit is further used to merge the plurality of the same type of test data, and then divide the merged same type of test data into first same type of test data and second same type of test data, send the first same type of test data to the first FPGA, send the second same type of test data to the second FPGA, or send the merged same type of test data to the first FPGA or the second FPGA; The first FPGA is further used to process the first test data of the same type and output it to the microprocessor, or process the merged test data of the same type and output it to the microprocessor; The second FPGA is further used to process the second similar test data and output it to the microprocessor, or process the merged similar test data and output it to the microprocessor; Among them, the similar test signals include the first similar test signal and the second similar test signal, and the similar test signals are high-frequency pulse signals and / or low-frequency pulse signals and / or alternating current signals and / or direct current signals.

18. The test system according to claim 17, characterized in that: The test channel control module includes: a converter, an amplifier and a test channel control unit; The converter is used to send the received test mode instruction of the same type of memristor array to the test channel control unit through the amplifier; The test channel control unit is used to identify multiple similar memristor arrays according to the similar memristor array test mode instruction, and if multiple similar memristor arrays are identified, control to open similar test channels in the test channel control unit that are connected to the multiple similar memristor arrays, and send similar test channel opening instructions to the first FPGA and the second FPGA; The converter is further used to send the received heterogeneous memristor array test mode instruction to the test channel control unit through the amplifier; The test channel control unit is also used to identify multiple heterogeneous memristor arrays according to the heterogeneous memristor array test mode instruction. If multiple heterogeneous memristor arrays are identified, the test channel control unit is controlled to open the heterogeneous test channels corresponding to the multiple heterogeneous memristor arrays, and a heterogeneous test channel opening instruction is sent to the first FPGA and the second FPGA.

19. The test system according to claim 18, characterized in that: The CPLD is further used to send the first heterogeneous test signal and / or the second heterogeneous test signal to the converter; The converter is used for performing digital-to-analog conversion on the first heterogeneous test signal and / or the second heterogeneous test signal and then outputting the converted signal; The amplifier is used to amplify the converted first heterogeneous test signal and / or the converted first heterogeneous test signal and then output it; The test channel control unit is used to send the amplified first heterogeneous test signal and the amplified first heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array respectively, or send the amplified first heterogeneous test signal or the amplified second heterogeneous test signal to the first heterogeneous memristor array and the second heterogeneous memristor array; The test channel control unit is further configured to receive a first heterogeneous test feedback signal output by the first heterogeneous memristor array and a second heterogeneous test feedback signal output by the second heterogeneous memristor array; The amplifier is further used to amplify the first heterogeneous test feedback signal and the second heterogeneous test feedback signal and then output them; The converter is further used to perform analog-to-digital conversion on the amplified first heterogeneous test feedback signal and the amplified second heterogeneous test feedback signal, converting them into first heterogeneous test data and second heterogeneous test data and outputting them to the CPLD; The CPLD is further used to send the first heterogeneous test data and the second heterogeneous test data to the first FPGA and the second FPGA respectively, or send the first heterogeneous test data and the second heterogeneous test data to the first FPGA or the second FPGA; The CPLD is further used to send the combined similar test signal to the converter, or send the first similar test signal or the second similar test signal to the converter; The converter is further used to perform digital-to-analog conversion on the combined similar test signal and then output it, or perform digital-to-analog conversion on the first similar test signal or the second similar test signal and then output it; The amplifier is further used to amplify the converted similar test signal and output it, or to amplify the converted first similar test signal or the converted second similar test signal and output it; The test channel control unit is further used to send the amplified similar test signal to each of the similar memristor arrays, or send the amplified first similar test signal or the amplified second similar test signal to each of the similar memristor arrays; The test channel control unit is further used to receive similar test feedback signals output by each of the similar memristor arrays; The amplifier is also used to amplify each of the test feedback signals of the same type and then output them; The converter is also used to perform analog-to-digital conversion on each amplified test feedback signal of the same type, and convert it into each test data of the same type and output it to the CPLD; The CPLD is also used to send each of the same type of test data to the merging unit.

20. The test system according to any one of claims 14 to 19, characterized in that: The test start control module also includes a third output encryption interface; The microprocessor is further configured to obtain a similar memristor array fault analysis report based on the similar test data and a preset similar data range, or obtain a heterogeneous memristor array fault analysis report based on the heterogeneous test data and a preset heterogeneous data range, and send a fault analysis export instruction to the data selector when receiving a memristor array fault analysis instruction; The data selector is further configured to, after receiving the fault analysis export instruction, open a fault analysis export channel connected to the third output encryption interface, and send the same type of memristor array fault analysis report or the different type of memristor array fault analysis report to the third output encryption interface; The third output encryption interface is used to encrypt and output the similar memristor array fault analysis report or the heterogeneous memristor array fault analysis report.

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